Display panel and display apparatus

Abstract

The present application relates to a display panel and a display apparatus. In the display panel, a light-emitting structure of at least one light-emitting device comprises a plurality of light-emitting sub-structures, an isolation layer comprises a partition wall located between adjacent light-emitting sub-structures, and the orthographic projection of a first electrode of the at least one light-emitting device on an array substrate covers the orthographic projection, on the array substrate, of the partition wall corresponding to the at least one light-emitting device, and the orthographic projections, on the array substrate, of the plurality of light-emitting sub-structures corresponding to the at least one light-emitting device. By means of the present application, the problem of poor display can be alleviated.

Description

Display panel and display device

[0001] Cross-references

[0002] This application claims priority to Chinese Patent Application No. 202411849695.0, filed on December 13, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor packaging technology, and in particular to a display panel and display device. Background Technology

[0004] Organic Light Emitting Diode (OLED) display technology is considered the most promising next-generation flat panel display technology. Compared with liquid crystal display technology, OLED display technology has advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed.

[0005] In traditional display panel manufacturing, a fine metal mask (FMM) is typically used to pattern the light-emitting pixels. FMM technology is mature and has extensive mass production experience. However, FMM technology also suffers from limitations in precision, high development costs, and long development cycles. Fine metal mask-less technology eliminates the limitations of traditional OLED processes on display size, resolution, and other screen performance characteristics, offering advantages such as high performance, full-size display, and agile delivery. Patents CN118251982A, CN115666161A, CN116648095A, CN117062489A, CN118678742A, CN118785761A, CN115224220A, CN118678729A, CN118660529A, and CN118660589A describe relevant aspects of fine metal mask-less technology and are provided for reference.

[0006] However, current OLED display panels still suffer from display defects. Summary of the Invention

[0007] Therefore, it is necessary to provide a display panel and display device that improves upon the above-mentioned problems.

[0008] In a first aspect, embodiments of this application provide a display panel, comprising: an array substrate; an isolation layer located on one side of the array substrate, and including an isolation structure and a plurality of isolation openings formed by the isolation structure, the plurality of isolation openings including a plurality of first isolation openings, a plurality of second isolation openings and a plurality of third isolation openings; a plurality of light-emitting devices, including a plurality of first light-emitting devices corresponding to the plurality of first isolation openings, a plurality of second light-emitting devices corresponding to the plurality of second isolation openings and a plurality of third light-emitting devices corresponding to the plurality of third isolation openings; the first light-emitting devices, the second light-emitting devices and the third light-emitting devices are configured to emit light of different colors; the light-emitting devices include a first electrode, a light-emitting structure and a second electrode stacked thereon; wherein, the light-emitting structure of at least one light-emitting device includes a plurality of light-emitting substructures, the isolation layer includes a partition wall located between adjacent light-emitting substructures, and the orthographic projection of the first electrode of at least one light-emitting device on the array substrate covers the orthographic projection of the partition wall corresponding to at least one light-emitting device on the array substrate and the orthographic projection of the plurality of light-emitting substructures corresponding to at least one light-emitting device on the array substrate.

[0009] The display panel provided in this application embodiment divides a single light-emitting structure into multiple substructures by having at least one light-emitting device comprise a plurality of substructures, and ensuring that the orthographic projection of the first electrode of the at least one light-emitting device covers the orthographic projection of each substructure. These substructures are electrically connected to the same driving circuit. This ensures that if one substructure fails, it will not affect the others, allowing them to continue emitting light normally, thus reducing the risk of display defects. Furthermore, the orthographic projection of the first electrode also covers the orthographic projection of the corresponding partition wall, resulting in a larger coverage area for the first electrode, which helps reduce its resistance and consequently lowers the power consumption of the display panel.

[0010] Secondly, embodiments of this application provide a display panel, comprising: an array substrate; a plurality of light-emitting unit groups disposed on the array substrate; each light-emitting unit group includes a plurality of light-emitting structures, the plurality of light-emitting structures including a plurality of first light-emitting structures, a plurality of second light-emitting structures and a plurality of third light-emitting structures, the centroids of the plurality of second light-emitting structures and the plurality of third light-emitting structures forming a first virtual polygon, at least one first light-emitting structure being located within the first virtual polygon; the first light-emitting structures, the second light-emitting structures and the third light-emitting structures emitting light of different colors; in the same light-emitting unit group, at least one light-emitting structure includes a plurality of light-emitting substructures spaced apart, and the plurality of light-emitting substructures are electrically connected to the same driving circuit in the array substrate.

[0011] Thirdly, embodiments of this application provide a display panel, comprising: an array substrate; a plurality of light-emitting unit groups disposed on the array substrate; each light-emitting unit group includes a plurality of light-emitting structures, the plurality of light-emitting structures including a plurality of first light-emitting structures, a plurality of second light-emitting structures and a plurality of third light-emitting structures, the centroids of the plurality of first light-emitting structures and the plurality of third light-emitting structures forming a first virtual polygon, at least one second light-emitting structure being located within the first virtual polygon; the first light-emitting structures, the second light-emitting structures and the third light-emitting structures emit light of different colors; in the same light-emitting unit group, at least one light-emitting structure includes a plurality of light-emitting substructures spaced apart, and the plurality of light-emitting substructures are electrically connected to the same driving circuit in the array substrate; the spacing between any two adjacent light-emitting structures is a third spacing, the spacing between any two adjacent light-emitting substructures in the same light-emitting structure is a fourth spacing, and the third spacing and the fourth spacing are not equal.

[0012] Fourthly, embodiments of this application provide a display device, including the display panel in any one of the embodiments of the first, second, and third aspects. Attached Figure Description

[0013] Figure 1 is a top view of a display panel provided in an embodiment of this application.

[0014] Figure 2 is a partial top view of some of the film layers of the display panel shown in Figure 1.

[0015] Figure 3 is a schematic diagram of a cross-sectional structure of section AA in Figure 2.

[0016] Figure 4 is a schematic diagram of the cross-sectional structure of section BB in Figure 2.

[0017] Figure 5 is a schematic diagram of another cross-sectional structure of section AA in Figure 2.

[0018] Figure 6 is a partial top view of the light-emitting structure in the display panel shown in Figure 2.

[0019] Figure 7 is a partial top view of the isolation layer in the display panel shown in Figure 2.

[0020] Figure 8 is a partial top view of the first electrode in the display panel shown in Figure 2.

[0021] Figure 9 is a partial top view of the isolation layer in Figure 7 and the first electrode in Figure 8.

[0022] Figure 10 is a partial top view of the pixel-defining layer in the display panel shown in Figure 2.

[0023] Figure 11 is a partial top view of the isolation layer in Figure 7 and the pixel limiting layer in Figure 10.

[0024] Figure 12 is a top view of the isolation structure and the first trace of the display panel shown in Figure 1.

[0025] Figure 13 is a top view of the light-emitting structure and the first trace of the display panel shown in Figure 1.

[0026] Figure 14 is a top view of the isolation layer of another display panel provided in an embodiment of this application.

[0027] Figure 15 is a schematic diagram of the arrangement of the light-emitting structure of the light-emitting device in the display panel shown in Figure 14.

[0028] Figure 16 is a schematic diagram of the arrangement of the light-emitting unit group in Figure 15.

[0029] Figures 17A-17F are schematic diagrams of several separation methods provided by an embodiment of this application for the arrangement of the light-emitting structure shown in Figure 14.

[0030] Figure 18 is a top view of an isolation layer of another display panel provided in an embodiment of this application.

[0031] Figure 19 is a schematic diagram of the arrangement of the light-emitting structure of the light-emitting device in the display panel shown in Figure 18.

[0032] Figures 20A-20Q are schematic diagrams of several separation methods provided by an embodiment of this application for the arrangement of the light-emitting structure shown in Figure 18.

[0033] Figure 21 is a top view of an isolation layer of a display panel according to an embodiment of this application.

[0034] Figure 22 is a schematic diagram of the arrangement of the light-emitting structure of the light-emitting device in the display panel shown in Figure 21.

[0035] Figures 23A-23H are schematic diagrams of several separation methods provided by an embodiment of this application for the arrangement of the light-emitting structure shown in Figure 21.

[0036] Figure 24 is a partial top view of the isolation layer of another display panel provided in an embodiment of this application.

[0037] Figure 25A is a partial top view of the isolation layer of another display panel provided in an embodiment of this application.

[0038] Figure 25B is a top view of a portion of the structure of the light-emitting device of the display panel shown in Figure 25A.

[0039] Figure 26A is a partial top view of the isolation layer of another display panel provided in an embodiment of this application.

[0040] Figure 26B is a top view of a portion of the structure of the light-emitting device of the display panel shown in Figure 26A.

[0041] Figure 27 is a top view schematic diagram of a partial structure of the light-emitting device of another display panel provided in an embodiment of this application.

[0042] Figure 28 is a top view schematic diagram of a partial structure of the light-emitting device of another display panel provided in an embodiment of this application.

[0043] Figure 29 is a top view schematic diagram of the light-emitting structure of another display panel provided in an embodiment of this application.

[0044] Figure 30 is a partial top view of the isolation layer of another display panel provided in an embodiment of this application.

[0045] Figure 31 is a top view of a portion of the structure of the light-emitting device of the display panel shown in Figure 30.

[0046] Figure 32 is a partial top view of the isolation layer of another display panel provided in an embodiment of this application.

[0047] Figure 33 is a top view of a portion of the structure of the light-emitting device of the display panel shown in Figure 32.

[0048] Figure 34 is another top view of a portion of the structure of the light-emitting device of the display panel shown in Figure 32.

[0049] Figure 35 is a partial top view of the isolation layer of another display panel provided in an embodiment of this application.

[0050] Figure 36 is a top view of a portion of the structure of the light-emitting device in the display panel shown in Figure 35. Detailed Implementation

[0051] To facilitate understanding of this application, a more comprehensive description of this application will be provided below with reference to the accompanying drawings.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0053] In related technologies, one or more light-emitting devices in an OLED display panel may fail, resulting in poor display quality.

[0054] In view of the above problems, embodiments of this application provide a display panel and a display device. On the one hand, when a certain light-emitting substructure fails, it will not affect other light-emitting substructures, which can still emit light normally, thereby reducing the risk of display failure of the display panel. On the other hand, the orthographic projection of the first electrode also covers the orthographic projection of the corresponding partition wall, which can make the coverage area of ​​the first electrode larger, which is beneficial to reduce the resistance of the first electrode, thereby reducing the power consumption of the display panel.

[0055] Referring to Figures 1-5, this application provides a display panel 10, which may be an organic light-emitting diode display panel 10 (OLED) or a quantum dot electroluminescent display panel 10 (QLED).

[0056] Specifically, the display panel 10 includes an array substrate 11, an isolation layer 12, and a plurality of light-emitting devices 13. As shown in Figures 2 and 7, the isolation layer 12 is located on one side of the array substrate 11 and includes an isolation structure 12a and a plurality of isolation openings 12c formed by the isolation structure 12a. The plurality of isolation openings 12c includes a plurality of first isolation openings 12c-1, a plurality of second isolation openings 12c-2, and a plurality of third isolation openings 12c-3. Referring to Figures 2, 4, and 7, the plurality of light-emitting devices 13 includes a plurality of first light-emitting devices 13a corresponding to a plurality of first isolation openings 12c-1, a plurality of second light-emitting devices 13b corresponding to a plurality of second isolation openings 12c-2, and a plurality of third light-emitting devices 13c corresponding to a plurality of third isolation openings 12c-3; the first light-emitting devices 13a, second light-emitting devices 13b, and third light-emitting devices 13c are configured to emit light of different colors; each light-emitting device 13 includes a first electrode 131, a light-emitting structure 132, and a second electrode 133 stacked together, wherein the first electrode 131 can be an anode, and the second electrode 133 can be a cathode. Exemplarily, the first light-emitting devices 13a are arranged one-to-one with the first isolation openings 12c-1, the second light-emitting devices 13b are arranged one-to-one with the second isolation openings 12c-2, and the third light-emitting devices 13c are arranged one-to-one with the third isolation openings 12c-3.

[0057] As shown in Figures 6, 7, 8 and 9, the light-emitting structure 132 of at least one light-emitting device 13 includes a plurality of light-emitting substructures 1321, and the isolation layer 12 includes a partition wall 12b located between adjacent light-emitting substructures 1321, that is: the partition wall 12b divides the light-emitting structure 132 into a plurality of light-emitting substructures 1321.

[0058] The first electrode 131 of the at least one light-emitting device 13 is covered by the orthogonal projection on the array substrate 11, the orthogonal projection of the partition wall 12b corresponding to the at least one light-emitting device 13 on the array substrate 11, and the orthogonal projection of the plurality of light-emitting substructures 1321 corresponding to the at least one light-emitting device 13 on the array substrate 11.

[0059] The display panel 10 provided in this application embodiment includes a light-emitting structure 132 of at least one light-emitting device 13 comprising multiple light-emitting substructures 1321, and the orthographic projection of the first electrode 131 of the at least one light-emitting device 13 covers the orthographic projection of each light-emitting substructure 1321. This effectively divides a light-emitting structure 132 into multiple light-emitting substructures 1321 via a partition wall 12b, and these multiple light-emitting substructures 1321 are electrically connected to the same driving circuit. Thus, when a light-emitting substructure 1321 fails (such as due to particle residue causing dark spot failure, encapsulation failure, etc.), it will not affect other light-emitting substructures 1321, which can still emit light normally, thereby reducing the risk of display defects in the display panel 10. Furthermore, the orthographic projection of the first electrode 131 also covers the orthographic projection of the corresponding partition wall 12b, allowing for a larger coverage area of ​​the first electrode 131, which helps reduce the resistance of the first electrode 131 and thus reduces the power consumption of the display panel 10.

[0060] In one embodiment, among the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c, the light-emitting structure 132 of at least one color of the light-emitting device 13 includes multiple light-emitting substructures 1321. This is equivalent to dividing the light-emitting structure 132 of the same color into multiple light-emitting substructures 1321, which helps to maintain consistency among the light-emitting structures 132 of the same color and improves display uniformity. Optionally, among the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c, the light-emitting structure 132 of at least two colors of the light-emitting device 13 includes multiple light-emitting substructures 1321. Thus, compared to the method of "separating" the light-emitting structure 132 of a single color, this embodiment "separates" the light-emitting structures 132 of two colors, enabling both colors of the light-emitting structure 132 to overcome display defects caused by failures (such as dark spot failures due to particle residue, encapsulation failures, etc.), further reducing the risk of display defects. Optionally, each light-emitting device 13 has a light-emitting structure 132 including multiple light-emitting substructures 1321. Thus, this embodiment designs the light-emitting structures 132 of the three colors to be "separated", which can enable the light-emitting structures 132 of the three colors to overcome display defects caused by failures (such as dark spot failures caused by particle residues, encapsulation failures, etc.), further reducing the risk of display defects.

[0061] In one embodiment, as shown in FIG7, the isolation opening 12c corresponding to the at least one light-emitting device 13 includes a plurality of sub-isolation openings 12c1, and a partition wall 12b is provided between two adjacent sub-isolation openings 12c1; the plurality of sub-isolation openings 12c1 correspond one-to-one with a plurality of light-emitting substructures 1321. Thus, it is equivalent to using the partition wall 12b to divide the isolation opening 12c into a plurality of sub-isolation openings 12c1.

[0062] In one embodiment, as shown in FIG7, in the orthographic projection of the partition wall 12b on the array substrate 11, the projection edge S1 adjacent to one sub-isolation opening 12c1 is parallel to the projection edge S1 adjacent to the other sub-isolation opening 12c1. This allows the partition wall 12b to have a more regular shape and occupies less space. Furthermore, with a fixed spacing between the two sub-isolation openings 12c1, the space of the two sub-isolation openings 12c1 can be maximized, thereby increasing the area occupied by the light-emitting substructure 1321 and thus improving the aperture ratio. Due to manufacturing process errors, the parallelism of A and B described herein includes not only absolute parallelism but also approximate parallelism. For example, when the included angle between A and B is between -5° and 5°, A and B are also considered parallel.

[0063] Optionally, as shown in FIG1, the array substrate 11 includes a plurality of scan lines 11b arranged at intervals along the second direction Y, and each scan line 11b extends along a first direction X intersecting the second direction Y; the orthographic projection of the sub-isolation opening 12c1 on the array substrate 11 includes at least one projection edge S1 parallel to the second direction Y, that is: part of the sidewall of the sub-isolation opening 12c1 is parallel to the second direction Y.

[0064] In some embodiments, the second electrode 133 needs to overlap with the isolation layer 12 (such as the isolation structure 12a or the partition wall 12b) to achieve electrical connection between the second electrode 133 and the isolation layer 12. Furthermore, during the vapor deposition of the second electrode 133, the vapor deposition source scans along the first direction X, making it easier for the vapor deposition material to be deposited onto a portion of the sidewall of the isolation layer 12 (the sidewall parallel to the second direction Y), thereby ensuring good overlap performance between the second electrode 133 and the isolation layer 12.

[0065] Optionally, the orthographic projection of each isolation opening 12c onto the array substrate 11 includes at least one projection edge S1 parallel to the second direction Y. As mentioned above, this facilitates the deposition of vapor-deposited material onto a portion of the sidewalls (sidewalls parallel to the second direction Y) of the isolation layer 12, thereby enabling the second electrode 133 to have better overlap performance with the isolation layer 12.

[0066] In one embodiment, within the same isolation opening 12c, the areas of the orthographic projections of each sub-isolation opening 12c1 onto the array substrate 11 are all equal. Here, "the orthographic projection of the sub-isolation opening 12c1 onto the array substrate 11" refers to the orthographic projection of the wall surface at the smallest aperture of the sub-isolation opening 12c1 onto the array substrate 11. This facilitates ensuring that the areas of each light-emitting substructure 1321 are equal, thereby improving the uniformity of light emission. Due to manufacturing process errors, the equality of A and B described herein includes not only absolute equality but also approximate equality. For example, when A and B satisfy the relationship 0.95B≤A≤1.05B, or 0.95A≤B≤1.05A, A and B are also considered equal.

[0067] Optionally, within the same isolation opening 12c, the shapes of the orthographic projections of each sub-isolation opening 12c1 onto the array substrate 11 are all identical. This helps to maintain consistency in the shape of each light-emitting substructure 1321, thereby not only further improving the uniformity of light emission but also helping to reduce color deviation at a large viewing angle.

[0068] Optionally, within the same isolation opening 12c, the orthographic projections of any two adjacent sub-isolation openings 12c1 onto the array substrate 11 are arranged axially symmetrically. This helps maintain the axial symmetry of the shape of the light-emitting substructure 1321, thereby not only further improving the uniformity of light emission but also helping to reduce angular deviation at a large viewing angle. For example, two adjacent sub-isolation openings 12c1 can be symmetrically arranged about the centerline of the partition wall 12b between them.

[0069] Optionally, within the same isolation opening 12c, the orthographic projections of any two adjacent sub-isolation openings 12c1 onto the array substrate 11 are centrally symmetrical. Thus, as shown in FIG29, this helps maintain the central symmetry of the shape of the light-emitting substructure 1321, thereby not only further improving the uniformity of light emission but also helping to reduce color deviation at a large viewing angle. Exemplarily, two adjacent sub-isolation openings 12c1 can be centrally symmetrical about the centroid of the partition wall 12b between them.

[0070] In one embodiment, at least two sub-isolation openings 12c1 within the same isolation opening 12c have unequal areas projected onto the array substrate 11. This allows designers to customize the arrangement of the light-emitting substructures 1321 according to actual needs, thereby improving the display effect.

[0071] Optionally, as shown in FIG12, the array substrate 11 further includes a first trace 11d. In at least two sub-isolation openings 12c1 of the same isolation opening 12c, the orthographic projection of at least one sub-isolation opening 12c1 on the array substrate 11 overlaps with the orthographic projection of the first trace 11d on the array substrate 11, and the orthographic projection of at least one sub-isolation opening 12c1 on the array substrate 11 does not overlap with the orthographic projection of the first trace 11d on the array substrate 11. It is understood that, as shown in FIG13, in the light-emitting substructures 1321 corresponding to the two sub-isolation openings 12c1, one light-emitting substructure 1321 overlaps with the first trace 11d, and the other light-emitting substructure 1321 does not overlap with the first trace 11d. This is equivalent to differentiating the projected area of ​​the sub-isolation opening 12c1 based on the overlap between the sub-isolation opening 12c1 and the first trace 11d (e.g., overlapping or non-overlapping). This allows designers to differentiate the area of ​​the light-emitting substructure 1321 based on the overlap between the light-emitting substructure 1321 and the first trace 11d. It is understood that traces in the array substrate 11 are prone to reflection. When the first trace 11d is located below the light-emitting substructure 1321, it can easily affect the light-emitting effect of the light-emitting substructure 1321. Therefore, when the first trace 11d overlaps with the light-emitting structure 132, designers need to perform some special design to reduce the impact of the first trace 11d on the light-emitting effect. It is understood that the above-mentioned differentiated design helps to reduce the impact of the first trace 11d on the light-emitting effect. For example, the first trace 11d can be a trace used to transmit an anode signal; this embodiment does not specifically limit the type of signal transmitted by the first trace 11d.

[0072] Optionally, as shown in FIG12, the orthographic projection of at least one sub-isolation opening 12c1 on the array substrate 11 overlaps with the orthographic projection of the first trace 11d on the array substrate 11, and the overlapping projections are symmetrically arranged about the center line of the orthographic projection of the at least one sub-isolation opening 12c1 on the array substrate 11. It can be understood that, as shown in FIG13, the orthographic projection of a light-emitting substructure 1321 on the array substrate 11 overlaps with the orthographic projection of the first trace 11d on the array substrate 11, and the overlapping projections are symmetrically arranged about the center line of the orthographic projection of the light-emitting substructure 1321 on the array substrate 11.

[0073] Taking the orientation in Figure 13 as an example, the overlapping orthographic projections of the upper light-emitting substructure 1321 and the first trace 11d are symmetrically arranged about the horizontal centerline of the light-emitting substructure 1321. When an observer views the display panel 10 from above and below at a wide viewing angle, the observed display effect is almost identical. Therefore, the above arrangement helps to improve the viewing angle distortion phenomenon at a wide viewing angle.

[0074] In one embodiment, as shown in Figure 7, the minimum spacing between two adjacent isolation openings 12c is the first spacing a. Within the same isolation opening 12c, the minimum spacing between two adjacent sub-isolation openings 12c1 is the second spacing b. The first spacing a and the second spacing b are not equal. This allows designers to adaptively adjust the size of the isolation openings 12c according to actual needs. For example, when the first spacing a is less than the second spacing b, it is equivalent to sparsely arranging the light-emitting sub-structures 1321 of the light-emitting structure 132. This facilitates the placement of conductive structures 11c for connecting the anode and the driving circuit in the area between adjacent light-emitting sub-structures 1321, allowing designers to easily position the conductive structures 11c according to actual needs and reducing the limitations imposed by the arrangement of the light-emitting structure 132 on the via structure's placement. When the first spacing a is greater than the second spacing b, it is equivalent to more compactly arranging the light-emitting sub-structures 1321 of the light-emitting structure 132, which helps to maximize the aperture ratio and minimize the loss of aperture ratio caused by the "separating light-emitting structure 132".

[0075] Optionally, the second spacing b is smaller than the first spacing a, that is, the first spacing a is greater than the second spacing b. In this way, the light-emitting substructures 1321 of the light-emitting structure 132 can be arranged more compactly, and the light-emitting area of ​​the light-emitting substructures 1321 can be set to be larger, which is conducive to maximizing the aperture ratio and thus minimizing the loss of aperture ratio caused by the "separated light-emitting structure 132", ensuring the display effect.

[0076] Optionally, the difference between the first pitch a and the second pitch b is greater than 0 μm and less than or equal to 16 μm. For example, the difference between the first pitch a and the second pitch b can be 0.1 μm, 1 μm, 3 μm, 5 μm, 8 μm, 12 μm, 14 μm, 16 μm, or any two of the above values. By ensuring that the difference between the first pitch a and the second pitch b is within the above range, it is beneficial to improve the aperture ratio and ensure display quality.

[0077] In one embodiment, at least a portion of the second electrodes 133 of the light-emitting devices 13 are electrically connected to the isolation layer 12. It is understood that the isolation layer 12 can be electrically connected to the driving circuit of the display panel 10. In this embodiment, the second electrodes 133 of the light-emitting devices 13 are connected to the driving circuit via the isolation layer 12. This allows for a more optimized wiring layout within the display area of ​​the display panel 10.

[0078] Optionally, as shown in Figures 3-5, both the isolation structure 12a and the partition wall 12b include a conductive portion 121 and a blocking portion 122 stacked along a direction away from the array substrate 11. The orthographic projection of the conductive portion 121 on the array substrate 11 lies within the orthographic projection of the blocking portion 122 on the array substrate 11. At least a portion of the second electrodes 133 of the light-emitting devices 13 are in contact with the conductive portion 121. In this way, the second electrodes 133 can be electrically connected to the isolation layer 12. The "orthographic projection of the sub-isolation opening 12c1 on the array substrate 11" refers to the orthographic projection of the lower surface (bottom surface) of the blocking portion 122 surrounding the sub-isolation opening 12c1 on the array substrate 11.

[0079] In one embodiment, the conductive portion 121 includes at least one metal layer. In one example, the conductive portion 121 includes one metal layer. Further, the material of the conductive portion 121 includes at least one of a metal and a metal oxide. Exemplarily, the metal may be silver, copper, titanium, aluminum, molybdenum, etc. The metal oxide may be tin oxide, zinc oxide, cadmium oxide, indium oxide, indium tin oxide, zinc indium oxide, zinc gallium oxide, zinc aluminum oxide, titanium tantalum oxide, etc.

[0080] In one embodiment, the material of the blocking portion 122 includes titanium or molybdenum.

[0081] Optionally, the second electrode 133 of at least one light-emitting device 13 includes a plurality of sub-electrode portions 1331 corresponding one-to-one with the plurality of light-emitting substructures 1321, and each sub-electrode portion 1331 is in contact with the conductive portion 121. In this way, the sub-electrode portions 1331 corresponding to each light-emitting substructure 1321 are electrically connected to the isolation layer 12, avoiding damage to the sub-electrode portions 1331 on one light-emitting substructure 1321 from affecting the sub-electrode portions 1331 on other light-emitting substructures 1321, thereby improving the light emission reliability of the display panel 10.

[0082] Optionally, at least a portion of the outer edge of each sub-electrode portion 1331 covers the sidewall of the conductive portion 121 near the isolation opening 12c. This allows the sub-electrode portion 1331 and the conductive portion 121 to have a larger contact area, reducing the electrical connection resistance.

[0083] If a second electrode 133 is a single structure and is not divided into multiple sub-electrode portions 1331, then at least a portion of the outer edge of the second electrode 133 covers the sidewall of the conductive portion 121 near the isolation opening 12c.

[0084] Optionally, in the same light-emitting device 13, the maximum distance between the outer edge of each sub-electrode portion 1331 and the array substrate 11 is equal. In other words, the overlap height of each sub-electrode portion 1331 on the isolation layer 12 is consistent. Due to the influence of the manufacturing process, "approximately equal" can also be considered as equal. The above arrangement helps to keep the electrical connection resistance between each sub-electrode portion 1331 and the isolation layer 12 consistent, which helps to improve the uniformity of light emission.

[0085] Optionally, the orthographic projection of the first electrode 131 of at least one light-emitting device 13 on the array substrate 11 covers the orthographic projection of the side surface of the blocking portion 122 of the partition wall 12b corresponding to at least one light-emitting device 13 on the array substrate 11, that is: the orthographic projection of the first electrode 131 on the array substrate 11 covers the orthographic projection of the lower surface (bottom surface) of the blocking portion 122 of the partition wall 12b on the array substrate 11.

[0086] In one embodiment, as shown in Figures 2-5, the display panel 10 further includes a plurality of encapsulation portions 14 corresponding one-to-one with a plurality of light-emitting devices 13, each encapsulation portion 14 being disposed on the side of the corresponding light-emitting device 13 away from the array substrate 11. Exemplarily, the encapsulation portion 14 is an inorganic film layer.

[0087] Optionally, the orthographic projection of the encapsulation portion 14 corresponding to at least one light-emitting device 13 onto the array substrate 11 covers the orthographic projection of the partition wall 12b corresponding to the at least one light-emitting device 13 onto the array substrate 11 and the orthographic projection of the plurality of light-emitting substructures 1321 corresponding to the at least one light-emitting device 13 onto the array substrate 11. That is, the encapsulation portion 14 is a continuous film layer structure, which allows for a larger contact area between the encapsulation portion 14 and other film layers in the display panel 10, improving the connection stability of the encapsulation portion 14 and enhancing the encapsulation reliability.

[0088] Optionally, a light-emitting material layer 161 and an electrode material layer 162 are further provided between the partition wall 12b and the encapsulation part 14.

[0089] Optionally, as shown in FIG5, the encapsulation portion 14 corresponding to at least one light-emitting device 13 includes a plurality of sub-encapsulation portions 141 spaced apart. The plurality of sub-encapsulation portions 141 correspond one-to-one with a plurality of light-emitting substructures 1321, and the sub-encapsulation portions 141 are disposed on the side of the corresponding light-emitting substructure 1321 away from the array substrate 11. In this way, it is equivalent to encapsulating each light-emitting substructure 1321 individually. Thus, if the encapsulation of one sub-encapsulation portion 141 fails, it will not affect the encapsulation performance of other sub-encapsulation portions 141, allowing other light-emitting substructures 1321 to still emit light normally, reducing the risk of display defects in the display panel 10.

[0090] In one embodiment, as shown in Figures 3, 4 and 10, the display panel 10 further includes a pixel defining layer 15, which is disposed between the array substrate 11 and the isolation layer 12. The pixel defining layer 15 forms a plurality of pixel openings 15a, which correspond one-to-one with a plurality of light-emitting devices 13. At least a portion of each light-emitting device 13 is disposed within the corresponding pixel opening 15a.

[0091] Optionally, at least one light-emitting device 13 has a pixel opening 15a that includes a plurality of sub-pixel openings 15a1, and the plurality of sub-pixel openings 15a1 correspond one-to-one with a plurality of light-emitting substructures 1321. It is understood that the plurality of sub-pixel openings 15a1 of the pixel opening 15a are connected one-to-one with the plurality of sub-isolation openings 12c1 of the isolation opening 12c corresponding to the pixel opening 15a.

[0092] Optionally, the spacing between two adjacent pixel openings 15a is the third spacing c, and the spacing between two adjacent sub-pixel openings 15a1 within the same pixel opening 15a is the fourth spacing d. The third spacing c and the fourth spacing d are not equal. This allows designers to adaptively adjust the size of the pixel openings 15a according to actual needs. For example, when the third spacing c is less than the fourth spacing d, it is equivalent to sparsely arranging the light-emitting sub-structures 1321 of the light-emitting structure 132. This facilitates the placement of conductive structures 11c for connecting the anode and the driving circuit in the area between adjacent light-emitting sub-structures 1321, making it easier for designers to set the position of the conductive structures 11c according to actual needs and reducing the limitations imposed by the arrangement of the light-emitting structure 132 on the placement of the conductive structures 11c. When the third spacing c is greater than the second spacing b, it is equivalent to arranging the light-emitting sub-structures 1321 of the light-emitting structure 132 more compactly, which helps to maximize the aperture ratio and minimize the loss of aperture ratio caused by the "separation of the light-emitting structure 132".

[0093] Optionally, as shown in FIG11, the maximum distance between the orthographic projection outer contour of the sub-isolation opening 12c1 on the array substrate 11 and the orthographic projection outer contour of the corresponding sub-pixel opening 15a1 on the array substrate 11 is a first distance e. Here, "orthographic projection outer contour of the sub-isolation opening 12c1 on the array substrate 11" refers to the orthographic projection contour of the wall surface at the smallest diameter of the sub-isolation opening 12c1 on the array substrate 11. "Orthographic projection outer contour of the sub-pixel opening 15a1 on the array substrate 11" refers to the orthographic projection of the edge of the sub-pixel opening 15a1 on the side closer to the array substrate 11 on the array substrate 11.

[0094] Specifically, within the same isolation opening 12c, the first distance e corresponding to at least two sub-isolation openings 12c1 is equal. This helps to ensure that at least two sub-isolation openings 12c1 within the same isolation opening 12c are aligned with the corresponding sub-pixel openings 15a1 within the same pixel opening 15a, thereby improving the display uniformity of characters positioned slightly below the viewpoint.

[0095] Optionally, within the same isolation opening 12c, the first distance e corresponding to each sub-isolation opening 12c1 is equal. This helps to ensure that all sub-isolation openings 12c1 within the same isolation opening 12c are aligned with the corresponding sub-pixel openings 15a1 within the same pixel opening 15a, thereby improving the display uniformity of characters positioned slightly below the viewpoint.

[0096] In one embodiment, as shown in FIG14, the inner wall of the isolation opening 12c includes a first straight edge S2 parallel to the plane of the array substrate 11. A plurality of first isolation openings 12c-1 are arranged along a first direction X to form a plurality of first isolation opening rows 12f. A plurality of second isolation openings 12c-2 and a plurality of third isolation openings 12c-3 are alternately arranged along the first direction X to form a plurality of second isolation opening rows 12g. The plurality of first isolation opening rows 12f and the plurality of second isolation opening rows 12g are alternately arranged along a second direction Y intersecting the first direction X. Adjacent second isolation openings 12c-2 and third isolation openings 12c-3 are located within a first virtual quadrilateral N1. The first straight edge S2 of at least one of the second isolation openings 12c-2 and third isolation openings 12c-3 is located on the edge of the first virtual quadrilateral N1, and at least one first isolation opening 12c-1 is located within the first virtual quadrilateral N1. Exemplarily, the first direction X and the second direction Y are perpendicular. The above arrangement allows the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c to be arranged in a specific manner, which is beneficial to giving the display panel 10 a better display effect. Due to manufacturing process errors, the perpendicularity of A and B as described herein includes not only absolute perpendicularity but also approximate perpendicularity. For example, when the included angle between A and B is between 85° and 95°, A and B are also considered to be perpendicular.

[0097] In one example, the first straight edge S2 is located on the surface of the conductive portion 121 near the isolation opening 12c. In another example, the first straight edge S2 is located on the surface of the blocking portion 122 near the isolation opening 12c.

[0098] Optionally, the first straight edge S2 of the second isolation opening 12c-2 and the third isolation opening 12c-3 are both located on the edge of the first virtual quadrilateral N1.

[0099] Optionally, the first straight edge S2 is located on the surface of the conductive part 121 near the isolation opening 12c, and a portion of the edge of the second electrode 133 of each light-emitting device 13 is disposed on the first straight edge S2; thus, it is beneficial to improve the connection performance between the second electrode 133 and the conductive part 121, thereby helping to reduce the lap resistance.

[0100] Optionally, the second isolation opening 12c-2 is located at the first vertex N2-1 of the second virtual quadrilateral N2, and the third isolation opening 12c-3 is located at the second vertex N2-2 of the second virtual quadrilateral N2. The first vertex N2-1 and the second vertex N2-2 are alternately and intermittently arranged. Further, the first isolation opening 12c-1 is located inside the second virtual quadrilateral N2, and the center of the first isolation opening 12c-1 (i.e., the centroid of the first isolation opening 12c-1) is offset from the center of the second virtual quadrilateral N2. If the first isolation opening 12c-1 includes multiple first sub-isolation openings 12c1-1, then the centroid of the first isolation opening 12c-1 is the centroid of the shape enclosed by the outer edges of the multiple first isolation openings 12c-1.

[0101] Optionally, along the first direction X, the second virtual quadrilateral N2 has a first side N2-3 and a second side N2-4 opposite to each other, the length of the first side N2-3 being less than the length of the second side N2-4. Further, the second virtual quadrilateral N2 also includes a third side N2-5 and a fourth side N2-6 opposite to each other along the second direction Y. Optionally, the first side N2-3 and the second side N2-4 are parallel. Optionally, the second virtual quadrilateral N2 is a trapezoid.

[0102] Optionally, as shown in Figures 14, 15 and 16, the first isolation opening 12c-1 includes two first sub-isolation openings 12c1-1, the first light-emitting structure 132a includes two first light-emitting sub-structures 1321a, and the second light-emitting structure 132b and the third light-emitting structure 132c are not separated.

[0103] Optionally, as shown in Figure 17A, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, and the first light-emitting structure 132a and the third light-emitting structure 132c are not separated. Optionally, as shown in Figure 17B, the third light-emitting structure 132c includes two third light-emitting substructures 1321c, and the first light-emitting structure 132a and the second light-emitting structure 132b are not separated. Optionally, as shown in Figure 17C, the first light-emitting structure 132a includes two first light-emitting substructures 1321a, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, and the third light-emitting structure 132c is not separated. Optionally, as shown in Figure 17D, the first light-emitting structure 132a includes two first light-emitting substructures 1321a, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, and the third light-emitting structure 132c includes two third light-emitting substructures 1321c. Optionally, as shown in Figure 17E, the first light-emitting structure 132a includes four first light-emitting substructures 1321a, the second light-emitting structure 132b includes four second light-emitting substructures 1321b, and the third light-emitting structure 132c includes four third light-emitting substructures 1321c. Optionally, as shown in Figure 17F, the first light-emitting structure 132a includes two first light-emitting substructures 1321a, the second light-emitting structure 132b includes four second light-emitting substructures 1321b, and the third light-emitting structure 132c includes four third light-emitting substructures 1321c. It can be understood that in the arrangements shown in Figures 17A-17F, the four first light-emitting structures 132a, the two second light-emitting structures 132b, and the two third light-emitting structures 132c together constitute a light-emitting unit group 17, and multiple light-emitting unit groups 17 are arranged in an array.

[0104] In one embodiment, as shown in FIG18, a plurality of first isolation openings 12c-1, a plurality of second isolation openings 12c-2, and a plurality of third isolation openings 12c-3 are arranged along a first direction X to form a plurality of third isolation opening rows 12h, and the plurality of third isolation opening rows 12h are arranged sequentially along a second direction Y intersecting the first direction X; in the same third isolation opening row 12h, the first isolation openings 12c-1, the second isolation openings 12c-2, and the third isolation openings 12c-3 are arranged alternately. Exemplarily, the first direction X and the second direction Y are perpendicular. This arrangement allows the display panel 10 to have a better display effect.

[0105] Optionally, the array substrate 11 includes multiple scan lines 11b spaced apart along the second direction Y, each scan line 11b extending along the first direction X; the inner wall of the isolation opening 12c includes a first straight side S2, which is parallel to the second direction Y. Thus, when the second electrode 133 is deposited, the deposition source scans along the first direction X, making it easier for the deposition material to be deposited onto the first straight side S2, thereby ensuring good adhesion between the second electrode 133 and the isolation layer 12.

[0106] Optionally, the dimensions of the first isolation opening 12c-1 along the second direction Y, the second isolation opening 12c-2 along the second direction Y, and the third isolation opening 12c-3 along the second direction Y are all equal. In this way, the lengths of the first light-emitting structure 132a, the second light-emitting structure 132b, and the third light-emitting structure 132c can be kept consistent, which is beneficial to maximizing the aperture ratio.

[0107] Optionally, as shown in Figures 18 and 19, the first isolation opening 12c-1 includes two first sub-isolation openings 12c1-1 arranged along the second direction Y, the second isolation opening 12c-2 includes two second sub-isolation openings 12c1-2 arranged along the second direction Y, and the third isolation opening 12c-3 includes two third sub-isolation openings 12c1-3 arranged along the second direction Y. The first light-emitting structure 132a includes two first light-emitting substructures 1321a, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, and the third light-emitting structure 132c includes two third light-emitting substructures 1321c.

[0108] Optionally, as shown in Figure 20A, the third light-emitting structure 132c includes two third light-emitting substructures 1321c, and the first light-emitting structure 132a and the second light-emitting structure 132b are not separated. Optionally, as shown in Figure 20B, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, and the first light-emitting structure 132a and the third light-emitting structure 132c are not separated. Optionally, as shown in Figure 20C, the first light-emitting structure 132a includes two first light-emitting substructures 1321a, and the second light-emitting structure 132b and the third light-emitting structure 132c are not separated. Optionally, as shown in Figure 20D, the first light-emitting structure 132a includes two first light-emitting substructures 1321a, the third light-emitting structure 132c includes two third light-emitting substructures 1321c, and the second light-emitting structure 132b is not separated. Optionally, as shown in Figure 20E, the first light-emitting structure 132a includes two first light-emitting substructures 1321a, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, and the third light-emitting structure 132c is not separated. Optionally, as shown in Figure 20F, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, the third light-emitting structure 132c includes two third light-emitting substructures 1321c, and the first light-emitting structure 132a is not separated. Optionally, as shown in Figure 20G, the first light-emitting structure 132a includes two first light-emitting substructures 1321a, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, and the third light-emitting structure 132c includes three third light-emitting substructures 1321c. Optionally, as shown in FIG20H, the first light-emitting structure 132a includes two first light-emitting substructures 1321a, the second light-emitting structure 132b includes three second light-emitting substructures 1321b, and the third light-emitting structure 132c includes two third light-emitting substructures 1321c. Optionally, as shown in FIG20I, the first light-emitting structure 132a includes three first light-emitting substructures 1321a, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, and the third light-emitting structure 132c includes two third light-emitting substructures 1321c. Optionally, as shown in FIG20J, the first light-emitting structure 132a includes three first light-emitting substructures 1321a, the second light-emitting structure 132b includes three second light-emitting substructures 1321b, and the third light-emitting structure 132c includes two third light-emitting substructures 1321c. Optionally, as shown in Figure 20K, the first light-emitting structure 132a includes three first light-emitting substructures 1321a, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, and the third light-emitting structure 132c includes three third light-emitting substructures 1321c. Optionally, as shown in Figure 20L, the first light-emitting structure 132a includes two first light-emitting substructures 1321a, the second light-emitting structure 132b includes three second light-emitting substructures 1321b, and the third light-emitting structure 132c includes three third light-emitting substructures 1321c.Optionally, as shown in Figure 20M, the first light-emitting structure 132a includes three first light-emitting substructures 1321a, the second light-emitting structure 132b includes three second light-emitting substructures 1321b, and the third light-emitting structure 132c includes three third light-emitting substructures 1321c. Optionally, as shown in Figure 20N, the first light-emitting structure 132a includes three first light-emitting substructures 1321a, the second light-emitting structure 132b includes four second light-emitting substructures 1321b, and the third light-emitting structure 132c includes three third light-emitting substructures 1321c. Optionally, as shown in Figure 20O, the first light-emitting structure 132a includes four first light-emitting substructures 1321a, the second light-emitting structure 132b includes four second light-emitting substructures 1321b, and the third light-emitting structure 132c includes three third light-emitting substructures 1321c. Optionally, as shown in Figure 20P, the first light-emitting structure 132a includes four first light-emitting substructures 1321a, the second light-emitting structure 132b includes three second light-emitting substructures 1321b, and the third light-emitting structure 132c includes four third light-emitting substructures 1321c. Optionally, as shown in Figure 20Q, the first light-emitting structure 132a includes four first light-emitting substructures 1321a, the second light-emitting structure 132b includes three second light-emitting substructures 1321b, and the third light-emitting structure 132c includes three third light-emitting substructures 1321c. It can be understood that in the arrangements shown in Figures 20A-20Q, one first light-emitting structure 132a, one second light-emitting structure 132b, and one third light-emitting structure 132c together constitute a light-emitting unit group 17, and multiple light-emitting unit groups 17 are arranged in an array.

[0109] The more light-emitting substructures 1321 there are in the light-emitting structure 132, the smaller the area ratio of a single light-emitting substructure 1321. When a certain light-emitting substructure 1321 fails, the impact on the overall light-emitting effect of the light-emitting structure 132 is small.

[0110] In one embodiment, as shown in FIG21, a plurality of first isolation openings 12c-1 and a plurality of second isolation openings 12c-2 are alternately arranged along the second direction Y to form a plurality of first isolation opening columns 12i, a plurality of third isolation openings 12c-3 are arranged along the second direction Y to form a plurality of second isolation opening columns 12j, and the plurality of first isolation opening columns 12i and the plurality of second isolation opening columns 12j are alternately arranged along a first direction X intersecting the second direction Y. Exemplarily, the first direction X and the second direction Y are perpendicular. This allows the display panel 10 to have a better display effect.

[0111] Optionally, as shown in FIG21, the first isolation opening 12c-1 includes a plurality of first sub-isolation openings 12c1-1 arranged along the first direction X, and a partition wall 12b is provided between two adjacent first sub-isolation openings 12c1-1. The second isolation opening 12c-2 includes a plurality of second sub-isolation openings 12c1-2 arranged along the first direction X, and a partition wall 12b is provided between two adjacent second sub-isolation openings 12c1-2. The third isolation opening 12c-3 includes a plurality of third sub-isolation openings 12c1-3 arranged along the second direction Y, and a partition wall 12b is provided between two adjacent third sub-isolation openings 12c1-3. In this way, the size of the first sub-isolation opening 12c1-1 in the second direction Y is larger than its size in the first direction X; the size of the second sub-isolation opening 12c1-2 in the second direction Y is larger than its size in the first direction X; and the size of the third sub-isolation opening 12c1-3 in the second direction Y is larger than its size in the first direction X. In other words, the long sides of the first sub-isolation opening 12c1-1, the second sub-isolation opening 12c1-2, and the third sub-isolation opening 12c1-3 are all located in the second direction Y. Thus, when the second electrode 133 is deposited, the evaporation source scans along the first direction X, and the evaporation material is more easily deposited onto the long sides of each sub-isolation opening 12c1, thereby giving the second electrode 133 better adhesion to the isolation layer 12.

[0112] Optionally, the extension direction (length direction) of the partition wall 12b between two adjacent first sub-isolation openings 12c1-1 intersects with the extension direction (length direction) of the partition wall 12b between two adjacent third sub-isolation openings 12c1-3. Further, the extension direction of the partition wall 12b between two adjacent first sub-isolation openings 12c1-1 is perpendicular to the extension direction of the partition wall 12b between two adjacent third sub-isolation openings 12c1-3.

[0113] Optionally, the extension direction (length direction) of the partition wall 12b between two adjacent second isolation openings 12c-2 intersects the extension direction (length direction) of the partition wall 12b between two adjacent third sub-isolation openings 12c1-3. Further, the extension direction of the partition wall 12b between two adjacent second isolation openings 12c-2 is perpendicular to the extension direction of the partition wall 12b between two adjacent third sub-isolation openings 12c1-3.

[0114] Optionally, the first isolation opening 12c-1 includes two first sub-isolation openings 12c1-1, the second isolation opening 12c-2 includes two second sub-isolation openings 12c1-2, and the third isolation opening 12c-3 includes two third sub-isolation openings 12c1-3. As shown in FIG22, the first light-emitting structure 132a includes two first light-emitting substructures 1321a, the second light-emitting structure 132b includes two second light-emitting substructures 1321b, and the third light-emitting structure 132c includes two third light-emitting substructures 1321c. It should be noted that the number of the first sub-isolation openings 12c1-1, the second sub-isolation openings 12c1-2, and the third sub-isolation openings 12c1-3 can also be other values, and this embodiment of the application does not impose any particular limitation.

[0115] Optionally, as shown in FIG23A, the third light-emitting structure 132c includes two third light-emitting substructures 1321c arranged along the second direction Y. The first light-emitting structure 132a and the second light-emitting structure 132b are not separated. Optionally, as shown in FIG23B, the second light-emitting structure 132b includes two second light-emitting substructures 1321b arranged along the second direction Y, and the third light-emitting structure 132c includes two third light-emitting substructures 1321c arranged along the second direction Y. The first light-emitting structure 132a is not separated. Optionally, as shown in FIG23C, the first light-emitting structure 132a includes two first light-emitting substructures 1321a arranged along the second direction Y, and the third light-emitting structure 132c includes two third light-emitting substructures 1321c arranged along the second direction Y. The second light-emitting structure 132b is not separated. Optionally, as shown in FIG23D, the first light-emitting structure 132a includes two first light-emitting substructures 1321a arranged along the second direction Y, the second light-emitting structure 132b includes two second light-emitting substructures 1321b arranged along the second direction Y, and the third light-emitting structure 132c includes four third light-emitting substructures 1321c arranged along the second direction Y. Optionally, as shown in FIG23E, the first light-emitting structure 132a includes two first light-emitting substructures 1321a arranged along the second direction Y, the second light-emitting structure 132b includes two second light-emitting substructures 1321b arranged along the second direction Y, and the third light-emitting structure 132c includes four third light-emitting substructures 1321c, and the four third light-emitting substructures 1321c are arranged in two rows along the first direction X, with two third light-emitting substructures 1321c in each row. Optionally, as shown in Figure 23F, the first light-emitting structure 132a includes two first light-emitting substructures 1321a arranged along the second direction Y; the second light-emitting structure 132b includes four second light-emitting substructures 1321b, arranged in two rows along the first direction X, with two substructures 1321b in each row; and the third light-emitting structure 132c includes four third light-emitting substructures 1321c, arranged in two rows along the first direction X, with two substructures 1321c in each row. Optionally, as shown in Figure 23G, the first light-emitting structure 132a includes four first light-emitting substructures 1321a, arranged in two rows along the first direction X, with two substructures 1321a in each row. The second light-emitting structure 132b includes two second light-emitting substructures 1321b arranged along the second direction Y. The third light-emitting structure 132c includes four third light-emitting substructures 1321c, and the four third light-emitting substructures 1321c are arranged in two rows along the first direction X, with two third light-emitting substructures 1321c in each row.Optionally, as shown in Figure 23H, the first light-emitting structure 132a includes four first light-emitting substructures 1321a, which are arranged in two rows along the first direction X, with two first light-emitting substructures 1321a in each row. The second light-emitting structure 132b includes four second light-emitting substructures 1321b, which are arranged in two rows along the first direction X, with two second light-emitting substructures 1321b in each row. The third light-emitting structure 132c includes four third light-emitting substructures 1321c, which are arranged in two rows along the first direction X, with two third light-emitting substructures 1321c in each row. It can be understood that in the arrangement shown in Figures 20A-20Q, one first light-emitting structure 132a, one second light-emitting structure 132b, and one third light-emitting structure 132c together constitute a light-emitting unit group 17, and multiple light-emitting unit groups 17 are arranged in an array.

[0116] In one embodiment, the first light-emitting device 13a emits light with a wavelength between 505nm and 545nm, i.e., the first light-emitting device 13a is a green light-emitting device 13; the second light-emitting device 13b emits light with a wavelength between 600nm and 650nm, i.e., the second light-emitting device 13b is a red light-emitting device 13; and the third light-emitting device 13c emits light with a wavelength between 440nm and 480nm, i.e., the third light-emitting device 13c is a blue light-emitting device 13.

[0117] Specifically, the light-emitting structure 132 (second light-emitting structure 132b) of the second light-emitting device 13b includes multiple light-emitting substructures 1321 (second light-emitting substructures 1321b), and the second isolation opening 12c-2 includes multiple second sub-isolation openings 12c1-2. That is, the red light-emitting structure 132 is divided into multiple light-emitting substructures 1321.

[0118] The inventors discovered through research that the red light-emitting device 13 is prone to dark spot failure due to the influence of the manufacturing process sequence. By dividing the red light-emitting structure 132 into multiple light-emitting substructures 1321, when a certain light-emitting substructure 1321 experiences a dark spot failure, it will not affect other light-emitting substructures 1321, thereby effectively improving the problem of dark spot failure.

[0119] Optionally, the orthographic projection of the second sub-isolation opening 12c1-2 onto the array substrate 11 is a polygon. Here, the polygon can be a quadrilateral, pentagon, hexagon, heptagon, octagon, nonagon, etc.

[0120] Optionally, as shown in FIG17A, the light-emitting structure 132 (second light-emitting structure 132b) of the second light-emitting device 13b includes two light-emitting substructures 1321 (second light-emitting substructure 1321b), and the second isolation opening 12c-2 includes two second sub-isolation openings 12c1-2.

[0121] Optionally, as shown in Figure 17E, the light-emitting structure 132 (second light-emitting structure 132b) of the second light-emitting device 13b includes four light-emitting substructures 1321 (second light-emitting substructures 1321b), and the second isolation opening 12c-2 includes four second sub-isolation openings 12c1-2. This allows for a greater number of second light-emitting substructures 1321b. When one of the second light-emitting substructures 1321b fails, the remaining second light-emitting substructures 1321b have a larger light-emitting area, resulting in a better display effect.

[0122] Optionally, the centroid line connecting the orthographic projections of the four second sub-isolation openings 12c1-2 onto the array substrate 11 is a quadrilateral. That is, the centroid line connecting the orthographic projections of the four second light-emitting substructures 1321b onto the array substrate 11 is a quadrilateral. For example, the quadrilateral can be a trapezoid, rectangle, rhombus, square, etc. Optionally, the centroid line connecting the orthographic projections of the four second sub-isolation openings 12c1-2 onto the array substrate 11 is a regular quadrilateral. That is, the centroid line connecting the orthographic projections of the four second light-emitting substructures 1321b onto the array substrate 11 is a regular quadrilateral. In this way, the arrangement of the second light-emitting substructures 1321b can be more regular. When one second light-emitting substructure 1321b fails, the other three second light-emitting substructures 1321b can emit light normally, and the display effect of the other three second light-emitting substructures 1321b is less different from the display effect of the four second light-emitting substructures 1321b under normal conditions.

[0123] In one embodiment, the light-emitting structure 132 of the first light-emitting device 13a includes a plurality of light-emitting substructures 1321, and the first isolation opening 12c-1 includes a plurality of first sub-isolation openings 12c1-1. That is, the green light-emitting structure 132 is divided into a plurality of light-emitting substructures 1321.

[0124] The inventors discovered through research that due to the influence of the manufacturing process sequence, the green light-emitting device 13 is prone to dark spot failure. By dividing the green light-emitting structure 132 into multiple light-emitting substructures 1321, when a certain light-emitting substructure 1321 experiences a dark spot failure, it will not affect other light-emitting substructures 1321, thereby effectively improving the problem of dark spot failure.

[0125] Optionally, the orthographic projection of the first sub-isolation opening 12c1-1 onto the array substrate 11 is a polygon. Here, the polygon can be a quadrilateral, pentagon, hexagon, heptagon, octagon, nonagon, etc.

[0126] Optionally, as shown in FIG17C, the light-emitting structure 132 (first light-emitting structure 132a) of the first light-emitting device 13a includes two light-emitting substructures 1321 (first light-emitting substructure 1321a), and the first isolation opening 12c-1 includes two first sub-isolation openings 12c1-1.

[0127] Optionally, as shown in FIG17E, the light-emitting structure 132 (first light-emitting structure 132a) of the first light-emitting device 13a includes four light-emitting substructures 1321 (first light-emitting substructure 1321a), and the first isolation opening 12c-1 includes four first sub-isolation openings 12c1-1.

[0128] In this way, the number of first light-emitting substructures 1321a can be increased. When one of the first light-emitting substructures 1321a fails, the remaining first light-emitting substructures 1321a have a larger light-emitting area and a better display effect.

[0129] Optionally, the centroid line connecting the orthographic projections of the four first sub-isolation openings 12c1-1 onto the array substrate 11 is a quadrilateral. That is, the centroid line connecting the orthographic projections of the four first light-emitting substructures 1321a onto the array substrate 11 is a quadrilateral. For example, the quadrilateral can be a trapezoid, rectangle, rhombus, square, etc. Optionally, the centroid line connecting the orthographic projections of the four first sub-isolation openings 12c1-1 onto the array substrate 11 is a regular quadrilateral. That is, the centroid line connecting the orthographic projections of the four first light-emitting substructures 1321a onto the array substrate 11 is a regular quadrilateral. In this way, the arrangement of the first light-emitting substructures 1321a can be more regular. When one first light-emitting substructure 1321a fails, the other three first light-emitting substructures 1321a can emit light normally, and the display effect of the other three first light-emitting substructures 1321a is less different from the display effect of the four first light-emitting substructures 1321a under normal conditions.

[0130] In one embodiment, the light-emitting structure 132 of the third light-emitting device 13c includes multiple light-emitting substructures 1321, and the third isolation opening 12c-3 includes multiple third sub-isolation openings 12c1-3. That is, the blue light-emitting structure 132 is divided into multiple light-emitting substructures 1321. This helps to improve the display defects of the blue light-emitting device 13.

[0131] Optionally, the orthographic projection of the third sub-isolation opening 12c1-3 onto the array substrate 11 is a polygon. Here, the polygon can be a quadrilateral, pentagon, hexagon, heptagon, octagon, nonagon, etc.

[0132] Optionally, as shown in Figure 17D, the light-emitting structure 132 (third light-emitting structure 132c) of the third light-emitting device 13c includes two light-emitting substructures 1321 (third light-emitting substructures 1321c), and the third isolation opening 12c-3 includes two third sub-isolation openings 12c1-3. It should be noted that the blue light-emitting structure 132 has a relatively low lifespan. Dividing the blue light-emitting structure 132 into two light-emitting substructures 1321 can both improve the display defect problem and extend the lifespan of the blue light-emitting structure 132.

[0133] Optionally, as shown in Figures 17E and 17F, the light-emitting structure 132 (third light-emitting structure 132c) of the third light-emitting device 13c includes four light-emitting substructures 1321 (third light-emitting substructures 1321c), and the third isolation opening 12c-3 includes four third sub-isolation openings 12c1-3. This allows for a more regular arrangement of the third light-emitting substructures 1321c. When one of the third light-emitting substructures 1321c fails, the other three third light-emitting substructures 1321c can still emit light normally, and the display effect of the other three third light-emitting substructures 1321c is less different from the display effect of the four third light-emitting substructures 1321c under normal conditions.

[0134] Optionally, the centroid line connecting the orthographic projections of the four third sub-isolation openings 12c1-3 onto the array substrate 11 is a quadrilateral. That is, the centroid line connecting the orthographic projections of the four third light-emitting structures 1321c onto the array substrate 11 is a quadrilateral. For example, the quadrilateral can be a trapezoid, rectangle, rhombus, square, etc. Optionally, the centroid line connecting the orthographic projections of the four third sub-isolation openings 12c1-3 onto the array substrate 11 is a regular quadrilateral. That is, the centroid line connecting the orthographic projections of the four third light-emitting structures 1321c onto the array substrate 11 is a regular quadrilateral.

[0135] Referring to Figures 1-36, an embodiment of this application provides a display panel 10, which includes an array substrate 11 and a plurality of light-emitting unit groups 17 disposed on the array substrate 11.

[0136] Specifically, as shown in Figures 15 and 16, the light-emitting unit group 17 includes multiple light-emitting structures 132, which include multiple first light-emitting structures 132a, multiple second light-emitting structures 132b, and multiple third light-emitting structures 132c. The centroids of the multiple second light-emitting structures 132b and the multiple third light-emitting structures 132c form a first virtual polygon N4, and at least one first light-emitting structure 132a is located within the first virtual polygon N4. The first light-emitting structures 132a, second light-emitting structures 132b, and third light-emitting structures 132c emit light of different colors. For example, one of the first light-emitting structures 132a, second light-emitting structures 132b, and third light-emitting structures 132c emits red light, another emits blue light, and yet another emits green light.

[0137] In the same light-emitting unit group 17, at least one light-emitting structure 132 includes a plurality of light-emitting substructures 1321 arranged at intervals, and the plurality of light-emitting substructures 1321 are electrically connected to the same driving circuit in the array substrate 11.

[0138] The display panel 10 provided in this application embodiment includes at least one light-emitting structure 132 comprising multiple substructures, and these multiple light-emitting substructures 1321 are electrically connected to the same driving circuit. In this way, when one light-emitting substructure 1321 fails (such as dark spot failure due to particle residue, encapsulation failure, etc.), it will not affect other light-emitting substructures 1321, and the other light-emitting substructures 1321 can still emit light normally, thereby reducing the risk of display defects in the display panel 10.

[0139] The first light-emitting device 13a includes a first electrode 131, a first light-emitting structure 132a, and a second electrode 133 stacked together; the second light-emitting device 13b includes a first electrode 131, a second light-emitting structure 132b, and a second electrode 133 stacked together; and the third light-emitting device 13c includes a first electrode 131, a third light-emitting structure 132c, and a second electrode 133 stacked together. The first electrode 131 can be an anode, and the second electrode 133 can be a cathode.

[0140] In one embodiment, the display panel 10 further includes an isolation layer 12 disposed on the array substrate 11. The isolation layer 12 includes an isolation structure 12a and a plurality of opening groups 12e. The opening group 12e includes a plurality of isolation openings 12c. The plurality of isolation openings 12c includes a plurality of first isolation openings 12c-1, a plurality of second isolation openings 12c-2, and a plurality of third isolation openings 12c-3. A plurality of first light-emitting structures 132a correspond one-to-one with a plurality of first isolation openings 12c-1, a plurality of second light-emitting structures 132b correspond one-to-one with a plurality of second isolation openings 12c-2, and a plurality of third light-emitting structures 132c correspond one-to-one with a plurality of third isolation openings 12c-3. At least a portion of the light-emitting structure 132 is disposed within the corresponding isolation opening 12c. The isolation layer 12 also includes a partition wall 12b located between adjacent light-emitting substructures 1321.

[0141] Optionally, the second electrode 133 of the light-emitting device 13 is electrically connected to the isolation structure 12a.

[0142] In one embodiment, within the same light-emitting unit group 17, at least one color light-emitting structure 132 includes a plurality of light-emitting substructures 1321 spaced apart. This effectively divides the light-emitting structure 132 of the same color into multiple light-emitting substructures 1321, which helps maintain consistency among the light-emitting structures 132 of the same color and improves display uniformity.

[0143] Optionally, in the same light-emitting unit group 17, at least two color light-emitting structures 132 include multiple light-emitting substructures 1321 arranged at intervals. Thus, compared to the method of "separating" the light-emitting structure 132 of one color, the "separating" design of the light-emitting structures 132 of two colors in this embodiment can enable both color light-emitting structures 132 to overcome display defects caused by failures (such as dark spot failures caused by particle residue, encapsulation failures, etc.), further reducing the risk of display defects.

[0144] Optionally, in the same light-emitting unit group 17, each light-emitting structure 132 includes a plurality of light-emitting substructures 1321 arranged at intervals. In this way, the light-emitting structures 132 of the three colors are designed to be "separated", which can enable the light-emitting structures 132 of the three colors to overcome display problems caused by failure (such as dark spot failure caused by particle residue, encapsulation failure, etc.), and further reduce the risk of display failure.

[0145] In one embodiment, within the same light-emitting structure 132, the adjacent edges of two adjacent light-emitting substructures 1321 are straight edges and parallel to each other. This allows the light-emitting substructures 1321 to have a more regular shape, while minimizing the space between them. Furthermore, with a fixed spacing between the two light-emitting substructures 1321, the space between them can be maximized, thereby increasing the area occupied by the light-emitting substructures 1321 and consequently improving the aperture ratio.

[0146] Optionally, as shown in FIG1, the array substrate 11 includes a plurality of scan lines 11b arranged at intervals along the second direction Y, and each scan line 11b extends along a first direction X intersecting the second direction Y; the light-emitting substructure 1321 includes at least one straight edge parallel to the second direction Y.

[0147] It should be noted that, in some embodiments, the second electrode 133 needs to overlap with the isolation layer 12 (such as the isolation structure 12a or the partition wall 12b) to achieve electrical connection between the second electrode 133 and the isolation layer 12. Furthermore, during the vapor deposition of the second electrode 133, the vapor deposition source scans along the first direction X, making it easier for the vapor deposition material to be deposited onto a portion of the sidewall of the isolation layer 12 (the sidewall parallel to the second direction Y), thereby ensuring good overlap performance between the second electrode 133 and the isolation layer 12.

[0148] Optionally, each light-emitting structure 132 includes at least one straight edge parallel to the second direction Y.

[0149] In one embodiment, the areas of each light-emitting substructure 1321 in the same light-emitting structure 132 are equal. This helps to improve the uniformity of light emission. Optionally, the shapes of each light-emitting substructure 1321 in the same light-emitting structure 132 are identical. This not only further improves the uniformity of light emission but also helps to reduce color deviation at a large viewing angle.

[0150] Optionally, within the same light-emitting structure 132, any two adjacent light-emitting substructures 1321 are arranged axially symmetrically. This not only further improves the uniformity of light emission but also helps to reduce angular deviation at a wide viewing angle. For example, two adjacent light-emitting substructures 1321 can be arranged symmetrically about the centerline of the partition wall 12b between them.

[0151] Optionally, within the same light-emitting structure 132, any two adjacent light-emitting substructures 1321 are arranged in a centrally symmetrical manner. This not only further improves the uniformity of light emission but also helps to reduce color deviation at a large viewing angle. For example, two adjacent light-emitting substructures 1321 can be centrally symmetrical about the centroid of the partition wall 12b between them.

[0152] In one embodiment, the areas of at least two light-emitting substructures 1321 of at least one light-emitting structure 132 are not equal. This allows designers to specially design the arrangement of the light-emitting substructures 1321 according to actual needs, thereby improving the display effect.

[0153] Optionally, as shown in FIG13, the array substrate 11 further includes a first trace 11d. Among the at least two light-emitting substructures 1321, the orthographic projection of at least one light-emitting substructure 1321 on the array substrate 11 overlaps with the orthographic projection of the first trace 11d on the array substrate 11, and the orthographic projection of at least one light-emitting substructure 1321 on the array substrate 11 does not overlap with the orthographic projection of the first trace 11d on the array substrate 11.

[0154] Optionally, the orthographic projection of at least one light-emitting substructure 1321 on the array substrate 11 overlaps with the orthographic projection of the first trace 11d on the array substrate 11, and the overlapping projections are symmetrically arranged about the center line of the orthographic projection of at least one light-emitting substructure 1321 on the array substrate 11. This is equivalent to differentiating the separation of the light-emitting structure 132 based on the overlap between the light-emitting structure 132 and the first trace 11d (e.g., overlapping or non-overlapping), which is beneficial for designers to differentiate the area of ​​the light-emitting substructure 1321 according to the overlap between the light-emitting substructure 1321 and the first trace 11d. It is understood that traces in the array substrate 11 are prone to reflection, and when the first trace 11d is located below the light-emitting substructure 1321, it can easily affect the light-emitting effect of the light-emitting substructure 1321. Therefore, when the first trace 11d overlaps with the light-emitting structure 132, designers need to perform some special design to reduce the impact of the first trace 11d on the light-emitting effect. Understandably, the aforementioned differentiated design helps to reduce the impact of the first trace 11d on the luminous effect.

[0155] In one embodiment, referring to FIG3, the first electrode 131 corresponding to the light-emitting structure 132, which includes multiple light-emitting substructures 1321, includes multiple sub-electrodes 1313; the sub-electrodes 1313 are connected to the light-emitting substructures 1321 in a one-to-one correspondence. Further, referring to FIG25B, adjacent sub-electrodes 1313 within the same first electrode 131 are connected by connecting lines 1314. Thus, when a short-circuit defect occurs in one sub-electrode 1313, the connecting line 1314 can be burned off by a laser, thereby ensuring that other sub-electrodes 1313 can function normally, which helps to improve display defects caused by short circuits.

[0156] Optionally, as shown in Figures 25B, 26B, 27, 28, 31, 33, 34, and 36, the display panel 10 further includes a plurality of conductive structures 11c corresponding to the plurality of first electrodes 131. Each first electrode 131 is electrically connected to a corresponding driving circuit through at least one conductive structure 11c. For example, the conductive structure 11c may be a via structure. It should be noted that the conductive structure 11c is connected to the protrusion 1312 of the first electrode 131. Specifically, each sub-electrode 1313 of the first electrode 131 is connected to the protrusion 1312, and the protrusion 1312 is connected to the conductive structure 11c, thereby electrically connecting each sub-electrode 1313 to the corresponding driving circuit.

[0157] In one embodiment, as shown in Figures 25B, 26B, 27, and 28, at least one light-emitting structure 132 includes two light-emitting substructures 1321. The first electrode 131 corresponding to the light-emitting structure 132 includes two sub-electrodes 1313, and the two sub-electrodes 1313 are connected by a connecting line 1314. It should be noted that the light-emitting structure 132 here can be a first light-emitting structure 132a, a second light-emitting structure 132b, or a third light-emitting structure 132c. In one example, as shown in Figures 26B and 28, a conductive structure 11c is located between the two sub-electrodes 1313 and is connected to the connecting line 1314. Further, each sub-electrode 1313 is connected to the conductive structure 11c via a connecting line 1314. In another example, as shown in Figures 25B and 27, the conductive structure 11c is connected to the side of one sub-electrode 1313 facing away from the other sub-electrode 1313. Further, the two sub-electrodes 1313 are connected by a connecting line 1314. Optionally, as shown in Figures 25A and 25B, at least a portion of the orthographic projection of the connecting line 1314 on the array substrate 11 lies within the orthographic projection of the partition wall 12b on the array substrate 11.

[0158] In one embodiment, as shown in Figures 31, 33, 34, and 36, at least one light-emitting structure 132 includes four light-emitting substructures 1321. The first electrode 131 corresponding to the light-emitting structure 132 includes four sub-electrodes 1313, and each sub-electrode 1313 is directly connected to at least one connecting line 1314. It should be noted that the light-emitting structure 132 here can be a first light-emitting structure 132a, a second light-emitting structure 132b, or a third light-emitting structure 132c. Optionally, the centroid line connecting the four sub-electrodes 1313 is a third virtual quadrilateral N3. The third virtual quadrilateral N3 can be a square, rectangle, rhombus, trapezoid, etc. Optionally, the conductive structure 11c electrically connects the four sub-electrodes 1313 to the corresponding driving circuit.

[0159] Optionally, as shown in Figure 31, the conductive structure 11c is located within the third virtual quadrilateral N3, and each sub-electrode 1313 is connected to the conductive structure 11c via a connecting line 1314. Specifically, each sub-electrode 1313 is connected to the same protrusion 1312 via a connecting line 1314, and the protrusion 1312 is connected to the conductive structure 11c. Thus, if any sub-electrode 1313 experiences a short-circuit defect, the connecting line 1314 between the sub-electrode 1313 and the protrusion 1312 can be burned out, allowing the other three light-emitting sub-structures 1321 to emit light normally.

[0160] Optionally, as shown in Figure 33, the third virtual quadrilateral N3 has a first corner N3-1, a second corner N3-2, a third corner N3-3, and a fourth corner N3-4. The conductive structure 11c is located outside the third virtual quadrilateral N3 and is connected to the sub-electrode 1313 located at the first corner N3-1. A connecting line 1314 connects the sub-electrode 1313 located at the first corner N3-1 and the sub-electrode 1313 located at the second corner N3-2. A connecting line 1314 connects the sub-electrode 1313 located at the second corner N3-2 and the sub-electrode 1313 located at the third corner N3-3. A connecting line 1314 connects the sub-electrode 1313 located at the third corner N3-3 and the sub-electrode 1313 located at the fourth corner N3-4. Thus, if a short circuit occurs in the sub-electrode 1313 located at the fourth corner N3-4, the connecting line 1314 between the sub-electrode 1313 at the fourth corner N3-4 and the sub-electrode 1313 located at the third corner N3-3 will be burned out, and the sub-electrodes 1313 at the first corner N3-1, the second corner N3-2, and the third corner N3-3 will all function normally. If a short circuit occurs in the sub-electrode 1313 located at the third corner N3-3, the connecting line 1314 between the sub-electrode 1313 at the third corner N3-3 and the sub-electrode 1313 located at the second corner N3-2 will be burned out, and the sub-electrodes 1313 at the first corner N3-1 and the second corner N3-2 will all function normally. If a short circuit defect occurs in the sub-electrode 1313 located at the second corner N3-2, then the connecting line 1314 between the sub-electrode 1313 located at the first corner N3-1 and the sub-electrode 1313 located at the second corner N3-2 will be burned out, and the sub-electrode 1313 located at the first corner N3-1 can work normally.

[0161] Optionally, as shown in Figure 34, the third virtual quadrilateral N3 has a first corner N3-1, a second corner N3-2, a third corner N3-3, and a fourth corner N3-4. A conductive structure 11c is located outside the third virtual quadrilateral N3. Sub-electrodes 1313 located at the first corner N3-1 and at the fourth corner N3-4 are each connected to a conductive structure 11c. A connecting line 1314 connects the sub-electrodes 1313 located at the first corner N3-1 and the second corner N3-2, and also connects the sub-electrodes 1313 located at the third corner N3-3 and the fourth corner N3-4.

[0162] In one example, no connecting line 1314 is provided between the sub-electrode 1313 located at the second corner N3-2 and the sub-electrode 1313 located at the third corner N3-3. Therefore, if a short circuit occurs in the sub-electrode 1313 located at the second corner N3-2, the connecting line 1314 between the sub-electrode 1313 located at the second corner N3-2 and the sub-electrode 1313 located at the first corner N3-1 will be burned out, and the sub-electrodes 1313 located at the first corner N3-1, the fourth corner N3-4, and the third corner N3-3 will all function normally. Similarly, if a short circuit occurs in the sub-electrode 1313 located at the third corner N3-3, the connecting line 1314 between the sub-electrode 1313 located at the third corner N3-3 and the sub-electrode 1313 located at the fourth corner N3-4 will be burned out, and the sub-electrodes 1313 located at the first corner N3-1, the second corner N3-2, and the third corner N3-3 will all function normally. If a short circuit occurs in the sub-electrode 1313 located at the first corner N3-1, then the sub-electrode 1313 located at the first corner N3-1 and the protrusion 1312 connected to it will be burned off, and the sub-electrodes 1313 located at the third corner N3-3 and the fourth corner N3-4 will both work normally. If a short circuit occurs in the sub-electrode 1313 located at the fourth corner N3-4, then the sub-electrode 1313 located at the fourth corner N3-4 and the protrusion 1312 connected to it will be burned off, and the sub-electrodes 1313 located at the first corner N3-1 and the second corner N3-2 will both work normally.

[0163] In one example, as shown in Figure 34, a connecting line 1314 connects the sub-electrode 1313 located at the second corner N3-2 and the sub-electrode 1313 located at the third corner N3-3. If a short circuit defect occurs in the sub-electrode 1313 located at the second corner N3-2, the connecting line 1314 between the sub-electrode 1313 located at the second corner N3-2 and the sub-electrode 1313 located at the first corner N3-1 is burned out, and the connecting line 1314 between the sub-electrode 1313 located at the second corner N3-2 and the sub-electrode 1313 located at the third corner N3-3 is also burned out. The sub-electrodes 1313 located at the first corner N3-1, the fourth corner N3-4, and the third corner N3-3 can all work normally. If a short circuit occurs in the sub-electrode 1313 located at the third corner N3-3, then the connecting line 1314 between the sub-electrode 1313 located at the third corner N3-3 and the sub-electrode 1313 located at the fourth corner N3-4 is burned out, and the connecting line 1314 between the sub-electrode 1313 located at the third corner N3-3 and the sub-electrode 1313 located at the second corner N3-2 is also burned out. The sub-electrodes 1313 located at the first corner N3-1, the second corner N3-2, and the third corner N3-3 can then function normally. If a short circuit occurs in the sub-electrode 1313 located at the first corner N3-1, then the sub-electrode 1313 located at the first corner N3-1 and the protrusion 1312 connected to it are burned out, and the connecting line 1314 between the sub-electrode 1313 located at the first corner N3-1 and the sub-electrode 1313 located at the second corner N3-2 is also burned out. The sub-electrodes 1313 located at the third corner N3-3 and the fourth corner N3-4 can then function normally. If the sub-electrode 1313 located at the fourth corner N3-4 is short-circuited, then the sub-electrode 1313 located at the fourth corner N3-4 and the protrusion 1312 connected to it will be burned off, and the connecting line 1314 between the sub-electrode 1313 located at the fourth corner N3-4 and the sub-electrode 1313 located at the third corner N3-3 will be burned off. The sub-electrodes 1313 located at the first corner N3-1 and the second corner N3-2 can work normally.

[0164] Optionally, as shown in Figure 36, the third virtual quadrilateral N3 has a first corner N3-1, a second corner N3-2, a third corner N3-3, and a fourth corner N3-4. A protrusion 1312 is provided between the sub-electrode 1313 located at the first corner N3-1 and the sub-electrode 1313 located at the fourth corner N3-4. Both the sub-electrode 1313 at the first corner N3-1 and the sub-electrode 1313 at the fourth corner N3-4 are connected to the protrusion 1312, thereby connecting to the conductive structure 11c, and the conductive structure 11c is located between the two sub-electrodes 1313. A connecting line 1314 connects the sub-electrode 1313 located at the first corner N3-1 and the sub-electrode 1313 located at the second corner N3-2, and a connecting line 1314 connects the sub-electrode 1313 located at the third corner N3-3 and the sub-electrode 1313 located at the fourth corner N3-4. If a short circuit occurs in the sub-electrode 1313 located at the second corner N3-2, then the connecting line 1314 between the sub-electrode 1313 located at the second corner N3-2 and the sub-electrode 1313 located at the first corner N3-1 will be burned out, and the sub-electrodes 1313 located at the first corner N3-1, the fourth corner N3-4, and the third corner N3-3 will all function normally. If a short circuit occurs in the sub-electrode 1313 located at the third corner N3-3, then the connecting line 1314 between the sub-electrode 1313 located at the third corner N3-3 and the sub-electrode 1313 located at the fourth corner N3-4 will be burned out, and the sub-electrodes 1313 located at the first corner N3-1, the second corner N3-2, and the third corner N3-3 will all function normally. If a short circuit occurs in the sub-electrode 1313 located at the first corner N3-1, then the sub-electrode 1313 located at the first corner N3-1 and the protrusion 1312 connected to it will be burned off, and the sub-electrodes 1313 located at the third corner N3-3 and the fourth corner N3-4 will both work normally. If a short circuit occurs in the sub-electrode 1313 located at the fourth corner N3-4, then the sub-electrode 1313 located at the fourth corner N3-4 and the protrusion 1312 connected to it will be burned off, and the sub-electrodes 1313 located at the first corner N3-1 and the second corner N3-2 will both work normally.

[0165] In one embodiment, the orthographic projection of the metal layer in the array substrate 11 does not overlap with at least a partial orthographic projection of the connecting line 1314. It should be noted that during the burning-off process of the connecting line 1314, the laser can also irradiate the connecting line 1314 from the back of the display panel 10, thereby burning off the connecting line 1314. Understandably, in this case, the metal film layer in the array substrate 11 should not overlap with the laser irradiation area of ​​the connecting line 1314 to prevent blocking the laser.

[0166] In one embodiment, the isolation structure 12a is provided with a through hole 12d corresponding to the connecting line 1314. Specifically, the orthographic projection of the hole wall of the through hole 12d on the array substrate 11 overlaps with the orthographic projection of the corresponding connecting line 1314 on the substrate. Thus, the connecting line 1314 can be directly illuminated from the front of the display panel 10 through the through hole 12d. It should be noted that the through hole 12d can also be reused as a light-transmitting hole to increase the light transmittance of the display panel 10.

[0167] In one example, referring to Figures 25A and 25B, a through hole 12d is provided between two sub-isolation openings 12c1. In one example, referring to Figures 26A and 26B, a corresponding through hole 12d is provided on the outer side of each sub-isolation opening 12c1. In one example, referring to Figures 30 and 31, four through holes 12d are provided between four sub-isolation openings 12c1, and each through hole 12d corresponds to one sub-isolation opening 12c1. In one example, referring to Figures 32 and 33, a through hole 12d is provided between the sub-isolation opening 12c1 located at the first corner N3-1 and the sub-isolation opening 12c1 located at the second corner N3-2, a through hole 12d is provided between the sub-isolation opening 12c1 located at the second corner N3-2 and the sub-isolation opening 12c1 located at the third corner N3-3, and a through hole 12d is provided between the sub-isolation opening 12c1 located at the third corner N3-3 and the sub-isolation opening 12c1 located at the fourth corner N3-4. In one example, as shown in Figures 35 and 36, a through hole 12d is provided between the sub-isolation opening 12c1 located at the first corner N3-1 and the sub-isolation opening 12c1 located at the second corner N3-2; a through hole 12d is provided between the sub-isolation opening 12c1 located at the second corner N3-2 and the sub-isolation opening 12c1 located at the third corner N3-3; a through hole 12d is provided between the sub-isolation opening 12c1 located at the third corner N3-3 and the sub-isolation opening 12c1 located at the fourth corner N3-4; and two through holes 12d are provided between the sub-isolation opening 12c1 located at the first corner N3-1 and the sub-isolation opening 12c1 located at the fourth corner N3-4.

[0168] In one embodiment, as shown in FIG9, the orthographic projection of the first electrode 131 corresponding to the light-emitting structure 132, which includes multiple light-emitting substructures 1321, onto the array substrate 11 covers the orthographic projection of the light-emitting substructure 1321 corresponding to the light-emitting structure 132 onto the array substrate 11 and the orthographic projection of the partition wall 12b corresponding to the light-emitting structure 132 onto the array substrate 11. That is, the first electrode 131 is a complete block structure. This is beneficial to increasing the area of ​​the first electrode 131 and reducing the resistance of the first electrode 131.

[0169] Optionally, as shown in FIG8, the first electrode 131 corresponding to the first light-emitting structure 132a includes a first main body portion 1311a, and the orthographic projection of each first light-emitting substructure 1321a of the first light-emitting structure 132a on the array substrate 11 is located within the orthographic projection of the first main body portion 1311a on the array substrate 11. Exemplarily, the shape of the first main body portion 1311a can be a regular block shape.

[0170] Optionally, the first main body 1311a is electrically connected to the driving circuit in the array substrate 11 via a conductive structure 11c. It is understood that the array substrate 11 is provided with multiple first driving circuits 11a, multiple second driving circuits, and multiple third driving circuits. The first electrode 131 of the first light-emitting device 13a is electrically connected to the first driving circuit 11a, the first electrode 131 of the second light-emitting device 13b is electrically connected to the second driving circuit, and the first electrode 131 of the third light-emitting device 13c is electrically connected to the third driving circuit.

[0171] Optionally, the first electrode 131 further includes a first protrusion 1312a connected to the first main body portion 1311a. The first protrusion 1312a is electrically connected to the driving circuit in the array substrate 11 through a conductive structure 11c. In this way, the orthographic projection of the conductive structure 11c connected to the first protrusion 1312a on the array substrate 11 is outside the orthographic projection of the first light-emitting structure 132a on the array substrate 11, thus avoiding any adverse effect of the conductive structure 11c on the light emission of the first light-emitting structure 132a.

[0172] Optionally, as shown in FIG9, the orthographic projection of the first protrusion 1312a on the array substrate 11 is located within the orthographic projection of the isolation structure 12a on the array substrate 11.

[0173] In one embodiment, as shown in Figures 3, 4, and 5, the isolation structure 12a includes a conductive portion 121 and a blocking portion 122 stacked along a direction away from the array substrate 11. The orthographic projection of the conductive portion 121 on the array substrate 11 lies within the orthographic projection of the blocking portion 122 on the array substrate 11. At least a portion of the second electrodes 133 are in contact with the conductive portion 121. In this way, the isolation structure 12a can serve as a trace to connect the second electrodes 133 to the driving circuit, thereby optimizing the trace layout within the display area of ​​the display panel 10.

[0174] Optionally, the second electrode 133 corresponding to the light-emitting structure 132, which includes multiple light-emitting substructures 1321, includes multiple sub-electrode portions 1331 corresponding one-to-one with the multiple light-emitting substructures 1321, and each sub-electrode portion 1331 is in contact with the conductive portion 121. Thus, each sub-electrode portion 1331 is electrically connected to the isolation structure 12a, preventing damage to one sub-electrode portion 1331 from affecting other sub-electrode portions 1331, thereby improving the light-emitting reliability of the display panel 10. Optionally, at least a portion of the outer edge of each sub-electrode portion 1331 covers the sidewall of the conductive portion 121 near the isolation opening 12c. This allows for a larger contact area between the sub-electrode portion 1331 and the conductive portion 121, reducing electrical connection resistance. Optionally, in the same light-emitting device 13, the maximum distance between the outer edge of each sub-electrode portion 1331 and the array substrate 11 is equal. In other words, the overlap height of each sub-electrode portion 1331 on the conductive portion 121 is consistent. It should be emphasized here that, due to the influence of the manufacturing process, "approximately equal" can also be considered as equal. The above arrangement helps to keep the electrical connection resistance between each sub-electrode 1331 and the conductive part 121 consistent, which helps to improve the uniformity of light emission.

[0175] Optionally, the display panel 10 further includes a plurality of first encapsulation portions 14a, which are correspondingly disposed with a plurality of first light-emitting structures 132a. The first encapsulation portions 14a are located on the side of the corresponding first light-emitting structure 132a away from the array substrate 11. For example, the first encapsulation portion 14a can be an inorganic film layer. Optionally, as shown in FIG2, the orthographic projection of the first encapsulation portion 14a on the array substrate 11 covers the orthographic projection of the plurality of first light-emitting substructures 1321a corresponding to the first light-emitting structure 132a on the array substrate 11 and the orthographic projection of the partition wall 12b corresponding to the first light-emitting structure 132a on the array substrate 11. That is, the first encapsulation portion 14a is a continuous film layer structure. In this way, the contact area between the first encapsulation portion 14a and other film layers in the display panel 10 can be larger, improving the connection stability of the first encapsulation portion 14a and enhancing the encapsulation reliability.

[0176] Optionally, a layer of light-emitting material 161 and an electrode material layer 162 are further stacked between the partition wall 12b between two adjacent first light-emitting substructures 1321a and the first encapsulation portion 14a. In one embodiment, the first encapsulation portion 14a includes a plurality of first sub-encapsulation portions 141a spaced apart, with each of the first sub-encapsulation portions 141a corresponding to a plurality of first light-emitting substructures 1321a. The first sub-encapsulation portions 141a are located on the side of the corresponding first light-emitting substructure 1321a away from the array substrate 11. This is equivalent to encapsulating each light-emitting substructure 1321 individually. Thus, if one first sub-encapsulation portion 141a fails to encapsulate, it will not affect the encapsulation performance of other first sub-encapsulation portions 141a, ensuring that other light-emitting substructures 1321 can emit light normally, reducing the risk of display defects in the display panel 10.

[0177] In one embodiment, the display panel 10 further includes a plurality of second encapsulation portions 14b, which are correspondingly disposed with a plurality of second light-emitting structures 132b. The second encapsulation portions 14b are located on the side of the corresponding second light-emitting structure 132b away from the array substrate 11. Exemplarily, the second encapsulation portions 14b can be inorganic film layers. In one embodiment, the orthographic projection of the second encapsulation portions 14b onto the array substrate 11 covers the orthographic projections of the plurality of second light-emitting substructures 1321b corresponding to the second light-emitting structure 132b onto the array substrate 11, as well as the orthographic projections of the partition walls 12b corresponding to the second light-emitting structure 132b onto the array substrate 11. That is, the second encapsulation portions 14b are continuous film layer structures. This allows for a larger contact area between the second encapsulation portions 14b and other film layers in the display panel 10, improving the connection stability of the second encapsulation portions 14b and enhancing encapsulation reliability.

[0178] Optionally, a layer of light-emitting material 161 and an electrode material layer 162 are further stacked between the partition wall 12b between two adjacent second light-emitting substructures 1321b and the second encapsulation portion 14b. In one embodiment, the second encapsulation portion 14b includes a plurality of second sub-encapsulation portions (not shown) spaced apart, with each of the second sub-encapsulation portions corresponding to a plurality of second light-emitting substructures 1321b. The second sub-encapsulation portions are located on the side of the corresponding second light-emitting substructure 1321b away from the array substrate 11. This is equivalent to individually encapsulating each second light-emitting substructure 1321b. Thus, if one second sub-encapsulation portion fails, it will not affect the encapsulation performance of other second sub-encapsulation portions, ensuring that all other second light-emitting substructures 1321b can emit light normally, reducing the risk of display defects in the display panel 10.

[0179] In one embodiment, the display panel 10 further includes a plurality of third encapsulation portions 14c, which are correspondingly disposed with a plurality of third light-emitting structures 132c. The third encapsulation portions 14c are located on the side of the corresponding third light-emitting structure 132c away from the array substrate 11. Exemplarily, the third encapsulation portions 14c can be inorganic film layers. In one embodiment, the orthographic projection of the third encapsulation portions 14c on the array substrate 11 covers the orthographic projections of the plurality of third light-emitting substructures 1321c corresponding to the third light-emitting structure 132c on the array substrate 11 and the orthographic projection of the partition wall 12b corresponding to the third light-emitting structure 132c on the array substrate 11. That is, the third encapsulation portions 14c are continuous film layer structures. This allows for a larger contact area between the third encapsulation portions 14c and other film layers in the display panel 10, improving the connection stability of the third encapsulation portions 14c and enhancing encapsulation reliability.

[0180] Optionally, a layer of light-emitting material 161 and an electrode material layer 162 are further stacked between the partition wall 12b between two adjacent third light-emitting substructures 1321c and the third encapsulation portion 14c. In one embodiment, the third encapsulation portion 14c includes a plurality of third sub-encapsulation portions (not shown) spaced apart, with each of the third sub-encapsulation portions corresponding to a plurality of third light-emitting substructures 1321c. The third sub-encapsulation portions are located on the side of the corresponding third light-emitting substructure 1321c away from the array substrate 11. This is equivalent to encapsulating each third light-emitting substructure 1321c individually. Thus, if one third sub-encapsulation portion fails, it will not affect the encapsulation performance of other third sub-encapsulation portions, ensuring that all other third light-emitting substructures 1321c can emit light normally, reducing the risk of display defects in the display panel 10.

[0181] In one embodiment, the light emitted by the first light-emitting structure 132a has a wavelength between 505nm and 545nm, meaning the first light-emitting device 13a is a green light-emitting device 13; the light emitted by the second light-emitting structure 132b has a wavelength between 600nm and 650nm, meaning the second light-emitting device 13b is a red light-emitting device 13; and the light emitted by the third light-emitting structure 132c has a wavelength between 440nm and 480nm, meaning the third light-emitting device 13c is a blue light-emitting device 13.

[0182] In the same light-emitting unit group 17, all second light-emitting structures 132b include multiple second light-emitting substructures 1321b. That is, the red light-emitting structure 132 is divided into multiple light-emitting substructures 1321. In one example, as shown in Figures 15 and 16, the number of second light-emitting substructures 1321b in the same second light-emitting structure 132b is equal to the number of second light-emitting structures 132b in the same light-emitting unit group 17, and both are 2. In another example, the number of second light-emitting substructures 1321b in the same second light-emitting structure 132b is an integer multiple of the number of third light-emitting structures 132c in the same light-emitting unit group 17. Specifically, as shown in Figure 17, the number of second light-emitting substructures 1321b in the same second light-emitting structure 132b is 1 times the number of third light-emitting structures 132c in the same light-emitting unit group 17. As shown in Figure 17E, the number of second light-emitting substructures 1321b in the same second light-emitting structure 132b is 2 times the number of third light-emitting structures 132c in the same light-emitting unit group 17. Optionally, as shown in Figures 17E and 17F, the number of second light-emitting substructures 1321b in the same second light-emitting structure 132b is twice the number of third light-emitting structures 132c in the same light-emitting unit group 17. Specifically, the number of second light-emitting substructures 1321b in the same second light-emitting structure 132b is 4, and the number of third light-emitting structures 132c in the same light-emitting unit group 17 is 2.

[0183] Optionally, the shape of the second light-emitting substructure 1321b is polygonal. For example, the shape of the second light-emitting substructure 1321b can be quadrilateral, pentagon, hexagon, heptagon, octagon, etc.

[0184] Optionally, as shown in FIG17A, the second light-emitting structure 132b includes two second light-emitting substructures 1321b. Optionally, as shown in FIG17E, the second light-emitting structure 132b includes four second light-emitting substructures 1321b. Optionally, as shown in FIG17E, the centroid line connecting the four second light-emitting substructures 1321b is a quadrilateral. Exemplarily, the centroid line connecting the four second light-emitting substructures 1321b is a square.

[0185] In one embodiment, within the same light-emitting unit group 17, all first light-emitting structures 132a include multiple first light-emitting substructures 1321a. Optionally, as shown in FIG17E, the number of first light-emitting substructures 1321a in the same first light-emitting structure 132a is equal to the number of first light-emitting structures 132a in the same light-emitting unit group 17, and both are 4.

[0186] Optionally, the shape of the first light-emitting substructure 1321a is polygonal. For example, the shape of the first light-emitting substructure 1321a can be quadrilateral, pentagon, hexagon, heptagon, octagon, etc.

[0187] Optionally, as shown in Figures 17C and 17D, the first light-emitting structure 132a includes two first light-emitting substructures 1321a.

[0188] In one embodiment, within the same light-emitting unit group 17, all third light-emitting structures 132c include multiple third light-emitting substructures 1321c. In one example, as shown in FIG17B, the number of third light-emitting substructures 1321c in the same third light-emitting structure 132c is equal to the number of third light-emitting structures 132c in the same light-emitting unit group 17, and both are 2.

[0189] In another example, the number of third light-emitting substructures 1321c in the same third light-emitting structure 132c is an integer multiple of the number of second light-emitting structures 132b in the same light-emitting unit group 17. Specifically, as shown in FIG17B, the number of third light-emitting substructures 1321c in the same third light-emitting structure 132c is one time the number of second light-emitting structures 132b in the same light-emitting unit group 17. As shown in FIG17E, the number of third light-emitting substructures 1321c in the same third light-emitting structure 132c is twice the number of second light-emitting structures 132b in the same light-emitting unit group 17. Optionally, as shown in FIG17E and FIG17F, the number of third light-emitting substructures 1321c in the same third light-emitting structure 132c is twice the number of second light-emitting structures 132b in the same light-emitting unit group 17. The number of third light-emitting substructures 1321c in the same third light-emitting structure 132c is 4, and the number of second light-emitting structures 132b in the same light-emitting unit group 17 is 2.

[0190] Optionally, the third light-emitting substructure 1321c has a polygonal shape. For example, the shape of the third light-emitting substructure 1321c can be a quadrilateral, pentagon, hexagon, heptagon, octagon, etc.

[0191] Optionally, as shown in Figure 17D, the third light-emitting structure 132c includes two third light-emitting substructures 1321c. Optionally, as shown in Figure 17E, the third light-emitting structure 132c includes four third light-emitting substructures 1321c. Optionally, the centroid line connecting the four third light-emitting substructures 1321c is a quadrilateral, such as a square.

[0192] In one embodiment, as shown in FIG17C, in the same light-emitting unit group 17, the number of first light-emitting substructures 1321a in the first light-emitting structure 132a is equal to the number of second light-emitting substructures 1321b in the second light-emitting structure 132b, and both are 2. Optionally, as shown in FIG17D, the number of first light-emitting substructures 1321a in the first light-emitting structure 132a is equal to the number of third light-emitting substructures 1321c in the third light-emitting structure 132c, and both are 2. Optionally, as shown in FIG17C, the number of first light-emitting substructures 1321a in the first light-emitting structure 132a is 2, and the number of second light-emitting substructures 1321b in the second light-emitting structure 132b is 2. Optionally, as shown in FIG17D, the number of first light-emitting substructures 1321a in the first light-emitting structure 132a is 2, the number of second light-emitting substructures 1321b in the second light-emitting structure 132b is 2, and the number of third light-emitting substructures 1321c in the third light-emitting structure 132c is 2. Optionally, as shown in Figure 17E, the number of first light-emitting substructures 1321a in the first light-emitting structure 132a is 4, the number of second light-emitting substructures 1321b in the second light-emitting structure 132b is 4, and the number of third light-emitting substructures 1321c in the third light-emitting structure 132c is 4. Optionally, as shown in Figure 17F, the number of first light-emitting substructures 1321a in the first light-emitting structure 132a is 2, the number of second light-emitting substructures 1321b in the second light-emitting structure 132b is 4, and the number of third light-emitting substructures 1321c in the third light-emitting structure 132c is 4.

[0193] In one embodiment, as shown in FIG16, the first virtual polygon N4 is a quadrilateral. Optionally, the first virtual polygon N4 includes a fifth side N4-1 and a seventh side N4-3 that are parallel to each other, and a sixth side N4-2 and an eighth side N4-4 that connect the fifth side N4-1 and the seventh side N4-3. Optionally, the length of the fifth side N4-1 is greater than the length of the seventh side N4-3.

[0194] Optionally, the centroids of multiple first light-emitting structures 132a are connected to form a second virtual polygon N5, and a second light-emitting structure 132b is located within the second virtual polygon N5.

[0195] Optionally, the second virtual polygon N5 is a quadrilateral. The second virtual polygon N5 includes a ninth side N5-1 and an eleventh side N5-3 that are parallel to each other, and a tenth side N5-2 and a twelfth side N5-4 that connect the ninth side N5-1 and the eleventh side N5-3. Optionally, the length of the ninth side N5-1 is greater than the length of the eleventh side N5-3.

[0196] Optionally, both the first virtual polygon N4 and the second virtual polygon N5 are trapezoids.

[0197] In one embodiment, as shown in Figure 6, the spacing between any two adjacent light-emitting structures 132 is the third spacing c. Within the same light-emitting structure 132, the spacing between any two adjacent light-emitting substructures 1321 is the fourth spacing d, and the third spacing c and the fourth spacing d are not equal. Thus, by making the third spacing c and the fourth spacing d unequal, designers can adaptively adjust the placement of the light-emitting structures 132 according to actual needs. For example, when the fourth spacing d is less than the third spacing c, it is beneficial to maximize the aperture ratio and minimize the loss of aperture ratio caused by the "separating light-emitting structures 132"; when the fourth spacing d is greater than the third spacing c, it is beneficial to set a conductive structure 11c for connecting the anode and the driving circuit in the area between adjacent light-emitting substructures 1321, thereby facilitating the designer to set the position of the conductive structure 11c according to actual needs and reducing the limitation imposed by the arrangement of the light-emitting structures 132 on the placement position of the conductive structure 11c.

[0198] Optionally, the fourth spacing d is smaller than the third spacing c. This allows for a more compact arrangement of the light-emitting substructures 1321 of the light-emitting structure 132, while simultaneously increasing the light-emitting area of ​​the substructures 1321. This maximizes the aperture ratio and minimizes the loss caused by the "separated light-emitting structure 132," ensuring optimal display performance. Optionally, the difference between the third spacing c and the fourth spacing d is greater than 0 μm and less than or equal to 16 μm. For example, this difference can be 0.1 μm, 1 μm, 3 μm, 5 μm, 8 μm, 12 μm, 14 μm, 16 μm, or any two of these values. By ensuring the difference between the first spacing a and the second spacing b falls within this range, it is beneficial to increase the aperture ratio and guarantee optimal display performance. Optionally, the third spacing c is greater than or equal to 10 μm and less than or equal to 20 μm. For example, the third spacing c can be 0.1μm, 2μm, 4μm, 6μm, 10μm, 12μm, or between any two of the above values. Keeping the third spacing c within this range helps to improve the aperture ratio and ensure display quality. Optionally, the fourth spacing d is greater than 0μm and less than or equal to 12μm. For example, the fourth spacing d can be 10μm, 13μm, 14μm, 16μm, 18μm, 20μm, or between any two of the above values. Keeping the difference in the fourth spacing d within this range helps to improve the aperture ratio and ensure display quality. As shown in Figure 10, the spacing between any two adjacent pixel apertures 15a is the third spacing c. Within the same pixel aperture 15a, the spacing between any two adjacent pixel sub-apertures is the fourth spacing d.

[0199] This application provides a display panel 10, including an array substrate 11 and a plurality of light-emitting unit groups 17 disposed on the array substrate 11.

[0200] Further, as shown in Figures 15 and 16, the light-emitting unit group 17 includes multiple light-emitting structures 132, which include multiple first light-emitting structures 132a, multiple second light-emitting structures 132b, and multiple third light-emitting structures 132c. The centroids of the multiple first light-emitting structures 132a and the multiple third light-emitting structures 132c form a first virtual polygon N4, and at least one second light-emitting structure 132b is located within the first virtual polygon N4. The light emitted by the first light-emitting structures 132a, second light-emitting structures 132b, and third light-emitting structures 132c are of different colors. In the same light-emitting unit group 17, at least one light-emitting structure 132 includes multiple light-emitting substructures 1321 arranged at intervals, and the multiple light-emitting substructures 1321 are electrically connected to the same driving circuit in the array substrate 11. As shown in Figure 6, the spacing between any two adjacent light-emitting structures 132 is the third spacing c, and the spacing between any two adjacent light-emitting substructures 1321 in the same light-emitting structure 132 is the fourth spacing d. The third spacing c and the fourth spacing d are not equal.

[0201] The display panel 10 provided in this application embodiment includes at least one light-emitting structure 132 comprising multiple substructures, and these multiple light-emitting substructures 1321 are electrically connected to the same driving circuit. This ensures that if one light-emitting substructure 1321 fails, it will not affect other light-emitting substructures 1321, which can still emit light normally, thereby reducing the risk of display defects in the display panel 10. Furthermore, by making the fourth spacing d and the third spacing c unequal, designers can adaptively adjust the placement of the light-emitting structures 132 according to actual needs. For example, when the fourth spacing d is smaller than the third spacing c, it is beneficial to maximize the aperture ratio and minimize the loss of aperture ratio caused by the "separating light-emitting structures 132"; when the fourth spacing d is larger than the third spacing c, it is beneficial to set via structures for connecting the anode and driving circuit in the area between adjacent light-emitting substructures 1321, thereby facilitating designers to set the position of the via structures according to actual needs and reducing the limitations imposed by the arrangement of the light-emitting structures 132 on the placement of the via structures.

[0202] This application provides a display device, including the display panel 10 in any of the foregoing embodiments.

[0203] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A display panel, comprising: Array substrate; An isolation layer is located on one side of the array substrate and includes an isolation structure and a plurality of isolation openings formed by the isolation structure. The plurality of isolation openings include a plurality of first isolation openings, a plurality of second isolation openings, and a plurality of third isolation openings. Multiple light-emitting devices, including multiple first light-emitting devices corresponding to the multiple first isolation openings, multiple second light-emitting devices corresponding to the multiple second isolation openings, and multiple third light-emitting devices corresponding to the multiple third isolation openings; The first light-emitting device, the second light-emitting device, and the third light-emitting device are configured to emit light of different colors; each light-emitting device includes a first electrode, a light-emitting structure, and a second electrode stacked together. Wherein, the light-emitting structure of at least one of the light-emitting devices includes a plurality of light-emitting substructures, the isolation layer includes a partition wall located between adjacent light-emitting substructures, and the orthographic projection of the first electrode of at least one of the light-emitting devices on the array substrate covers the orthographic projection of the partition wall corresponding to at least one of the light-emitting devices on the array substrate and the orthographic projection of the plurality of light-emitting substructures corresponding to at least one of the light-emitting devices on the array substrate.

2. The display panel according to claim 1, wherein, In the first light-emitting device, the second light-emitting device, and the third light-emitting device, the light-emitting structure of the light-emitting device of at least one color includes multiple light-emitting substructures; Alternatively, in the first light-emitting device, the second light-emitting device, and the third light-emitting device, the light-emitting structure of at least two of the light-emitting devices of different colors includes multiple light-emitting substructures; Alternatively, the light-emitting structure of each of the light-emitting devices may include multiple light-emitting substructures.

3. The display panel according to claim 1, wherein, The isolation opening corresponding to at least one of the light-emitting devices includes a plurality of sub-isolation openings, and a partition wall is provided between two adjacent sub-isolation openings; the plurality of sub-isolation openings correspond one-to-one with the plurality of light-emitting substructures; in the orthographic projection of the partition wall on the array substrate, the projection edge adjacent to one of the sub-isolation openings is parallel to the projection edge adjacent to the other sub-isolation opening. The array substrate includes multiple scan lines spaced apart along a second direction, and each scan line extends along a first direction intersecting the second direction; the orthographic projection of the sub-isolation opening on the array substrate includes at least one projection edge parallel to the second direction; The orthographic projection of each isolation opening on the array substrate includes at least one projection edge parallel to the second direction.

4. The display panel according to claim 1, wherein, The isolation opening corresponding to at least one of the light-emitting devices includes multiple sub-isolation openings, and a partition wall is provided between two adjacent sub-isolation openings; the multiple sub-isolation openings correspond one-to-one with the multiple light-emitting sub-structures; wherein... In the same isolation opening, the areas of the orthographic projections of each of the sub-isolation openings on the array substrate are all equal; Alternatively, within the same isolation opening, the orthographic projections of each of the sub-isolation openings on the array substrate have the same shape. Alternatively, within the same isolation opening, the orthographic projections of any two adjacent sub-isolation openings on the array substrate are arranged axially symmetrically; or, within the same isolation opening, the orthographic projections of any two adjacent sub-isolation openings on the array substrate are arranged centrally symmetrically.

5. The display panel according to claim 1, wherein, The isolation opening corresponding to at least one of the light-emitting devices includes multiple sub-isolation openings, and a partition wall is provided between two adjacent sub-isolation openings; the multiple sub-isolation openings correspond one-to-one with the multiple light-emitting substructures; in the same isolation opening, the areas of the orthographic projections of at least two sub-isolation openings on the array substrate are not equal; The array substrate further includes a first trace. Among the at least two sub-isolation openings, at least one sub-isolation opening has its orthographic projection on the array substrate overlapping with the orthographic projection of the first trace on the array substrate, and at least one sub-isolation opening has its orthographic projection on the array substrate not overlapping with the orthographic projection of the first trace on the array substrate. At least one of the sub-isolation openings has its orthographic projection on the array substrate overlapping with the orthographic projection of the first trace on the array substrate, and the overlapping projections are symmetrically arranged about the center line of the orthographic projection of the at least one sub-isolation opening on the array substrate.

6. The display panel according to claim 1, wherein, The minimum distance between two adjacent isolation openings is the first distance; The isolation opening corresponding to at least one of the light-emitting devices includes multiple sub-isolation openings, and a partition wall is provided between two adjacent sub-isolation openings; the multiple sub-isolation openings correspond one-to-one with the multiple light-emitting sub-structures; in the same isolation opening, the minimum distance between two adjacent sub-isolation openings is a second distance; wherein... The first spacing is not equal to the second spacing; Or the second spacing is smaller than the first spacing; Alternatively, the difference between the first spacing and the second spacing is greater than 0 μm and less than or equal to 16 μm.

7. The display panel according to claim 1, wherein, At least a portion of the second electrodes of the light-emitting devices are electrically connected to the insulating layer; Alternatively, both the isolation structure and the partition wall include conductive portions and blocking portions stacked along a direction away from the array substrate, wherein the orthographic projection of the conductive portion on the array substrate is located within the orthographic projection of the blocking portion on the array substrate; and at least a portion of the second electrodes of the light-emitting devices are in contact with the conductive portions. Alternatively, the second electrode of the at least one light-emitting device includes a plurality of sub-electrode portions corresponding one-to-one with the plurality of light-emitting substructures, each of the sub-electrode portions being in contact with the conductive portion; at least a portion of the outer edge of each of the sub-electrode portions covers the sidewall of the conductive portion near the isolation opening; in the same light-emitting device, the maximum distance between the outer edge of each of the sub-electrode portions and the array substrate is equal. Alternatively, the orthographic projection of the first electrode of the at least one light-emitting device on the array substrate covers the orthographic projection of the surface of the blocking portion of the partition wall corresponding to the at least one light-emitting device on the array substrate.

8. The display panel according to claim 1, wherein, The display panel further includes a plurality of encapsulation portions corresponding one-to-one with the plurality of light-emitting devices, each encapsulation portion being disposed on the side of the corresponding light-emitting device away from the array substrate; wherein... The orthographic projection of the encapsulation portion corresponding to at least one of the light-emitting devices on the array substrate covers the orthographic projection of the partition wall corresponding to at least one of the light-emitting devices on the array substrate and the orthographic projection of the plurality of light-emitting substructures corresponding to at least one light-emitting device on the array substrate; a layer of light-emitting material and an electrode material are also stacked between the partition wall and the encapsulation portion; Alternatively, the packaging portion corresponding to the at least one light-emitting device includes a plurality of sub-packaging portions spaced apart, the plurality of sub-packaging portions corresponding one-to-one with the plurality of light-emitting substructures, and the sub-packaging portions being disposed on the side of the corresponding light-emitting substructure away from the array substrate; Alternatively, the display panel may further include a pixel defining layer disposed between the array substrate and the isolation layer, the pixel defining layer forming a plurality of pixel openings, the plurality of pixel openings corresponding one-to-one with the plurality of light-emitting devices, and at least a portion of each light-emitting device being disposed within the corresponding pixel opening; The pixel opening corresponding to at least one of the light-emitting devices includes multiple sub-pixel openings, and the multiple sub-pixel openings correspond one-to-one with the multiple light-emitting substructures.

9. The display panel according to claim 1, wherein, The inner wall of the isolation opening includes a first straight edge parallel to the plane of the array substrate. The plurality of first isolation openings are arranged along a first direction to form a plurality of first isolation opening rows. The plurality of second and third isolation openings are alternately arranged along the first direction to form a plurality of second isolation opening rows. The plurality of first and second isolation opening rows are alternately arranged along a second direction intersecting the first direction. Adjacent second and third isolation openings are located within a first virtual quadrilateral. At least one of the second and third isolation openings has its first straight edge located on the edge of the first virtual quadrilateral, and at least one first isolation opening is located within the first virtual quadrilateral. A portion of the edge of the second electrode of each of the light-emitting devices is disposed on the first straight edge; Alternatively, the second isolation opening is located at the first vertex of the second virtual quadrilateral, and the third isolation opening is located at the second vertex of the second virtual quadrilateral, with the first and second vertices alternating and spaced apart; the first isolation opening is located inside the second virtual quadrilateral, and the center of the first isolation opening is offset from the center of the second virtual quadrilateral. Alternatively, along the first direction, the second virtual quadrilateral has a first side and a second side that are opposite to each other, the length of the first side being less than the length of the second side; the first side and the second side are parallel.

10. The display panel according to claim 1, wherein, The plurality of first isolation openings, the plurality of second isolation openings, and the plurality of third isolation openings are arranged along a first direction to form a plurality of third isolation opening rows, and the plurality of third isolation opening rows are arranged sequentially along a second direction intersecting the first direction; in the same third isolation opening row, the first isolation openings, the second isolation openings, and the third isolation openings are arranged alternately in sequence; Alternatively, the array substrate includes a plurality of scan lines spaced apart along the second direction, each scan line extending along the first direction; the inner wall of the isolation opening includes a first straight side, the first straight side being parallel to the second direction; Alternatively, the dimensions of the first isolation opening along the second direction, the dimensions of the second isolation opening along the second direction, and the dimensions of the third isolation opening along the second direction are all equal.

11. The display panel according to claim 1, wherein, The plurality of first isolation openings and the plurality of second isolation openings are alternately arranged along a second direction to form a plurality of first isolation opening columns, and the plurality of third isolation openings are arranged along the second direction to form a plurality of second isolation opening columns. The plurality of first isolation opening columns and the plurality of second isolation opening columns are alternately arranged along a first direction intersecting the second direction; wherein... The first isolation opening includes a plurality of first sub-isolation openings arranged along the first direction, and a partition wall is provided between two adjacent first sub-isolation openings; the second isolation opening includes a plurality of second sub-isolation openings arranged along the first direction, and a partition wall is provided between two adjacent second sub-isolation openings; the third isolation opening includes a plurality of third sub-isolation openings arranged along the second direction, and a partition wall is provided between two adjacent third sub-isolation openings. Alternatively, the extending direction of the partition wall between two adjacent first sub-isolation openings intersects with the extending direction of the partition wall between two adjacent third sub-isolation openings; The extending direction of the partition wall between two adjacent second isolation openings intersects with the extending direction of the partition wall between two adjacent third sub-isolation openings; Alternatively, the first isolation opening may include two first sub-isolation openings, the second isolation opening may include two second sub-isolation openings, and the third isolation opening may include two third sub-isolation openings.

12. The display panel according to claim 1, wherein, The first light-emitting device emits light with a wavelength between 505nm and 545nm, the second light-emitting device emits light with a wavelength between 600nm and 650nm, and the third light-emitting device emits light with a wavelength between 440nm and 480nm; wherein, The light-emitting structure of the second light-emitting device includes a plurality of light-emitting substructures, and the second isolation opening includes a plurality of second sub-isolation openings; The second sub-isolation opening has a polygonal shape when projected onto the array substrate; Alternatively, the light-emitting structure of the second light-emitting device includes two light-emitting substructures, and the second isolation opening includes two second sub-isolation openings; Alternatively, the light-emitting structure of the second light-emitting device includes four light-emitting substructures, and the second isolation opening includes four second sub-isolation openings; The centroid line connecting the orthographic projections of the four second sub-isolation openings onto the array substrate is a quadrilateral. Alternatively, the light-emitting structure of the first light-emitting device may include a plurality of light-emitting substructures, and the first isolation opening may include a plurality of first sub-isolation openings; The shape of the orthographic projection of the first sub-isolation opening onto the array substrate is polygonal; Alternatively, the light-emitting structure of the first light-emitting device includes two light-emitting substructures, and the first isolation opening includes two first sub-isolation openings; Alternatively, the light-emitting structure of the first light-emitting device includes four light-emitting substructures, and the first isolation opening includes four first sub-isolation openings; The centroid line connecting the orthographic projections of the four first sub-isolation openings onto the array substrate is a quadrilateral. Alternatively, the light-emitting structure of the third light-emitting device may include a plurality of light-emitting substructures, and the third isolation opening may include a plurality of third sub-isolation openings; The shape of the orthographic projection of the third sub-isolation opening onto the array substrate is a polygon; Alternatively, the light-emitting structure of the third light-emitting device may include two light-emitting substructures, and the third isolation opening may include two third sub-isolation openings; Alternatively, the light-emitting structure of the third light-emitting device includes four light-emitting substructures, and the third isolation opening includes four third sub-isolation openings; The centroid of the orthographic projections of the four third sub-isolation openings onto the array substrate forms a quadrilateral.

13. A display panel, comprising: Array substrate; Multiple light-emitting unit groups are disposed on the array substrate; The light-emitting unit group includes multiple light-emitting structures, which include multiple first light-emitting structures, multiple second light-emitting structures and multiple third light-emitting structures. The centroids of the multiple second light-emitting structures and the multiple third light-emitting structures are connected to form a first virtual polygon, and at least one first light-emitting structure is located within the first virtual polygon. The first light-emitting structure, the second light-emitting structure, and the third light-emitting structure emit light of different colors; In the same light-emitting unit group, at least one light-emitting structure includes a plurality of light-emitting substructures arranged at intervals, and the plurality of light-emitting substructures are electrically connected to the same driving circuit in the array substrate.

14. The display panel according to claim 13, wherein, In the same group of light-emitting units, the light-emitting structure of at least one color includes a plurality of light-emitting substructures arranged at intervals; wherein, In the same group of light-emitting units, the light-emitting structures of at least two colors include a plurality of light-emitting substructures arranged at intervals; Alternatively, in the same group of light-emitting units, each light-emitting structure includes a plurality of light-emitting substructures arranged at intervals.

15. The display panel according to claim 13, wherein, In the same light-emitting structure, the adjacent edges of two adjacent light-emitting substructures are straight edges, and the adjacent edges are parallel. Alternatively, the array substrate includes a plurality of scan lines spaced apart along a second direction, each scan line extending along a first direction intersecting the second direction; the light-emitting substructure includes at least one straight edge parallel to the second direction; Each of the light-emitting structures includes at least one straight edge parallel to the second direction.

16. The display panel according to claim 13, wherein, In the same light-emitting structure, the areas of each light-emitting substructure are equal; In the same light-emitting structure, all light-emitting substructures have the same shape; In the same light-emitting structure, any two adjacent light-emitting substructures are arranged axially symmetrically; or, in the same light-emitting structure, any two adjacent light-emitting substructures are arranged centrally symmetrically. Alternatively, the areas of at least two of the light-emitting substructures of at least one of the light-emitting structures are not equal; Alternatively, the array substrate may further include a first trace, wherein in the at least two light-emitting substructures, the orthographic projection of at least one light-emitting substructure on the array substrate overlaps with the orthographic projection of the first trace on the array substrate, and the orthographic projection of at least one light-emitting substructure on the array substrate does not overlap with the orthographic projection of the first trace on the array substrate. At least one of the light-emitting substructures has its orthographic projection on the array substrate overlapping with the orthographic projection of the first trace on the array substrate, and the overlapping projections are symmetrically arranged about the center line of the orthographic projection of the at least one light-emitting substructure on the array substrate.

17. The display panel according to claim 13, wherein, The display panel further includes a plurality of first electrodes corresponding one-to-one with a plurality of light-emitting structures; the first electrodes are disposed between the corresponding light-emitting structure and the array substrate; The first electrode corresponding to the light-emitting structure, which includes multiple light-emitting substructures, includes multiple sub-electrodes; the sub-electrodes are connected to the light-emitting substructures in a one-to-one correspondence; in the same first electrode, adjacent sub-electrodes are connected by connecting lines; The display panel further includes a plurality of conductive structures corresponding to the plurality of first electrodes, each first electrode being electrically connected to the corresponding driving circuit through at least one of the conductive structures; wherein... At least one of the light-emitting structures includes two light-emitting substructures, and the first electrode corresponding to the light-emitting structure includes two sub-electrodes, which are connected by the connecting line; the conductive structure is located between the two sub-electrodes and is connected to the connecting line; or, the conductive structure is connected to the side of one sub-electrode away from the other sub-electrode. At least a portion of the orthographic projection of the connecting line on the array substrate lies within the orthographic projection of the partition wall on the array substrate; Alternatively, at least one of the light-emitting structures includes four light-emitting substructures, and the first electrode corresponding to the light-emitting structure includes four sub-electrodes, each of which is directly connected to at least one of the connecting lines; The centroid line connecting the four sub-electrodes forms a third virtual quadrilateral; The conductive structure electrically connects the four sub-electrodes to the corresponding driving circuits; The conductive structure is located within the third virtual quadrilateral, and each of the sub-electrodes is connected to the conductive structure via a connecting line. The third virtual quadrilateral has a first corner, a second corner, a third corner, and a fourth corner. The conductive structure is located outside the third virtual quadrilateral and is connected to the sub-electrode located at the first corner. A connecting line connects the sub-electrode located at the first corner and the sub-electrode located at the second corner. A connecting line connects the sub-electrode located at the second corner and the sub-electrode located at the third corner. A connecting line connects the sub-electrode located at the third corner and the sub-electrode located at the fourth corner. The third virtual quadrilateral has a first corner, a second corner, a third corner, and a fourth corner. The conductive structure is located outside the third virtual quadrilateral. The sub-electrode located at the first corner and the sub-electrode located at the fourth corner are respectively connected to one of the conductive structures. A connecting line connects the sub-electrode located at the first corner and the sub-electrode located at the second corner, and a connecting line connects the sub-electrode located at the third corner and the sub-electrode located at the fourth corner. A connecting line connects the sub-electrode located at the second corner and the sub-electrode located at the third corner; The third virtual quadrilateral has a first corner, a second corner, a third corner, and a fourth corner. The sub-electrode located at the first corner and the sub-electrode located at the fourth corner are both connected to the conductive structure, and the conductive structure is located between the two sub-electrodes. A connecting line connects the sub-electrode located at the first corner and the sub-electrode located at the second corner, and a connecting line connects the sub-electrode located at the third corner and the sub-electrode located at the fourth corner.

18. The display panel according to claim 13, wherein, The display panel further includes a plurality of first electrodes corresponding one-to-one with a plurality of light-emitting structures; the first electrodes are disposed between the corresponding light-emitting structure and the array substrate; The orthographic projection of the first electrode corresponding to the light-emitting structure, which includes multiple light-emitting substructures, onto the array substrate, the orthographic projection of the light-emitting substructure corresponding to the light-emitting structure onto the array substrate, and the orthographic projection of the partition wall corresponding to the light-emitting structure onto the array substrate; The first electrode corresponding to the first light-emitting structure includes a first main body portion, and the orthographic projection of each first light-emitting substructure of the first light-emitting structure on the array substrate is located within the orthographic projection of the first main body portion on the array substrate; The first main body is electrically connected to the driving circuit in the array substrate through a conductive structure; The first electrode further includes a first protrusion connected to the first main body portion, and the first protrusion is electrically connected to the driving circuit in the array substrate through a conductive structure; The orthographic projection of the first protrusion on the array substrate lies within the orthographic projection of the isolation structure on the array substrate.

19. The display panel according to claim 17, wherein, The display panel further includes an isolation layer disposed on the array substrate. The isolation layer includes an isolation structure and a plurality of opening groups. The opening groups include a plurality of isolation openings. The plurality of isolation openings include a plurality of first isolation openings, a plurality of second isolation openings, and a plurality of third isolation openings. The plurality of first light-emitting structures correspond one-to-one with the plurality of first isolation openings, the plurality of second light-emitting structures correspond one-to-one with the plurality of second isolation openings, and the plurality of third light-emitting structures correspond one-to-one with the plurality of third isolation openings. At least a portion of the light-emitting structure is disposed within the corresponding isolation opening. The isolation layer further includes a partition wall located between adjacent light-emitting substructures. The isolation structure is provided with through holes corresponding to the connecting lines. The orthographic projection of the hole wall on the array substrate overlaps with the orthographic projection of the corresponding connecting line on the array substrate; or, the orthographic projection of the metal layer in the array substrate does not overlap with at least a portion of the orthographic projection of the connecting line. Alternatively, the display panel may further include a plurality of second electrodes corresponding one-to-one with the plurality of light-emitting structures, wherein the second electrodes are disposed on the side of the corresponding light-emitting structure away from the array substrate; the second electrodes are electrically connected to the isolation structure; The isolation structure includes a conductive portion and a blocking portion stacked along a direction away from the array substrate, wherein the orthographic projection of the conductive portion on the array substrate is located within the orthographic projection of the blocking portion on the array substrate; at least a portion of the second electrodes are in contact with the conductive portion; The second electrode corresponding to the light-emitting structure, which includes multiple light-emitting substructures, includes multiple sub-electrode portions that correspond one-to-one with the multiple light-emitting substructures, and each of the sub-electrode portions is in contact with the conductive portion; At least a portion of the outer edge of each of the sub-electrodes covers the sidewall of the conductive portion near the isolation opening; In the same light-emitting device, the maximum distance between the outer edge of each sub-electrode and the array substrate is equal; The display panel further includes a plurality of first encapsulation portions, which are correspondingly disposed with respect to the plurality of first light-emitting structures. The first encapsulation portions are disposed on the side of the corresponding first light-emitting structure away from the array substrate. The first encapsulation portion covers the orthogonal projection of the first light-emitting structure on the array substrate, the orthogonal projection of the plurality of first light-emitting substructures corresponding to the first light-emitting structure on the array substrate, and the orthogonal projection of the partition wall corresponding to the first light-emitting structure on the array substrate; A layer of light-emitting material and an electrode material are also stacked between the partition wall between two adjacent first light-emitting substructures and the first encapsulation part; The first encapsulation portion includes a plurality of first sub-encapsulation portions spaced apart, the plurality of first sub-encapsulation portions being correspondingly disposed to the plurality of first light-emitting substructures, and the first sub-encapsulation portions being disposed on the side of the corresponding first light-emitting substructure away from the array substrate; The display panel further includes a plurality of second encapsulation portions, which are correspondingly disposed with respect to the plurality of second light-emitting structures. The second encapsulation portions are disposed on the side of the corresponding second light-emitting structure away from the array substrate. The second encapsulation portion covers the orthogonal projection of the array substrate on the array substrate, the orthogonal projection of the plurality of second light-emitting substructures corresponding to the second light-emitting structure on the array substrate, and the orthogonal projection of the partition wall corresponding to the second light-emitting structure on the array substrate; A layer of light-emitting material and an electrode material are also stacked between the partition wall between two adjacent second light-emitting substructures and the second encapsulation part; The second encapsulation portion includes a plurality of second sub-encapsulation portions spaced apart, the plurality of second sub-encapsulation portions being disposed corresponding to the plurality of second light-emitting substructures, and the second sub-encapsulation portions being disposed on the side of the corresponding second light-emitting substructure away from the array substrate; The display panel further includes a plurality of third encapsulation portions, which are correspondingly disposed with respect to the plurality of third light-emitting structures. The third encapsulation portions are disposed on the side of the corresponding third light-emitting structure away from the array substrate. The orthographic projection of the third encapsulation part on the array substrate covers the orthographic projection of the plurality of third light-emitting substructures corresponding to the third light-emitting structure on the array substrate and the orthographic projection of the partition wall corresponding to the third light-emitting structure on the array substrate; A layer of light-emitting material and a layer of electrode material are also stacked between the partition wall between two adjacent third light-emitting substructures and the third encapsulation part; The third encapsulation portion includes a plurality of third sub-encapsulation portions spaced apart. The plurality of third sub-encapsulation portions are correspondingly arranged with the plurality of third light-emitting substructures. The third sub-encapsulation portions are located on the side of the corresponding third light-emitting substructure away from the array substrate.

20. A display device comprising a display panel as described in any one of claims 1-19.

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