Memory management method and memory controller

Abstract

The present disclosure provides a memory management method and a memory controller. The method comprises: acquiring block usage statuses of a plurality of physical blocks of a rewritable non-volatile memory module and a working state of a storage device; when the working state is a busy state, on the basis of the block usage statuses and a host write requirement, determining whether to perform a garbage collection operation; and when the garbage collection operation is performed during a host write operation, dynamically adjusting the write speed of the host write operation on the basis of the number of a plurality of remaining blocks. The method significantly improves the execution efficiency of garbage collection operations by monitoring physical block usage statuses and host write behavior in real time and incorporating a dynamic write speed adjustment mechanism, thereby effectively improving the write performance of a storage device under high load.

Description

Memory management methods and memory controllers Technical Field

[0001] This disclosure relates to the field of memory technology, specifically to a memory management method and a memory controller. Background Technology

[0002] Non-volatile memory refers to computer memory that retains its data even when the current is cut off. It has advantages such as non-volatile data, low power consumption, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Common non-volatile memory is memory configured with NAND flash (such as solid-state drives), which has the characteristics of high read and write speeds and no need for mechanical structures to access data.

[0004] In existing storage devices, the total number of available physical blocks in a rewritable non-volatile memory module (e.g., NAND flash memory) is fixed. As the host system continues to perform write operations, the physical blocks in the storage device are constantly consumed. When the physical blocks are about to run out, the storage device's firmware must initiate a garbage collection operation to release physical blocks occupied by invalid data. However, to ensure that the release rate of physical blocks is faster than the rate at which they are consumed, the storage device must limit the write speed of host write operations. In existing technologies, if the garbage collection operation releases physical blocks slowly, the storage device may suddenly limit host write operations to a lower speed range, and the resulting sharp drop in write speed may cause performance lag in the host system. Summary of the Invention

[0005] This disclosure provides a memory controller and its control method that adjust the write speed based on the working status of the storage device, the usage of data blocks, and the dynamic behavior of the host, which can solve the technical problem in the prior art where a sudden decrease in the write speed of the storage device causes the host system to lag.

[0006] One or more embodiments of this disclosure provide a memory management method applicable to a storage device configured with a rewritable non-volatile memory module. The method includes: acquiring block usage information of multiple physical blocks of the rewritable non-volatile memory module; acquiring the operating state of the storage device; when the operating state of the storage device is busy, then: determining whether to perform a garbage collection operation based on the block usage information of the multiple physical blocks and the host write demand of the storage device; and when the garbage collection operation is performed during a host write operation, dynamically adjusting the write speed of the host write operation based on the number of remaining blocks among the multiple physical blocks.

[0007] In one or more embodiments of this disclosure, the method further includes: when the working state of the storage device is an idle state, obtaining a first total effective data amount of a plurality of first written physical blocks in the plurality of physical blocks, and determining whether to perform a pre-garbage collection operation based on the first total effective data amount; and pausing the pre-garbage collection operation when a host write instruction is received during the execution of the pre-garbage collection operation.

[0008] In one or more embodiments of this disclosure, the step of determining whether to perform the pre-garbage collection operation based on the first total effective data volume includes: obtaining a first effective data ratio between the first total effective data volume and the total storage space of the plurality of first written physical blocks; when the first effective data ratio is less than a first effective data ratio threshold, determining to perform the pre-garbage collection operation, wherein the step of pausing the pre-garbage collection operation includes: not limiting the write speed of another host write operation corresponding to the host write instruction.

[0009] In one or more embodiments of this disclosure, the step of determining whether to perform the garbage collection operation based on the block usage of the plurality of physical blocks and the host write demand of the storage device includes: obtaining a first total number of a plurality of remaining blocks that have not yet been written to in the plurality of physical blocks; recording a second total number of a plurality of second written physical blocks in the plurality of remaining blocks; determining the host write demand when the ratio of the second total number to the first total number exceeds a usage threshold; determining to perform the garbage collection operation if the determined host write demand is a high demand; and determining not to perform the garbage collection operation if the determined host write demand is not a high demand.

[0010] In one or more embodiments of this disclosure, the step of determining the host write demand includes: obtaining a second total effective data volume of the plurality of second written physical blocks; obtaining a second effective data ratio between the second total effective data volume and the total storage space of the plurality of second written physical blocks; and determining that the host write demand is a high demand when the second effective data ratio exceeds a second effective data ratio threshold.

[0011] In one or more embodiments of this disclosure, the step of performing the garbage collection operation includes: selecting one or more target recycling physical blocks from the plurality of physical blocks to perform the garbage collection operation on the one or more target recycling physical blocks, wherein the effective data percentage of each target recycling physical block is less than a threshold for the effective data percentage.

[0012] In one or more embodiments of this disclosure, the step of dynamically adjusting the write speed of the host write operation based on the number of remaining blocks in the plurality of physical blocks includes: obtaining the garbage collection write speed of the garbage collection operation; and adjusting the write speed of the current host write operation based on the first total number of remaining blocks that have not yet been written in the plurality of physical blocks and the garbage collection write speed.

[0013] In one or more embodiments of this disclosure, the step of adjusting the write speed of the current host write operation based on the first total number of the plurality of remaining blocks that have not yet been written in the plurality of physical blocks and the recycling write speed includes: obtaining a first remaining percentage between the first total number and the total number of the plurality of physical blocks; and adjusting the write speed using the recycling write speed based on the first remaining percentage.

[0014] In one or more embodiments of this disclosure, the step of adjusting the write speed using the garbage collection write speed according to the first remaining percentage includes: obtaining the current remaining percentage range corresponding to the first remaining percentage; determining a corresponding speed adjustment factor according to the remaining percentage range, wherein a lower remaining percentage range corresponds to a lower speed adjustment factor; and adjusting the write speed using the garbage collection write speed of the garbage collection operation and the speed adjustment factor, wherein if the remaining percentage range is the highest remaining percentage range, the write speed of the host write operation is not adjusted.

[0015] In one or more embodiments of this disclosure, the step of dynamically adjusting the write speed of the host write operation based on the number of the plurality of remaining blocks in the plurality of physical blocks further includes: when the first total number of the plurality of remaining blocks that have not yet been written in the plurality of physical blocks reaches a critical remaining number, determining that the remaining percentage range is the minimum remaining percentage range, and performing the following steps: selecting one or more target reclaimed physical blocks from the plurality of physical blocks to perform the garbage collection operation on the one or more target reclaimed physical blocks; obtaining the effective data percentage of each target reclaimed physical block; and adjusting the write speed of the host write operation based on the effective data percentage of the target reclaimed physical block and the target reclaimed write speed of the corresponding target reclaimed physical block.

[0016] In one or more embodiments of this disclosure, the step of adjusting the write speed of the host write operation based on the effective data ratio of the target reclaimed physical block and the target reclaimed write speed corresponding to the target reclaimed physical block includes: determining an emergency speed adjustment factor based on a comparison result of the effective data ratio and another reclaimed effective data ratio threshold; and adjusting the write speed of the host write operation using the target reclaimed write speed and the emergency speed adjustment factor.

[0017] In one or more embodiments of this disclosure, the step of pausing the pre-garbage collection operation further includes: obtaining the current execution progress of the pre-garbage collection operation; recording the interruption point information corresponding to the current execution progress; and setting a recovery flag based on the interruption point information, wherein after the host write instruction is executed, it is determined whether to resume the execution of the pre-garbage collection operation based on the recovery flag.

[0018] In one or more embodiments of this disclosure, the step of determining the host write demand includes: setting a sliding time window; within the sliding time window, calculating the cumulative write data volume based on the logical address range of the received host write instructions; and when the cumulative write data volume exceeds a preset data volume threshold, determining that the host write demand is the high demand.

[0019] In one or more embodiments of this disclosure, the step of adjusting the write speed using the garbage collection operation's recycling write speed and the speed adjustment factor includes: obtaining the previous write speed; calculating the speed difference between the current target write speed and the previous write speed; determining whether a smooth transition is needed based on the speed difference; and if it is determined that a smooth transition is needed, gradually adjusting the write speed to the target write speed within a preset transition period.

[0020] Based on the above, the memory management method and memory controller provided in this disclosure effectively reduce the overhead of centralized garbage collection when physical blocks are about to be exhausted by performing garbage collection in advance based on the amount of effective data when the storage device is idle; the write demand is predicted by using a host write behavior analysis mechanism, and a graded rate limiting strategy is implemented based on the number of remaining physical blocks, making the adjustment of the write speed more gradual; in the critical state, the rate limiting ratio is dynamically adjusted based on the effective data ratio of the target reclaimed physical block, avoiding a sudden drop in write speed due to low garbage collection efficiency, and significantly improving the performance stability of the storage device under high load conditions. Attached Figure Description

[0021] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0022] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0023] Figure 2 is a flowchart of a memory management method according to an embodiment of the present invention;

[0024] Figure 3 is a flowchart of determining host write requirements according to an embodiment of the present invention;

[0025] Figure 4 is a flowchart of dynamically adjusting the write speed according to an embodiment of the present invention;

[0026] Figure 5 is a flowchart of dynamically adjusting the write speed under critical conditions according to an embodiment of the present invention;

[0027] Figure 6 is a schematic diagram showing the relationship between the speed adjustment ratio and the remaining percentage according to an embodiment of the present invention;

[0028] Figure 7 is a schematic diagram showing the relationship between the emergency speed adjustment ratio and the proportion of effective data according to an embodiment of the present invention. Detailed Implementation

[0029] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0030] Figure 1 is a block diagram illustrating a host system and storage device according to an embodiment of the present disclosure. Referring to Figure 1, the host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0031] Storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0032] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0033] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0034] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0035] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0036] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0037] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10.

[0038] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data. Furthermore, in this embodiment, the control instructions / program codes can also be executed to implement the memory management method provided in this disclosure. The control instructions / program codes corresponding to memory management can also be implemented as hardware circuit units to implement the memory management method provided in this disclosure.

[0039] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0040] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0041] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., performing a write operation based on a write instruction from the host system 10, also called a host write operation). Another example is reading data from one or more physical units of the rewritable non-volatile memory module 220 (data can be read from one or more memory cells in one or more physical units) via the memory interface control circuit 213 and writing the read data to the host system 10 (e.g., host memory 120) via the connection interface circuit 230 (e.g., performing a read operation based on a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0042] The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, perform write (also known as programming), read, or erase operations (also known as erasure) on the rewritable non-volatile memory module 220.

[0043] Furthermore, data to be written to the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 needs to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0044] In this disclosure, the memory controller 210 establishes a Logical to Physical address mapping table (L2P mapping table) and a Physical to Logical address mapping table (P2L mapping table) to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages, or logical columns) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages, physical columns) configured for the rewritable non-volatile memory module 220. In other words, the memory controller 210 can use the L2P mapping table (also called the logical to physical mapping table) to look up the physical unit mapped to a logical unit (e.g., look up the physical page mapped to a logical page; look up the physical address mapped to a logical address), and the memory controller 210 can use the P2L mapping table (also called the physical to logical mapping table) to look up the logical unit mapped to a physical unit (e.g., look up the logical page mapped to a physical page; look up the logical address mapped to a physical address).

[0045] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various mapping tables, index tables, block usage information of physical blocks, various total effective data volumes, various effective data percentages, various remaining percentages, speed adjustment ratios for each remaining percentage interval, cumulative write data statistics within a sliding time window, interrupt point information and its recovery identifier, etc., and system data associated with this memory management method), so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214.

[0046] In one embodiment, the memory controller 210 reserves a specific area in the buffer memory 214 for storing various mapping tables and index information. The memory controller 210 performs hierarchical caching of this data based on access frequency and importance: frequently accessed mapping table information is stored in a fast-access area, while less frequently used information is stored in a normal area. When the buffer memory 214 is insufficient, the memory controller 210 prioritizes writing less frequently used information back to the rewritable non-volatile memory module 220. To improve data reliability, the memory controller 210 also periodically synchronizes important mapping information from the buffer memory 214 to the rewritable non-volatile memory module 220 and records the synchronization timestamp so that the system can be restored to the most recent valid state in case of an anomaly.

[0047] In another embodiment, the memory controller 210 stores these data structures in a preset area of ​​the buffer memory and periodically synchronizes their updated state to the rewritable non-volatile memory module to ensure data persistence and consistency. In some embodiments, when the memory controller 210 restarts, the latest state of these data structures can be restored from the rewritable non-volatile memory module, ensuring that the system can continue previous storage management operations.

[0048] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store data written by the host system 10.

[0049] In this embodiment, the rewritable non-volatile memory module 220 has multiple word lines, each of which is electrically connected to multiple memory cells, also called columns (or physical columns). Multiple columns on the same word line form a physical programming unit (also called a physical page or physical page). Each physical page corresponds to a physical address to record the location of the data stored in the physical page. Furthermore, multiple physical pages can form a physical block (also called a physical erase unit or physical block). Each memory die (chip) in the multiple memory dies of the rewritable non-volatile memory module has multiple planes, and each plane has multiple physical blocks. It should be noted that this disclosure is not limited to the size of each physical page and logical page.

[0050] The memory cell type (also known as the memory mode) represents the number of bits that each memory cell can store. Common types include SLC (single-level cell, 1 bit per cell), MLC (multi-level cell, 2 bits per cell), and TLC (triple-level cell, 3 bits per cell). Different memory modes vary in terms of storage density, read / write speed, and endurance, affecting the overall performance and characteristics of flash memory.

[0051] Figure 2 is a flowchart of a memory management method according to an embodiment of the present invention;

[0052] Referring to Figure 2, in one embodiment, the memory controller 210 executes a memory management method. Specifically, in step S210, the memory controller 210 acquires the block usage status of multiple physical blocks of the rewritable non-volatile memory module 220. The memory controller 210 communicates with the rewritable non-volatile memory module 220 through the memory interface control circuit 213 to obtain usage status information for each physical block, including used space, remaining space, and the effective data amount of each data block (written block). This information is cached in the buffer memory 214 for subsequent analysis by the processor 211.

[0053] Next, in step S220, the memory controller 210 acquires the operating status of the storage device 20.

[0054] In one embodiment, the processor 211 monitors for write requests from the host system 10 via the data management circuit 212. If no write request is received from the host system 10 within a predetermined time window, the storage device 20 is determined to be in an idle state; conversely, if the host system 10 is detected to be performing a write operation or waiting to perform a write operation, the storage device 20 is determined to be in a busy state.

[0055] In another embodiment, the processor 211 may also consider other factors to determine the working state, such as: system load level, current write queue length, and utilization rate of buffer memory 214.

[0056] Next, in step S230, when the working state of the storage device 20 is busy, the memory controller 210 determines whether to perform a garbage collection operation based on the block usage of the plurality of physical blocks and the host write requirements.

[0057] Figure 3 is a flowchart for determining host write requirements according to an embodiment of the present invention.

[0058] Referring to FIG3, in one embodiment, the memory controller 210 performs a method for determining host write requests. When the storage device 20 is in a busy state, the memory controller 210 determines the host write requests according to the following steps, thereby deciding whether to perform a garbage collection operation.

[0059] In step S310, the processor 211 obtains the first total number of remaining blocks that have not yet been written to among the multiple physical blocks of the rewritable non-volatile memory module 220 through the memory interface control circuit 213. The processor 211 temporarily stores this first total number in the buffer memory 214 for subsequent calculation and judgment.

[0060] Next, in step S320, the processor 211 obtains a second total number of the multiple second written physical blocks within the most recent predetermined period. Specifically, the processor 211 continuously monitors and records the number of physical blocks actually consumed by the host system 10 during write operations within the predetermined period (e.g., the most recent 100 milliseconds or other times, not limited thereto). This second total number is also temporarily stored in the buffer memory 214.

[0061] Next, in step S330, the processor 211 determines whether it is necessary to determine host write requirements based on the first total number and the second total number. Specifically, the processor 211 calculates the ratio of the second total number to the first total number. When this ratio exceeds a preset usage threshold (e.g., 10% or other predetermined proportions, not limited thereto), it indicates that the physical block consumption rate has been relatively fast recently, and the processor 211 determines that it is necessary to further determine host write requirements (e.g., start the operation of determining host write requirements). Conversely, if the ratio does not exceed the usage threshold, the processor 211 returns to step S310 to continue monitoring the physical block usage.

[0062] If it is determined in step S330 that a host write requirement needs to be determined, then processor 211 obtains the total effective data amount of the plurality of second written physical blocks in step S340.

[0063] In one embodiment, the processor 211 can obtain the second total effective data amount through a real-time counter mechanism. Specifically, when the host system 10 performs a write operation, the processor 211 maintains a valid data counter for each second written physical block. When new data is written, the counter of the corresponding physical block is incremented by one; when data is overwritten or deleted, the counter of the source physical block is decremented by one, and the counter of the target physical block is incremented by one. The processor 211 can obtain the second total effective data amount by accumulating the values ​​of these counters.

[0064] In another embodiment, the processor 211 can obtain the second total valid data amount by scanning a mapping table. Specifically, the processor 211 maintains a logical-to-physical mapping table in the buffer memory 214, recording whether each physical address stores valid data. By scanning this mapping table, the processor 211 can count the number of addresses mapped in each second written physical block, thereby calculating the second total valid data amount.

[0065] In another embodiment, the processor 211 may employ a hybrid acquisition method. Specifically, a counter is used for real-time statistics during normal writing, and the count value is periodically corrected by scanning a mapping table, thereby improving the accuracy of the second total effective data volume statistics.

[0066] Next, in step S350, the processor 211 obtains the second effective data ratio between the second total effective data amount and the total storage space of the plurality of second written physical blocks. Specifically, the processor 211 first calculates the total storage space of these second written physical blocks, and then divides the second total effective data amount by the total storage space to obtain the second effective data ratio.

[0067] Next, in step S360, the processor 211 determines whether the proportion of the second valid data exceeds a second valid data proportion threshold. When the proportion of the second valid data exceeds a preset threshold (e.g., 90% or other predetermined proportion, which is not limited to this), it indicates that the recently written data block contains a large amount of valid data. Based on this, the processor 211 determines in step S370 that the current host write demand is high, and performs a garbage collection operation in step S380 (this garbage collection operation will be performed even if a host write operation is currently being performed).

[0068] Conversely, if the proportion of the second valid data does not exceed the threshold, the processor 211 determines in step S390 that the host write demand is not high. In this case, the processor 211 can perform the following operations: First, the processor 211 maintains the current host write speed at a high level without activating the write speed limiting mechanism. Second, the processor 211 can prioritize allocating system resources to host write operations, while postponing garbage collection until the storage device 20 becomes idle. In this way, the memory controller 210 ensures host write performance.

[0069] In one embodiment, when it is determined that a garbage collection operation needs to be performed, the processor 211 selects one or more target physical blocks for garbage collection from a plurality of physical blocks. Specifically, the processor 211 obtains the effective data percentage of each physical block and selects physical blocks whose effective data percentage is less than a threshold for the effective data percentage (e.g., 30% or other predetermined percentage, which is not limited thereto) as target physical blocks for garbage collection. By selecting physical blocks with less effective data for garbage collection, the overhead of data movement can be reduced and the execution efficiency of garbage collection can be improved.

[0070] Through the aforementioned multi-judgment mechanism based on physical block usage, the memory controller 210 can promptly identify high-intensity write behavior of the host system 10 and initiate garbage collection operations in advance, thereby avoiding passive garbage collection only when physical block resources are scarce. This predictive management method significantly improves the performance of the storage device 20 under high load conditions.

[0071] In some embodiments, the processor 211 may dynamically adjust the above threshold according to the actual application scenario of the storage device 20, for example:

[0072] (1) The threshold for the second effective data percentage can be reduced in high-performance mode. The advantage of reducing the threshold for the second effective data percentage in high-performance mode is that, since high-performance mode usually has high requirements for write speed and response time, reducing the threshold means that even if the proportion of effective data in a data block is relatively low, it will still be judged as a high write demand. In this way, reducing the threshold for the second effective data percentage in high-performance mode can trigger garbage collection operations earlier, release physical block resources in advance, and avoid being forced to perform garbage collection when physical block resources are scarce, thereby reducing write latency.

[0073] (2) Increasing the usage threshold in low-power mode: The advantage of increasing the usage threshold in low-power mode is that low-power mode prioritizes reducing system resource consumption. Increasing the usage threshold means that a higher proportion of physical block consumption is required to trigger garbage collection. In this way, increasing the usage threshold in low-power mode can reduce unnecessary garbage collection operations and reduce power consumption. In addition, since low-power mode has lower performance requirements, it can tolerate higher write latency.

[0074] In one embodiment, if the processor 211 determines that the host write demand is high, it decides to perform a garbage collection operation. Conversely, if it determines that the host write demand is not high, it temporarily refrains from performing a garbage collection operation. Through this judgment mechanism based on host write behavior analysis, the memory controller 210 can initiate a garbage collection operation at an appropriate time, effectively balancing storage performance and resource utilization efficiency.

[0075] In another embodiment, the processor 211 may employ a sliding time window mechanism to determine host write demand. Specifically, the processor 211 sets a fixed-size sliding time window (e.g., 100 milliseconds or other predetermined time, not limited thereto), which continuously advances over time. Within this time window, the processor 211 records and accumulates the logical address range of each write instruction sent by the host system 10, calculating the cumulative write data volume. When the cumulative write data volume exceeds a preset data volume threshold, the processor 211 determines that the current host write demand is high. This sliding time window-based determination method can accurately reflect the write pressure of the host system 10 within a specific time period.

[0076] Returning to Figure 2, in step S240, when a garbage collection operation is performed during a host write operation, the memory controller 210 dynamically adjusts the write speed of the host write operation based on the number of remaining blocks. Specifically, the processor 211 obtains the garbage collection write speed and adjusts the write speed based on a first remaining percentage between the first total number of remaining blocks and the total number of physical blocks. For example, when the first remaining percentage is in different ranges, the processor 211 uses different speed adjustment ratios, with lower remaining percentage ranges corresponding to lower speed adjustment ratios. If the remaining percentage range is the lowest remaining percentage range, the processor 211 further adjusts the write speed based on the effective data percentage of the target reclaimed physical blocks to ensure a smooth transition in system performance.

[0077] Through the above steps, the memory controller 210 can dynamically adjust the write speed according to the host's write behavior, effectively avoiding a sudden drop in write speed and improving the performance stability of the storage device 20.

[0078] In another embodiment, when storage device 20 is idle (e.g., no write command is received from host system 10 for 100 consecutive milliseconds), memory controller 210 performs preventative garbage collection management. Specifically, processor 211 first obtains the first total valid data amount of multiple first written physical blocks in rewritable non-volatile memory module 220 through memory interface control circuit 213. Processor 211 temporarily stores this data amount information in buffer memory 214.

[0079] Subsequently, the processor 211 calculates the first effective data ratio between the first total effective data volume and the total storage space of the plurality of first written physical blocks. Specifically, the processor 211 first obtains the total storage space size of these first written physical blocks, and then divides the first total effective data volume by the total storage space to obtain the first effective data ratio. When the first effective data ratio is less than a preset first effective data ratio threshold (e.g., 70% or other predetermined ratio, which is not limited to this), it indicates that there is a large amount of invalid data in the current storage space, and the processor 211 determines that a pre-garbage collection operation needs to be performed accordingly.

[0080] During this pre-garbage collection operation, if the data management circuit 212 receives a write command from the host system 10, the processor 211 will immediately pause the currently executing garbage collection operation. Specifically, the processor 211 records the execution progress of the current garbage collection operation and prioritizes allocating system resources to host write operations. It is worth noting that since this garbage collection operation is performed preventively during idle time, when pausing this operation to process host write commands, the processor 211 does not impose any restrictions on the write speed of the host write operation, thereby ensuring that host write performance is not affected.

[0081] When pausing the pre-garbage collection operation, the processor 211 can perform a series of state saving operations. Specifically, the processor 211 first obtains the current execution progress of the garbage collection operation, including the number of physical blocks processed, the address of the physical block currently being processed, and the processing position within that physical block. Subsequently, the processor 211 records this interruption point information in the buffer memory 214, which can be used for location positioning when the garbage collection operation is resumed later.

[0082] The processor 211 also sets a recovery flag based on the recorded interrupt point information. Specifically, the recovery flag contains several fields: the physical block identifier currently being processed, the offset address of the operation within the block, the proportion of garbage collection completed, and the priority of the garbage collection operation. This information is organized into a state description structure and stored in a predetermined area of ​​the buffer memory 214.

[0083] After the host write instruction is executed, the processor 211 determines whether to resume the pre-garbage collection operation based on the recovery flag. Specifically, the processor 211 first checks whether the storage device 20 has returned to an idle state, then assesses the amount of incomplete garbage collection, and, considering the current system resource usage, decides whether to immediately resume the garbage collection operation. If the conditions are met, the processor 211 continues the garbage collection operation from the interrupt location based on the previously saved interrupt point information, ensuring that the storage space is effectively organized.

[0084] This pause and resume mechanism allows the memory controller 210 to dynamically switch between host write operations and garbage collection operations, ensuring host write performance without losing garbage collection progress information.

[0085] Through this preventative garbage collection mechanism, the memory controller 210 can make full use of system idle time to organize storage space without affecting the normal write operation of the host system 10, effectively improving the overall performance of the storage device 20.

[0086] Figure 4 is a flowchart of dynamically adjusting the write speed according to an embodiment of the present invention.

[0087] Referring to FIG4, in one embodiment, the memory controller 210 performs a method for dynamically adjusting the write speed. When a garbage collection operation is performed during a host write operation, the processor 211 performs the dynamic adjustment of the write speed of the host write operation according to the number of remaining blocks among the plurality of physical blocks.

[0088] In step S410, the processor 211 obtains the write speed of the garbage collection operation. In simple terms, the processor 211 monitors the actual write speed of copying valid data from the source physical block to the target physical block during the garbage collection process via the memory interface control circuit 213.

[0089] In one embodiment, the memory controller 210 obtains the garbage collection write speed of the garbage collection operation in the following manner. Specifically, when performing a garbage collection operation, the processor 211 monitors the process of moving data from the source physical block to the target physical block through the memory interface control circuit 213. The processor 211 records the number of bytes moved within each preset time interval (e.g., 1 millisecond) and stores this value in the buffer memory 214. By calculating the average number of bytes written over multiple consecutive time intervals, the processor 211 can obtain the actual garbage collection write speed of the current garbage collection operation.

[0090] In step S420, the processor 211 obtains a first remaining percentage between the first total number of remaining blocks that have not yet been written to the plurality of physical blocks and the total number of the plurality of physical blocks. Specifically, the processor 211 first obtains the total number of physical blocks (also called remaining blocks) that have not yet been written to in the rewritable non-volatile memory module 220 through the memory interface control circuit 213, and then divides this number by the total number of physical blocks to obtain the first remaining percentage.

[0091] In step S430, the processor 211 obtains the current remaining percentage range corresponding to the first remaining percentage. Specifically, the processor 211 presets multiple remaining percentage ranges, for example: 50%-100% is the first range (also called the highest remaining percentage range), 30%-50% is the second range (also called the high remaining percentage range), 10%-30% is the third range (also called the medium remaining percentage range), and less than 10% is the fourth range (also called the low remaining percentage range). The processor 211 maps the currently calculated first remaining percentage to these preset ranges. It should be noted that the specific settings of each of the above ranges can be changed according to actual needs.

[0092] In step S440, the processor 211 determines the corresponding speed adjustment multiplier based on the remaining percentage range. Specifically, a higher remaining percentage range corresponds to a higher speed adjustment multiplier. For example, the first range corresponds to an unlimited speed adjustment multiplier, the second range corresponds to a speed adjustment multiplier of 5 (also called a high speed adjustment multiplier), the third range corresponds to a speed adjustment multiplier of 3 (also called a medium speed adjustment multiplier), and the fourth range corresponds to a speed adjustment multiplier of 1.5 (also called a low speed adjustment multiplier). This design ensures a high write speed when there is sufficient remaining space, and gradually reduces the write speed when there is insufficient remaining space. It should be noted that the values ​​5, 3, and 1.5 corresponding to the high, medium, and low speed adjustment multipliers are exemplary values ​​used to illustrate the relative magnitude relationship, and the present invention is not limited thereto.

[0093] In step S450, the processor 211 adjusts the write speed using the garbage collection write speed and the speed adjustment factor. Specifically, if the current first remaining percentage is in a first range (i.e., the highest remaining percentage range), the processor 211 does not limit the write speed of the host write operation. If the first remaining percentage is in another range, the processor 211 limits the host write speed to a corresponding multiple of the garbage collection write speed.

[0094] Through this multi-level rate limiting mechanism based on the number of remaining blocks, the memory controller 210 can reasonably adjust the host write speed while ensuring stable system operation.

[0095] Figure 6 is a schematic diagram showing the relationship between the speed adjustment ratio and the remaining percentage according to an embodiment of the present invention.

[0096] Referring to Figure 6, in one embodiment, graph CT61 illustrates the relationship between the speed adjustment factor of the memory controller 210 and the total number of remaining blocks. The horizontal axis represents the total number of remaining blocks, and this axis is divided into the lowest remaining percentage range (RS61), the medium remaining percentage range (RS62), the high remaining percentage range (RS63), and the highest remaining percentage range (RS64). The vertical axis represents the speed adjustment factor.

[0097] Specifically, when the total number of remaining blocks is in the highest remaining percentage range RS64, the processor 211 does not limit the host write speed. When the total number of remaining blocks is in other ranges, the processor 211 limits the host write speed according to the speed adjustment factor corresponding to the current range. Among them, RS63 corresponds to a high speed adjustment factor, RS62 corresponds to a medium speed adjustment factor, and RS61 corresponds to a low speed adjustment factor.

[0098] When the total number of remaining blocks reaches the critical remaining quantity, processor 211 determines that it is currently in the minimum remaining percentage range RS61. In this case, processor 211 executes an emergency garbage collection strategy: First, it selects one or more target reclaimed physical blocks (physical blocks used to perform pre-garbage collection operations) from multiple physical blocks. Processor 211 obtains the effective data percentage of each target reclaimed physical block through memory interface control circuit 213, and calculates the optimal data relocation strategy based on this percentage information.

[0099] For each target reclaimed physical block, the processor 211 obtains its actual target reclaim write speed and determines the corresponding write speed limit based on the percentage of valid data in that physical block. Specifically, when the percentage of valid data in the target reclaimed physical block is low, the processor 211 can use a relatively high write speed limit; when the percentage of valid data is high, a lower write speed limit is used to ensure the reliability of data transfer. Through this mechanism, the memory controller 210 can maintain stable system operation even in emergency situations.

[0100] In one embodiment, when the processor 211 adjusts the write speed based on the percentage of valid data in the target reclaimed physical block, the following steps are specifically executed. The processor 211 first compares the percentage of valid data in the target reclaimed physical block with another preset threshold for the percentage of valid data (e.g., 50% or other predetermined percentages, not limited thereto). Specifically, if the percentage of valid data in the target reclaimed physical block is lower than this threshold, the processor 211 sets the emergency speed adjustment multiplier to, for example, 1x. This indicates that the amount of valid data in the current target reclaimed physical block is relatively small, and the garbage collection operation can be completed faster. For example, after a physical block is released during a pre-garbage collection operation, the host can write data to fill an empty physical block.

[0101] Conversely, if the percentage of valid data exceeds this threshold, the processor 211 sets the emergency speed adjustment factor to, for example, between 2 and 3 times, to handle larger data migration volumes. For example, after a pre-garbage collection operation releases one physical block, host write data can fill 2 to 3 physical blocks, thereby slowing down the decline in host write speed. Subsequently, the processor 211 uses the product of the target garbage collection write speed and the determined emergency speed adjustment factor to set the write speed limit for host write operations.

[0102] It is worth mentioning that the diagonal lines SL1 and SL2 in Figure 6 represent a smooth transition mechanism. In this embodiment, the processor 211 can use linear interpolation to calculate the speed adjustment factor at the boundary of adjacent intervals to avoid sudden changes in write speed when switching intervals.

[0103] More specifically, in one embodiment, to avoid abrupt changes in write speed, processor 211 implements a smooth transition mechanism. Specifically, when the write speed needs to be adjusted, processor 211 first retrieves the previous write speed value from buffer memory 214. Processor 211 then calculates the speed difference between the current target write speed and the previous write speed. When this difference exceeds a preset threshold (e.g., the current speed change exceeds 30% of the previous speed or other predetermined proportions), processor 211 determines that a smooth transition is required.

[0104] During a smooth transition, the processor 211 gradually adjusts the write speed from the previous value to the target write speed within a preset transition period (e.g., 10 milliseconds or other predetermined time). Specifically, the processor 211 evenly distributes the speed difference across multiple adjustment steps, with each adjustment step occurring at equal time intervals, thereby achieving a linear transition in write speed. This smooth transition mechanism avoids drastic fluctuations in write speed.

[0105] Figure 5 is a flowchart of dynamically adjusting the write speed under critical conditions according to an embodiment of the present invention.

[0106] Referring to Figure 5, in one embodiment, when the first total number of remaining blocks that have not yet been written to in a plurality of physical blocks reaches a critical remaining quantity (e.g., 3), the memory controller 210 executes a special write speed adjustment procedure. It should be noted that the specific value of the critical remaining quantity can be determined according to requirements.

[0107] In step S510, the processor 211 selects one or more target physical blocks for garbage collection from the plurality of physical blocks to perform garbage collection operations on these physical blocks. Specifically, the processor 211 scans the usage status of all physical blocks through the memory interface control circuit 213 and preferentially selects physical blocks with a lower percentage of valid data as target physical blocks for garbage collection.

[0108] In step S520, processor 211 obtains the effective data percentage of each target recycling physical block. Processor 211 reads the effective data distribution information in these physical blocks through memory interface control circuit 213, and calculates the actual percentage of effective data in each target recycling physical block relative to the storage space of each target recycling physical block.

[0109] In step S530, the processor 211 determines the emergency speed adjustment multiplier based on a comparison between the effective data percentage and another threshold for the effective data percentage of the target reclaimed physical block. Specifically, if the effective data percentage of the target reclaimed physical block is low, a larger speed adjustment multiplier is used; if the effective data percentage is high, a smaller speed adjustment multiplier is used to avoid excessive reduction in write speed.

[0110] In step S540, the processor 211 adjusts the write speed of the host write operation using the target recycling write speed and the emergency speed adjustment multiplier. Through this dynamic adjustment mechanism based on the effective data percentage, the memory controller 210 can maintain reasonable write performance even in critical conditions.

[0111] Figure 7 is a schematic diagram showing the relationship between the emergency speed adjustment ratio and the proportion of effective data according to an embodiment of the present invention.

[0112] Referring to Figure 7, Chart CT71 illustrates the relationship between the emergency speed adjustment multiplier and the effective data percentage under critical conditions. The horizontal axis represents the effective data percentage of the target recovered physical block, and this horizontal axis is divided into two regions, RS71 and RS72, by another effective data percentage threshold. The vertical axis represents the corresponding emergency speed adjustment multiplier.

[0113] When the percentage of valid data in the target physical block to be reclaimed is in the RS71 region (i.e., less than another threshold for the percentage of valid data to be reclaimed), it indicates that the garbage collection operation is relatively efficient. At this time, the processor 211 uses a lower emergency speed adjustment multiplier (e.g., 1x) because each garbage collection operation can release new free blocks more quickly.

[0114] Conversely, when the percentage of valid data is in the RS72 region (i.e., exceeding another threshold for the percentage of valid data to be recycled), it indicates that the garbage collection operation needs to move a large amount of valid data, resulting in relatively low efficiency. In this case, the processor 211 uses a higher emergency speed adjustment factor (e.g., 2 to 3 times) to give the garbage collection operation more execution time and avoid drastic fluctuations in write speed.

[0115] Through this differentiated adjustment mechanism based on the proportion of effective data, the memory controller 210 can maintain stable operation of the system even in critical conditions.

[0116] Finally, this embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code runs in the processor of a host system, the processor 211 executes the process steps of the above-described memory management method and implements the functions of the memory controller 210. This computer program product can be specifically implemented through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0117] Based on the above, the memory management method and memory controller provided in this disclosure can achieve the following technical effects:

[0118] First, by pre-executing garbage collection based on the percentage of valid data when the storage device 20 is idle, and pausing the operation promptly upon receiving a host write command, the garbage collection pressure on the storage device 20 under high load is reduced. Specifically, the processor 211 ensures that the garbage collection operation can continue at the appropriate time by recording interruption point information and setting a recovery flag, effectively balancing storage performance and resource utilization.

[0119] Second, based on the host write behavior analysis mechanism, the processor 211 can identify write demands and predict resource consumption trends in advance. By monitoring the physical block usage and effective data ratio within a predetermined period, or by combining the cumulative write data volume within a sliding time window, the processor 211 achieves accurate assessment of host write demands.

[0120] Third, a multi-level speed limiting strategy is implemented based on the number of remaining physical blocks to avoid sudden changes in write speed. The processor 211 presets multiple remaining percentage ranges and corresponding speed adjustment ratios, and adopts a multi-stage transition mechanism when switching between ranges to make the adjustment of write speed more stable.

[0121] Fourth, a differentiated adjustment mechanism based on the proportion of effective data is adopted in critical states. The processor 211 selects an appropriate emergency speed adjustment multiplier by evaluating the proportion of effective data in the target reclaimed physical block, thus avoiding the problem of performance drop caused by excessive restriction of write speed.

[0122] Fifth, intelligent smooth adjustment of write speed is achieved. The processor 211 calculates the difference between the target write speed and the previous write speed, and activates a smooth transition mechanism when necessary to ensure that the write speed is gradually adjusted to the target value within a preset transition period, thereby improving the operational stability of the storage device.

[0123] Through the above technical solutions, the memory management method provided in this disclosure significantly improves the performance of storage devices under various load conditions, and is especially suitable for application scenarios that require frequent data writing.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method applicable to storage devices equipped with rewritable non-volatile memory modules, characterized in that, The method includes: Obtain the block usage status of multiple physical blocks of the rewritable non-volatile memory module; When the storage device is busy, based on the block usage of the plurality of physical blocks and the host write demand of the storage device, it is determined whether to perform a garbage collection operation; and When the garbage collection operation is performed during a host write operation, the write speed of the host write operation is dynamically adjusted based on the number of remaining blocks in the plurality of physical blocks.

2. The memory management method according to claim 1, characterized in that, Also includes: When the storage device is idle, the first total valid data amount of multiple first written physical blocks among the plurality of physical blocks is obtained, and a pre-garbage collection operation is determined based on the first total valid data amount: and The pre-garbage collection operation is paused when a host write instruction is received during the execution of the pre-garbage collection operation.

3. The memory management method according to claim 2, characterized in that, The steps for determining whether to perform the pre-garbage collection operation based on the first total valid data volume include: Obtain the first effective data ratio between the first total effective data volume and the total storage space of the plurality of first written physical blocks; When the proportion of the first valid data is less than the first valid data proportion threshold, it is determined that the pre-garbage collection operation will be performed.

4. The memory management method according to claim 1, characterized in that, The step of determining whether to perform the garbage collection operation based on the block usage of the multiple physical blocks and the host write requirements of the storage device includes: Obtain the first total number of remaining blocks that have not yet been written among the plurality of physical blocks; Record the second total number of the second physical blocks that have been written within the plurality of remaining blocks; When the ratio of the second total number to the first total number exceeds the usage threshold, the host write requirement is determined; and If the host write demand is determined to be high, the garbage collection operation is executed.

5. The memory management method according to claim 4, characterized in that, The steps for determining the host write requirements include: Obtain the second total valid data amount of the plurality of second written physical blocks; Obtain the percentage of the second total valid data volume relative to the total storage space of the plurality of second written physical blocks; and When the proportion of the second valid data exceeds the threshold of the second valid data proportion, the host write demand is determined to be high demand.

6. The memory management method according to claim 5, characterized in that, The steps for performing the waste recycling operation include: One or more target reclaimed physical blocks are selected from the plurality of physical blocks to perform the garbage collection operation on the one or more target reclaimed physical blocks, wherein the effective data percentage of each target reclaimed physical block is less than the threshold for the effective data percentage.

7. The memory management method according to claim 1, characterized in that, The step of dynamically adjusting the write speed of the host write operation based on the number of remaining blocks among the plurality of physical blocks includes: Obtain the write speed of the garbage collection operation; The write speed of the current host write operation is adjusted based on the first total number of remaining blocks that have not yet been written in the plurality of physical blocks and the recycling write speed.

8. The memory management method according to claim 7, characterized in that, The step of adjusting the write speed of the current host write operation based on the first total number of the plurality of remaining blocks that have not yet been written in the plurality of physical blocks and the recycling write speed includes: Obtain the first remaining percentage between the first total number and the total number of the plurality of physical blocks; The write speed is adjusted using the recycling write speed based on the first remaining percentage.

9. The memory management method according to claim 8, characterized in that, The step of adjusting the write speed using the recycling write speed based on the first remaining percentage includes: Obtain the current remaining percentage range corresponding to the first remaining percentage; Based on the remaining percentage range, a corresponding speed adjustment factor is determined, wherein a lower remaining percentage range corresponds to a lower speed adjustment factor; and The write speed is adjusted using the recycling write speed of the garbage collection operation and the speed adjustment factor.

10. The memory management method according to claim 9, characterized in that, The step of dynamically adjusting the write speed of the host write operation based on the number of remaining blocks in the plurality of physical blocks further includes: When the first total number of remaining blocks that have not yet been written to in the plurality of physical blocks reaches the critical remaining quantity, the remaining percentage interval is determined to be the minimum remaining percentage interval, and the following steps are performed: Select one or more target reclaimed physical blocks from the plurality of physical blocks to perform the garbage collection operation on the one or more target reclaimed physical blocks; Obtain the percentage of valid data for each target recycled physical block; The write speed of the host write operation is adjusted based on the effective data ratio of the target reclaimed physical block and the target reclaimed write speed of the corresponding target reclaimed physical block.

11. The memory management method according to claim 10, characterized in that, The step of adjusting the write speed of the host write operation based on the effective data ratio of the target reclaimed physical block and the target reclaim write speed of the corresponding target reclaimed physical block includes: Based on the comparison between the aforementioned effective data percentage and another threshold for the effective data percentage, the emergency velocity adjustment multiplier is determined; and The write speed of the host write operation is adjusted using the target recycling write speed and the emergency speed adjustment factor.

12. The memory management method according to claim 2, characterized in that, The step of suspending the pre-garbage collection operation also includes: Obtain the current execution progress of the pre-garbage collection operation; Record the interruption point information corresponding to the current execution progress; and A recovery flag is set based on the interruption point information. Once the host write instruction is executed, the system determines whether to resume the pre-garbage collection operation based on the recovery flag.

13. The memory management method according to claim 4, characterized in that, The steps for determining the host write requirements include: Set a sliding time window; Within the sliding time window, the cumulative amount of data written is calculated based on the logical address range of the received host write instructions; and When the cumulative amount of written data exceeds a preset data volume threshold, the host write demand is determined to be a high demand.

14. The memory management method according to claim 9, characterized in that, The step of adjusting the write speed using the garbage collection write speed and the speed adjustment factor includes: Get the last write speed; Calculate the speed difference between the current target write speed and the previous write speed; Determine whether a smooth transition is needed based on the speed difference; and If it is determined that a smooth transition is required, the write speed is gradually adjusted to the target write speed during a preset transition period.

15. A memory controller for controlling a storage device configured with a rewritable non-volatile memory module, characterized in that, The memory controller includes: A memory interface control circuit is used to electrically connect to the rewritable non-volatile memory module; A data management circuit, electrically connected to the connection interface circuit of the storage device, is used to receive data and instructions from the host system via the connection interface circuit; Buffer memory, used to cache data; and A processor electrically connected to the memory interface control circuit, the data management circuit, and the buffer memory, wherein the processor is configured to: Obtain the block usage status of multiple physical blocks of the rewritable non-volatile memory module; Obtain the block usage status of multiple physical blocks of the rewritable non-volatile memory module; When the storage device is busy, based on the block usage of the plurality of physical blocks and the host write demand of the storage device, it is determined whether to perform a garbage collection operation; and When the garbage collection operation is performed during a host write operation, the write speed of the host write operation is dynamically adjusted based on the number of remaining blocks in the plurality of physical blocks.

16. The memory controller according to claim 15, characterized in that, The processor is also configured to: When the storage device is in an idle state, the first total effective data amount of the first written physical blocks among the plurality of physical blocks is obtained, and a pre-garbage collection operation is determined based on the first total effective data amount. as well as The pre-garbage collection operation is paused when a host write instruction is received during the execution of the pre-garbage collection operation.

17. The memory controller according to claim 16, characterized in that, The step of determining whether to perform the pre-garbage collection operation based on the first total valid data volume: Obtain the first effective data ratio between the first total effective data volume and the total storage space of the plurality of first written physical blocks; When the proportion of the first valid data is less than the first valid data proportion threshold, it is determined that the pre-garbage collection operation will be performed.

18. The memory controller according to claim 15, characterized in that, The step of determining whether to perform the garbage collection operation based on the block usage of the multiple physical blocks and the host write requirements of the storage device includes: Obtain the first total number of remaining blocks that have not yet been written among the plurality of physical blocks; Record the second total number of the second physical blocks that have been written within the plurality of remaining blocks; When the ratio of the second total number to the first total number exceeds the usage threshold, the host write requirement is determined; and If the determined host write demand is high, then the garbage collection operation is executed.

19. The memory controller according to claim 18, characterized in that, The steps for determining the host write requirements include: Obtain the second total valid data amount of the plurality of second written physical blocks; Obtain the percentage of the second total valid data volume relative to the total storage space of the plurality of second written physical blocks; and When the proportion of the second valid data exceeds the threshold of the second valid data proportion, the host write demand is determined to be high demand.

20. The memory controller according to claim 19, characterized in that, The steps for performing the waste recycling operation include: One or more target reclaimed physical blocks are selected from the plurality of physical blocks to perform the garbage collection operation on the one or more target reclaimed physical blocks, wherein the effective data percentage of each target reclaimed physical block is less than the threshold for the effective data percentage.

21. The memory controller according to claim 15, characterized in that, The step of dynamically adjusting the write speed of the host write operation based on the number of remaining blocks among the plurality of physical blocks includes: Obtain the write speed of the garbage collection operation; The write speed of the current host write operation is adjusted based on the first total number of remaining blocks that have not yet been written in the plurality of physical blocks and the recycling write speed.

22. The memory controller according to claim 21, characterized in that, The step of adjusting the write speed of the current host write operation based on the first total number of the plurality of remaining blocks that have not yet been written in the plurality of physical blocks and the recycling write speed includes: Obtain the first remaining percentage between the first total number and the total number of the plurality of physical blocks; The write speed is adjusted using the recycling write speed based on the first remaining percentage.

23. The memory controller according to claim 22, characterized in that, The step of adjusting the write speed using the recycling write speed based on the first remaining percentage includes: Obtain the current remaining percentage range corresponding to the first remaining percentage; Based on the remaining percentage range, a corresponding speed adjustment factor is determined, wherein a lower remaining percentage range corresponds to a lower speed adjustment factor; and The write speed is adjusted using the recycling write speed of the garbage collection operation and the speed adjustment factor.

24. The memory controller according to claim 23, characterized in that, The step of dynamically adjusting the write speed of the host write operation based on the number of remaining blocks in the plurality of physical blocks further includes: When the first total number of remaining blocks that have not yet been written to in the plurality of physical blocks reaches the critical remaining quantity, the remaining percentage interval is determined to be the minimum remaining percentage interval, and the following steps are performed: Select one or more target reclaimed physical blocks from the plurality of physical blocks to perform the garbage collection operation on the one or more target reclaimed physical blocks; Obtain the percentage of valid data for each target recycled physical block; The write speed of the host write operation is adjusted based on the effective data ratio of the target reclaimed physical block and the target reclaimed write speed of the corresponding target reclaimed physical block.

25. The memory controller according to claim 24, characterized in that, The step of adjusting the write speed of the host write operation based on the effective data ratio of the target reclaimed physical block and the target reclaim write speed of the corresponding target reclaimed physical block includes: Based on the comparison between the aforementioned effective data percentage and another threshold for the effective data percentage, the emergency velocity adjustment multiplier is determined; and The write speed of the host write operation is adjusted using the target recycling write speed and the emergency speed adjustment factor.

26. The memory controller according to claim 16, characterized in that, The step of suspending the pre-garbage collection operation also includes: Obtain the current execution progress of the pre-garbage collection operation; Record the interruption point information corresponding to the current execution progress; and A recovery flag is set based on the interruption point information. Once the host write instruction is executed, the system determines whether to resume the pre-garbage collection operation based on the recovery flag.

27. The memory controller according to claim 18, characterized in that, The steps for determining the host write requirements include: Set a sliding time window; Within the sliding time window, the cumulative amount of data written is calculated based on the logical address range of the received host write instructions; and When the cumulative amount of written data exceeds a preset data volume threshold, the host write demand is determined to be a high demand.

28. The memory controller according to claim 23, characterized in that, The step of adjusting the write speed using the garbage collection write speed and the speed adjustment factor includes: Get the last write speed; Calculate the speed difference between the current target write speed and the previous write speed; Determine whether a smooth transition is needed based on the speed difference; and If it is determined that a smooth transition is required, the write speed is gradually adjusted to the target write speed during a preset transition period.

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