Memory operation method and memory chip
By measuring and storing operation depth information during wafer testing, and combining this with a phased execution and verification method, the problem of uncontrollable threshold voltage in charge-trapping flash memory chips was solved, thus optimizing the performance of the memory chips.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- PUYA SEMICON SHANGHAI CO LTD
- Filing Date
- 2025-11-27
- Publication Date
- 2026-06-18
AI Technical Summary
In existing charge-trap flash memory chips, the uncertainty of charge escape during erase or programming operations makes it difficult to accurately control the threshold voltage, which affects the performance of the memory chip.
In wafer testing, the operational depth information of the memory cells is pre-determined, and this depth information is used for depth verification during actual operation to ensure that the threshold voltage change of the memory cells is within the expected range. By performing operations in stages and verifying the depth information, precise control is achieved.
The overall performance of the memory chip has been optimized to ensure that the threshold voltage is within the expected range, thereby improving the accuracy and reliability of operation.
Smart Images

Figure CN2025138201_18062026_PF_FP_ABST