Chip computing power test method and apparatus, and storage medium

Abstract

Provided in the embodiments of the present description are a chip computing power test method and apparatus, and a storage medium. The method comprises: determining a test environment for a chip under test, the required computing power of the chip in the test environment varying according to a preset rule; operating said chip in the test environment; for said chip in operation, collecting first variation data, second variation data, process delays and accuracies of said chip, wherein the first variation data is data used for characterizing the change of the chip temperature over time, and the second variation data is data used for characterizing the change of the output computing power over time; and, on the basis of the first variation data, the second variation data, the process delays and the accuracies of said chip, evaluating the degree of computing power fluctuation of said chip. The technical solution provided by the present application solves the problems in the prior art that it is difficult to truly reflect the actual performance of a chip, thus reducing the accuracy of chip evaluation.

Description

A chip computing power testing method, apparatus, and storage medium This application claims priority to Chinese Patent Application No. 202411817608.3, filed on December 11, 2024, with the full title of which is "A chip-based test apparatus and storage medium for measuring the strength of a device". Technical Field

[0001] This document relates to the field of chip performance evaluation technology, and in particular to a chip computing power testing method, device and storage medium. Background Technology

[0002] With the continuous development of the new energy vehicle industry and the increasing value of automotive electronics in the era of intelligent vehicles, automotive computing chips have become the core of intelligent vehicle development. Driven by various applications, the computing performance requirements for intelligent vehicle computing chips are constantly growing.

[0003] Current automotive chip evaluations primarily use computing power as the standard for evaluating actual performance. The computing power refers to the chip's peak computing power, which reflects the chip's extreme processing capabilities.

[0004] However, the true performance of automotive computing chips is affected by factors such as task diversity, software SDK (Software Development Kit), algorithms and models, environment, energy efficiency ratio, and real-world application scenarios. Therefore, existing technologies can hardly accurately reflect the true performance of chips, thus reducing the accuracy of chip evaluation. Summary of the Invention

[0005] In view of the above solutions, this application aims to provide a chip computing power testing method, apparatus and storage medium to solve at least one of the above technical problems.

[0006] In a first aspect, one or more embodiments of this specification provide a chip computing power testing method, including: determining the test environment of the chip to be tested, wherein the chip's required computing power varies according to preset rules in the test environment;

[0007] The chip under test is run in the test environment;

[0008] For a running chip under test, first change data, second change data, process delay, and accuracy of the chip under test are collected. The first change data characterizes the chip temperature change over time, and the second change data characterizes the output computing power change over time.

[0009] The computing power fluctuation of the chip under test is evaluated based on the first change data, the second change data, the process delay, and the accuracy.

[0010] Furthermore, the operating environment of the chip under test is determined, including:

[0011] Determine the chip's operating temperature and the percentage of its computing power in the test environment, where the percentage of computing power is the ratio of output computing power to baseline computing power.

[0012] Furthermore, the test environment includes multiple scenarios, each with different computing power requirements; and

[0013] The chip's required computing power varies according to preset rules, including:

[0014] The multiple scenarios are switched according to a preset cycle or time sequence.

[0015] Furthermore, the latency and accuracy of the data acquisition process include:

[0016] Collect process delays and accuracy rates for each of the described scenarios.

[0017] Furthermore, for each scenario, the computing power fluctuation of the chip under test is evaluated based on the first change data, the second change data, the process latency, and the accuracy, including:

[0018] Based on the first and second change data, determine the curve of output computing power changing with temperature; and

[0019] The computing power fluctuation of the chip under test is evaluated based on the curve of output computing power changing with temperature, the process delay, and the accuracy.

[0020] Secondly, embodiments of this application provide a chip computing power testing device, including: a determination module, an operation module, an acquisition module, and a data processing module;

[0021] The determining module is used to determine the test environment of the chip to be tested, in which the computing power required by the chip changes according to a preset rule;

[0022] The running module is used to run the chip under test in the test environment;

[0023] The acquisition module is used to acquire first change data, second change data, process delay, and accuracy of the chip under test during operation. The first change data characterizes the chip temperature change over time, and the second change data characterizes the output computing power change over time.

[0024] The data processing module is used to evaluate the computing power fluctuation of the chip under test based on the first change data, the second change data, the process delay, and the accuracy.

[0025] Furthermore, the determining module is used to determine the chip's operating environment temperature and the chip's computing power percentage in the test environment, wherein the computing power percentage is the percentage of the output computing power to the benchmark computing power.

[0026] Furthermore, the test environment includes multiple scenarios, each with different computing power requirements; and,

[0027] The determining module is used to switch the multiple scenarios according to a preset cycle or time sequence.

[0028] Furthermore, the data processing module is used to determine the curve of output computing power changing with temperature based on the first change data and the second change data; determine the computing power loss based on the process delay and the accuracy; and evaluate the computing power fluctuation of the chip under test based on the curve of output computing power changing with temperature and the computing power loss.

[0029] Thirdly, embodiments of this application provide a computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, which, when executed by a processor, implements the chip computing power testing method as described in any of the first aspects.

[0030] Compared with the prior art, this application can achieve at least the following technical effects:

[0031] Addressing the constantly changing computing power requirements in real-world driving scenarios, this application focuses on evaluating the computing power fluctuations of chips. Specifically, the required computing power is continuously varied in a test environment. Simultaneously, data reflecting these variations (first variation data, second variation data, process latency, and accuracy) is collected to quantify these changes. Finally, based on the first variation data, second variation data, process latency, and accuracy, an evaluation of the computing power fluctuations is completed, enabling an accurate assessment of the chip's computing power under near-real-world conditions. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 is a flowchart of a chip computing power testing method provided in one or more embodiments of this specification;

[0034] Figure 2 is a schematic diagram illustrating the changes in output computing power and demand computing power over time according to one or more embodiments of this specification;

[0035] Figure 3 is a schematic diagram illustrating the variation of process delay and required computing power over time according to one or more embodiments of this specification;

[0036] Figure 4 is a schematic diagram illustrating the changes in accuracy, output computing power, and required computing power over time according to one or more embodiments of this specification;

[0037] Figure 5 is a schematic diagram showing the changes in temperature, output computing power, and required computing power over time provided in one or more embodiments of this specification;

[0038] Figure 6 is a schematic diagram of the structure of a chip computing power testing device provided in one or more embodiments of this specification. Detailed Implementation

[0039] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0040] The output computing power, process latency, and accuracy obtained through DIMPS (Dhrystone Million Instructions Per Second per Megahertz) testing represent performance results under constant conditions, which is common practice in the industry. However, this measurement method only represents the chip's baseline computing power. Because chip design and operators are optimized for application environments, benchmark tests cannot fully represent the chip's actual computing power under real-world conditions. For example, in a real-world environment, only 50 computing power is needed for driving on a flat road. If only the baseline computing power is considered, any computing power greater than 50 would suffice. However, real-world scenarios are far more complex than simply driving on a flat road; sudden braking, turning, and inclines / declines are common occurrences. Each scenario has different computing power requirements, meaning that the required computing power in real-world scenarios is constantly changing. This constant change in required computing power cannot be addressed solely by the baseline computing power. When the required computing power changes, the chip's output computing power must also change. In this process, the output computing power cannot always match the required computing power; this mismatch is computing power fluctuation. Therefore, computing power fluctuation is a direct reflection of chip performance in real-world scenarios.

[0041] To evaluate computing power fluctuations, this application provides a computing power testing method, as shown in Figure 1, including the following steps:

[0042] Step 1: Determine the test environment for the chip to be tested.

[0043] In this embodiment of the application, in order to simulate a real environment, the computing power required by the chip in the test environment varies according to a preset rule.

[0044] Step 2: Run the chip under test in the test environment.

[0045] In this embodiment, the chip is tested in an environment where the required computing power changes continuously. Specifically, multiple curves, slopes, or road conditions can be set in the test environment to reflect the constantly changing computing power requirements.

[0046] The method for setting up a scene is as follows:

[0047] S1. Determine the data collection location category: roads, cities, residents, campuses, pedestrians.

[0048] S2. Determine the data types to be acquired: grayscale image (png), color image (png), 3D Velodyne point cloud (bin), GPS / IMU data (txt), calibration file, tag file (xml).

[0049] S3. Expand the data type description:

[0050] Column 1 String: Object category, mainly including 8 categories: cars, trucks, lorries, pedestrians, sitting people, cyclists, trams, and miscellaneous items.

[0051] Column 2 Float: Whether it is truncated, the value is between 0 and 1.

[0052] Column 3 Int: Whether it is occluded, with 0, 1, 2, 3 indicating the degree of occlusion.

[0053] Column 4 Rad: Observation angle alpha, expressed in radians, ranging from -π to π.

[0054] Column 5-8 Float: 2D bounding box of an object, xmin, ymin, xmax, ymax.

[0055] Column 9-11 Float: 3D size of the object, h, w, l.

[0056] Column 12-14 Float: Object position, x, y, z in the camera coordinate system.

[0057] Column 15 Rad: Spatial orientation of the object, representing the angle between the object's forward direction and the x-axis of the camera coordinate system, ranging from -π to π.

[0058] Column 16 Float: Confidence score.

[0059] The above methods can simulate various scenarios and road conditions in a test environment. It should be noted that the above embodiments are preferred solutions of this application, and those skilled in the art will conceive of other methods to achieve various scenarios and road conditions in a simulated environment.

[0060] Step 3: For the chip under test in operation, collect the first change data, the second change data, the process delay, and the accuracy of the chip under test.

[0061] In this embodiment, the first change data is used to characterize the chip temperature change over time, and the second change data is used to characterize the output computing power change over time.

[0062] Based on the simulation technology described in step 2, virtual sensors can be set up to collect the chip's temperature, addressing the initial change in data. Temperature significantly affects chip performance. In real-world scenarios, chip temperature inevitably rises, inevitably altering chip performance. Therefore, temperature is a primary factor influencing computing power fluctuations.

[0063] Regarding the second change in data, the output computing power is the amount of data the chip can process per unit time, reflecting the chip's computing capabilities. Chips have various computing modules, such as a CPU, GPU, and NPU, but this application primarily tests the computing power of the CPU within the chip. Output computing power can be measured using specialized software, such as benchmarks.

[0064] Process latency refers to the waiting time within a chip during the completion of instructions, algorithms, and processing. Data retrieval and storage within the chip require time. After completing an instruction, the computing unit needs to store the old data and retrieve the new data before it can perform calculations on the new data; this time is called process latency. Therefore, process latency can cause fluctuations in computing power. In real-world scenarios, process latency originates from four aspects: 1. Instruction latency: the time required from instruction fetching to execution completion; 2. Data latency: the time required to read data from memory or other storage devices; 3. Communication latency: the time required for communication between cores in a multi-core processor; 4. Cache latency: the latency when accessing the CPU cache. Therefore, in real-world scenarios, process latency has a more significant impact on computing power fluctuations. Process latency is the difference between the actual and theoretical values ​​of data processed by the chip.

[0065] Regarding accuracy, it doesn't actually affect computing power output. However, during testing and application, erroneous data is discarded by default. Therefore, higher accuracy during chip computation means higher output computing power and less computing power loss in dynamic scenarios. Furthermore, accuracy is a comprehensive reflection of the performance of various modules within the chip. In real-world scenarios, as chip temperature increases, the performance of each module changes, causing fluctuations in accuracy and consequently, fluctuations in computing power during testing. Accuracy is the ratio of erroneous data output to all output data within a given time period.

[0066] Step 4: Evaluate the degree of computing power fluctuation of the chip under test based on the first change data, the second change data, the process delay, and the accuracy.

[0067] In the embodiments of this application, as mentioned above, in real-world scenarios, the first changed data, the second changed data, the process delay, and the accuracy all affect the fluctuation of computing power. Therefore, it is possible to select one or more of the first changed data, the second changed data, the process delay, and the accuracy to evaluate the fluctuation of computing power.

[0068] For example, accuracy and process latency can be evaluated from the perspective of computing power loss when a chip switches between multiple scenarios. The greater the computing power loss, the more prone it is to computing power fluctuations. Each chip has its own operating temperature range; the chip's temperature fluctuation can be determined based on the first change data. Then, computing power fluctuation can be determined based on the chip's temperature fluctuation; the faster the temperature change and the closer it is to the chip's limit temperature, the greater the computing power fluctuation. The second change data can directly reflect the change in output computing power, thus directly obtaining the magnitude of the computing power change; the greater the magnitude of the computing power change, the greater the computing power fluctuation. Furthermore, the above evaluation methods can be combined arbitrarily to obtain a more objective evaluation.

[0069] Specifically, as shown in Figure 2, as the computing power required by the scene changes, the first dashed red box on the left shows that the output computing power lags behind the required computing power. The longer this delay, the higher the chip's latency in responding to sudden changes in computing power. The second red dashed box on the left shows that when the required computing power decreases from 80 to 55, the chip's output computing power also decreases lagging and is lower than the required computing power. As the computing power recovers, it gradually increases, but soon the required computing power suddenly increases to 90. At this point, the output computing power gradually recovers and increases, quickly reaching 90 computing power, indicating that the chip has the ability to adapt to scene changes. The system has a certain predictive ability; the faster the response, the stronger the predictive ability, and the smaller the corresponding computing power fluctuation. The third dashed box also shows a situation where the output computing power is lower than the required computing power during the computing power reduction process, but it quickly stabilizes and matches the required computing power. This indicates that the scheduler predicted future computing power changes and aligned them with the required computing power to reduce power consumption. The fourth red dashed box also shows a sudden change in required computing power. The decrease in computing power indicates that the chip temperature or other factors caused computing power instability, but the output computing power quickly recovered to the required computing power. The shorter the recovery time, the smaller the computing power fluctuation. Furthermore, the sudden drop in the graph corresponds to computing power loss; the smaller the drop, the smaller the computing power fluctuation.

[0070] As shown in Figure 3, the process latency increases with increasing computing power demand and decreases with decreasing computing power demand, which is consistent with normal test results. However, looking at the degree of change in the process latency curve, specifically the latency within the red dashed box in the figure, the latency is higher when the demand computing power decreases from 75 to 55 than when it increased to 44 MHz 50 seconds prior. Similarly, the latency is higher when the demand computing power decreases from 90 to 55 than when it decreased from 75 to 55. This is because the chip temperature increases during the test, leading to greater internal heat dissipation pressure and consequently increasing latency. Later in the test, when the demand computing power recovers to 55, the latency decreases, but not to the level seen at the beginning of the test when the chip temperature was lower. Therefore, it can be seen that chip temperature has a significant impact on process latency, indicating that chip temperature is crucial in influencing computing power fluctuations and that a combination of chip temperature and process latency can be used to evaluate computing power fluctuations.

[0071] As shown in Figure 4, accuracy is related to the required computing power and decreases accordingly as the demand increases. In the figure, because accuracy affects output computing power efficiency (higher efficiency means lower computing power loss), a lag occurs when the required computing power increases. When the required computing power decreases, the output computing power also decreases accordingly. However, due to the accuracy issue, when the required computing power drops to its lowest point, the output computing power will be even lower to reduce the impact of accuracy; that is, when computing power efficiency decreases, the output computing power decreases, leading to increased computing power fluctuations. As the required computing power stabilizes and accuracy improves, the output computing power will slowly climb to a stable level; that is, when computing power efficiency increases, the output computing power increases, thus reducing computing power fluctuations. During testing, accuracy also increases with test pressure. In the later stages of testing, the accuracy under the same required computing power will be lower, which also affects the situation in the figure where the output exceeds the required computing power at 250 seconds, due to the impact of decreasing accuracy. Therefore, the stability of chip computing power can also be evaluated by the ratio of output computing power to required computing power; the lower the ratio, the smaller the computing power fluctuations.

[0072] Similar to process latency, accuracy also changes with the required computing power, but higher accuracy is always better. As the testing process lengthens, it becomes apparent that under the same required computing power conditions, the accuracy in the later stages of testing is lower than in the earlier stages. This is related to the increased chip temperature in the later stages of testing. From an evaluation perspective, the chip with the smallest changes in its various parameters (process latency, output computing power, and accuracy) under the same required computing power can be considered to have higher output computing power reliability. Therefore, it can be seen that chip temperature has a significant impact on accuracy, indicating that chip temperature is an important factor affecting computing power fluctuations, and that computing power fluctuations can be evaluated by combining chip temperature and accuracy.

[0073] As shown in Figure 5, temperature is a parameter used to observe the thermal power control of a chip. It can be used to evaluate the chip's manufacturing process capabilities, thermal design, and stability. The trend in the figure shows that when the required computing power is 75, the temperature remains stable, indicating that the heat dissipation capacity can control the temperature under this condition. When the required computing power reaches 90, both the temperature and the output computing power increase, which is consistent with the chip's physical characteristics. However, due to limited heat dissipation, the chip temperature reaches a peak of 100 degrees Celsius. When the required computing power decreases from 90 to 55, the temperature will not return to its previous level due to the limited heat dissipation capacity. This will lead to the temperature reaching 100 when the required computing power increases to 70. At this point, the chip can be considered to have reached its maximum heat dissipation value. At this point, the output computing power is higher than the required computing power, indicating that the chip is using more computing power to mitigate the impact of temperature. The extent to which this output computing power exceeds the required computing power can be used to evaluate the stability of the chip's output computing power.

[0074] Therefore, the technical solution of this application simulates real-world scenarios by setting up constantly changing scenarios. By collecting first and second change data, as well as process latency and accuracy, a data foundation is laid for improving the accuracy of evaluating computing power fluctuations. Finally, computing power fluctuations can be evaluated from multiple dimensions, thereby improving the applicability and accuracy of computing power testing.

[0075] In this embodiment of the application, when determining the operating environment of the chip to be tested, the chip's operating environment temperature and the chip's computing power percentage in the test environment are determined, wherein the computing power percentage is the percentage of output computing power to the baseline computing power.

[0076] Specifically, because multiple scenarios need to be set up during the testing process, and the ambient temperature of each scenario may be different (for example, the temperature on a cloudy day is usually lower than that on a sunny day), the ambient temperature will affect the final result. To eliminate this effect, this application defines a test temperature variation to replace the chip temperature. The definition of test temperature variation is:

[0077] Chip operating temperature - test ambient temperature = test temperature change

[0078] Therefore, when determining the operating environment of the chip to be tested, the chip's operating temperature should be determined.

[0079] The required computing power for the test simulation environment is set according to the percentage of the chip's output computing power to the baseline computing power. This setting avoids the impact of different computing power of chips of different sizes, while allowing for more flexible implementation of various scenarios and reducing the impact between different chip specifications.

[0080] In this embodiment, the test environment includes multiple scenarios, each with different computing power requirements. The chip's computing power requirement changes according to preset rules, including switching between the multiple scenarios according to a preset cycle or sequence. As mentioned earlier, temperature change is a significant factor affecting computing power fluctuations; therefore, testing computing power fluctuations requires changing the chip's temperature during the test. To achieve this, the test environment needs to set up multiple scenarios, each with different computing power requirements. For example, a flat road and a turn are two scenarios in the test environment. When changing from a flat road to a turn, the chip's computing power requirement increases, which means increased power consumption, leading to a rise in chip temperature. Therefore, if the tester wants to observe the computing power fluctuations of the chip during a 10°C increase, they can set up 50 turns and 50 flat roads, allowing the chip temperature to gradually increase and providing the tester with relevant data. Preferably, to ensure a steady rather than rapid temperature increase, a turn can be selected every minute, or a flat road scenario can be followed by two turn scenarios, thus ensuring a stable increase in chip temperature.

[0081] In this embodiment of the application, the temperature of each scene in the test environment will change, that is, the temperature of each scene will have a certain temperature. In order to make the computing power evaluation closer to the actual scene, the tester can analyze the computing power fluctuation for each scene in the test environment. Specifically, for each scene, based on the first change data and the second change data, the curve of output computing power changing with temperature is determined; based on the curve of output computing power changing with temperature, the process delay and the accuracy, the computing power fluctuation of the chip under test is evaluated.

[0082] To illustrate the feasibility of the above solution, this application provides a specific example:

[0083] For the specific simulated scenario of "rainy mountain road," the design for changes in computing power first defines that the occurrence of rain means the computing power in the simulated scenario cannot be lower than 60% of the benchmark computing power of the test chip. When a curve appears, the required computing power will increase to 100% and remain at that level for the time it takes to navigate the curve. After exiting the curve, the required computing power will return to 60%. This "rainy mountain road" scenario has 100 curves. It is known that increasing computing power will increase the chip's operating temperature, so the temperature during testing will also increase. As the test progresses, the accumulated temperature will cause a degradation in output computing power, process latency, and accuracy. As the number of tests increases, the chip's operating temperature will eventually reach a constant level due to limited heat dissipation. Consequently, the fluctuations in output computing power, process latency, and accuracy will decrease once the temperature stabilizes. Finally, the reliability of the computing power is assessed by comparing the relative changes in output computing power, process latency, and accuracy with the baseline computing power at this point. For example, the ratio of the change in output computing power to the change in baseline computing power is used; the smaller the relative change, the smaller the computing power fluctuation. Simultaneously, the time required for the chip to reach this state of minimal computing power fluctuation is recorded. A longer time indicates that the chip's computing power is less affected by temperature and can flexibly adapt to changes in computing power, resulting in smaller computing power fluctuations. Conversely, a shorter time indicates that the chip is more affected by temperature, quickly reaching its maximum temperature and experiencing rapid degradation in computing power, suggesting poor flexibility in computing power allocation to changing scenarios and greater computing power fluctuations.

[0084] This application provides a chip computing power testing device, as shown in FIG6, including: a determination module 201, a running module 202, a data acquisition module 203 and a data processing module 204;

[0085] The determination module 201 is used to determine the test environment of the chip to be tested, in which the computing power required by the chip changes according to preset rules;

[0086] The running module 202 is used to run the chip under test in a test environment;

[0087] The acquisition module 203 is used to acquire first change data, second change data, process delay, and accuracy of the chip under test during operation. The first change data characterizes the chip temperature change over time, and the second change data characterizes the output computing power change over time.

[0088] The data processing module 204 is used to evaluate the degree of computing power fluctuation of the chip under test based on the first change data, the second change data, the process delay, and the accuracy.

[0089] In this embodiment of the application, the determining module 201 is used to determine the chip's operating environment temperature and the chip's computing power percentage in the test environment, wherein the computing power percentage is the percentage of the output computing power to the benchmark computing power.

[0090] In this embodiment of the application, the test environment includes multiple scenarios, each with different computing power requirements; and,

[0091] The determination module 201 is used to switch the multiple scenarios according to a preset period or time sequence.

[0092] In this embodiment of the application, the data processing module 204 is used to determine the curve of output computing power changing with temperature based on the first change data and the second change data; determine the computing power loss based on the process delay and the accuracy; and evaluate the computing power fluctuation of the chip under test based on the curve of output computing power changing with temperature and the computing power loss.

[0093] This application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the chip computing power testing method described in any of the above embodiments.

[0094] It should be noted that the embodiments concerning storage media in this specification and the embodiments concerning blockchain-based service provision methods in this specification are based on the same inventive concept. Therefore, the specific implementation of this embodiment can be referred to the implementation of the corresponding blockchain-based service provision method described above, and the repeated parts will not be described again.

[0095] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0096] In the 1930s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology). However, with technological advancements, many improvements to the methodology today can be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that an improvement to the methodology cannot be implemented using hardware physical modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must also be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0097] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0098] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0099] For ease of description, the above apparatus is described by dividing it into various functional units. Of course, when implementing the embodiments of this specification, the functions of each unit can be implemented in one or more software and / or hardware.

[0100] Those skilled in the art will understand that one or more embodiments of this specification can be provided as a method, system, or computer program product. Therefore, one or more embodiments of this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0101] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0102] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0103] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0104] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0105] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0106] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0107] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0108] One or more embodiments of this specification can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a particular task or implement a particular abstract data type. One or more embodiments of this specification can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0109] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0110] The above description is merely an embodiment of this document and is not intended to limit the scope of this document. Various modifications and variations can be made to this document by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this document should be included within the scope of the claims of this document.

Claims

1. A chip computing power testing method, characterized in that... include: Determine the test environment for the chip to be tested, in which the chip's computing power requirements vary according to preset rules; The chip under test is run in the test environment; For the chip under test in operation, first change data, second change data, process delay and accuracy of the chip under test are collected, wherein the first change data is used to characterize the chip temperature change over time, and the second change data is used to characterize the output computing power change over time. as well as The computing power fluctuation of the chip under test is evaluated based on the first change data, the second change data, the process delay, and the accuracy. The test environment includes multiple scenarios, each with different computing power requirements; and The chip's required computing power varies according to preset rules, including: The multiple scenarios are switched according to a preset cycle or time sequence; Data acquisition latency and accuracy include: Collect process delays and accuracy under each of the aforementioned scenarios; For each scenario, the computing power fluctuation of the chip under test is evaluated based on the first change data, the second change data, process latency, and accuracy, including: Based on the first and second change data, determine the curve of output computing power changing with temperature; and The computing power fluctuation of the chip under test is evaluated based on the curve of output computing power changing with temperature, the process delay, and the accuracy.

2. The method according to claim 1, characterized in that, Determine the operating environment of the chip under test, including: Determine the chip's operating temperature and the percentage of its computing power in the test environment, where the percentage of computing power is the ratio of output computing power to baseline computing power.

3. A chip computing power testing device, characterized in that... include: The module consists of a determination module, a running module, a data acquisition module, and a data processing module. The determining module is used to determine the test environment of the chip to be tested, in which the computing power required by the chip changes according to a preset rule; The running module is used to run the chip under test in the test environment; The acquisition module is used to acquire first change data, second change data, process delay, and accuracy of the chip under test during operation. The first change data characterizes the chip temperature change over time, and the second change data characterizes the output computing power change over time. The data processing module is used to evaluate the degree of computing power fluctuation of the chip under test based on the first change data, the second change data, the process delay, and the accuracy of the chip under test. The test environment includes multiple scenarios, each with different computing power requirements; and, The determining module is used to switch the multiple scenarios according to a preset period or time sequence; The data processing module is used to determine the curve of output computing power changing with temperature based on the first change data and the second change data; The computing power loss is determined based on the process delay and the accuracy; and the computing power fluctuation of the chip under test is evaluated based on the curve of the output computing power changing with temperature and the computing power loss.

4. The apparatus according to claim 3, characterized in that, The determining module is used to determine the chip's operating environment temperature and the chip's computing power percentage in the test environment, wherein the computing power percentage is the percentage of the output computing power to the benchmark computing power.

5. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the chip computing power testing method as described in any one of claims 1 to 2.

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