Verification method and device of bus assembly, bus assembly, medium and product

Abstract

The application relates to a verification method and device of a bus assembly, the bus assembly, a medium and a product. The method comprises the following steps: after receiving a data packet to be transmitted, allocating a corresponding data packet identifier to the data packet; in the process of transmitting the data packet and the data packet identifier by the bus assembly, sampling the data packet to obtain input data packet information of the data packet, and storing the input data packet information of the data packet and the data packet identifier in association; after the data packet and the corresponding data packet identifier are transmitted to a design under test (DUT) of the bus assembly, sampling data packets output by an output channel of the DUT to obtain output data packet information of the data packet and the data packet identifier; and verifying the data transmission accuracy of the bus assembly according to the output data packet information and the input data packet information corresponding to the data packet identifier. The method can improve the accuracy and efficiency of verification and reduce the cost.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, bus component, medium, and product for verifying a bus component. Background Technology

[0002] With the rapid development of the SOC (System on Chip) design industry and the increasing demands of chip applications, the application requirements of bus components are increasing. However, these component IPs usually perform conversion and transformation operations on the input data packets before outputting them, making it difficult to directly compare the data at both ends of the input and output to verify the correctness of the DUT (Device Under Test) function, as is the case with traditional verification methods. This can easily lead to missed verifications and incorrect verifications. At the same time, the conversion of data packets can cause the loss of original information, making data flow tracing difficult.

[0003] Traditional bus component verification uses a method of directly comparing data at the input and output ends to ensure the correctness of the bus component's function. However, as the design complexity increases and the number of channels increases, data packets undergo multiple transformations within the component, and the information carried by the output data packets changes. If the traditional method is continued, it is easy to encounter false verifications or missed verifications, resulting in a decrease in the verification efficiency and quality of verification test cases, and thus increasing chip costs. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, bus component, medium, and product for verifying bus components to address the aforementioned technical problems, thereby improving the accuracy and efficiency of verification and reducing costs.

[0005] Firstly, this application provides a method for verifying a bus component, including:

[0006] Upon receiving the data packet to be transmitted, a corresponding data packet identifier is assigned to the data packet;

[0007] During the transmission of the data packet and data packet identifier by the bus component, the data packet is sampled to obtain the input data packet information of the data packet, and the input data packet information and data packet identifier of the data packet are associated and stored.

[0008] After the data packet and its corresponding data packet identifier are transmitted to the design under test (DUT) of the bus component, the data packets output by the output channel of the DUT are sampled to obtain the output data packet information and data packet identifier of the data packet.

[0009] The accuracy of data transmission of the bus component is verified based on the output data packet information and input data packet information corresponding to the data packet identifier.

[0010] In one embodiment, the method further includes:

[0011] Select any free bit in the bus component as the target identifier bit;

[0012] The assigned data packet identifier is added to the target identifier bit; wherein the target identifier bit is used to transmit the data packet identifier.

[0013] In one embodiment, selecting any free bit in the bus component as the target identifier bit includes:

[0014] Based on the historical verification information of the bus component, the historical identifier bit is determined; wherein, the historical verification information is information generated during the process of verifying the data transmission accuracy of the bus component in a historical period;

[0015] Based on the historical identifier bits, determine the number of times each bit in the bus component has been used;

[0016] Select the least used bit from the free bits and use it as the target identifier bit.

[0017] In one embodiment, verifying the data transmission accuracy of the bus component based on the output data packet information and input data packet information corresponding to the data packet identifier includes:

[0018] Based on the data packet identifier corresponding to the data packet, the input data packet information corresponding to the data packet identifier is read from the core storage module of the bus component;

[0019] The consistency comparison result of the data packet is obtained by comparing the output data packet information and the input data packet information.

[0020] Based on the consistency comparison results, the accuracy of data transmission of the bus component is verified.

[0021] In one embodiment, the associated storage of the input data packet information and the data packet identifier of the data packet includes:

[0022] The input data packet information and data packet identifier of the data packet are associated and stored in the data packet recorder of the bus component;

[0023] After the data packet and its corresponding identifier are transmitted to the design under test (DUT) of the bus component, the method further includes:

[0024] The transmitted data packets are sampled at a preset node of the DUT to obtain the data packet identifier;

[0025] Based on the data packet identifier, the input data packet information corresponding to the data packet identifier in the data packet recorder is synchronized to the core storage module of the bus component.

[0026] In one embodiment, the method further includes:

[0027] In response to the inconsistency of the consistency comparison result, an error alarm message is generated based on the data packet identifier.

[0028] Secondly, this application also provides a verification device for a bus component, comprising:

[0029] The identifier allocation module is used to assign a corresponding data packet identifier to the data packet after receiving the data packet to be transmitted;

[0030] The first sampling module is used to sample the data packet and the data packet identifier during the transmission of the data packet and the data packet identifier by the bus component, obtain the input data packet information of the data packet, and store the input data packet information and the data packet identifier together.

[0031] The second sampling module is used to sample the data packets output by the output channel of the DUT after the data packet and the corresponding data packet identifier are transmitted to the DUT of the bus component, so as to obtain the output data packet information and data packet identifier of the data packet.

[0032] The component verification module is used to verify the accuracy of data transmission of the bus component based on the output data packet information and input data packet information corresponding to the data packet identifier.

[0033] Thirdly, this application also provides a bus component, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0034] Upon receiving the data packet to be transmitted, a corresponding data packet identifier is assigned to the data packet;

[0035] During the transmission of the data packet and data packet identifier by the bus component, the data packet is sampled to obtain the input data packet information of the data packet, and the input data packet information and data packet identifier of the data packet are associated and stored.

[0036] After the data packet and its corresponding data packet identifier are transmitted to the design under test (DUT) of the bus component, the data packets output by the output channel of the DUT are sampled to obtain the output data packet information and data packet identifier of the data packet.

[0037] The accuracy of data transmission of the bus component is verified based on the output data packet information and input data packet information corresponding to the data packet identifier.

[0038] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0039] Upon receiving the data packet to be transmitted, a corresponding data packet identifier is assigned to the data packet;

[0040] During the transmission of the data packet and data packet identifier by the bus component, the data packet is sampled to obtain the input data packet information of the data packet, and the input data packet information and data packet identifier of the data packet are associated and stored.

[0041] After the data packet and its corresponding data packet identifier are transmitted to the design under test (DUT) of the bus component, the data packets output by the output channel of the DUT are sampled to obtain the output data packet information and data packet identifier of the data packet.

[0042] The accuracy of data transmission of the bus component is verified based on the output data packet information and input data packet information corresponding to the data packet identifier.

[0043] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0044] Upon receiving the data packet to be transmitted, a corresponding data packet identifier is assigned to the data packet;

[0045] During the transmission of the data packet and data packet identifier by the bus component, the data packet is sampled to obtain the input data packet information of the data packet, and the input data packet information and data packet identifier of the data packet are associated and stored.

[0046] After the data packet and its corresponding data packet identifier are transmitted to the design under test (DUT) of the bus component, the data packets output by the output channel of the DUT are sampled to obtain the output data packet information and data packet identifier of the data packet.

[0047] The accuracy of data transmission of the bus component is verified based on the output data packet information and input data packet information corresponding to the data packet identifier.

[0048] The aforementioned verification method, apparatus, bus component, medium, and product for the bus component, upon receiving a data packet to be transmitted, assigns a corresponding data packet identifier to the data packet. During the transmission of the data packet and data packet identifier by the bus component, the data packet is sampled to obtain the input data packet information, and the input data packet information and data packet identifier are associated and stored. After the data packet and its corresponding data packet identifier are transmitted to the Design Under Test (DUT) of the bus component, the data packets output by the DUT's output channel are sampled to obtain the output data packet information and data packet identifier. Based on the output data packet information and input data packet information corresponding to the data packet identifier, the accuracy of data transmission of the bus component is verified. This scheme, by assigning a unique data packet identifier to each data packet and associating and storing the sampled information on both the input and output sides, achieves unique identification and tracking of data packets throughout the entire transmission link of the bus component. When a transmission defect is detected, it is not necessary to compare all input and output data packet by packet; the corresponding input and output information can be quickly located using the data packet identifier, significantly shortening the defect location time, improving verification efficiency and quality, and reducing chip costs. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a flowchart illustrating a verification method for a bus component in one embodiment;

[0051] Figure 2 This is a schematic diagram of the process of injecting packet identifiers in one embodiment;

[0052] Figure 3 This is a flowchart illustrating the process of verifying the accuracy of data transmission of a bus component in one embodiment;

[0053] Figure 4 This is a schematic diagram illustrating the process of synchronizing data to the core storage module in one embodiment;

[0054] Figure 5 This is a schematic diagram of the structure of a bus component in one embodiment;

[0055] Figure 6 This is a flowchart illustrating a verification method for a bus component in another embodiment;

[0056] Figure 7 This is a structural block diagram of a verification device for a bus component in one embodiment;

[0057] Figure 8 This is an internal structure diagram of a bus component in one embodiment. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0059] The bus component verification method provided in this application can be applied to application environments that verify the correctness of data transmission of the bus component. The bus component verification method provided in this application can be executed by different modules within the bus component.

[0060] In one exemplary embodiment, such as Figure 1 As shown, a verification method for a bus component is provided. Taking the application of this method to a bus component as an example, the specific steps include:

[0061] S101: After receiving the data packet to be transmitted, assign a corresponding data packet identifier to the data packet.

[0062] The data packet identifier is a unique tag assigned to each data packet to be transmitted. Its core function is to identify, track, and associate data packets throughout the entire data transmission chain. The number of data packets to be transmitted can be one or multiple.

[0063] In this embodiment, a tag generator is integrated into the bus component. It continuously monitors for new data packets to be transmitted by detecting the data validity signal of the bus input channel. When the data validity signal is detected, the tag generator assigns a unique data packet identifier to the data packet.

[0064] For example, each data packet can be assigned a unique identifier as a label by periodically randomizing or accumulating the identifiers according to the sending order. All subsequent sampling, data, and command comparisons rely on this unique identifier. This allows for easy derivation of all information for each data packet from its identifier within the environment, without altering the transmission bus.

[0065] S102, during the process of transmitting data packets and data packet identifiers in the bus component, the data packets are sampled to obtain the input data packet information, and the input data packet information and data packet identifier are associated and stored.

[0066] Among them, the input data packet information refers to the structured data set obtained by sampling the full-dimensional characteristics of the data packet and its transmission environment during the transmission of data packets by the bus component.

[0067] In this embodiment, an upstream packet driver is integrated into the bus component to drive the packets. At the same time, the packets are sampled and the input packet information of the sampled packets is stored in the packet logger.

[0068] The upstream packet driver performs parallel sampling of packets and packet identifiers in the bus transmission path based on a preset sampling clock, generating complete input packet information. It then generates a sampling association index for the currently sampled input packet information and packet identifier. The index includes: sampling timestamp, bus channel number, and sampling batch number, used to uniquely identify this sampling record.

[0069] In one embodiment, the data packet can be either a write operation data packet or a read operation data packet. For read operation data packets, the upstream packet driver samples the read data packets returned from the downstream as the source of the read direction data to be compared, and checks the correctness of the DUT read data. For write operation data packets, the upstream packet driver samples the data packets and stores the samples in the packet logger. The sampled data will be used as golden data to check the DUT's read and write data later.

[0070] S103 After the data packet and the corresponding data packet identifier are transmitted to the DUT of the bus component, the data packet output by the DUT's output channel is sampled to obtain the output data packet information and data packet identifier.

[0071] Among them, the output data packet information refers to the structured data set obtained by sampling the full-dimensional characteristics of the data packets processed by the DUT and their transmission environment in the output channel of the DUT.

[0072] In this embodiment of the application, a downstream data sampler is integrated into the bus component to sample the output of all channels simultaneously. At this time, regardless of which output channel the data packet comes from, the data packet identifier can be easily obtained and the data packet can be restored.

[0073] Furthermore, in one embodiment, the downstream data sampler also samples the downstream output commands of the DUT and sends the command information to the core storage module (golden memory) of the bus component, where the commands are reconstructed based on the tags. Simultaneously, it samples the downstream write-direction data packets and sends the command information to one end of the corresponding SCB to complete the comparison of the correctness of the write data.

[0074] S104 verifies the accuracy of data transmission of the bus component based on the output data packet information and input data packet information corresponding to the data packet identifier.

[0075] After detecting that the storage-ready flag of the associated storage module and the sampling task completion signal of the output sampling module are both set, the verification startup process begins, and the working state is switched to verification. Further, using the data packet identifier as an index, the input data packet information associated with the data packet identifier is obtained, and the input data packet information is compared with the output data packet information for consistency. Finally, based on the comparison results, the data transmission accuracy of the bus component is verified.

[0076] In the aforementioned verification method for the bus component, after receiving the data packet to be transmitted, a corresponding data packet identifier is assigned to the data packet. During the transmission of the data packet and data packet identifier by the bus component, the data packet is sampled to obtain the input data packet information, and the input data packet information and data packet identifier are associated and stored. After the data packet and its corresponding data packet identifier are transmitted to the DUT of the bus component, the data packet output from the DUT's output channel is sampled to obtain the output data packet information and data packet identifier. Based on the output data packet information and input data packet information corresponding to the data packet identifier, the accuracy of data transmission of the bus component is verified. This scheme, by assigning a unique data packet identifier to each data packet and associating and storing the sampled information on both the input and output sides, achieves unique identification and tracking of data packets throughout the entire transmission link of the bus component. When a transmission defect is detected, it is not necessary to compare all input and output data packet by packet; the corresponding input and output information can be quickly located using the data packet identifier, significantly shortening the defect location time, improving verification efficiency and quality, and reducing chip costs.

[0077] Optionally, in one embodiment, such as Figure 2 As shown, a method for injecting packet identifiers is provided, which specifically includes the following steps:

[0078] S201, select any free bit in the bus component as the target identifier bit.

[0079] In this embodiment, the tag generator integrated in the bus component randomly selects which bits of the bus component will be used as the positions for adding data packet identifiers in this simulation before the simulation begins. To ensure balanced use of the bus bit width, a random method can be used to determine the bits. To ensure the efficiency of the overall verification environment, the randomization is only performed once before each simulation begins.

[0080] In one embodiment, historical identifier bits are determined based on historical verification information of the bus component; wherein, historical verification information is information generated during the process of verifying the accuracy of data transmission of the bus component in a historical period; the usage count of each bit in the bus component is determined based on the historical identifier bits; the bit with the fewest usage counts is selected from the idle bits as the target identifier bit. A global bit usage count counter can be initialized, with the counter index being the position of each bit in the bus frame structure, and the initial value being 0. The set of historical identifier bits in the historical verification information is traversed, and the usage count of each historical identifier bit is accumulated. After the statistics are completed, a bus bit usage count statistics table is generated, which includes the position of each bit, whether it is an idle bit, and the cumulative usage count.

[0081] All idle bits are selected from the bus bit usage statistics table to generate a candidate list of idle bits, and bits that are temporarily idle and have been reserved by the bus protocol are filtered out. The candidate list of idle bits is traversed to find the bit with the fewest usages. The selected bit is determined as the target identifier bit. In this embodiment, the selection of the target identifier bit is driven by historical verification information, prioritizing the use of the least used idle bits to avoid long-term, high-frequency use of some idle bits. During the long-term operation of the bus component, the usage frequency of all idle bits can be balanced, reducing hardware aging caused by excessive use of a single bit, thereby extending the lifespan of the bus component and improving system stability in long-term verification scenarios.

[0082] S202, add the allocated packet identifier to the destination identifier bit.

[0083] The target identifier bit is used to identify the data packet.

[0084] In this embodiment of the application, the allocated data packet identifier is filled into the selected target identifier bit.

[0085] In this embodiment, the data packet identifier is transmitted by reusing the idle bits of the bus component. This eliminates the need to modify the core frame structure of the bus protocol or add an independent identifier transmission channel, significantly reducing the deployment cost and compatibility risks of the solution.

[0086] Optionally, in an exemplary embodiment, such as Figure 3 As shown, a method for verifying the accuracy of data transmission of bus components is provided, specifically including the following steps:

[0087] S301 reads the input data packet information corresponding to the data packet identifier from the core storage module of the bus component according to the data packet identifier.

[0088] It should be noted that after associating and storing the input data packet information and data packet identifier, upon receiving a preset synchronization command, the association between the input data packet information and data packet identifier needs to be stored in the core storage module of the bus component.

[0089] After detecting that the sampling completion signal of the output sampling module is set, the input data packet information corresponding to the data packet identifier is read from the core storage module of the bus component according to the data packet identifier.

[0090] S302, compare the consistency between the output data packet information and the input data packet information to obtain the consistency comparison result of the data packet.

[0091] Based on the packet identifiers of all data packets, a list of identifiers to be verified is generated and sorted in order of identifier for easy batch processing. A multi-dimensional consistency comparison is performed between the output and input data packet information to generate comparison results.

[0092] Furthermore, in response to inconsistencies in the consistency comparison results, error alarm messages are generated based on the packet identifier. By generating structured error alarm messages based on packet identifiers when consistency comparison results are inconsistent, accurate early warning and rapid location of transmission defects in bus components are achieved.

[0093] S303 verifies the accuracy of data transmission of bus components based on the consistency comparison results.

[0094] In this embodiment, the comparison results are recorded for each data packet to be verified, and specific inconsistency details are associated with them. Combined with global comparison indicators, the verification conclusion of the data transmission accuracy of the bus component is determined.

[0095] In this embodiment, the core logic of reading data packet identifier index, multi-dimensional consistency comparison, and generating global conclusions enables efficient verification of the accuracy of bus component data transmission, thereby improving the accuracy and reliability of bus component verification.

[0096] Optionally, in one embodiment, the input data packet information and data packet identifier can be associated and stored in the data packet logger of the bus component. It should be noted that the data stored in the data packet logger will not be actively updated in the core storage module of the bus component. Based on this, such as... Figure 4 As shown, a method for synchronizing data to the core storage module of a bus component is provided, specifically including the following steps:

[0097] S401, the transmitted data packets are sampled at the preset node of the DUT to obtain the data packet identifier.

[0098] In this embodiment of the application, the bus component integrates a DUT sampler, which is used to sample and parse the tagged signal at a preset node of the DUT, and restore the data packet identifier of the sampled data packet by reversing the steps in the tag generator.

[0099] S402 synchronizes the input data packet information corresponding to the data packet identifier in the data packet recorder to the core storage module of the bus component according to the data packet identifier of the data packet.

[0100] Furthermore, the DUT sampler can accurately find the corresponding input data packet information from the data packet recorder by parsing the data packet identifier. The data packets sampled in this module must be the ones that will officially enter the subsequent data processing and transformation logic of the DUT. Therefore, at the same time, the update signal of the golden memory (core storage module) is triggered, and the write data in the data packet indexed according to the data packet identifier is updated to the corresponding position in the data buffer of the golden memory.

[0101] The DUT sampler also uses the data packet identifier to restore the original command information of the sampled command and sends it to one end of the corresponding SCB as reference data, waiting for the data at the other end to be compared.

[0102] The core storage module updates the data in the buffer according to the DUT access order, using it as reference data when comparing data in the read direction. Since all the data in the data buffer is sampled from upstream write data within the verification environment, and the DUT sampler ensures that the write data update order of the environment data buffer is consistent with the DUT update data order, using the data in the data buffer as reference data for the read direction achieves the goal of verifying the DUT's data paths in both read and write directions with maximum decoupling from the DUT, while also enabling accurate data comparison through marker signals.

[0103] From the outside, no matter how complex the internal design of the DUT is, the ultimate goal is to access the correct data at the correct address. Therefore, the data structure in the data buffer only has two elements, address and data, in a one-to-one correspondence, discarding redundant information. By using the data buffer to simulate the final requirement, it does not depend on the DUT channel state or bind to each channel of the DUT, thus completing a true end-to-end data comparison.

[0104] In addition, the core storage module restores the command based on the markers carried on the bus and matches it with the command sent out after sampling by the DUT to complete the command comparison.

[0105] In this embodiment, the input data packet information and data packet identifier are first associated and stored in the data packet logger (temporary storage unit), instead of being directly written to the core storage module. During the transmission of data packets by the bus components, the data packet logger undertakes the task of real-time storage. The core storage module does not need to respond to high-frequency real-time write requests; it only needs to receive the synchronization request of the input data packet information corresponding to the data packet identifier when the DUT preset node is triggered. This design significantly reduces the real-time access pressure on the core storage module, avoids the occupation of bus bandwidth or transmission resources due to storage operations, and ensures that the data transmission efficiency of the bus components is not affected by the verification process.

[0106] In one embodiment, such as Figure 5 The diagram illustrates the structure of a bus component. This bus component includes a tag generator, an upstream packet driver, a packet logger, golden memory (core storage module), a downstream sampling collector, a DUT sampler, a front-end module, and the DUT. The tag generator performs tag selection control (selecting any free bit in the bus component as the target identifier bit), generates unique tags (assigning a corresponding packet identifier to a packet), and injects tags (adding the assigned packet identifier to the target identifier bit). The upstream packet driver is used for write data sampling and read data sampling, storing the sampled write data in the write data logger. Golden memory is used for command parsing and data buffering. The downstream sampling collector performs command sampling and write data sampling on the multi-channel output data of the DUT. The DUT sampler samples the transmitted data packets at preset nodes of the DUT. The read data sampled by the upstream packet driver is compared with the corresponding read data stored in the data buffer; the write data stored in the data buffer is compared with the write data sampled by the downstream sampling collector; the golden memory parses the commands sampled by the downstream sampling collector, and compares the parsed commands with the commands sampled by the DUT sampler.

[0107] Figure 6 This is a flowchart illustrating a verification method for a bus component in another embodiment. Based on the above embodiments, this embodiment provides an optional example of a verification method for a bus component. (Combined with...) Figure 6 The specific implementation process is as follows:

[0108] S601 selects any free bit in the bus component as the target identifier bit.

[0109] Optionally, the historical identifier bits are determined based on the historical verification information of the bus component; wherein, the historical verification information is the information generated during the process of verifying the accuracy of data transmission of the bus component in a historical period; and the number of times each bit in the bus component is used is determined based on the historical identifier bits.

[0110] Select the least used bit from the free bits and use it as the target identifier bit.

[0111] S602, after receiving the data packet to be transmitted, assigns a corresponding data packet identifier to the data packet.

[0112] S603, add the allocated packet identifier to the destination identifier bit.

[0113] The target identifier bit is used to identify the data packet.

[0114] S604 samples the data packets during the transmission of data packets and data packet identifiers by the bus components to obtain the input data packet information.

[0115] S605 associates and stores the input data packet information and data packet identifier in the data packet logger of the bus component.

[0116] S606: After the data packet and its corresponding data packet identifier are transmitted to the DUT of the bus component, the transmitted data packet is sampled at the preset node of the DUT to obtain the data packet identifier.

[0117] S607 synchronizes the input data packet information corresponding to the data packet identifier in the data packet recorder to the core storage module of the bus component according to the data packet identifier of the data packet.

[0118] S608 samples the data packets output from the DUT's output channel to obtain the output data packet information and data packet identifier.

[0119] S609 reads the input data packet information corresponding to the data packet identifier from the core storage module of the bus component according to the data packet identifier.

[0120] S610, compare the consistency between the output data packet information and the input data packet information to obtain the consistency comparison result of the data packet.

[0121] Optionally, in response to an inconsistent consistency comparison result, an error alarm message is generated based on the packet identifier.

[0122] S611 verifies the accuracy of data transmission of bus components based on the consistency comparison results.

[0123] The specific processes of S601-S611 described above can be found in the description of the above method embodiments. Their implementation principles and technical effects are similar, and will not be repeated here.

[0124] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0125] Based on the same inventive concept, this application also provides a bus component verification apparatus for implementing the bus component verification method described above. This apparatus can be applied to or integrated into a chip or chip module, for example. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations of one or more bus component verification apparatus embodiments provided below can be found in the limitations of the bus component verification method described above, and will not be repeated here.

[0126] In one exemplary embodiment, such as Figure 7 As shown, a bus component verification device 700 is provided, including: an identifier allocation module 710, a first sampling module 720, a second sampling module 730, and a component verification module 740, wherein:

[0127] The identifier allocation module 710 is used to assign a corresponding data packet identifier to the data packet after receiving the data packet to be transmitted.

[0128] The first sampling module 720 is used to sample data packets during the transmission of data packets and data packet identifiers by the bus component, obtain the input data packet information of the data packet, and associate and store the input data packet information and data packet identifier of the data packet.

[0129] The second sampling module 730 is used to sample the data packets output by the output channel of the DUT after the data packets and corresponding data packet identifiers are transmitted to the DUT of the bus component, so as to obtain the output data packet information and data packet identifier of the data packets.

[0130] The component verification module 740 is used to verify the accuracy of data transmission of the bus component based on the output data packet information and input data packet information corresponding to the data packet identifier.

[0131] The verification device for the aforementioned bus component, upon receiving a data packet to be transmitted, assigns a corresponding data packet identifier to the packet. During the transmission of the data packet and its identifier by the bus component, the data packet is sampled to obtain the input data packet information, and the input data packet information and the data packet identifier are associated and stored. After the data packet and its corresponding identifier are transmitted to the Design Under Test (DUT) of the bus component, the data packets output from the DUT's output channel are sampled to obtain the output data packet information and its identifier. Based on the output data packet information and input data packet information corresponding to the data packet identifier, the accuracy of data transmission by the bus component is verified. This scheme, by assigning a unique data packet identifier to each data packet and associating and storing the sampled information on both the input and output sides, achieves unique identification and tracking of data packets throughout the entire transmission chain of the bus component. When a transmission defect is detected, it is not necessary to compare all input and output data packet by packet; the corresponding input and output information can be quickly located using the data packet identifier, significantly shortening the defect location time, improving verification efficiency and quality, and reducing chip costs.

[0132] In one embodiment, the verification device 700 for the bus component further includes an identifier selection module, comprising:

[0133] The bit selection unit is used to select any free bit in the bus component as the target identifier bit.

[0134] The identifier injection unit is used to add the allocated data packet identifier to the target identifier bit; wherein the target identifier bit is used to transmit the data packet identifier.

[0135] In one embodiment, the bit selection unit is specifically used for:

[0136] Based on the historical verification information of the bus component, the historical identifier bit is determined; where the historical verification information is the information generated during the process of verifying the accuracy of data transmission of the bus component in a historical period; based on the historical identifier bit, the number of times each bit in the bus component is used is determined; the bit with the fewest usage times is selected from the idle bits as the target identifier bit.

[0137] In one embodiment, the component verification module 740 is specifically used for:

[0138] Based on the data packet identifier corresponding to the data packet, the input data packet information corresponding to the data packet identifier is read from the core storage module of the bus component; the consistency between the output data packet information and the input data packet information is compared to obtain the consistency comparison result of the data packet; based on the consistency comparison result, the accuracy of data transmission of the bus component is verified.

[0139] In one embodiment, the first sampling module 720 is further configured to:

[0140] The input data packet information and data packet identifier are associated and stored in the data packet logger of the bus component.

[0141] The component verification module 740 is also used for:

[0142] The transmitted data packets are sampled at the preset node of the DUT to obtain the data packet identifier; based on the data packet identifier, the input data packet information corresponding to the data packet identifier in the data packet recorder is synchronized to the core storage module of the bus component.

[0143] In one embodiment, the verification device 700 for the bus component further includes an early warning module for:

[0144] In response to an inconsistent consistency comparison result, an error alarm message is generated based on the packet identifier.

[0145] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0146] In one exemplary embodiment, a bus component is provided, the internal structure of which can be shown as follows: Figure 8 As shown, the bus component includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is connected to the system bus via the I / O interfaces. The processor of this bus component provides computing and control capabilities. The memory of the bus component includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and databases. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The I / O interfaces of the bus component are used for exchanging information between the processor and external devices. The communication interface of the bus component is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a verification method for the bus component.

[0147] Those skilled in the art will understand that Figure 8The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the bus components applied thereto. Specific bus components may include more or fewer parts than shown in the figure, or combine certain parts, or have different part arrangements.

[0148] In one exemplary embodiment, a bus component is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0149] After receiving the data packet to be transmitted, assign a corresponding data packet identifier to the data packet;

[0150] During the transmission of data packets and data packet identifiers by the bus component, the data packets are sampled to obtain the input data packet information, and the input data packet information and data packet identifier are associated and stored.

[0151] After the data packet and its corresponding data packet identifier are transmitted to the DUT of the bus component, the data packets output by the DUT's output channel are sampled to obtain the output data packet information and data packet identifier.

[0152] The accuracy of data transmission of the bus component is verified based on the output data packet information and input data packet information corresponding to the data packet identifier.

[0153] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0154] Select any free bit in the bus component as the target identifier bit; add the allocated data packet identifier to the target identifier bit; wherein, the target identifier bit is used to transmit the data packet identifier.

[0155] In one embodiment, when the processor executes a computer program to select any free bit in a bus component as the target identifier bit, it also performs the following steps:

[0156] Based on the historical verification information of the bus component, the historical identifier bit is determined; where the historical verification information is the information generated during the process of verifying the accuracy of data transmission of the bus component in a historical period; based on the historical identifier bit, the number of times each bit in the bus component is used is determined; the bit with the fewest usage times is selected from the idle bits as the target identifier bit.

[0157] In one embodiment, when the processor executes a computer program to verify the accuracy of data transmission of the bus component based on the output data packet information and input data packet information corresponding to the data packet identifier, it also performs the following steps:

[0158] Based on the data packet identifier corresponding to the data packet, the input data packet information corresponding to the data packet identifier is read from the core storage module of the bus component; the consistency between the output data packet information and the input data packet information is compared to obtain the consistency comparison result of the data packet; based on the consistency comparison result, the accuracy of data transmission of the bus component is verified.

[0159] In one embodiment, when the processor executes a computer program to associate and store the input data packet information and data packet identifier, it also performs the following steps:

[0160] The input data packet information and data packet identifier are associated and stored in the data packet logger of the bus component;

[0161] Based on this, after the processor executes the computer program to transmit the data packet and its corresponding identifier to the design under test (DUT) of the bus component, it also performs the following steps:

[0162] The transmitted data packets are sampled at the preset node of the DUT to obtain the data packet identifier; based on the data packet identifier, the input data packet information corresponding to the data packet identifier in the data packet recorder is synchronized to the core storage module of the bus component.

[0163] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0164] In response to an inconsistent consistency comparison result, an error alarm message is generated based on the packet identifier.

[0165] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0166] After receiving the data packet to be transmitted, assign a corresponding data packet identifier to the data packet;

[0167] During the transmission of data packets and data packet identifiers by the bus component, the data packets are sampled to obtain the input data packet information, and the input data packet information and data packet identifier are associated and stored.

[0168] After the data packet and its corresponding data packet identifier are transmitted to the DUT of the bus component, the data packets output by the DUT's output channel are sampled to obtain the output data packet information and data packet identifier.

[0169] The accuracy of data transmission of the bus component is verified based on the output data packet information and input data packet information corresponding to the data packet identifier.

[0170] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0171] Select any free bit in the bus component as the target identifier bit; add the allocated data packet identifier to the target identifier bit; wherein, the target identifier bit is used to transmit the data packet identifier.

[0172] In one embodiment, when the processor executes a computer program to select any free bit in a bus component as the target identifier bit, it also performs the following steps:

[0173] Based on the historical verification information of the bus component, the historical identifier bit is determined; where the historical verification information is the information generated during the process of verifying the accuracy of data transmission of the bus component in a historical period; based on the historical identifier bit, the number of times each bit in the bus component is used is determined; the bit with the fewest usage times is selected from the idle bits as the target identifier bit.

[0174] In one embodiment, when the processor executes a computer program to verify the accuracy of data transmission of the bus component based on the output data packet information and input data packet information corresponding to the data packet identifier, it also performs the following steps:

[0175] Based on the data packet identifier corresponding to the data packet, the input data packet information corresponding to the data packet identifier is read from the core storage module of the bus component; the consistency between the output data packet information and the input data packet information is compared to obtain the consistency comparison result of the data packet; based on the consistency comparison result, the accuracy of data transmission of the bus component is verified.

[0176] In one embodiment, when the processor executes a computer program to associate and store the input data packet information and data packet identifier, it also performs the following steps:

[0177] The input data packet information and data packet identifier are associated and stored in the data packet logger of the bus component;

[0178] Based on this, after the processor executes the computer program to transmit the data packet and its corresponding identifier to the design under test (DUT) of the bus component, it also performs the following steps:

[0179] The transmitted data packets are sampled at the preset node of the DUT to obtain the data packet identifier; based on the data packet identifier, the input data packet information corresponding to the data packet identifier in the data packet recorder is synchronized to the core storage module of the bus component.

[0180] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0181] In response to an inconsistent consistency comparison result, an error alarm message is generated based on the packet identifier.

[0182] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0183] After receiving the data packet to be transmitted, assign a corresponding data packet identifier to the data packet;

[0184] During the transmission of data packets and data packet identifiers by the bus component, the data packets are sampled to obtain the input data packet information, and the input data packet information and data packet identifier are associated and stored.

[0185] After the data packet and its corresponding data packet identifier are transmitted to the DUT of the bus component, the data packets output by the DUT's output channel are sampled to obtain the output data packet information and data packet identifier.

[0186] The accuracy of data transmission of the bus component is verified based on the output data packet information and input data packet information corresponding to the data packet identifier.

[0187] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0188] Select any free bit in the bus component as the target identifier bit; add the allocated data packet identifier to the target identifier bit; wherein, the target identifier bit is used to transmit the data packet identifier.

[0189] In one embodiment, when the processor executes a computer program to select any free bit in a bus component as the target identifier bit, it also performs the following steps:

[0190] Based on the historical verification information of the bus component, the historical identifier bit is determined; where the historical verification information is the information generated during the process of verifying the accuracy of data transmission of the bus component in a historical period; based on the historical identifier bit, the number of times each bit in the bus component is used is determined; the bit with the fewest usage times is selected from the idle bits as the target identifier bit.

[0191] In one embodiment, when the processor executes a computer program to verify the accuracy of data transmission of the bus component based on the output data packet information and input data packet information corresponding to the data packet identifier, it also performs the following steps:

[0192] Based on the data packet identifier corresponding to the data packet, the input data packet information corresponding to the data packet identifier is read from the core storage module of the bus component; the consistency between the output data packet information and the input data packet information is compared to obtain the consistency comparison result of the data packet; based on the consistency comparison result, the accuracy of data transmission of the bus component is verified.

[0193] In one embodiment, when the processor executes a computer program to associate and store the input data packet information and data packet identifier, it also performs the following steps:

[0194] The input data packet information and data packet identifier are associated and stored in the data packet logger of the bus component;

[0195] Based on this, after the processor executes the computer program to transmit the data packet and its corresponding identifier to the design under test (DUT) of the bus component, it also performs the following steps:

[0196] The transmitted data packets are sampled at the preset node of the DUT to obtain the data packet identifier; based on the data packet identifier, the input data packet information corresponding to the data packet identifier in the data packet recorder is synchronized to the core storage module of the bus component.

[0197] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0198] In response to an inconsistent consistency comparison result, an error alarm message is generated based on the packet identifier.

[0199] It should be noted that the data involved in this application (including but not limited to data used for analysis, data stored, data displayed, etc.) are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0200] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0201] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0202] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for verifying a bus component, characterized in that, The method includes: Upon receiving the data packet to be transmitted, a corresponding data packet identifier is assigned to the data packet; During the transmission of the data packet and data packet identifier by the bus component, the data packet is sampled to obtain the input data packet information of the data packet, and the input data packet information and data packet identifier of the data packet are associated and stored. After the data packet and its corresponding data packet identifier are transmitted to the design under test (DUT) of the bus component, the data packets output by the output channel of the DUT are sampled to obtain the output data packet information and data packet identifier of the data packet. The accuracy of data transmission of the bus component is verified based on the output data packet information and input data packet information corresponding to the data packet identifier.

2. The method according to claim 1, characterized in that, The method further includes: Select any free bit in the bus component as the target identifier bit; The assigned data packet identifier is added to the target identifier bit; wherein the target identifier bit is used to transmit the data packet identifier.

3. The method according to claim 2, characterized in that, The selection of any free bit in the bus component as the target identifier bit includes: Based on the historical verification information of the bus component, the historical identifier bit is determined; wherein, the historical verification information is information generated during the process of verifying the data transmission accuracy of the bus component in a historical period; Based on the historical identifier bits, determine the number of times each bit in the bus component has been used; Select the least used bit from the free bits and use it as the target identifier bit.

4. The method according to claim 1, characterized in that, The step of verifying the data transmission accuracy of the bus component based on the output data packet information and input data packet information corresponding to the data packet identifier includes: Based on the data packet identifier corresponding to the data packet, the input data packet information corresponding to the data packet identifier is read from the core storage module of the bus component; The consistency comparison result of the data packet is obtained by comparing the output data packet information and the input data packet information. Based on the consistency comparison results, the accuracy of data transmission of the bus component is verified.

5. The method according to claim 4, characterized in that, The associated storage of the input data packet information and data packet identifier of the data packet includes: The input data packet information and data packet identifier of the data packet are associated and stored in the data packet recorder of the bus component; After the data packet and its corresponding identifier are transmitted to the design under test (DUT) of the bus component, the method further includes: The transmitted data packets are sampled at a preset node of the DUT to obtain the data packet identifier; Based on the data packet identifier, the input data packet information corresponding to the data packet identifier in the data packet recorder is synchronized to the core storage module of the bus component.

6. The method according to claim 4, characterized in that, The method further includes: In response to the inconsistency of the consistency comparison result, an error alarm message is generated based on the data packet identifier.

7. A verification device for a bus component, characterized in that, The device includes: The identifier allocation module is used to assign a corresponding data packet identifier to the data packet after receiving the data packet to be transmitted; The first sampling module is used to sample the data packet and the data packet identifier during the transmission of the data packet and the data packet identifier by the bus component, obtain the input data packet information of the data packet, and store the input data packet information and the data packet identifier together. The second sampling module is used to sample the data packets output by the output channel of the DUT after the data packet and the corresponding data packet identifier are transmitted to the DUT of the bus component, so as to obtain the output data packet information and data packet identifier of the data packet. The component verification module is used to verify the accuracy of data transmission of the bus component based on the output data packet information and input data packet information corresponding to the data packet identifier.

8. A bus component comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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