Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises: a base, and a plurality of sub-pixels (20) disposed on the base; a plurality of data lines (Data), which are located in an active area (AA), electrically connected to the plurality of sub-pixels (20) and configured to transmit data signals to the plurality of sub-pixels (20); a multiplexing circuit (10), which is at least partially located in the active area (AA) and is connected to the plurality of data lines (Data); a plurality of data output lines (SL), which are at least located in a non-active area (BB) and are connected to the multiplexing circuit (10), the number of the plurality of data output lines (SL) being less than the number of the plurality of data lines (Data); and a shielding structure (30), which is at least partially located in the active area (AA), the orthographic projection of the shielding structure (30) on the base at least partially overlapping with the orthographic projection of a light-emitting device of at least one of the sub-pixels on the base and at least partially overlapping with the orthographic projection of the multiplexing circuit (10) on the base.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411803660.3, filed on December 9, 2024, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate and a display device.

[0006] In a first aspect, this disclosure provides a display substrate, comprising:

[0007] The substrate includes: a display area and a non-display area located on at least one side of the display area;

[0008] Multiple sub-pixels are located on one side of the substrate and in the display area. At least one of the multiple sub-pixels includes a pixel driving circuit and a light-emitting device. The pixel driving circuit is used to drive the light-emitting device.

[0009] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, configured to transmit data signals to the multiple sub-pixels;

[0010] A multiplexing circuit, at least partially located in the display area and connected to the multiple data lines;

[0011] Multiple data output lines are located at least in the non-display area and connected to the multiplexing circuit, wherein the number of multiple data output lines is less than the number of multiple data lines;

[0012] A shielding structure, at least partially located in the display area, wherein the orthographic projection of the shielding structure on the substrate at least partially overlaps with the orthographic projection of the light-emitting device of the at least one sub-pixel on the substrate, and at least partially overlaps with the orthographic projection of the multiplexing circuit on the substrate.

[0013] In an exemplary embodiment, the multiplexing circuit includes: multiple multiplexing sub-circuits and multiple multiplexing control signal lines. The multiple multiplexing sub-circuits are located on the side of the multiple multiplexing control signal lines close to the display area and are arranged along a first direction. The multiple multiplexing control signal lines extend along the first direction and are arranged along a second direction, and the first direction and the second direction intersect.

[0014] Each of the plurality of multiplexed sub-circuits is electrically connected to at least one of the plurality of data output lines and at least two of the plurality of data lines, and is configured to transmit the data signal provided by the at least one data output line to the at least two data lines in a time-division manner under the control of the plurality of multiplexed control signal lines.

[0015] Each multiplexed sub-circuit includes multiple multiplexed transistors, and the orthographic projection of the light-emitting device of the at least one sub-pixel on the substrate at least partially overlaps with the orthographic projection of at least one of the multiple multiplexed transistors on the substrate, and the multiple multiplexed control signal lines are electrically connected to the control electrodes of the multiple multiplexed transistors.

[0016] In an exemplary embodiment, the orthographic projection of the light-emitting device of the at least one sub-pixel on the substrate overlaps with the orthographic projection portion of at least one of the plurality of multiplexed control signal lines on the substrate, and / or overlaps with the orthographic projection portion of the at least one multiplexed transistor on the substrate.

[0017] In an exemplary embodiment, the light-emitting device of the at least one sub-pixel includes a first electrode, which is electrically connected to the pixel driving circuit. The orthographic projection of the first electrode on the substrate overlaps with the orthographic projection portion of at least one of the plurality of multiplexed control signal lines on the substrate, and / or overlaps with the orthographic projection portion of the at least one multiplexed transistor on the substrate.

[0018] In an exemplary embodiment, the shielding structure is located between the first electrode and the at least one multiplexed transistor in a direction perpendicular to the substrate.

[0019] In an exemplary embodiment, the orthographic projection of the shielding structure on the substrate and the orthographic projection of the pixel driving circuit of the plurality of sub-pixels on the substrate do not overlap.

[0020] In an exemplary embodiment, the non-display area includes a bonding area and a border area, the bonding area being located on one side of the display area, the border area being located on the other side of the display area, and the bonding area and the border area being connected. The light-emitting device of the at least one sub-pixel further includes a second electrode, and the display substrate further includes:

[0021] Multiple first power lines are located in the display area. The first power lines extend at least partially along the second direction and are electrically connected to the multiple sub-pixels. The orthographic projection of the first power lines on the substrate and the orthographic projection of the multiple multiplexed sub-circuits on the substrate do not overlap.

[0022] The first power supply line is located in the display area and the binding area, and is electrically connected to the plurality of first power lines;

[0023] The second power supply line is located in the frame area and the bonding area, and is electrically connected to the second electrode. The orthographic projection of the second power supply line on the substrate is located on the side of the orthographic projection of the first power supply line on the substrate away from the display area.

[0024] The shielding structure is electrically connected to one of the first power supply line and the second power supply line.

[0025] In an exemplary embodiment, the first power supply line includes: a first power connection line, a second power connection line, and a third power connection line;

[0026] The first power connection line is located in the display area and the bonding area, and is electrically connected to the plurality of first power lines. The orthographic projection of the first power connection line on the substrate overlaps with the orthographic projection of the multiplexing circuit on the substrate, and also overlaps with the orthographic projection of the plurality of multiplexing control signal lines on the substrate.

[0027] The second power connection line is located in the bonding area and is electrically connected to the first power connection line. The orthographic projection of the second power connection line on the substrate is located on the side of the orthographic projection of the first power connection line on the substrate away from the display area.

[0028] The third power connection line is located in the bonding area and is electrically connected to the second power connection line. The orthographic projection of the third power connection line on the substrate is located on the side of the orthographic projection of the second power connection line on the substrate that is away from the display area.

[0029] In an exemplary embodiment, the first power connection line includes: a power connection segment and a plurality of power branch segments, the power connection segment being connected to the plurality of power branch segments, the power connection segment extending at least partially along the first direction, and the power branch segments extending at least partially along the second direction;

[0030] The number of the plurality of power branch segments is less than the number of the plurality of first power lines, and at least one of the plurality of power branch segments has its orthographic projection on the substrate overlapping with the orthographic projection of the multiplexing circuit on the substrate.

[0031] In an exemplary embodiment, the boundary of the display area includes: a plurality of rounded corner boundaries, the display area is divided into a plurality of display sub-areas arranged along the first direction, the display sub-area including the rounded corner boundaries is called the first display sub-area, and the display area other than the first display sub-area is called the second display sub-area;

[0032] The plurality of power supply branch segments are located in the second display sub-area.

[0033] In an exemplary embodiment, the circuit structure layer is further included: a circuit structure layer disposed on the substrate, the circuit structure layer including: a gate metal layer group and a source / drain metal layer group sequentially stacked on the substrate, the source / drain metal layer group including: a first source / drain metal layer to an Nth source / drain metal layer, where N is a positive integer greater than or equal to 2;

[0034] The multiple multiplexed control signal lines are located in the first source-drain metal layer, the first power supply line and the second power supply line are located in at least one of the source-drain metal layers from the first source-drain metal layer to the Nth source-drain metal layer, and the shielding structure is located in one of the source-drain metal layers other than the first source-drain metal layer.

[0035] In an exemplary implementation, N = 2 or 3;

[0036] When N=3, at least a portion of the shielding structure is located in the first display sub-area and the second display sub-area. The shielding structure is located in the third source-drain metal layer and is electrically connected to one of the first power supply line and the second power supply line. The orthographic projection of the shielding structure on the substrate also overlaps at least partially with the orthographic projections of the plurality of multiplexed sub-circuits, the plurality of multiplexed control signal lines and the first power connection line on the substrate.

[0037] Alternatively, when N=2, the shielding structure is located in the first display sub-area, the shielding structure is located in the second source / drain metal layer and is electrically connected to the second power supply line, and the orthographic projection of the shielding structure on the substrate also overlaps at least partially with the orthographic projections of the plurality of multiplexed sub-circuits and the plurality of multiplexed control signal lines on the substrate;

[0038] Alternatively, when N=2, at least a portion of the shielding structure is located in the first display sub-region and the second display sub-region. The shielding structure is located in the second source / drain metal layer and is electrically connected to the first power supply line. The orthographic projection of the shielding structure on the substrate also overlaps at least partially with the orthographic projections of the plurality of multiplexed sub-circuits and the plurality of multiplexed control signal lines on the substrate. The shielding structure and the plurality of first power connection lines are an integral structure.

[0039] In an exemplary embodiment, the shielding structure includes: a plurality of spaced-apart shielding portions, the shielding portions being disposed in a second source / drain metal layer;

[0040] At least one of the plurality of spaced shielding portions has its orthographic projection on the substrate at least partially overlapping with the orthographic projection of the first electrode of the light-emitting device on the substrate.

[0041] In an exemplary embodiment, the at least one shielding portion and at least one of the plurality of power branch segments are integral structures.

[0042] In an exemplary implementation, N = 3;

[0043] The shielding structure includes: multiple shielding lines located in the third source / drain metal layer; at least a portion of at least one of the multiple shielding lines extends along the second direction and is electrically connected to the second power supply line;

[0044] The orthographic projection of the at least one shielding line on the substrate overlaps with the orthographic projections of the plurality of multiplexed sub-circuits, the plurality of multiplexed control signal lines, and the first power connection line on the substrate, and also overlaps with the orthographic projection of the at least one power branch segment on the substrate.

[0045] In an exemplary embodiment, when N=3, the first power line is located in at least one of the first and second source / drain metal layers.

[0046] The first power connection line is located in the second source-drain metal layer, the second power connection line is located in the first source-drain metal layer, one of the second source-drain metal layer and the third source-drain metal layer, and the third power connection line is located in one of the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer.

[0047] The second power supply line is located in at least one of the first source / drain metal layers, the second source / drain metal layer, and the third source / drain metal layer.

[0048] In an exemplary embodiment, when N=2, the first power line is located in at least one film layer of the first source / drain metal layer and the second source / drain metal layer.

[0049] The first power connection line is located in the second source / drain metal layer, the second power connection line is located in one of the first source / drain metal layers and the second source / drain metal layer, and the third power connection line is located in one of the first source / drain metal layers and the second source / drain metal layer.

[0050] The second power supply line is located in at least one of the first source / drain metal layers and the second source / drain metal layer.

[0051] In an exemplary embodiment, the bonding area includes: a lead area, a bending area, and a composite circuit area arranged sequentially away from the display area;

[0052] The second power connection line is located in the lead area and the bend area, the third power connection line is located in the composite circuit area, and the second power supply line portion is located in the lead area, the bend area, and the composite circuit area.

[0053] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0054] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0055] Overview of the attached figures

[0056] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0057] Figure 1 is a schematic diagram of a display device;

[0058] Figure 2 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0059] Figure 3 is a timing diagram of a pixel driving circuit.

[0060] Figure 4 is a schematic diagram of the multiplexing circuit connection;

[0061] Figure 5 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0062] Figure 6 is a schematic diagram of a portion of the film layers in Figure 5;

[0063] Figure 7 is a schematic diagram of the multiplexing circuit;

[0064] Figure 8 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment;

[0065] Figure 9 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment;

[0066] Figure 10 is a schematic diagram of some of the film layers in Figures 8 and 9;

[0067] Figure 11 is a partially enlarged schematic diagram of Figure 8;

[0068] Figure 12 is a partially enlarged schematic diagram of Figure 9;

[0069] Figure 13 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment;

[0070] Figure 14 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment;

[0071] Figure 15 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment;

[0072] Figure 16 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment;

[0073] Figure 17 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment;

[0074] Figure 18 is a schematic diagram of a portion of the film layers in Figure 17;

[0075] Figure 19 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment;

[0076] Figure 20 is a schematic diagram of a portion of the film layers in Figure 19;

[0077] Figure 21 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment;

[0078] Figure 22 is a schematic diagram of a partial cross-section along AA in Figure 6;

[0079] Figure 23 is a schematic diagram of a partial cross-section along AA in Figure 6;

[0080] Figure 24 is a schematic diagram of a partial cross-section along AA in Figure 6;

[0081] Figure 25 is a schematic diagram of a partial cross-section along AA in Figure 6;

[0082] Figure 26 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure.

[0083] Detailed Explanation

[0084] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0085] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0086] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0087] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0088] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0089] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0090] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0091] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0092] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0093] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0094] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0095] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0096] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0097] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0098] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driving circuit, a scan driving circuit, a light-emitting driving circuit, and a pixel array. The timing controller is connected to the data driving circuit, the scan driving circuit, and the light-emitting driving circuit. The data driving circuit is connected to multiple data signal lines (D1 to Dn), the scan driving circuit is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driving circuit is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driving circuit to the data driving circuit, provide clock signals, scan start signals, etc. of specifications suitable for the scan driving circuit to the scan driving circuit, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driving circuit to the light-emitting driving circuit. The data driving circuit can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driving circuit can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan driving circuit can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driving circuit can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driving circuit can generate emission signals to be provided to light-emitting signal lines EM1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver circuit can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines EM1 to Eo. For example, the light-emitting driver circuit can be constructed in the form of a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0099] The display substrate may include multiple pixel units arranged in a matrix, at least one of the multiple pixel units including multiple sub-pixels. Each sub-pixel includes: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. Each of the first, second, and third sub-pixels includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first, second, and third sub-pixels are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first, second, and third sub-pixels are respectively connected to the pixel driving circuit of their respective sub-pixels, and the light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0100] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0101] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged in a horizontal, vertical, or triangular manner, etc., and this disclosure does not limit the arrangement.

[0102] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0103] In an exemplary embodiment, the display substrate may include: a data signal line, a scan signal line, a light emission signal line, at least one initial signal line, at least one reset signal line, and a first power supply line.

[0104] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.

[0105] In an exemplary embodiment, Figure 2 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 2, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit can be connected to seven signal lines (data signal line Data, scan signal line Gate, first reset signal line Reset1, light emission signal line EM, initial signal line INIT, first power supply line VDD, and second power supply line VSS). Specifically, the control electrode of the first transistor T1 is connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the second node N2; the control electrode of the second transistor T2 is connected to the scan signal line Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3; the control electrode of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the first node N1. The control electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The control electrode of the seventh transistor T7 is connected to the second reset signal line Reset2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. The first terminal of the storage capacitor C is connected to the first power supply line VDD, and the second terminal of the storage capacitor C is connected to the first node N1.

[0106] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and the first electrode. The fourth transistor T4 can be referred to as a switching transistor or a scanning transistor. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors.

[0107] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The scan signal line Gate is the scan signal line in the pixel driving circuit of this display row, and the first reset signal line Reset1 is the scan signal line in the pixel driving circuit of the previous display row. The first reset signal line Reset1 of this display row and the scan signal line Gate in the pixel driving circuit of the previous display row are the same signal line, which can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0108] In an exemplary embodiment, for at least one pixel driving circuit, the second reset signal line may be the same signal line as the first reset signal line, or it may be the same signal line as the scan signal line.

[0109] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0110] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0111] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0112] In an exemplary embodiment, the scan signal line Gate, the first reset signal line Reset1, the second reset signal line Reset2, the light emission signal line EM, the first initial signal line INIT1, and the second initial signal line INIT2 can extend in the horizontal direction, while the first power supply line VDD and the data signal line Data can extend in the vertical direction.

[0113] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (Organic Light Emitting Diode), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0114] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0115] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode, including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0116] Figure 3 is a timing diagram of a pixel driving circuit. The following describes an exemplary embodiment of this disclosure through the operation of the pixel driving circuit illustrated in Figure 2. The pixel driving circuit in Figure 2 includes seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. All seven transistors are P-type transistors.

[0117] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0118] In the first stage A1, also known as the reset stage, the signals on the first reset signal line Reset1 and the second reset signal line Reset2 are low-level signals, while the signals on the scan signal line Gate and the light emission signal line EM are high-level signals. The first transistor T1 and the seventh transistor T7 are turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0119] The first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is provided to the second node N2 to initialize (reset) the storage capacitor C, clearing the original charge in the storage capacitor. The seventh transistor T7 is turned on, and the initial voltage of the second initial signal line INIT2 is provided to the first terminal of the light-emitting device L to initialize (reset) the first terminal of the light-emitting device L, clearing the pre-stored voltage inside it, and completing the initialization.

[0120] The second stage, A2, is called the data writing stage or threshold compensation stage. The Gate signal is low, while the Reset1, Reset2, and EM signals are high. The Data signal outputs the data voltage. The second transistor T2 and the fourth transistor T4 are turned on, while the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0121] The second transistor T2 and the fourth transistor T4 are turned on. The data voltage output by the data signal line Data is provided to the first node N1 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal (first node N1) of the storage capacitor C is Vdd-|Vth|, where Vdd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor T3.

[0122] The third stage, A3, is called the light-emitting stage. The light-emitting signal line EM is at a low level, while the scan signal line Gate / first reset signal line Reset1 and second reset signal line Reset2 are at a high level. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off.

[0123] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L, driving the light-emitting device L to emit light.

[0124] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the first node N1 is Vdata - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth). 2 =K*[(Vdd-Vdata+|Vth|)-Vth] 2 =K*(Vdd-Vdata) 2

[0125] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, and Vdd is the power supply voltage output by the first power supply line VDD.

[0126] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0127] In exemplary embodiments, the light-emitting device may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). Typical dimensions (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. Typical dimensions (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0128] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0129] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0130] On a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer disposed on the substrate, a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0131] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The driving circuit layer for each sub-pixel may include multiple transistors and storage capacitors constituting the pixel driving circuit. The light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit via a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving force of the anode and cathode. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0132] In an exemplary embodiment, the display substrate may further include a multiplexing circuit. Figure 4 is a schematic diagram of the multiplexing circuit connection. As shown in Figure 4, the multiplexing circuit is electrically connected to multiple data signal lines Data and multiple data output lines SL. The number of data output lines SL is less than the number of data signal lines Data, which simplifies the structure of the data driving circuit.

[0133] The display substrate may include a display area and a non-display area. A multiplexing circuit may be disposed in the display area. In this case, the orthographic projection of the first electrode of at least one light-emitting device on the substrate at least partially overlaps with the orthographic projection of the multiplexing circuit on the substrate. This causes the signal transmitted by the multiplexing circuit to interfere with the signal of the first electrode of at least one light-emitting device, reducing the reliability of the display substrate.

[0134] Therefore, this disclosure provides a display substrate and a display device.

[0135] Figure 5 is a schematic diagram of the structure of the display substrate provided in the embodiment of this disclosure, and Figure 6 is a schematic diagram of a portion of the film layers in Figure 5. As shown in Figures 5 and 6, the embodiment of this disclosure provides a display substrate, including: a substrate, the substrate including: a display area AA and a non-display area BB located on at least one side of the display area AA. A plurality of sub-pixels are located on one side of a substrate and in a display area AA. At least one sub-pixel 20 of the plurality of sub-pixels includes: a pixel driving circuit 21 and a light-emitting device, wherein the pixel driving circuit 21 is used to drive the light-emitting device; a plurality of data lines Data, located in the display area AA and electrically connected to the plurality of sub-pixels, configured to transmit data signals to the plurality of sub-pixels 20; a multiplexing circuit 10, at least partially located in the display area AA and connected to the plurality of data lines Data; a plurality of data output lines SL, at least located in a non-display area BB and connected to the multiplexing circuit 10, wherein the number of the plurality of data output lines SL is less than the number of the plurality of data lines Data; and a shielding structure 30, at least partially located in the display area AA, wherein the orthographic projection of the shielding structure 30 on the substrate at least partially overlaps with the orthographic projection of the light-emitting device of at least one sub-pixel on the substrate, and at least partially overlaps with the orthographic projection of the multiplexing circuit 10 on the substrate.

[0136] By setting a shielding structure, this disclosure can reduce the impact of signals transmitted by multiplexed circuits on the first electrode of the first light-emitting device, thereby improving the reliability of the display substrate and thus improving the display effect of the display substrate.

[0137] Figure 7 is a schematic diagram of the multiplexing circuit. Referring to Figures 5 to 7, the multiplexing circuit 10 includes: multiple multiplexing sub-circuits 11 and multiple multiplexing control signal lines 12. The multiple multiplexing sub-circuits 11 are located on the side of the multiple multiplexing control signal lines 12 closest to the display area AA and arranged along a first direction D1. The multiple multiplexing control signal lines 12 extend along the first direction D1 and are arranged along a second direction D2. The first direction D1 and the second direction D2 intersect.

[0138] In an exemplary embodiment, the intersection of the first direction D1 and the second direction D2 means that the included angle between the first direction D1 and the second direction D2 is approximately 70 to 90 degrees. The first direction D1 and the second direction D2 may be located in the same plane. For example, the first direction D1 may be a row direction, parallel to the extension direction of the scan line; the second direction D2 may be a column direction, parallel to the extension direction of the data line.

[0139] In an exemplary embodiment, as shown in FIG7, each multiplexing sub-circuit 11 of the plurality of multiplexing sub-circuits is electrically connected to at least one data output line SL and at least two data lines Data of the plurality of data output lines, configured to transmit the data signal provided by at least one data output line SL to at least two data lines Data in a time-division manner under the control of the plurality of multiplexing control signal lines 12. Exemplarily, each multiplexing sub-circuit 11 may be electrically connected to one data output line SL and two data lines Data, or it may be electrically connected to one data output line SL and three data lines Data, or it may be electrically connected to one data output line SL and M data lines Data, where M is a positive integer greater than or equal to 4.

[0140] In an exemplary embodiment, the number of data lines Data connected to a multiplexed subcircuit 11 is the same as the number of multiplexed control signal lines 12.

[0141] In an exemplary embodiment, the light-emitting device includes a first electrode 22, an organic light-emitting layer, and a second electrode. Figure 5 only shows the first electrode 22 of the light-emitting device.

[0142] In an exemplary embodiment, as shown in FIG7, each multiplexed sub-circuit includes multiple multiplexed transistors RT, the orthographic projection of the light-emitting device of at least one sub-pixel on the substrate overlaps with the orthographic projection of at least one of the multiple multiplexed transistors RT on the substrate, and multiple multiplexed control signal lines 12 are electrically connected to the control electrodes of the multiple multiplexed transistors RT.

[0143] In an exemplary embodiment, as shown in FIG5, the orthographic projection of the light-emitting device of at least one sub-pixel on the substrate overlaps with the orthographic projection of at least one multiplexed control signal line 12 among the multiple multiplexed control signal lines on the substrate, and / or overlaps with the orthographic projection of at least one multiplexed transistor RT on the substrate. FIG5 is illustrated using the example of the orthographic projection of the light-emitting device of at least one sub-pixel on the substrate overlapping with the orthographic projection of at least one multiplexed control signal line 12 among the multiple multiplexed control signal lines on the substrate, and overlapping with the orthographic projection of at least one multiplexed transistor RT on the substrate.

[0144] In an exemplary embodiment, as shown in FIG5, the first electrode 22 is electrically connected to the pixel driving circuit. The orthographic projection of the first electrode 22 on the substrate overlaps with the orthographic projection portion of at least one of the multiplexed control signal lines 12 on the substrate, and / or overlaps with the orthographic projection portion of at least one multiplexed transistor RT on the substrate.

[0145] In an exemplary embodiment, the number of data transmission lines SL is equal to the number of data lines Data divided by the number of multiplexed control signal lines 12.

[0146] In an exemplary embodiment, as shown in FIG5, the shielding structure 30 is located between the first electrode 22 and the multiplexed transistor RT in a direction perpendicular to the substrate.

[0147] In an exemplary embodiment, as shown in FIG5, the orthographic projection of the shielding structure 30 on the substrate and the orthographic projection of at least one pixel driving circuit 21 on the substrate do not overlap. This lack of overlap reduces the impact of the shielding structure on the pixel driving circuit 21, further improving the reliability of the display substrate.

[0148] In an exemplary embodiment, as shown in Figures 5 and 6, the non-display area AA includes a bonding area B1 and a border area B2. The bonding area B1 is located on one side of the display area AA, and the border area B2 is located on at least one side of the display area AA. In the exemplary embodiment, the border area B2 and the bonding area B1 are connected and together surround the display area AA. For example, the bonding area B1 may be the lower border of the display substrate, and the border area B2 may include the upper border, left border, and right border of the display substrate.

[0149] In an exemplary embodiment, as shown in Figures 5 and 6, multiple multiplexed control signal lines 12 are located in the binding area B1 of the non-display area BB.

[0150] As shown in Figures 5 and 6, the display substrate also includes: multiple first power lines VDD located in the display area AA. The first power lines VDD extend at least partially along the second direction D2 and are electrically connected to the pixel driving circuit 21.

[0151] As shown in Figure 5, the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the multiplexing circuit 10 on the substrate do not overlap.

[0152] As shown in Figure 5, the first power supply line VL1 is located in the display area and the binding area B1, and is electrically connected to multiple first power supply lines VDD.

[0153] As shown in Figure 5, the second power supply line VL2 is located in the frame area B2 and the bonding area B1, and is electrically connected to the second electrode of the light-emitting device. The orthographic projection of the second power supply line VL2 on the substrate is located on the side of the first power supply line VL1 on the substrate that is away from the display area AA.

[0154] In an exemplary embodiment, the shielding structure 30 is electrically connected to one of the first power supply line VL1 and the second power supply line. This electrical connection allows the shielding structure to transmit DC signals, further enhancing its shielding effect, improving the reliability of the display substrate, and ultimately enhancing its display performance.

[0155] In an exemplary embodiment, the shielding structure 30 may be an integral structure with the connected power supply line, or the shielding structure 30 may be located on a different film layer from the connected power supply line, and the shielding structure 30 may overlap with the connected power supply line and be connected through a via, or the shielding structure 30 may be located on a different film layer from the connected power supply line, and the shielding structure 30 may not overlap with the connected power supply line and be connected through a connecting electrode. This disclosure does not impose any limitations on this.

[0156] In an exemplary embodiment, as shown in Figures 5 and 6, the bonding area B1 includes a lead area B11, a bending area B12, and a composite circuit area B13 arranged sequentially along the distance from the display area AA.

[0157] In an exemplary embodiment, the lead area B11 can be provided with multiple leads, which are led out in a fan-out routing manner. One end of the multiple leads is connected to multiple data signal lines Data in the display area, and the other end of the multiple leads crosses the bending area B12 and connects to the integrated circuit of the composite circuit area B13, so that the integrated circuit applies data signal lines Data through the leads.

[0158] In an exemplary embodiment, the bending region B12 can be bent with a curvature in a third direction, which can reverse the surface of the composite circuit region B13. That is, the upward-facing surface of the composite circuit region B13 can be transformed into a downward-facing surface by bending the bending region B12. The third direction intersects the first direction D1 and the second direction D2 respectively. In an exemplary embodiment, when the bending region B12 is bent, the composite circuit region B13 can overlap with the display area AA in the third direction (thickness direction).

[0159] In an exemplary embodiment, the composite circuit area B13 may include an anti-static area, a driver chip area, and a bonding pin area.

[0160] In an exemplary embodiment, the anti-static area includes an electrostatic discharge circuit 41 and a test circuit 42, wherein the electrostatic discharge circuit 41 is configured to prevent electrostatic damage to the display substrate by eliminating static electricity.

[0161] In an exemplary embodiment, the driving chip region includes an integrated circuit (IC) 43, wherein multiple leads are connected to the integrated circuit 43. The integrated circuit 43 can generate driving signals required to drive sub-pixels and can provide the driving signals to the sub-pixels in the display area. For example, the driving signal can be a data signal that drives the brightness of the sub-pixels. The integrated circuit 43 can be bonded to the driving chip region by an anisotropic conductive film or other means, and the width of the integrated circuit 43 in the first direction D1 can be smaller than the width of the composite circuit region B3 in the first direction D1.

[0162] In an exemplary embodiment, the bonding pin area includes a plurality of pins (PINs) located on the display substrate and a flexible printed circuit (FPC) 44, which can be bonded to the plurality of pins (PINs) of the bonding pin area.

[0163] In an exemplary embodiment, as shown in Figures 5 and 6, the first power supply line VL1 includes: a first power connection line VL11, a second power connection line VL12, and a third power connection line VL13.

[0164] In an exemplary embodiment, as shown in FIG6, the first power connection line VL11 is located in the display area AA and the bonding area B1, and is electrically connected to multiple first power lines VDD. In the exemplary embodiment, the first power connection line VL11 and the multiple first power lines VDD can be an integral structure. The orthographic projection of the first power connection line VL11 on the substrate at least partially overlaps with the orthographic projection of the multiplexing circuit 10 on the substrate and the orthographic projection of the multiple multiplexed control signal lines 12 on the substrate.

[0165] In an exemplary embodiment, as shown in FIG6, the second power connection line VL12 is located in the bonding area B1 and is electrically connected to the first power connection line VL11. The orthographic projection of the second power connection line VL12 on the substrate is located on the side of the orthographic projection of the first power connection line VL11 on the substrate that is away from the display area AA. Exemplarily, the second power connection line VL12 may be located in the lead area B11 and the bending area B12.

[0166] In an exemplary embodiment, the third power connection line VL13 is located in the bonding area B1 and is electrically connected to the second power connection line VL12. The orthographic projection of the third power connection line VL13 on the substrate is located on the side of the orthographic projection of the second power connection line VL12 on the substrate that is away from the display area AA. Exemplarily, the third power connection line VL13 may be located in the composite circuit area B13.

[0167] In an exemplary embodiment, the first power connection line VL11 and the second power connection line VL12 can be arranged in the same layer or in different layers. When the first power connection line VL11 and the second power connection line VL12 are arranged in different layers, the orthographic projection of the first power connection line VL11 on the substrate at least partially overlaps with the orthographic projection of the second power connection line VL12 on the substrate. The second power connection line VL12 and the third power connection line VL13 can be arranged in the same layer or in different layers. When the second power connection line VL12 and the third power connection line VL13 are arranged in different layers, the orthographic projection of the third power connection line VL13 on the substrate at least partially overlaps with the orthographic projection of the second power connection line VL12 on the substrate. Figures 5 and 6 are illustrated with the example of the first power connection line VL11 and the second power connection line VL12 being arranged in different layers, and the second power connection line VL12 and the third power connection line VL13 being arranged in different layers.

[0168] In an exemplary embodiment, the second power connection line VL12 may also extend to the border area.

[0169] In an exemplary embodiment, the second power supply line VL2 may be located in the border area B2 and the bonding area B1. A portion of the second power supply line VL2 is located in the lead area B11, the bending area B12, and the composite circuit area B13.

[0170] In an exemplary embodiment, as shown in FIG6, the first power connection line VL11 includes: a power connection segment L1 and a plurality of power branch segments L2, the power connection segment L1 is connected to the plurality of power branch segments L2, the power connection segment L1 extends at least partially along a first direction D1, and the power branch segments L2 extend at least partially along a second direction D2.

[0171] In an exemplary embodiment, as shown in FIG6, the number of power branch segments L2 is less than the number of first power lines VDD, and at least a portion of the orthographic projection of at least one power branch segment L2 on the substrate overlaps at least partially with the orthographic projection of the multiplexing circuit 10 and the multiple multiplexed control signal lines 12 on the substrate.

[0172] In an exemplary embodiment, as shown in Figures 5 and 6, the boundary of the display area AA includes multiple rounded corner boundaries CR. The display area AA is divided into multiple display sub-areas arranged along the first direction D1. The display sub-area whose boundary includes rounded corner boundaries is called the first display sub-area AA1, and the display area AA excluding the first display sub-area AA1 is called the second display sub-area AA2. In the exemplary embodiment, in the first direction D1, the second display sub-area AA2 is located on the side of the first display sub-area AA1 away from the non-display area.

[0173] In an exemplary embodiment, as shown in FIG6, multiple power branch segments L2 are located in the second display sub-area AA2.

[0174] In an exemplary embodiment, the display substrate further includes: a circuit structure layer disposed on the substrate, the circuit structure layer including: a gate metal layer group and a source / drain metal layer group sequentially stacked on the substrate, the source / drain metal layer group including: a first source / drain metal layer to an Nth source / drain metal layer, where N is a positive integer greater than or equal to 2.

[0175] In an exemplary embodiment, multiple multiplexed control signal lines 12 may be located in the first source / drain metal layer.

[0176] In an exemplary embodiment, the first power supply line VL1 and the second power supply line VL2 are located in at least one of the first source / drain metal layers to the Nth source / drain metal layer.

[0177] In an exemplary embodiment, the shielding structure 30 is located in one of the source / drain metal layers other than the first source / drain metal layer.

[0178] In an exemplary embodiment, the gate metal layer group may include: a first gate metal layer and a second gate metal layer, or may include: a first gate metal layer, a second gate metal layer, and a third gate metal layer. When the gate metal layer group includes: a first gate metal layer and a second gate metal layer, the first gate metal layer includes: a control electrode of a transistor, one of the plates of a storage capacitor, a scan signal line, a light emission signal line, and at least one reset signal line. The second gate metal layer includes: the other plate of the storage capacitor.

[0179] In an exemplary embodiment, at least one initial signal line may be located in at least one gate metal layer.

[0180] In an exemplary implementation, N = 2 or 3.

[0181] In an exemplary embodiment, when N=3, at least a portion of the shielding structure is located in the first display sub-region and the second display sub-region. The shielding structure is located in the third source-drain metal layer and is electrically connected to one of the first power supply line and the second power supply line. The orthographic projection of the shielding structure on the substrate also overlaps with the orthographic projection portions of the multiple multiplexed sub-circuits, the multiple multiplexed control signal lines, and the first power connection line on the substrate.

[0182] In an exemplary embodiment, when N=3, the first power line is located in at least one of the first source / drain metal layers and the second source / drain metal layer; the first power connection line is located in the second source / drain metal layer; the second power connection line is located in one of the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer; the third power connection line is located in one of the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer; and the second power supply line is located in at least one of the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

[0183] In an exemplary embodiment, when N=2, the shielding structure is located in the first display sub-region, the shielding structure is located in the second source-drain metal layer, and is electrically connected to the second power supply line. The orthographic projection of the shielding structure on the substrate also overlaps with the orthographic projection portions of multiple multiplexed sub-circuits and multiple multiplexed control signal lines on the substrate.

[0184] In an exemplary embodiment, when N=2, at least a portion of the shielding structure is located in the first display sub-region and the second display sub-region. The shielding structure is located in the second source-drain metal layer and is electrically connected to the first power supply line. The orthographic projection of the shielding structure on the substrate also overlaps with the orthographic projection portions of multiple multiplexed sub-circuits and multiple multiplexed control signal lines on the substrate. The shielding structure and the first power connection line are an integral structure.

[0185] In an exemplary embodiment, when N=2, the first power line is located in at least one of the first source / drain metal layers and the second source / drain metal layer; the first power connection line is located in the second source / drain metal layer; the second power connection line is located in one of the first source / drain metal layers and the second source / drain metal layer; the third power connection line is located in one of the first source / drain metal layers and the second source / drain metal layer; and the second power supply line is located in at least one of the first source / drain metal layers and the second source / drain metal layer.

[0186] In an exemplary embodiment, FIG8 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment, FIG9 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment, FIG10 is a partial film layer schematic diagram of FIG8 and FIG9, FIG11 is a partially enlarged schematic diagram of FIG8, and FIG12 is a partially enlarged schematic diagram of FIG9. FIG8 and FIG9 are illustrated with N=3 as an example. As shown in FIG8 and FIG9, at least a portion of the shielding structure 30 is located in the first display sub-region AA1 and the second display sub-region AA2. The shielding structure 30 is located in the third source-drain metal layer and is electrically connected to the second power supply line VL2.

[0187] In an exemplary embodiment, the first electrode 22 of the light-emitting device may include an electrode body portion and an electrode connection portion connected to each other. The electrode connection portion of the first electrode of the light-emitting device is electrically connected to the pixel driving circuit to which the light-emitting device is connected. The shape of the electrode body portion of the first electrode 22 of the light-emitting device may be rectangular or irregularly circular, and this disclosure does not limit it in any way. FIG8 is illustrated with an example of the first electrode 22 of the light-emitting device having an irregularly circular shape. FIG9 is illustrated with an example of the first electrode 22 of the light-emitting device having a rectangular shape.

[0188] In an exemplary embodiment, as shown in Figures 8 and 9, the orthographic projection of the shielding structure 30 on the substrate also at least partially overlaps with the orthographic projections of the multiple multiplexed sub-circuits 11, the multiple multiplexed control signal lines 12, and the first power connection line VL11 on the substrate.

[0189] In an exemplary embodiment, in the display substrate provided in Figures 8 and 9, the first power line VDD may be located in at least one of the first and second source / drain metal layers. Figure 8 illustrates an example where the first power line VDD is located in the second source / drain metal layer.

[0190] In an exemplary embodiment, in the display substrate provided in Figures 8 and 9, the first power connection line VL11 is located in the second source / drain metal layer, the second power connection line VL12 is located in the first source / drain metal layer, one of the second source / drain metal layer and the third source / drain metal layer, and the third power connection line (not shown in the figures) is located in one of the first source / drain metal layer, the second source / drain metal layer and the third source / drain metal layer.

[0191] In an exemplary embodiment, in the display substrate provided in Figures 8 and 9, the second power supply line VL2 may be located in at least one of the first source / drain metal layers, the second source / drain metal layer, and the third source / drain metal layer. Exemplarily, when the second power supply line VL2 is located in the third source / drain metal layer, the second power supply line VL2 may be integrally formed with the shielding structure 30.

[0192] In an exemplary embodiment, in the display substrate provided in FIG8 and FIG9, the shielding structure 30 can be a planar structure.

[0193] In an exemplary embodiment, as shown in FIG10, the reset transistor RT includes: an active pattern, a control electrode RT12, a first electrode RT13, and a second electrode RT14. The active pattern includes: a channel region and a first region and a second region located on both sides of the channel region.

[0194] In an exemplary embodiment, as shown in FIG10, the second pole RT14 of all multiplexed transistors in the same multiplexed sub-circuit is the same electrode.

[0195] In an exemplary embodiment, as shown in FIG10, the display substrate further includes: a first via V1, a second via V2, a third via V3, a fourth via V4, and a fifth via V5. The first via V1 exposes a first region of the active pattern of the reset transistor RT, the second via V2 exposes a second region of the active pattern of the reset transistor RT, the third via V3 exposes the control electrode RT12 of the reset transistor RT, the fourth via V4 exposes the data output line SL, and the fifth via V5 exposes the first electrode RT13 of the reset transistor RT. The first electrode RT13 of the reset transistor RT is connected to the first region of the active pattern of the reset transistor RT through the first via, the second electrode RT14 of the reset transistor RT is connected to the second region of the active pattern of the reset transistor RT through the second via, at least one reset control signal line 12 is connected to the control electrode RT12 of the reset transistor RT through the third via, the second electrode RT14 of the reset transistor RT is electrically connected to the data output line SL through the fourth via V4, and the data signal line Data is connected to the first electrode RT13 of the reset transistor RT through the fifth via.

[0196] In an exemplary embodiment, as shown in FIG10, the data output line SL includes: an integrally formed first output portion SL1 and a second output portion SL2, the first output portion SL1 extending along a first direction D1 and the second output portion SL2 extending along a second direction D2. A fourth via V4 exposes the first output portion SL1 of the data output line SL.

[0197] In an exemplary embodiment, as shown in FIG10, the orthographic projection of the first output section SL1 on the substrate at least partially overlaps with the orthographic projection of the second pole RT14 of at least one multiplexed transistor on the substrate, and does not overlap with the orthographic projection of the multiple multiplexed control signal lines 12 on the substrate. The orthographic projection of the second output section SL2 on the substrate partially overlaps with the orthographic projection of the multiple multiplexed control signal lines 12 and the first power supply line VL1 on the substrate.

[0198] In an exemplary embodiment, FIG13 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment. As shown in FIG13, N=2, the shielding structure 30 is located in the first display sub-region AA1, the shielding structure 30 is located in the second source / drain metal layer, and is electrically connected to the second power supply line VL2. FIG13 is illustrated using an example where the electrode body of the first electrode of the light-emitting device has an irregular circular shape.

[0199] In an exemplary embodiment, as shown in FIG13, the orthographic projection of the shielding structure 30 on the substrate at least partially overlaps with the orthographic projections of the plurality of reset sub-circuits and the plurality of multiplexed control signal lines 12 on the substrate. The shielding structure 30 is disposed on the same layer as the first power connection line.

[0200] In an exemplary embodiment, in the display substrate shown in FIG13, the first power line VDD may be located in at least one of the first source / drain metal layers and the second source / drain metal layer. FIG13 is illustrated with the example that the first power line VDD may be located in the second source / drain metal layer.

[0201] In an exemplary embodiment, in the display substrate provided in FIG13, the first power connection line VL11 is located in the second source / drain metal layer, the second power connection line VL12 is located in one of the first source / drain metal layers and the second source / drain metal layer, and the third power connection line VL13 is located in one of the first source / drain metal layers and the second source / drain metal layer.

[0202] In an exemplary embodiment, in the display substrate provided in FIG13, the second power supply line VL2 is located in at least one film layer of the first source / drain metal layer and the second source / drain metal layer. Exemplarily, when the second power supply line VL2 is located in the second source / drain metal layer, the second power supply line VL2 and the shielding structure 30 can be an integral structure.

[0203] In an exemplary embodiment, in the display substrate provided in FIG13, the shielding structure 30 can be a planar structure.

[0204] In an exemplary embodiment, FIG14 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment, and FIG15 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment. As shown in FIG14 and FIG15, N=3, at least a portion of the shielding structure 30 is located in the first display sub-region AA1 and the second display sub-region AA2, the shielding structure 30 is located in the third source-drain metal layer, and is electrically connected to the first power supply line VL1.

[0205] In an exemplary embodiment, as shown in FIG14, the orthographic projection of the shielding structure 30 on the substrate also at least partially overlaps with the orthographic projections of the multiple multiplexed sub-circuits, the multiple multiplexed control signal lines 12 and the first power connection line VL11 on the substrate.

[0206] In an exemplary embodiment, as shown in FIG14, the shielding structure 30 may be directly connected to the first power connection line VL11, or directly connected to the second power connection line VL12, or directly connected to the third power connection line VL13. This disclosure does not limit the connection in any way.

[0207] In an exemplary embodiment, in the display substrate provided in Figures 14 and 15, the first power line VDD is located in at least one film layer of the first source / drain metal layer and the second source / drain metal layer. Figures 14 and 15 are illustrated with the example of the first power line VDD being located in the second source / drain metal layer.

[0208] In an exemplary embodiment, in the display substrate provided in FIGS. 14 and 15, the first power connection line VL11 is located in the second source / drain metal layer, the second power connection line VL12 is located in one of the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer, and the third power connection line (not shown in the figures) is located in one of the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer. FIG. 14 is illustrated with the example of the second power connection line VL12 being located in the first source / drain metal layer, and FIG. 15 is illustrated with the example of the second power connection line VL12 being located in the third source / drain metal layer.

[0209] In an exemplary embodiment, in the display substrate provided in Figures 14 and 15, the second power supply line VL2 is located in at least one of the first source / drain metal layers, the second source / drain metal layer, and the third source / drain metal layer. Exemplarily, when the second power supply line VL2 is located in the third source / drain metal layer, the second power supply line VL2 can be integrated with the shielding structure.

[0210] In an exemplary embodiment, in the display substrate provided in FIG14 and FIG15, the shielding structure 30 can be a planar structure.

[0211] Figure 16 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment. As shown in Figure 16, N=2, at least a portion of the shielding structure 30 is located in the first display sub-region AA1 and the second display sub-region AA2, the shielding structure 30 is located in the second source / drain metal layer, and is electrically connected to the first power supply line VL1.

[0212] In an exemplary embodiment, as shown in FIG16, the orthographic projection of the shielding structure 30 on the substrate also at least partially overlaps with the orthographic projections of the multiple multiplexed sub-circuits and the multiple multiplexed control signal lines 12 on the substrate.

[0213] In an exemplary embodiment, as shown in FIG16, the shielding structure 30 and the multiple first power connection lines VL11 are integrated into one structure.

[0214] In an exemplary embodiment, in the display substrate shown in FIG16, the first power line VDD is located in at least one film layer of the first source / drain metal layer and the second source / drain metal layer. FIG16 is illustrated with the example of the first power line VDD being located in the second source / drain metal layer.

[0215] In an exemplary embodiment, in the display substrate provided in FIG16, the first power connection line VL11 is located in the second source / drain metal layer, the second power connection line VL16 is located in one of the first source / drain metal layers and the second source / drain metal layer, and the third power connection line VL13 is located in one of the first source / drain metal layers and the second source / drain metal layer.

[0216] In an exemplary embodiment, in the display substrate provided in FIG16, the second power supply line VL2 is located in at least one film layer of the first source / drain metal layer and the second source / drain metal layer.

[0217] In an exemplary embodiment, in the display substrate provided in FIG16, the shielding structure 30 can be a planar structure.

[0218] Figure 17 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment, and Figure 18 is a partial schematic diagram of the film layers in Figure 17. As shown in Figures 17 and 18, N = 2; the shielding structure 30 includes: a plurality of shielding portions 31 disposed at intervals, the shielding portions 31 being disposed in the second source / drain metal layer, and at least one shielding portion 31 having its orthographic projection on the substrate at least partially overlapping with the orthographic projection of the first electrode 22 of the first light-emitting device on the substrate.

[0219] In an exemplary embodiment, as shown in FIG17, at least one shielding portion 31 and at least one power branch segment L1 are integrally formed.

[0220] In an exemplary embodiment, in the display substrate provided in FIG17, the first power line VDD is located in at least one film layer of the first source / drain metal layer and the second source / drain metal layer. FIG17 is illustrated with the example of the first power line VDD being located in the second source / drain metal layer.

[0221] In an exemplary embodiment, in the display substrate provided in FIG17, the first power connection line VL11 is located in the second source / drain metal layer, the second power connection line VL12 is located in one of the first source / drain metal layers and the second source / drain metal layer, and the third power connection line VL13 is located in one of the first source / drain metal layers and the second source / drain metal layer.

[0222] In an exemplary embodiment, in the display substrate provided in FIG17, the second power supply line VL2 is located in at least one film layer of the first source / drain metal layer and the second source / drain metal layer.

[0223] Figure 19 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment (8), Figure 20 is a partial film layer schematic diagram of Figure 19, Figure 21 is a partially enlarged schematic diagram of a display substrate provided in an exemplary embodiment (9), and Figure 22 is a partial film layer schematic diagram of Figure 21. As shown in Figures 19 to 22, N = 3; the shielding structure 30 includes: multiple shielding lines 32, the shielding lines 32 are located in the third source / drain metal layer; the shielding lines 32 extend at least partially along the second direction D2 and are electrically connected to the second power supply line VL2.

[0224] In an exemplary embodiment, as shown in Figures 19 to 22, the orthographic projection of the shielding line 32 on the substrate at least partially overlaps with the orthographic projections of the multiple multiplexed control signal lines 12 and the first power connection line VL11 on the substrate, and at least partially overlaps with the orthographic projection of at least one power branch segment L1 on the substrate.

[0225] In an exemplary embodiment, in the display substrate provided in Figures 19 to 22, the first power line VDD is located in at least one film layer of the first source / drain metal layer and the second source / drain metal layer.

[0226] In an exemplary embodiment, in the display substrate provided in Figures 19 to 22, the first power connection line VL11 is located in the second source / drain metal layer, the second power connection line VL12 is located in the first source / drain metal layer, one of the second source / drain metal layer and the third source / drain metal layer, and the third power connection line VL13 is located in one of the first source / drain metal layer, the second source / drain metal layer and the third source / drain metal layer.

[0227] In an exemplary embodiment, in the display substrate provided in Figures 19 to 22, the second power supply line VL2 is located in at least one of the first source / drain metal layers, the second source / drain metal layer, and the third source / drain metal layer. Figure 19 illustrates an example where the second power supply line VL2 is located in the third source / drain metal layer, in which case the second power supply line VL2 and the shielding line 32 are integrally formed. Figure 20 illustrates an example where the second power supply line VL2 is located in the second source / drain metal layer, in which case the orthographic projection of the second power supply line VL2 on the substrate at least partially overlaps with the orthographic projection of the shielding line 32 on the substrate.

[0228] In an exemplary embodiment, the display substrate further includes a plurality of gate lines. The gate lines extend at least partially along a first direction and are electrically connected to sub-pixels.

[0229] In some examples, in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include at least: a substrate, and a circuit structure layer, a light-emitting structure layer, and an encapsulation structure layer sequentially disposed on the substrate. The circuit structure layer may include at least: pixel driving circuits for multiple sub-pixels, each sub-pixel's pixel driving circuit may include multiple transistors and at least one capacitor. The light-emitting structure layer may include at least: light-emitting devices for multiple sub-pixels. In other examples, a touch structure layer may be disposed on the side of the encapsulation structure layer away from the substrate to integrate touch functionality.

[0230] Figure 22 is a partial cross-sectional view along line AA in Figure 6. Figure 22 illustrates the structure of a sub-pixel in the display area as an example, with the gate metal layer group including a first gate metal layer and a second gate metal layer, and the source / drain metal layer group including a first source / drain metal layer and a second source / drain metal layer. Figure 22 also illustrates the pixel driving circuit of each sub-pixel, including a transistor 51 and a capacitor 53 as an example. The transistor 51 can be a low-temperature polycrystalline silicon thin-film transistor.

[0231] In an exemplary embodiment, as shown in FIG22, the circuit structure layer 42 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 100. A first insulating layer 101 (which may be called a buffer layer) may be disposed between the substrate and the semiconductor layer; a second insulating layer 102 (which may be called a first gate insulating layer) may be disposed between the semiconductor layer and the first gate metal layer; a third insulating layer 103 (which may be called a second gate insulating layer) may be disposed between the first gate metal layer and the second gate metal layer; a fifth insulating layer 105 (which may be called an interlayer insulating layer) may be disposed between the second gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 (which may also be called a passivation layer) and a seventh insulating layer 107 (which may also be called a first planarization layer) may be disposed between the first source / drain metal layer and the second source / drain metal layer, wherein the seventh insulating layer 107 may be located on the side of the sixth insulating layer 106 away from the substrate 100; and an eighth insulating layer 108 (which may also be called a second planarization layer) may be disposed on the side of the second source / drain metal layer away from the substrate 100. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fifth insulating layer 105, and the sixth insulating layer 106 can be inorganic insulating layers, while the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. This disclosure uses a display substrate comprising two gate metal layers and two source / drain metal layers as an example for illustration. However, this embodiment is not limited to this. In other examples, a bottom shielding metal layer (BSM) can be disposed on the side of the first insulating layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistors in the pixel driving circuit to prevent external light from affecting the performance of the transistors. In other examples, only the sixth or seventh insulating layer can be disposed between the first and second source / drain metal layers.

[0232] In an exemplary embodiment, as shown in FIG22, the semiconductor layer of the display area may include at least a first active layer 510 of the transistor 51 located in the display area. The first active layer 510 of the transistor 51 may include a first region 5101, a second region 5102, and a channel region 5100 located between the first region 5101 and the second region 5102.

[0233] In an exemplary embodiment, as shown in FIG22, the first gate metal layer of the display area may include at least: a first gate 513 of the transistor 51 located in the display area and a first electrode 531 of the capacitor 53. The orthogonal projection of the first gate 513 of the transistor 51 onto the substrate 100 may cover the orthogonal projection of the channel region 5100 of the first active layer 510 onto the substrate 100.

[0234] In an exemplary embodiment, as shown in FIG22, the second gate metal layer of the display area may include at least the second electrode 532 of the capacitor 53 located in the display area. The orthographic projections of the second electrode 532 and the first electrode 531 of the capacitor 53 onto the substrate 100 may at least partially overlap, for example, they may coincide.

[0235] In an exemplary embodiment, as shown in FIG22, the first source-drain metal layer of the display area may include at least a first source 511 and a first drain 512 of the transistor 51 located in the display area. The fifth insulating layer 105 may have multiple pixel vias (e.g., including a first pixel via and a second pixel via) in the display area. The fifth insulating layer 105, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 5101 of the first active layer 510; the fifth insulating layer 105, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 5102 of the first active layer 510. The first source 511 of the transistor 51 can be electrically connected to the first region 5101 of the first active layer 510 through the first pixel via, and the first drain 512 can be electrically connected to the second region 5102 of the first active layer 510 through the second pixel via.

[0236] In an exemplary embodiment, as shown in FIG22, the second source-drain metal layer of the display area may include at least a first transition electrode 541. The first transition electrode 541 can be electrically connected to the first drain 512 of the transistor 51 of the pixel driving circuit through a fifth pixel via formed by the sixth insulating layer 106 and the seventh insulating layer 107. In this example, the first transition electrode 541 can be used to realize the electrical connection between the pixel driving circuit and the light-emitting device.

[0237] In an exemplary embodiment, the gate lines of the display area may be located, for example, in the first gate metal layer and the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer; and the first power lines of the display area may be located, for example, in the second source-drain metal layer. This embodiment is not limited in this respect.

[0238] In an exemplary embodiment, as shown in FIG22, the light-emitting structure layer 43 may include a pixel definition layer 134 and a plurality of light-emitting devices located in the display area. For example, each light-emitting device may include a first electrode 131, an organic light-emitting layer 132, and a second electrode 133 stacked thereon. The first electrode 131 of the light-emitting device may be an anode, and the first electrode 131 may be disposed on an eighth insulating layer 108 and electrically connected to a first transition electrode 541 through a sixth pixel via formed in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 may have a plurality of pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 may emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0239] In an exemplary embodiment, the light-emitting structure layer may include an anode layer, an organic material layer, and a cathode layer. The anode layer includes a first electrode of at least one light-emitting device located in the display area. The organic material layer includes an organic light-emitting layer of at least one light-emitting device located in the display area. The cathode layer includes a second electrode of at least one light-emitting device located in the display area.

[0240] In an exemplary embodiment, the organic light-emitting layer 132 of the light-emitting device may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be utilized to emit light at the required grayscale.

[0241] In exemplary embodiments, the light-emitting layers of light-emitting devices of different colors can be different. For example, a red light-emitting device includes a red light-emitting layer, a green light-emitting device includes a green light-emitting layer, and a blue light-emitting device includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer located on one side of the light-emitting layer can be common layers, and the electron injection layer and electron transport layer located on the other side of the light-emitting layer can also be common layers. In exemplary embodiments, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In exemplary embodiments, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0242] In an exemplary embodiment, as shown in FIG22, the encapsulation structure layer 44 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external moisture cannot enter the light-emitting device. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 141 and the third encapsulation layer 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have intruded into the interior. However, this embodiment is not limited in this respect. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0243] In an exemplary embodiment, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be disposed in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be disposed in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0244] In an exemplary embodiment, as shown in FIG22, the touch structure layer 45 of the display area may include, in the direction perpendicular to the display substrate, a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a touch protective layer (TOC) 154 sequentially disposed therefrom. The touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the touch protective layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure interconnected with each other. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer 153. However, this embodiment is not limited in this respect. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In an exemplary embodiment, the first touch electrode may be a driving (Tx) electrode, and the second touch electrode may be a sensing (Rx) electrode. Alternatively, the first touch electrode may be a sensing (Rx) electrode, and the second touch electrode may be a driving (Tx) electrode. This embodiment is not limited in this respect.

[0245] In an exemplary embodiment, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of the following shapes: triangle, square, trapezoid, parallelogram, pentagon, hexagon, and other polygons, which are not limited to the embodiments disclosed herein.

[0246] In an exemplary embodiment, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by interlacing multiple metal wires. The metal mesh can include multiple mesh patterns, and the mesh patterns can be polygons composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0247] Figure 23 is a second partial cross-sectional view along AA in Figure 6. In an exemplary embodiment, as shown in Figure 23, the circuit structure layer 42 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 100. A fourth insulating layer 104 (which may be referred to as the third gate insulating layer) may be disposed between the second gate metal layer and the third gate metal layer; a fifth insulating layer 105 (which may be referred to as the interlayer insulating layer) may be disposed between the third gate metal layer and the first source / drain metal layer. The fourth insulating layer 104 may be an inorganic insulating layer. This disclosure is based on an example of a display substrate comprising three gate metal layers and two source / drain metal layers. However, this embodiment is not limited thereto. The remaining structure of the display area of ​​the display substrate in this example can be referred to the description of the embodiment shown in Figure 22, and will not be repeated here.

[0248] In an exemplary embodiment, the third gate metal layer may include a third electrode 533 of a capacitor located in the display area. The third electrode 533 is connected to the first electrode 531, and its orthographic projection on the substrate 100 at least partially overlaps with the orthographic projection of the second electrode 532 on the substrate 100, for example, they may coincide.

[0249] In an exemplary embodiment, the gate lines of the display area may be located in at least one of the first gate metal layer, the second gate metal layer, and the third gate metal layer; the data lines of the display area may be located in the second source-drain metal layer; and the first power lines of the display area may be located in the second source-drain metal layer. This embodiment is not limited in this respect.

[0250] Figure 24 is a partial cross-sectional view along AA in Figure 6. In an exemplary embodiment, as shown in Figure 24, the circuit structure layer 42 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 100. An eighth insulating layer 108 (which may also be called a second planarization layer) may be disposed between the second and third source / drain metal layers, and a ninth insulating layer 109 (which may also be called a third planarization layer) may be disposed on the side of the third source / drain metal layer away from the substrate 100. This disclosure is illustrated using a display substrate comprising two gate metal layers and three source / drain metal layers as an example. In this example, the electrical connection between the pixel driving circuit and the light-emitting device can be achieved through the first transition electrode 541 and the second transition electrode 542. The remaining structure of the display area of ​​the display substrate in this example can be described with reference to the embodiment shown in Figure 22, and will not be repeated here.

[0251] In an exemplary embodiment, the gate lines of the display area may be located, for example, in the first gate metal layer and the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer or the third source-drain metal layer; and the first power line of the display area may be located, for example, in the second source-drain metal layer or the third source-drain metal layer. This embodiment is not limited in this respect.

[0252] Figure 25 is a partial cross-sectional view along AA in Figure 6. In an exemplary embodiment, as shown in Figure 25, the circuit structure layer 42 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 100. A fourth insulating layer 104 (which may be referred to as the third gate insulating layer) may be disposed between the second and third gate metal layers, an eighth insulating layer 108 (which may also be referred to as the second planarization layer) may be disposed between the second and third source / drain metal layers, and a ninth insulating layer 109 (which may also be referred to as the third planarization layer) may be disposed on the side of the third source / drain metal layer away from the substrate 100. The fourth insulating layer 104 may be an inorganic insulating layer, and the ninth insulating layer 109 may be an organic insulating layer. This disclosure is illustrated using a display substrate comprising three gate metal layers and three source / drain metal layers as an example. In this example, the electrical connection between the pixel driving circuit and the light-emitting device can be achieved through the first transition electrode 541 and the second transition electrode 542. The remaining structure of the display area of ​​the display substrate in this example can be described with reference to the embodiments shown in Figures 22 and 23, and will not be repeated here.

[0253] In an exemplary embodiment, the gate lines of the display area may be located in at least one film layer of the first gate metal layer, the second gate metal layer, and the third gate metal layer, the data lines of the display area may be located in the second source-drain metal layer or the third source-drain metal layer, and the first power line of the display area may be located in the second source-drain metal layer or the third source-drain metal layer. This embodiment is not limited in this respect.

[0254] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0255] Figure 26 is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. As shown in Figure 26, an embodiment of the present disclosure also provides a display device 1000, including: a display substrate 2000 provided in any of the foregoing embodiments.

[0256] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0257] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0258] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0259] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The substrate includes: a display area and a non-display area located on at least one side of the display area; Multiple sub-pixels are located on one side of the substrate and in the display area. At least one of the multiple sub-pixels includes a pixel driving circuit and a light-emitting device. The pixel driving circuit is used to drive the light-emitting device. Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, configured to transmit data signals to the multiple sub-pixels; A multiplexing circuit, at least partially located in the display area and connected to the multiple data lines; Multiple data output lines are located at least in the non-display area and connected to the multiplexing circuit, wherein the number of multiple data output lines is less than the number of multiple data lines; A shielding structure, at least partially located in the display area, wherein the orthographic projection of the shielding structure on the substrate at least partially overlaps with the orthographic projection of the light-emitting device of the at least one sub-pixel on the substrate, and at least partially overlaps with the orthographic projection of the multiplexing circuit on the substrate.

2. The display substrate according to claim 1, wherein, The multiplexing circuit includes: multiple multiplexing sub-circuits and multiple multiplexing control signal lines. The multiple multiplexing sub-circuits are located on the side of the multiple multiplexing control signal lines close to the display area and are arranged along a first direction. The multiple multiplexing control signal lines extend along the first direction and are arranged along a second direction, and the first direction and the second direction intersect. Each of the plurality of multiplexed sub-circuits is electrically connected to at least one of the plurality of data output lines and at least two of the plurality of data lines, and is configured to transmit the data signal provided by the at least one data output line to the at least two data lines in a time-division manner under the control of the plurality of multiplexed control signal lines. Each multiplexed sub-circuit includes multiple multiplexed transistors, and the orthographic projection of the light-emitting device of the at least one sub-pixel on the substrate at least partially overlaps with the orthographic projection of at least one of the multiple multiplexed transistors on the substrate, and the multiple multiplexed control signal lines are electrically connected to the control electrodes of the multiple multiplexed transistors.

3. The display substrate according to claim 2, wherein, The orthographic projection of the light-emitting device of at least one sub-pixel on the substrate overlaps with the orthographic projection portion of at least one of the multiplexed control signal lines on the substrate, and / or overlaps with the orthographic projection portion of the at least one multiplexed transistor on the substrate.

4. The display substrate according to claim 3, wherein, The light-emitting device of the at least one sub-pixel includes a first electrode, which is electrically connected to the pixel driving circuit. The orthographic projection of the first electrode on the substrate overlaps with the orthographic projection portion of at least one of the plurality of multiplexed control signal lines on the substrate, and / or overlaps with the orthographic projection portion of the at least one multiplexed transistor on the substrate.

5. The display substrate according to claim 4, wherein, The shielding structure is located between the first electrode and the at least one multiplexed transistor in a direction perpendicular to the substrate.

6. The display substrate according to claim 1, wherein, The orthographic projection of the shielding structure on the substrate and the orthographic projection of the pixel driving circuit of the plurality of sub-pixels on the substrate do not overlap.

7. The display substrate according to claim 4 or 5, wherein, The non-display area includes a bonding area and a border area. The bonding area is located on one side of the display area, and the border area is located on the other side of the display area. The bonding area and the border area are connected. The light-emitting device of the at least one sub-pixel further includes a second electrode. The display substrate further includes: Multiple first power lines are located in the display area. The first power lines extend at least partially along the second direction and are electrically connected to the multiple sub-pixels. The orthographic projection of the first power lines on the substrate and the orthographic projection of the multiple multiplexed sub-circuits on the substrate do not overlap. The first power supply line is located in the display area and the binding area, and is electrically connected to the plurality of first power lines; The second power supply line is located in the frame area and the bonding area, and is electrically connected to the second electrode. The orthographic projection of the second power supply line on the substrate is located on the side of the orthographic projection of the first power supply line on the substrate away from the display area. The shielding structure is electrically connected to one of the first power supply line and the second power supply line.

8. The display substrate according to claim 7, wherein, The first power supply line includes: a first power connection line, a second power connection line, and a third power connection line; The first power connection line is located in the display area and the bonding area, and is electrically connected to the plurality of first power lines. The orthographic projection of the first power connection line on the substrate overlaps with the orthographic projection of the multiplexing circuit on the substrate, and also overlaps with the orthographic projection of the plurality of multiplexing control signal lines on the substrate. The second power connection line is located in the bonding area and is electrically connected to the first power connection line. The orthographic projection of the second power connection line on the substrate is located on the side of the orthographic projection of the first power connection line on the substrate away from the display area. The third power connection line is located in the bonding area and is electrically connected to the second power connection line. The orthographic projection of the third power connection line on the substrate is located on the side of the orthographic projection of the second power connection line on the substrate that is away from the display area.

9. The display substrate according to claim 8, wherein, The first power connection line includes: a power connection segment and a plurality of power branch segments, the power connection segment being connected to the plurality of power branch segments, the power connection segment extending at least partially along the first direction, and the power branch segments extending at least partially along the second direction; The number of the plurality of power branch segments is less than the number of the plurality of first power lines, and at least one of the plurality of power branch segments has its orthographic projection on the substrate overlapping with the orthographic projection of the multiplexing circuit on the substrate.

10. The display substrate according to claim 9, wherein, The boundary of the display area includes multiple rounded corner boundaries. The display area is divided into multiple display sub-areas arranged along the first direction. The display sub-area including the rounded corner boundaries is called the first display sub-area, and the display area other than the first display sub-area is called the second display sub-area. The plurality of power supply branch segments are located in the second display sub-area.

11. The display substrate according to claim 10, further comprising: A circuit structure layer disposed on the substrate, the circuit structure layer comprising: a gate metal layer group and a source / drain metal layer group sequentially stacked on the substrate, the source / drain metal layer group comprising: a first source / drain metal layer to an Nth source / drain metal layer, where N is a positive integer greater than or equal to 2; The multiple multiplexed control signal lines are located in the first source-drain metal layer, the first power supply line and the second power supply line are located in at least one of the source-drain metal layers from the first source-drain metal layer to the Nth source-drain metal layer, and the shielding structure is located in one of the source-drain metal layers other than the first source-drain metal layer.

12. The display substrate according to claim 11, wherein, N = 2 or 3; When N=3, at least a portion of the shielding structure is located in the first display sub-area and the second display sub-area. The shielding structure is located in the third source-drain metal layer and is electrically connected to one of the first power supply line and the second power supply line. The orthographic projection of the shielding structure on the substrate also overlaps at least partially with the orthographic projections of the plurality of multiplexed sub-circuits, the plurality of multiplexed control signal lines and the first power connection line on the substrate. Alternatively, when N=2, the shielding structure is located in the first display sub-area, the shielding structure is located in the second source / drain metal layer and is electrically connected to the second power supply line, and the orthographic projection of the shielding structure on the substrate also overlaps at least partially with the orthographic projections of the plurality of multiplexed sub-circuits and the plurality of multiplexed control signal lines on the substrate; Alternatively, when N=2, at least a portion of the shielding structure is located in the first display sub-region and the second display sub-region. The shielding structure is located in the second source / drain metal layer and is electrically connected to the first power supply line. The orthographic projection of the shielding structure on the substrate also overlaps at least partially with the orthographic projections of the plurality of multiplexed sub-circuits and the plurality of multiplexed control signal lines on the substrate. The shielding structure and the plurality of first power connection lines are an integral structure.

13. The display substrate according to claim 11, wherein, The shielding structure includes: a plurality of shielding parts arranged at intervals, wherein the shielding parts are disposed in the second source-drain metal layer; At least one of the plurality of spaced shielding portions has its orthographic projection on the substrate at least partially overlapping with the orthographic projection of the first electrode of the light-emitting device on the substrate.

14. The display substrate according to claim 13, wherein, The at least one shielding part and at least one of the plurality of power branch segments are integral structures.

15. The display substrate according to claim 11, wherein, N＝3； The shielding structure includes: multiple shielding lines located in the third source / drain metal layer; at least a portion of at least one of the multiple shielding lines extends along the second direction and is electrically connected to the second power supply line; The orthographic projection of the at least one shielding line on the substrate overlaps with the orthographic projections of the plurality of multiplexed sub-circuits, the plurality of multiplexed control signal lines, and the first power connection line on the substrate, and also overlaps with the orthographic projection of the at least one power branch segment on the substrate.

16. The display substrate according to any one of claims 12 to 15, wherein, When N=3, the first power line is located in at least one of the first and second source / drain metal layers. The first power connection line is located in the second source-drain metal layer, the second power connection line is located in the first source-drain metal layer, one of the second source-drain metal layer and the third source-drain metal layer, and the third power connection line is located in one of the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer. The second power supply line is located in at least one of the first source / drain metal layers, the second source / drain metal layer, and the third source / drain metal layer.

17. The display substrate according to any one of claims 12 to 15, wherein, When N=2, the first power line is located in at least one of the first source / drain metal layers and the second source / drain metal layer. The first power connection line is located in the second source / drain metal layer, the second power connection line is located in one of the first source / drain metal layers and the second source / drain metal layer, and the third power connection line is located in one of the first source / drain metal layers and the second source / drain metal layer. The second power supply line is located in at least one of the first source / drain metal layers and the second source / drain metal layer.

18. The display substrate according to claim 8, wherein, The bonding area includes: a lead wire area, a bending area, and a composite circuit area arranged sequentially away from the display area; The second power connection line is located in the lead area and the bend area, the third power connection line is located in the composite circuit area, and the second power supply line portion is located in the lead area, the bend area, and the composite circuit area.

19. A display device, comprising: The display substrate as described in any one of claims 1 to 18.

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