Memory access control circuit and method, electronic devices and medium
By introducing an MTE module into the memory access control circuit to compare virtual addresses and tags, the problem of increased memory access time caused by virtual address translation is solved, and more efficient memory access is achieved.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- VIVO MOBILE COMM CO LTD
- Filing Date
- 2025-12-09
- Publication Date
- 2026-06-18
AI Technical Summary
In existing technologies, when a central processing unit (CPU) accesses memory, it needs to translate the virtual address into a physical address before performing tag comparison, which increases the memory access time.
A Memory Tag Extension (MTE) module is introduced into the memory access control circuit. By obtaining the virtual address and access tag in the memory access request, the memory tag is retrieved from the cache for comparison, thus avoiding the translation from virtual address to physical address.
It reduces memory access time and improves memory access efficiency.
Smart Images
Figure CN2025141161_18062026_PF_FP_ABST
Abstract
Description
Memory access control circuits, methods, electronic devices and media
[0001] Cross-references to related applications
[0002] This application claims priority to Chinese Patent Application No. 202411821570.7, filed on December 11, 2024, the entire contents of which are incorporated herein by reference. Technical Field
[0003] This application belongs to the field of computer technology, and specifically relates to a memory access control circuit, method, electronic device, and medium. Background Technology
[0004] Memory Tagging Extension (MTE) is a new feature introduced in the Armv8.5-A architecture, designed to improve system security by detecting and preventing memory access violations through hardware mechanisms.
[0005] In related technologies, when a Central Processing Unit (CPU) initiates a memory access request via the MTE method, it first needs to use an address translation module to convert the virtual address of the memory unit to be accessed in the access request into a physical address. Then, based on the physical address, it retrieves the tag of the memory unit to be accessed from the tag storage area of the memory and compares it with the access tag in the access request. If the access tag in the access request matches the retrieved tag of the memory unit to be accessed, the CPU can access the memory unit to be accessed based on the physical address.
[0006] However, every time the CPU accesses memory, it needs to first translate the virtual address of the memory into a physical address before it can perform subsequent tag comparison, which increases the memory access time. Summary of the Invention
[0007] The purpose of this application is to provide a memory access control circuit, method, electronic device, and medium that can improve memory access efficiency.
[0008] In a first aspect, embodiments of this application provide a memory access control circuit, the memory access control circuit comprising:
[0009] The memory tag extends the MTE module, and the processor and first cache are connected to the MTE module;
[0010] The MTE module is used to obtain the virtual address and access tag of the memory unit to be accessed in memory from the memory access request transmitted by the processor; and obtain the memory tag of the memory unit to be accessed from the first cache according to the virtual address; and compare the access tag and the memory tag; and transmit the comparison result to the processor.
[0011] The processor is used to process the access results of the storage unit based on the comparison results. The storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.
[0012] Secondly, embodiments of this application provide an electronic device including a memory access control circuit as described in any one of the first aspects.
[0013] Thirdly, embodiments of this application provide a memory access control method, applied to the memory access control circuit described in the first aspect, the method comprising:
[0014] From the memory access request, obtain the virtual address and access tag of the memory unit to be accessed in memory;
[0015] Based on the virtual address, obtain the memory tag of the memory unit to be accessed;
[0016] The access tag and the memory tag are compared to obtain the comparison result;
[0017] Based on the comparison results, the access results of the storage unit are processed. The storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.
[0018] Fourthly, embodiments of this application provide an electronic device including a processor and a memory, wherein the memory stores programs or instructions executable on the processor, and the programs or instructions, when executed by the processor, implement the steps of the memory access control method as described in the third aspect.
[0019] Fifthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the memory access control method as described in the third aspect.
[0020] In a sixth aspect, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the memory access control method as described in the first aspect.
[0021] In a seventh aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the memory access control method as described in the first aspect.
[0022] In this embodiment, the memory access control circuit includes a Memory Tag Extension (MTE) module, a processor, and a first cache connected to the MTE module. The MTE module can obtain the virtual address and access tag of the memory unit to be accessed from the memory access request transmitted by the processor; obtain the memory tag of the memory unit to be accessed from the first cache based on the virtual address; compare the access tag and the memory tag; and transmit the comparison result to the processor. Therefore, the processor can process the access result of the memory unit, which is either the memory unit to be accessed or the cache unit corresponding to the virtual address, based on the comparison result. Thus, when accessing memory, the MTE module only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request, and obtain the memory tag of the memory unit to be accessed from the first cache based on the virtual address, and compare the access tag and the memory tag. Therefore, using the memory access control circuit of this application, tag comparison can be performed without converting the virtual address to a physical address, thereby effectively reducing the memory access time and improving memory access efficiency. Attached Figure Description
[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 is a schematic diagram of a memory access control circuit provided in an embodiment of this application;
[0025] Figure 2 is a schematic diagram of a memory access control circuit provided in an embodiment of this application;
[0026] Figure 3 is a schematic diagram of a memory access control circuit provided in an embodiment of this application;
[0027] Figure 4 is a schematic diagram of a memory access control circuit provided in an embodiment of this application;
[0028] Figure 5 is a schematic diagram of a memory access control circuit provided in an embodiment of this application;
[0029] Figure 6 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;
[0030] Figure 7 is a flowchart illustrating a memory access control method provided in an embodiment of this application;
[0031] Figure 8 is a flowchart illustrating a memory access control method provided in an embodiment of this application;
[0032] Figure 9 is a flowchart illustrating a memory access control method provided in an embodiment of this application;
[0033] Figure 10 is a flowchart illustrating a memory access control method provided in an embodiment of this application;
[0034] Figure 11 is a flowchart illustrating a memory access control method provided in an embodiment of this application;
[0035] Figure 12 is a schematic diagram of a memory access control circuit provided in an embodiment of this application;
[0036] Figure 13 is a flowchart illustrating a memory access control method provided in an embodiment of this application;
[0037] Figure 14 is a schematic diagram of a memory access control device provided in an embodiment of this application;
[0038] Figure 15 is a schematic diagram of a memory access control device provided in an embodiment of this application;
[0039] Figure 16 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;
[0040] Figure 17 is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application. Detailed Implementation
[0041] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.
[0042] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0043] The terms "at least one," "at least one of," etc., used in the specification and claims of this application refer to any one, any two, or a combination of two or more of the included items. For example, at least one of a, b, and c can mean: "a," "b," "c," "a and b," "a and c," "b and c," and "a, b, and c," where a, b, and c can be single or multiple. Similarly, "at least two" refers to two or more items, and its meaning is similar to that of "at least one."
[0044] The memory access control circuit, method, electronic device, and medium provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.
[0045] The following will explain the terminology used in the embodiments of this application.
[0046] 1) The Memory Management Unit (MMU) is a piece of computer hardware responsible for handling memory access requests from the Central Processing Unit (CPU). Its main functions include virtual address to physical address translation, memory protection, CPU cache control, and, in simpler computer architectures, bus arbitration and memory switching.
[0047] 2) The Translation Look Aside Buffer (TLB), also known as the page table cache or address-bypass cache, is a type of CPU cache used by the Memory Management Unit to improve the speed of virtual-to-physical address translation. All desktop and server processors (such as x86) use the TLB. The TLB has a fixed number of slots for storing tag page table entries that map virtual addresses to physical addresses. It is a typical example of Content-Addressable Memory (CAM). Its search keyword is the virtual memory address, and its search result is the physical address. If the requested virtual address exists in the TLB, the CAM will provide a very fast match, and the obtained physical address can then be used to access memory. If the requested virtual address is not in the TLB, the tag page table is used for virtual-to-physical address translation, but accessing the tag page table is much slower than using the TLB. Some systems allow the tag page table to be swapped to secondary memory, in which case virtual-to-physical address translation can take a very long time.
[0048] The Advanced eXtensible Interface (AXI) is a bus protocol and a key component of the Advanced Microcontroller Bus Architecture (AMBA) protocol proposed by ARM. It is an on-chip bus designed for high performance, high bandwidth, and low latency. In high-performance on-chip systems, the AXI bus is commonly used to connect multiple master and slave devices, enabling address and data transfer between multiple memory-mapped devices.
[0049] The AXI Coherency Extensions (ACE) protocol is a bus protocol designed by ARM to provide system-level cache coherency. Built on the AXI protocol, it adds extra signals and channels to support cache coherency, enabling multiple processors or agents to efficiently share data without software intervention to maintain cache consistency.
[0050] In the memory access control circuit provided in this application embodiment, by adding an MTE module connected to the processor, the MTE module can obtain the virtual address and access tag of the memory unit to be accessed from the memory access request transmitted by the processor; obtain the memory tag of the memory unit to be accessed from the first cache according to the virtual address; compare the access tag and the memory tag; and transmit the comparison result to the processor. Therefore, the processor can process the access result of the storage unit, which is the memory unit to be accessed or the cache unit corresponding to the virtual address, according to the comparison result. Thus, when accessing memory, the MTE module only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request, and obtain the memory tag of the memory unit to be accessed from the first cache according to the virtual address, and compare the access tag and the memory tag. Therefore, by using the memory access control circuit of this application, tag comparison can be performed without converting the virtual address to a physical address, thereby effectively reducing the memory access time and improving memory access efficiency.
[0051] This application provides a memory access control circuit. Figure 1 shows a schematic diagram of the structure of a memory access control circuit 100 provided in this application embodiment. As shown in Figure 1, the memory access control circuit 100 provided in this application embodiment may include:
[0052] The memory tag extension module 11, and the processor 12 and the first cache 13 connected to the MTE module 11.
[0053] MTE module 11 is used to obtain the virtual address and access tag of the memory unit to be accessed in memory from the memory access request transmitted by processor 12; and obtain the memory tag of the memory unit to be accessed from the first cache 13 according to the virtual address; and compare the access tag and the memory tag; and transmit the comparison result to processor 12; processor 12 is used to process the access result of the storage unit according to the comparison result, wherein the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.
[0054] In some embodiments of this application, the first buffer 13 described above is used to cache memory tags of a portion of memory units in memory.
[0055] In some embodiments of this application, the processor 12 can be a CPU or a CPU core, which can be determined according to actual needs. This embodiment does not impose specific limitations here.
[0056] In some embodiments of this application, the memory can be Double Data Rate Synchronous Dynamic Random Access Memory (DDR) or Static Random-Access Memory (SRAM), and this embodiment does not impose any specific limitations on it.
[0057] In some embodiments of this application, the MTE module 11 can determine the tag address corresponding to the virtual address, and then obtain the memory tag of the memory unit to be accessed from the cache unit with the tag address in the first cache 13.
[0058] In some embodiments of this application, if the comparison result indicates that the access tag and the memory tag match, the processor 12 can determine that the access to the storage unit is a legitimate access based on the comparison result, and the processor 12 can perform subsequent data processing on the access result.
[0059] In some embodiments of this application, if the comparison result indicates that the access tag and the memory tag do not match, the processor 12 can determine that the access to the storage unit is an illegal access based on the comparison result. The processor 12 can not perform any further data processing on the access result and record the illegal access to the storage unit.
[0060] It should be noted that if the processor 12 determines that the access to the above-mentioned storage unit is an illegal access based on the above comparison results, it can also record the illegal access to the above-mentioned storage unit and perform subsequent data processing on the access results. When the number of recorded illegal accesses reaches a preset number, no further data processing will be performed on the access results.
[0061] In some embodiments of this application, the comparison result indicates that the access tag and the memory tag match, which can be understood as the access tag and the memory tag being the same. Conversely, the comparison result indicates that the access tag and the memory tag do not match, which can be understood as the access tag and the memory tag being different.
[0062] For example, when both the access tag and the memory tag are 0x07, the MTE module 11 can determine that the access tag and the memory tag match. The MTE module 11 can then send the matching result of the access tag and the memory tag to the processor 12. The processor 12 can determine that the access to the storage unit is a legitimate access based on the matching result of the access tag and the memory tag, and the processor 12 can perform subsequent data processing on the access result.
[0063] For example, when the access tag is 0x07 and the memory tag is 0x08, the MTE module 11 can determine that the access tag and the memory tag do not match. The MTE module 11 can send the comparison result of the mismatch between the access tag and the memory tag to the processor 12. The processor 12 can determine that the access to the storage unit is an illegal access based on the comparison result of the mismatch between the access tag and the memory tag. The processor 12 can choose not to perform any further data processing on the access result and record this illegal access to the storage unit.
[0064] In the memory access control circuit provided in this application embodiment, by adding an MTE module connected to the processor, the MTE module can obtain the virtual address and access tag of the memory unit to be accessed from the memory access request transmitted by the processor; obtain the memory tag of the memory unit to be accessed from the first cache according to the virtual address; compare the access tag and the memory tag; and transmit the comparison result to the processor. Therefore, the processor can process the access result of the storage unit according to the comparison result, where the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address. Thus, when accessing memory, the MTE module only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request, and obtain the memory tag of the memory unit to be accessed from the first cache according to the virtual address, and compare the access tag and the memory tag. Therefore, by using the memory access control circuit of this application, tag comparison can be performed without converting the virtual address to a physical address, which can effectively reduce the memory access time and thus improve memory access efficiency.
[0065] In some embodiments of this application, referring to FIG1 and FIG2, the MTE module may include a separation module 111 and a comparison module 112 connected to the separation module 111. The separation module 111 is connected to the processor 12 and the first cache 13, and the comparison module 112 is connected to the processor 12.
[0066] In some embodiments of this application, the separation module 111 is used to separate the virtual address and the access tag from the memory access request, obtain the memory tag from the first cache 13 according to the virtual address, and transmit the access tag and the memory tag to the comparison module 112.
[0067] The comparison module 112 is used to compare the access tag and the memory tag and transmit the comparison result to the processor 12.
[0068] In some embodiments of this application, the length of the memory access request can be 16 bits. The data corresponding to the 4 high bits of the memory access request is the access tag, and the data corresponding to the 12 low bits of the memory access request is the virtual address.
[0069] In some embodiments of this application, after receiving the memory access request transmitted by the processor 12, the separation module 111 can separate the access tag from the four high bits of the memory access request and separate the virtual address from the twelve low bits of the memory access request.
[0070] In some embodiments of this application, the separation module 111 determines the tag address corresponding to the virtual address, and then obtains the memory tag of the memory unit to be accessed from the cache unit with the tag address in the first cache 13.
[0071] In some embodiments of this application, when the access tag and the memory tag are the same, the comparison module 112 determines that the access tag and the memory tag match, and transmits the comparison result of the access tag and the memory tag matching to the processor 12.
[0072] In some embodiments of this application, when the access tag and the memory tag are the same, the comparison module 112 determines that the access tag and the memory tag match, and transmits the comparison result where the access tag and the memory tag do not match to the processor 12.
[0073] Thus, by adding a separation module and a comparison module to the MTE module, the separation module can separate the virtual address access tag from the memory access request, retrieve the memory tag from the first cache based on the virtual address, and transmit the access tag and memory tag to the comparison module. The comparison module can compare the access tag and the memory tag and transmit the comparison result to the processor. When accessing memory, the separation module only needs to separate the virtual address and access tag of the memory unit to be accessed from the memory access request, and retrieve the memory tag of the memory unit to be accessed from the first cache based on the virtual address. This allows the comparison module to compare the access tag and memory tag transmitted by the separation module. Therefore, using the memory access control circuit of this application, tag comparison can be performed without converting the virtual address to a physical address, thereby effectively reducing the memory access time and improving memory access efficiency.
[0074] In some embodiments of this application, the separation module 111 is specifically used to determine the tag address corresponding to the virtual address according to a preset address mapping relationship; and to obtain the memory tag from the cache unit with the address of the tag address in the first cache 13.
[0075] In some embodiments of this application, the first cache 13 includes at least one cache unit, each cache unit is used to cache the memory tag of a memory unit, and the address of the cache unit and the virtual address of the memory unit where the memory tag cached by the cache unit is located satisfy the above address mapping relationship.
[0076] In some embodiments of this application, the address mapping relationship described above may include a one-to-one mapping relationship between M virtual addresses and M tag addresses. The separation module 111 may first search for the virtual address among the M virtual addresses in the address mapping relationship. After finding the virtual address, the tag address corresponding to the virtual address is determined according to the mapping relationship, where M is a positive integer.
[0077] In some embodiments of this application, since the virtual address is the virtual address of the memory unit to be accessed, the memory tag stored in the cache unit with the address corresponding to the virtual address in the first cache 13 is the memory tag of the memory unit to be accessed, thereby enabling the separation unit 111 to obtain the memory tag from the cache unit with the address corresponding to the tag address.
[0078] Thus, the separation module determines the tag address corresponding to the virtual address based on a preset address mapping relationship; and retrieves the memory tag from the cache unit with the tag address in the first cache. Therefore, the separation module can retrieve the memory tag without translating the virtual address into a physical address, effectively reducing the memory tag retrieval time and thus improving memory access efficiency.
[0079] In some embodiments of this application, the separation module 111 is further configured to obtain the upper memory tag from the memory unit with the address of the tag in the tag storage area of memory if it is determined that there is no cache unit with the address of the tag in the first cache 113.
[0080] In some embodiments of this application, if it is determined that there is no cache unit with the address of the above tag address in the first cache 113, it means that the memory tag of the memory unit to be accessed is not cached in the first cache 113, and the separation module 111 can obtain the memory tag from the tag storage unit with the address of the above tag address in the tag storage area of memory.
[0081] In some embodiments of this application, the tag storage area includes multiple tag storage units, the tag storage area can store memory tags of all memory units in memory, and each tag storage unit in the tag storage area stores the memory tag of one memory unit.
[0082] In some embodiments of this application, the address of each tag storage unit and the virtual address of the memory unit where the cached memory tag is located satisfy the above address mapping relationship. The separation module 111 can obtain the memory tag from the tag storage unit whose address corresponds to the tag address in the tag storage area based on the above address mapping relationship.
[0083] For example, there are 10 memory units in memory, including memory unit 1, memory unit 2... memory unit 9 and memory unit 10. The first cache 113 caches the memory tags of memory unit 1, memory unit 2, and memory unit 3. Assuming the memory unit to be accessed is memory unit 4, the first cache 113 does not have a cached unit with the tag address corresponding to the virtual address of memory unit 4. The separation module 111 can retrieve the memory tag from the tag storage unit with the tag address in the tag storage area of memory. The memory tag stored in the tag storage unit is the memory tag of memory unit 4.
[0084] In this way, the separation module obtains the memory tag from the memory cell with the tag address in the tag storage area of memory when it is determined that there is no cache cell with the tag address in the first cache. This allows the separation module to perform tag comparison without converting the virtual address to the physical address, and the comparison module can also perform tag comparison. This can effectively reduce the memory access time and improve memory access efficiency.
[0085] In some embodiments of this application, as shown in FIG1 and FIG3, the memory access control circuit 10 provided in the embodiments of this application may further include: an address translation module 14 connected to the processor 12 and the MTE module 11;
[0086] MTE module 111 is also used to transmit the aforementioned virtual address to address translation module 14;
[0087] Address translation module 14 is used to translate the above virtual address into a physical address;
[0088] The processor 112 is also used to access the memory unit corresponding to the physical address.
[0089] In some embodiments of this application, the storage unit corresponding to the above physical address can be understood as a storage unit whose address is the above physical address.
[0090] In some embodiments of this application, when the address translation module 14 translates the virtual address into a physical address, the processor 112 can read the physical address from the address translation module 14 and then access the storage unit with the physical address.
[0091] In some embodiments of this application, as shown in FIG3, the address translation module 14 may include a TLB module 141 and an MMU module 142 connected to the TLB module 141, and the TLB module 141 is connected to the MTE module 11.
[0092] In some embodiments of this application, the TLB module 141 is used to receive the virtual address transmitted by the MTE module 11 and query the tab table entries to find the physical address mapped to the virtual address.
[0093] In some embodiments of this application, if the TLB module 141 fails to find the physical address, the TLB module 141 can transmit the virtual address to the MMU module 142, and the MMU module 142 can convert the virtual address transmitted by the TLB module 141 into a virtual address.
[0094] Thus, by adding an address translation module to the memory access control circuit, the MTE module can transmit the virtual address to the address translation module, which can then convert the virtual address into a physical address. This allows the processor to quickly access the memory unit corresponding to the physical address, thereby improving the processor's memory access efficiency.
[0095] In some embodiments of this application, as shown in FIG3 and FIG4, the memory access control circuit provided in the embodiments of this application may further include: a second cache 15 connected to the processor 12 and the address translation module 14.
[0096] The processor 12 is specifically configured to access the cache unit when the second cache 15 has a cache unit with the physical address; or, when the second cache 15 does not have a cache unit with the physical address, access the memory unit to be accessed corresponding to the physical address in memory.
[0097] In some embodiments of this application, the second cache 15 can be a CPU cache, used to cache data in a portion of memory units.
[0098] In some embodiments of this application, the CPU cache may include N cache units, each of which is used to cache data in a memory unit, where N is an integer greater than or equal to 1.
[0099] In some embodiments of this application, the address of each cache unit can be the physical address of the memory unit corresponding to the data cached by that cache unit.
[0100] In some embodiments of this application, if there is a cache unit in the second cache 15 with the address of the above physical address, the cached data of the cache unit is the data of the memory unit to be accessed, and the processor 12 can obtain the data in the memory unit to be accessed by accessing the cache unit.
[0101] In some embodiments of this application, if there is no cache unit with the address of the physical address in the second cache 15, it means that the data in the memory unit to be accessed is not cached in the second cache 15, and the processor 12 can access the memory unit to be accessed with the address of the physical address in memory.
[0102] Thus, by adding a second cache in the memory access control circuit, the processor can access the cache unit when there is a cache unit with a physical address in the second cache. This allows the processor to access the memory unit to be accessed without accessing the main memory, thereby improving the processor's memory access efficiency.
[0103] In some embodiments of this application, the first buffer 13 may be a buffer in the second buffer 15.
[0104] In some embodiments of this application, in order to save space occupied by the cache, the first cache 13 can be set in the second cache 15, so that the first cache 13 becomes a cache in the second cache 15, thereby merging the first cache 13 and the second cache 15 into one cache.
[0105] Thus, since the first cache is a cache within the second cache, it is possible to merge the first and second caches into a single cache, thereby effectively saving cache space. Furthermore, because the first cache is a cache within the second cache, the processor does not need to access different caches separately to obtain memory tags and access cache units; it only needs to access the second cache to obtain memory tags and access cache units, thus greatly improving the processor's operational efficiency.
[0106] Figure 5 is a schematic diagram of a memory access control circuit provided in an embodiment of this application. The memory access control circuit provided in the embodiment of this application will be described in detail below with reference to Figure 5:
[0107] MTE module 11 is used to obtain the virtual address and access tag of the memory unit to be accessed in memory from the memory access request transmitted from processor 12; and obtain the memory tag of the memory unit to be accessed from the first cache 13 according to the virtual address; and compare the access tag and the memory tag; and transmit the comparison result to processor 12.
[0108] The processor 12 is used to process the access result of the storage unit according to the comparison result, wherein the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.
[0109] Specifically, the separation module 111 in the MTE module 11 is used to separate the virtual address and access tag of the memory unit to be accessed from the memory access request of the processor 12, and obtain the memory tag of the memory unit to be accessed from the first cache 13 according to the virtual address, and transmit the access tag and the memory tag to the comparison module 112 in the MTE module, and transmit the virtual address to the address translation module 14.
[0110] The comparison module 112 is used to compare the access tag and the memory tag and transmit the comparison result to the processor 12.
[0111] Specifically, the separation module 111 is used to determine the tag address corresponding to the virtual address according to the preset address mapping relationship; and to obtain the memory tag from the cache unit with the address of the tag address in the first cache 13.
[0112] The separation module 111 is further configured to, if it is determined that there is no cache unit with the address of the aforementioned tag in the first cache 13, retrieve the aforementioned memory tag from the tag unit with the address of the aforementioned tag in the tag storage area of memory.
[0113] The comparison module 112 is used to compare the access tag and the memory tag and transmit the comparison result to the processor 12.
[0114] Specifically, the comparison module 112 is used to compare whether the access tag and the memory tag match, and transmits the comparison result of whether the access tag and the memory tag match to the processor 12.
[0115] Address translation module 14 is used to translate the above virtual address into a physical address.
[0116] Specifically, the TLB module 141 in the address translation module 14 is used to receive the virtual address transmitted by the separation module 111 and query the tab table entries to map the physical address of the virtual address.
[0117] If the TLB module 141 fails to find the aforementioned physical address, the TLB module 141 is further configured to transmit the aforementioned virtual address to the MMU module 142 in the address translation module 14.
[0118] MMU module 142 is used to convert the virtual address transmitted by TLB module 141 into a virtual address.
[0119] The processor 12 is also configured to read the physical address from the address translation module 14 and access the memory unit corresponding to the physical address.
[0120] Specifically, the processor 12 is configured to access the cache unit when the second cache has a cache unit with the physical address; or, when the second cache does not have a cache unit with the physical address, access the memory unit to be accessed corresponding to the physical address in memory.
[0121] In summary, by employing the memory access control circuit provided in this application, when accessing memory, the MTE module only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request. Based on the virtual address, it can obtain the memory tag of the memory unit to be accessed from the first cache and compare the access tag and the memory tag. Therefore, by employing the memory access control circuit of this application, tag comparison can be performed without translating the virtual address into a physical address, thereby effectively reducing the memory access time and improving memory access efficiency.
[0122] An electronic device provided in this application embodiment, as shown in FIG6, includes the memory access control circuits shown in FIG1 to FIG5.
[0123] In the electronic device of this application embodiment, the memory access control circuit adds an MTE module connected to the processor. This allows the MTE module to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request transmitted by the processor; obtain the memory tag of the memory unit to be accessed from the first cache based on the virtual address; compare the access tag and the memory tag; and transmit the comparison result to the processor. Therefore, the processor can process the access result of the memory unit, which is either the memory unit to be accessed or the cache unit corresponding to the virtual address, based on the comparison result. Thus, when accessing memory, the MTE module only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request, and obtain the memory tag of the memory unit to be accessed from the first cache based on the virtual address, and compare the access tag and the memory tag. Therefore, using the memory access control circuit of this application, tag comparison can be performed without converting the virtual address to a physical address, thereby effectively reducing memory access time and improving memory access efficiency.
[0124] It should be noted that, since this electronic device includes the aforementioned memory access control circuit, it can achieve the same technical effect as the memory access control circuit described above when using this electronic device for memory access. To avoid repetition, it will not be described in detail here.
[0125] Figure 7 shows a schematic diagram of a memory access control method provided in an embodiment of this application. This memory access control method can be applied to the memory access control circuit in the above embodiments. As shown in Figure 7, the memory access control method provided in this application embodiment may include the following steps 101 to 104.
[0126] S101. Obtain the virtual address and access tag of the memory unit to be accessed from the memory access request;
[0127] S102. Obtain the memory tag of the memory unit to be accessed based on the virtual address;
[0128] S103. Compare the access tag and the memory tag to obtain the comparison result;
[0129] S104. Based on the comparison results, process the access results of the storage unit, which is the memory unit to be accessed or the cache unit corresponding to the virtual address.
[0130] In the memory access control method provided in this application, the virtual address and access tag of the memory unit to be accessed are obtained from the memory access request, and the memory tag of the memory unit to be accessed can be obtained based on the virtual address. The access tag and the memory tag are then compared. Therefore, by using the memory access control circuit of this application, tag comparison can be performed without converting the virtual address to a physical address, thereby effectively reducing the memory access time and improving memory access efficiency.
[0131] In some embodiments of this application, referring to FIG7 and FIG8, the above step S101 can be implemented by the following step 101a:
[0132] Step 101a: Separate the virtual address and access label from the memory access request.
[0133] Thus, when accessing memory, it is only necessary to separate the virtual address and access tag of the memory unit to be accessed from the memory access request. Based on the virtual address, the memory tag of the memory unit to be accessed can be obtained from the first cache, and the access tag and the memory tag can be compared. Therefore, the memory access control method of this application can perform tag comparison without translating the virtual address into a physical address, thereby effectively reducing the memory access time and improving memory access efficiency.
[0134] In some embodiments of this application, referring to FIG7 and FIG9, step 102 above can be implemented by the following steps 102a and 102b:
[0135] Step 102a: Determine the tag address corresponding to the virtual address based on the preset address mapping relationship.
[0136] Step 10ba: Obtain the memory tag from the cache unit with the tag address.
[0137] Thus, by determining the tag address corresponding to the virtual address based on the preset address mapping relationship, the memory tag is retrieved from the cache unit with the tag address in the first cache. Therefore, the memory tag can be retrieved without translating the virtual address into a physical address, thereby effectively reducing the memory tag retrieval time and improving memory access efficiency.
[0138] In some embodiments of this application, referring to FIG9 and FIG10, the memory access control method provided in the embodiments of this application may further include the following step 105:
[0139] Step 105: If it is determined that there is no cache unit with the address of the tag, then obtain the memory tag from the memory unit with the address of the tag.
[0140] Thus, by obtaining the memory tag from the memory unit with the tag address when it is determined that there is no cache unit with the tag address, tag comparison can be performed without converting the virtual address to the physical address, which can effectively reduce the memory access time and thus improve memory access efficiency.
[0141] In some embodiments of this application, referring to FIG8 and FIG11, before step 104 above, the memory access control method provided in the embodiments of this application may further include the following steps 106a and 106b:
[0142] Step 106a: Convert the virtual address to a physical address.
[0143] Step 106b: Access the storage unit corresponding to the physical address.
[0144] In this way, the virtual address is transmitted to the address translation module, which can convert the virtual address into a physical address, enabling fast access to the storage unit corresponding to the physical address, thereby improving the efficiency of memory access.
[0145] In some embodiments of this application, referring to FIG11 and FIG12, the above step 106b can be implemented by the following step 106b1 or the following step 106b2:
[0146] Step 106b1: If a cache unit with a physical address exists, access the cache unit.
[0147] Step 106b2: If there is no cache unit with a physical address, access the memory unit to be accessed corresponding to the physical address in memory.
[0148] Thus, by accessing the cache unit with the physical address in the second cache, the processor can access the memory unit to be accessed without accessing the main memory, thereby improving the processor's memory access efficiency.
[0149] The memory access control circuit provided in this application embodiment will be further described in detail below with reference to FIG12. As shown in FIG12, the memory access control circuit 120 may include: an MTE split logic module (equivalent to the above-mentioned split module) 121, an MTE check logic module (equivalent to the above-mentioned comparison module) 122 connected to the MTE split logic module 121, a CPU core 123, a tag cache (equivalent to the above-mentioned first cache) 124, a TLB (equivalent to the above-mentioned TLB module) 125, an MMU (equivalent to the above-mentioned MMU module) 126 connected to the TLB 125, and a CPU cache (equivalent to the above-mentioned second cache) 128 connected to the MMU 126 via a bus 127.
[0150] In some embodiments of this application, as shown in FIG13, the memory access control process of the memory access control circuit 120 may include the following steps 1301 to 1305:
[0151] Step 1301: CPUcore123 issues an access request to DDR memory (relative to the memory access request mentioned above).
[0152] For example, CPUcore123 issues a memory access request based on the virtual address of the memory cell to be accessed in DDR memory. This access request includes the virtual address of the memory cell to be accessed and the tag key corresponding to that virtual address (relative to the access tag mentioned above).
[0153] Step 1302: The MTE split logic module 121 separates the virtual address and tag key in the access request, and continues to access the data in the memory unit to be accessed through the bus 127 according to the virtual address.
[0154] For example, as shown in FIG12, bus 127 can be an AXI bus or an ACE bus.
[0155] Step 1303: MTE split logic module 121 simultaneously passes the tag key to MTE check logic module 122 and passes the tag lock address (equivalent to the tag address mentioned above) to tag cache 124.
[0156] For example, the MTE split logic module 121 can determine the tag address corresponding to the virtual address according to a preset address mapping relationship.
[0157] Step 1304: Tag cache124 retrieves the tag lock (equivalent to the memory tag mentioned above) from memory according to the corresponding tag key address and caches it.
[0158] For example, Tag cache124 can obtain a tag lock from the tag zone in memory (equivalent to the tag storage area mentioned above) according to the corresponding tag key address.
[0159] Step 1305: MTE check logic 122 obtains the corresponding tag lock from tag cache 124, compares the tag key and tag lock, and returns the check result (equivalent to the comparison result mentioned above) to CPUcore 123.
[0160] For example, if the check result in step 1305 is false, meaning the tag key and tag lock do not match, then the data access process in step 1302 will not proceed. If the check result in step 1302 is true, meaning the tag key and tag lock match, then the data access process in step 1302 can continue, and the virtual address will be translated into a physical address via TLB125 and MMU126 for access.
[0161] For example, when CPU core 123 accesses memory through MTE split logic module 121, it first checks in CPU cache 128 whether a cache unit with the physical address exists. If so, it accesses the data in that cache unit. If not, it accesses the data in the memory unit with the physical address to be accessed.
[0162] The memory access control circuit of this application offers several advantages. First, if the matching fails, subsequent access processes can be saved, effectively solving the time-consuming address translation problem in existing technologies and significantly improving memory access efficiency. Second, because the tags in existing MTEs are physical address-based, they are not very compatible with user-space virtual addresses, requiring address translation to find the tag, resulting in low memory access efficiency. Supporting virtual address tags allows direct tag lookup using virtual addresses, thereby improving memory access efficiency.
[0163] It should be noted that the specific implementation process of the above steps can be found in the relevant description of the above embodiments. To avoid repetition, this embodiment will not repeat the details here.
[0164] It should be noted that each of the above method embodiments, or various possible implementations of each method embodiment, can be executed individually or in combination of any two or more. The specific implementation can be determined according to actual usage requirements, and this application embodiment does not impose any restrictions on this.
[0165] The memory access control method provided in this application can be executed by a memory access control device. This application uses the execution of the memory access control method by a memory access control device as an example to illustrate the memory access control device provided in this application.
[0166] Figure 14 is a schematic diagram of the structure of a memory access control device 1400 provided in an embodiment of this application. The memory access control device 1400 includes: an acquisition module 1401 and a processing module 1402.
[0167] The acquisition module 1401 is configured to acquire the virtual address and access tag of the memory unit to be accessed in memory from the memory access request transmitted by the processor; acquire the memory tag of the memory unit to be accessed from the first cache according to the virtual address; compare the access tag and the memory tag; and transmit the comparison result to the processor.
[0168] The processing module 1402 is used to process the access result of the storage unit according to the comparison result, wherein the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.
[0169] In some embodiments of this application, the acquisition module 1401 is specifically used for:
[0170] Used to separate the virtual address and the access tag from the memory access request, and to obtain the memory tag from the first cache according to the virtual address, and to transmit the access tag and the memory tag to the comparison module;
[0171] The access tag and the memory tag are compared, and the comparison result is transmitted to the processor.
[0172] In some embodiments of this application, the acquisition module 1401 is specifically used for:
[0173] According to the preset address mapping relationship, the tag address corresponding to the virtual address is determined; and the memory tag is obtained from the cache unit with the address of the tag address in the first cache.
[0174] In some embodiments of this application, the acquisition module 1401 is specifically used for:
[0175] The separation module is further configured to, if it is determined that there is no cache unit with the address of the tag in the first cache, obtain the memory tag from the tag unit with the address of the tag in the tag storage area of memory.
[0176] In some embodiments of this application, as shown in FIG14 and FIG15, the memory access control device 1400 further includes: a conversion module 1403 and an acquisition module 1401, which are further configured to transmit the virtual address to the address conversion module.
[0177] Conversion module 1403 is used to convert the virtual address into a physical address;
[0178] The processing module 1402 is also used to access the storage unit corresponding to the physical address.
[0179] In some embodiments of this application, the processing module 1402 is specifically used for:
[0180] If a cache unit with the physical address exists in the second cache, the cache unit is accessed; or, if no cache unit with the physical address exists in the second cache, the memory unit corresponding to the physical address in memory is accessed.
[0181] In some embodiments of this application, the first buffer is a buffer within the second buffer.
[0182] In the memory access control device provided in this application embodiment, the memory access control device obtains the virtual address and access tag of the memory unit to be accessed in memory from the memory access request, and obtains the memory tag of the memory unit to be accessed based on the virtual address, and compares the access tag and the memory tag. Therefore, using the memory access control device of this application, tag comparison can be performed without converting the virtual address to a physical address, thereby effectively reducing the memory access time and improving memory access efficiency.
[0183] The memory access control device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device, augmented reality / virtual reality device, robot, wearable device, super mobile personal computer, netbook, or personal digital assistant, etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the specific implementation.
[0184] The memory access control device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.
[0185] The memory access control device provided in this application can implement the various processes implemented in the various embodiments of the above-described memory access control method. To avoid repetition, it will not be described again here.
[0186] Optionally, as shown in FIG16, this application embodiment also provides an electronic device 1600, including a processor 1601 and a memory 1602. The memory 1602 stores a program or instructions that can run on the processor 1601. When the program or instructions are executed by the processor 1601, they implement the various steps of the above-described memory access control method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.
[0187] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.
[0188] Figure 17 is a schematic diagram of the hardware structure of an electronic device that implements an embodiment of this application.
[0189] The electronic device 1700 includes, but is not limited to, components such as: a radio frequency unit 1701, a network module 1702, an audio output unit 1703, an input unit 1704, a sensor 1705, a display unit 1706, a user input unit 1707, an interface unit 1708, a memory 1709, and a processor 1710. Furthermore, the electronic device 1700 also includes a memory access control circuit 10. It should be noted that the functions and connections of the modules in the memory access control circuit 10 are described above and will not be repeated here.
[0190] Those skilled in the art will understand that the electronic device 1700 may also include a power supply (such as a battery) for powering various components. The power supply may be logically connected to the processor 1710 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. The electronic device structure shown in Figure 17 does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.
[0191] The processor 1710 is used to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request.
[0192] Based on the virtual address, obtain the memory tag of the memory unit to be accessed;
[0193] The access tag and the memory tag are compared to obtain the comparison result;
[0194] Based on the comparison results, the access results to the storage unit are processed, wherein the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.
[0195] In some embodiments of this application, the processor 1710 is specifically used for:
[0196] The virtual address and the access tag are separated from the memory access request.
[0197] In some embodiments of this application, the processor 1710 is specifically used for:
[0198] Based on the preset address mapping relationship, determine the tag address corresponding to the virtual address;
[0199] The memory tag is retrieved from the cache unit at the address of the tag.
[0200] In some embodiments of this application, the processor 1710 is further configured to:
[0201] If it is determined that there is no cache unit with the address of the tag, then the memory tag is obtained from the memory unit with the address of the tag.
[0202] In some embodiments of this application, the processor 1710 is further configured to:
[0203] Based on the comparison results, before processing the access results to the storage unit, the virtual address is converted into a physical address;
[0204] Access the storage unit corresponding to the physical address.
[0205] In some embodiments of this application, the processor 1710 is specifically used for:
[0206] If a cache unit with the physical address exists, the cache unit is accessed; or, if no cache unit with the physical address exists, the memory unit to be accessed corresponding to the physical address in memory is accessed.
[0207] In the electronic device provided in this application, the electronic device obtains the virtual address and access tag of the memory unit to be accessed from the memory access request; obtains the memory tag of the memory unit to be accessed based on the virtual address; compares the access tag and the memory tag to obtain a comparison result; and processes the access result of the storage unit, where the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address, based on the comparison result. Thus, when accessing memory, the electronic device only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request, and obtain the memory tag of the memory unit to be accessed based on the virtual address, and compare the access tag and the memory tag. Therefore, the electronic device using this application can effectively reduce the memory access time, thereby improving memory access efficiency.
[0208] It should be understood that, in this embodiment, the input unit 1704 may include a graphics processing unit (GPU) 17041 and a microphone 17042. The GPU 17041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 1706 may include a display panel 17061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 1707 includes at least one of a touch panel 17071 and other input devices 17072. The touch panel 17071 is also called a touch screen. The touch panel 17071 may include a touch detection device and a touch controller. Other input devices 17072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.
[0209] The memory 1709 can be used to store software programs and various data. The memory 1709 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 1709 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 1709 in this embodiment includes, but is not limited to, these and any other suitable types of memory.
[0210] Processor 1710 may include one or more processing units; optionally, processor 1710 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 1710.
[0211] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described memory access control method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.
[0212] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.
[0213] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the memory access control method embodiments described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.
[0214] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.
[0215] This application provides a computer program product that is stored in a storage medium and executed by at least one processor to implement the various processes of the memory access control method embodiments described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.
[0216] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0217] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0218] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A memory access control circuit, the memory access control circuit comprising: A memory tag extension (MTE) module, and a processor and a first cache connected to the MTE module; The MTE module is used to obtain the virtual address and access tag of the memory unit to be accessed in memory from the memory access request transmitted by the processor. Based on the virtual address, the memory tag of the memory unit to be accessed is obtained from the first cache; the access tag and the memory tag are compared; and the comparison result is transmitted to the processor. The processor is configured to process the access result of the storage unit based on the comparison result, wherein the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.
2. The memory access control circuit according to claim 1, wherein, The MTE module includes a separation module and a comparison module connected to the separation module. The separation module is connected to the processor and the first cache, and the comparison module is connected to the processor. The separation module is used to separate the virtual address and the access tag from the memory access request, obtain the memory tag from the first cache according to the virtual address, and transmit the access tag and the memory tag to the comparison module; The comparison module is used to compare the access tag and the memory tag, and transmit the comparison result to the processor.
3. The memory access control circuit according to claim 2, wherein, The separation module is specifically used to determine the tag address corresponding to the virtual address according to a preset address mapping relationship; and to obtain the memory tag from the cache unit with the address of the tag address in the first cache.
4. [Correction 07.01.2026 based on Rule 91] The memory access control circuit according to claim 3, wherein, The separation module is further configured to, if it is determined that there is no cache unit with the address of the tag in the first cache, obtain the memory tag from the tag unit with the address of the tag in the tag storage area of memory.
5. [Correction 07.01.2026 based on Rule 91] The memory access control circuit according to claim 1, wherein, The memory access control circuit further includes: an address translation module connected to the processor and the MTE module; The MTE module is also used to transmit the virtual address to the address translation module; The address translation module is used to convert the virtual address into a physical address; The processor is also used to access the storage unit corresponding to the physical address.
6. The memory access control circuit according to claim 5, wherein, The memory access control circuit further includes a second cache connected to the processor and the address translation module; The processor is specifically configured to access the cache unit when the second cache has a cache unit with the physical address; or, when the second cache does not have a cache unit with the physical address, access the memory unit to be accessed corresponding to the physical address in memory.
7. The circuit according to claim 6, wherein, The first cache is a cache within the second cache.
8. An electronic device comprising the memory access control circuitry according to any one of claims 1 to 7.
9. A memory access control method, applied to the memory access control circuit according to any one of claims 1 to 7, the method comprising: From the memory access request, obtain the virtual address and access tag of the memory unit to be accessed in memory; Based on the virtual address, obtain the memory tag of the memory unit to be accessed; The access tag and the memory tag are compared to obtain the comparison result; Based on the comparison results, the access results to the storage unit are processed, wherein the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.
10. The method according to claim 9, wherein, The step of obtaining the memory tag of the memory unit to be accessed based on the virtual address includes: The virtual address and the access tag are separated from the memory access request.
11. The method according to claim 9, wherein, The step of obtaining the memory tag of the memory unit to be accessed based on the virtual address includes: Based on the preset address mapping relationship, determine the tag address corresponding to the virtual address; The memory tag is retrieved from the cache unit at the address of the tag.
12. The method according to claim 11, wherein, The method further includes: If it is determined that there is no cache unit with the address of the tag, then the memory tag is obtained from the memory unit with the address of the tag.
13. The method according to claim 9, wherein, Before processing the access results of the storage unit based on the comparison results, the method further includes: Convert the virtual address to a physical address; Access the storage unit corresponding to the physical address.
14. The method according to claim 13, wherein, Accessing the storage unit corresponding to the physical address includes: If a cache unit with the physical address exists, the cache unit is accessed; or, if no cache unit with the physical address exists, the memory unit corresponding to the physical address in memory is accessed.
15. An electronic device comprising a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions, when executed by the processor, implementing the steps of the memory access control method as claimed in any one of claims 8 to 14.
16. A readable storage medium on which a program or instructions are stored, wherein the program or instructions, when executed by a processor, implement the steps of the memory access control method as described in any one of claims 8 to 14.
17. A chip comprising a processor and a communication interface coupled to the processor, the processor being configured to run a program or instructions to implement the steps of the memory access control method as described in any one of claims 8 to 14.