Integrated photonics circuit and method of manufacture

Abstract

An integrated photonics circuit comprising: a plurality of layers deposited on a substrate, the plurality of layers comprising: a plurality of cladding layers; and two patterned, optically coupled waveguide layers; wherein one of the cladding layers is sandwiched between the two waveguide layers; and wherein the cladding layer sandwiched between the two waveguide layers is configured to have a thickness wherein the waveguide layers are optically coupled and to allow the waveguide layers to be patterned independently.

Description

[0001] INTEGRATED PHOTONICS CIRCUIT AND METHOD OF MANUFACTURE

[0002] The present disclosure relates to an improved photonic integrated circuit.

[0003] BACKGROUND

[0004] Photonic Integrated Circuits (PIC) can be implemented in various ways.

[0005] For example, Figure 1 shows a photonic integrated circuit which uses two noninteracting, thin layers of silicon nitride 101, 102 (for example, the silicon nitride layers may each have a thickness of 100 nm) which act as individual waveguide layers. The main application of this circuit is trapped ion quantum computing, working at a target wavelength range of 405 nm to 1092 nm.

[0006] A problem with this configuration is that the non-interacting nature of the two silicon nitride layers makes the total layer stack very thick because there is a thick oxide layer between both silicon nitride layers. This is disadvantageous because it negatively impacts both thermal conductivity and stress of the circuit.

[0007] Further, the individual waveguide core layers are very thin, which leads to poor confinement for longer wavelengths in the near-infrared wavelength range. Additionally, because both silicon nitride layers are optically non-interacting, they can also not be combined to create a thicker, hybrid waveguide to increase the light confinement.

[0008] Turning now to Figure 2, another example whose main target application is trapped ion quantum computing can be seen, wherein the stack consists of three optically coupled waveguide layers comprising two layers of silicon nitride 202, 203 and one layer of aluminium oxide 201. The aluminium oxide layer 201 is used for edge coupling and low- loss routing, as a standalone waveguide layer; this is a low-confinement layer (due to low refractive index and limited thickness), which disadvantageously leads to large device footprints. The two silicon nitride layers 202, 203 in this example are often used in combination, as a hybrid, thicker waveguide to realise polarisation rotators or gratings because the use of two silicon nitride layers 202, 203 enables asymmetric designs for polarisation rotators and directional grating couplers. Disadvantageously, the thickness of both silicon nitride layers 202, 203 combined is still limited, leading to poor confinement for the longer wavelengths in the near-infrared spectrum, and thus large device footprints.

[0009] Figure 3 shows yet another example of the prior art, where a very thin (for example, 25 nm), low-confinement silicon nitride waveguide layer 302 is used for edge coupling and a combination of the 25 nm layer 302 and a 170 nm silicon nitride layer 301 is used for on-chip routing and devices.

[0010] However, the combined thickness of both silicon nitride layers 301, 302 in this example is still very thin, which leads to poor confinement for the longer wavelengths in the nearinfrared spectrum. Hence, relatively thick oxide cladding layers are required, resulting in a thick total layer stack which is disadvantageous from a thermal conductivity point of view and can lead to stress related issues.

[0011] As such, there is a need for an integrated photonics technology which overcomes the various existing issues associated with the currently available technology.

[0012] SUMMARY

[0013] According to a first aspect of the disclosure, there is provided an integrated photonics circuit comprising: a plurality of layers deposited on a substrate, the plurality of layers comprising: a plurality of cladding layers; and two patterned, optically coupled waveguide layers; wherein one of the cladding layers is sandwiched between the two waveguide layers; and wherein the cladding layer sandwiched between the two waveguide layers is configured to have a thickness wherein the waveguide layers are optically coupled and to allow the waveguide layers to be patterned independently.

[0014] Optionally, wherein a thickness of the two waveguide layers and the cladding layer sandwiched between them is between 400 nm and 1500 nm. Optionally, wherein the plurality of layers are deposited on a first surface of the substrate to form a layered structure comprising: a first cladding layer deposited on the first surface of the substrate; a first waveguide layer deposited on the first cladding layer; a second cladding layer deposited on the first waveguide layer; a second waveguide layer deposited on the second cladding layer; and a third cladding layer deposited on the second waveguide layer.

[0015] Optionally, wherein the second waveguide layer is thicker than the first waveguide layer; or wherein the first waveguide layer is thicker than second waveguide layer; or wherein the first waveguide layer and the second waveguide layer have the same thickness.

[0016] Optionally, wherein the waveguide layers are patterned to provide at least one of: a first waveguide, a second waveguide, a first grating coupler, and a second grating coupler.

[0017] Optionally, wherein the first waveguide is configured to provide high confinement and single-mode operation for longer wavelengths; and wherein the second waveguide is configured to provide high confinement and single-mode operation for shorter wavelengths.

[0018] Optionally, wherein the first grating coupler is patterned on the first waveguide layer or the second waveguide layer based on which layer is thinner.

[0019] Optionally, wherein a grating of the second grating coupler is patterned on the first waveguide layer or the second waveguide layer based on which layer is thicker.

[0020] Optionally, wherein when the grating is patterned on the second waveguide layer, an area of the first waveguide layer beneath the grating is not patterned.

[0021] Optionally, wherein the second cladding layer is an etch stop layer; wherein the etch stop layer is a material with a relatively low etch rate compared to the etch rate of the first and second waveguide layers. Optionally, wherein the etch stop layer is made of one of silicon oxide, aluminium oxide, hafnium oxide, calcium fluoride, or magnesium fluoride.

[0022] Optionally, wherein the first cladding layer and the third cladding layer are made of different materials.

[0023] Optionally, wherein the second cladding layer has a thickness that is configured such that: the first and second waveguide layers are optically coupled; and the second cladding layer acts as a buffer to prevent etching the first waveguide layer when etching the second waveguide layer.

[0024] Optionally, wherein the third cladding layer is configured to have a thickness such that loss is prevented when further layers are fabricated on the third cladding layer of the integrated photonics circuit.

[0025] Optionally, wherein the first cladding layer is configured to have a thickness such that loss is prevented when further layers are fabricated on a second surface of the substrate.

[0026] Optionally, wherein the cladding layers are made of a transparent material; and wherein the waveguide layers are made of a transparent material with a relatively higher refractive index than the refractive index of the cladding layers.

[0027] Optionally, wherein the waveguide layers are made of one of silicon nitride, aluminium nitride, lithium niobate, aluminium oxide, tantalum oxide, or hafnium oxide.

[0028] Optionally, wherein the cladding layers are made of one of silicon oxide, aluminium oxide, calcium fluoride, or magnesium fluoride.

[0029] Optionally, wherein the layers are deposited by low pressure chemical vapor deposition, LPCVD, plasma enhanced chemical vapor deposition, PECVD, atomic layer deposition, ALD, physical vapor deposition, PVD, or spin coating, or thermal oxidation. According to a second aspect of the disclosure, there is provided a method of manufacturing an integrated photonics circuit comprising: depositing a plurality of layers on a substrate; patterning the two waveguide layers; and when the waveguide layers have been patterned, depositing an additional cladding layer on an exposed surface of one of the two waveguide layers; wherein the plurality of layers includes two cladding layers, and two waveguide layers; and wherein one of the cladding layers is sandwiched between the two waveguide layers; wherein the cladding layer sandwiched between the two waveguide layers is configured to have a thickness wherein the waveguide layers are optically coupled and to allow the waveguide layers to be patterned independently.

[0030] Optionally, wherein the depositing comprises: depositing a first cladding layer on a substrate; depositing a first waveguide layer on the first cladding layer; depositing a second cladding layer on the first waveguide layer; depositing a second waveguide layer on the second cladding layer; and depositing a third cladding layer on the second waveguide layer.

[0031] Optionally, wherein after the second waveguide layer is deposited: the second waveguide layer is patterned; and subsequently to the second waveguide layer being patterned, the first waveguide layer is patterned.

[0032] Optionally, wherein the first waveguide layer is patterned after it is deposited and before the second cladding layer is deposited; and wherein the second waveguide layer is patterned, independently of the first waveguide layer, after it is deposited and before the third cladding layer is deposited.

[0033] Optionally, wherein the patterning is a subtractive process.

[0034] Optionally, wherein the patterning is performed using electron-beam and / or optical lithography. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The disclosure is described in further detail below by way of example only and with reference to the accompanying drawings in which:

[0036] Figure 1 shows a diagram of a layered structure of an integrated photonics circuit according to the prior art;

[0037] Figure 2 shows a diagram of a layered structure of an integrated photonics circuit according to the prior art;

[0038] Figure 3 shows a diagram of a layered structure of an integrated photonics circuit according to the prior art;

[0039] Figure 4 shows a simplified diagram of a layered structure of an integrated photonics circuit according to an embodiment of the disclosure;

[0040] Figure 5a shows a diagram of a stage of manufacture of a layered structure of an integrated photonics circuit;

[0041] Figure 5b shows a diagram of a stage of manufacture of a layered structure of an integrated photonics circuit;

[0042] Figure 6 is a flowchart illustrating a method of manufacture of an integrated photonics circuit;

[0043] Figure 7 is a flowchart illustrating a method of manufacture of an integrated photonics circuit; and

[0044] Figure 8 is a flowchart illustrating a method of manufacture of an integrated photonics circuit.

[0045] DETAILED DESCRIPTION

[0046] Many applications, including trapped ion quantum computing, require an integrated photonics technology meeting the following criteria:

[0047] 1. Visible to near-infrared spectrum single-mode operation with low optical loss and efficient out-of-plane coupling;

[0048] 2. Small device footprints (necessitating strong light confinement);

[0049] 3. Robustness to fabrication variations; 4. A thin total layer stack (to provide efficient heat transfer and to avoid stress buildup in the stack leading to cracking or excessive wafer bow).

[0050] It is desirable to provide a technology that meets all these criteria simultaneously. The current disclosure proposes a technology that implements all these criteria simultaneously, providing a high-confinement, single-mode waveguide platform for the visible to near-infrared spectrum based on a thin, multilayer stack.

[0051] While technologies with two optically coupled waveguide layers have been proposed, none of these technologies meet the four abovementioned criteria due to the design of their layer stacks.

[0052] The examples discussed in the current disclosure have the advantage that they can be manufactured with high yield, at low cost, and in high volumes. Additionally, the discussed examples can easily be combined with other existing semiconductor technologies, for example, electronics, and surface ion traps. These advantages are achieved because standard semiconductor processing techniques can be used to manufacture the disclosed examples.

[0053] Further, polarisation rotators and grating couplers with high directionality can be implemented using the disclosed technology because the use of two waveguide layers enables asymmetric waveguide designs.

[0054] In the foregoing disclosure, an “integrated photonics circuit” (or photonic integrated circuit, or integrated optical circuit) refers to a device configured to use photonic components to form a circuit by detecting, generating, transporting, and processing light.

[0055] A “substrate” refers to a layer (or layers) of material used to grow, fabricate, build, or deposit a plurality of layers on top of to provide a base to the layered structure. For example, the substrate may be a plurality of layers of different materials, which may act as a base upon which an integrated photonics circuit might be fabricated. The substrate may include layers which are patterned.

[0056] A “stack” refers to a plurality of layers of material deposited sequentially to form a layered structure.

[0057] “Optical coupling” refers to when at least two waveguide layers are disposed such that an optical interaction can happen between the waveguide layers. In more detail, for example, each waveguide layer may include a waveguide patterned on a first area such that light may propagate through the waveguide on each layer wherein, if the layers are close enough together, the light propagating through a first waveguide on a first waveguide layer is propagated differently (and thus interacts with a second waveguide on a second waveguide layer) when compared to how the light would have been propagated without the presence of the second waveguide. Thus, the waveguide layers can be described as optically coupled because there is an interaction between light propagating through the waveguide layers.

[0058] Figure 4 is a diagram showing an example layer stack of an integrated photonics circuit 400 comprising a plurality of layers deposited on a substrate 430, the plurality of layers comprising a plurality of cladding layers 410a, 410b, 410c; and two patterned, optically coupled waveguide layers 420a, 420b; wherein one of the cladding layers is sandwiched between the two waveguide layers; and wherein the cladding layer sandwiched between the two waveguide layers is configured to have a thickness wherein the waveguide layers are optically coupled and to allow the waveguide layers to be patterned independently.

[0059] The thickness of the two waveguide layers and the cladding layer sandwiched between them may be between 400 nm and 1500 nm.

[0060] The circuit takes the form of a stack comprising a plurality of layers which are deposited on a substrate. That is, each layer may be grown and / or deposited on a substrate; for example, the process may begin with a blank silicon wafer upon which the plurality of layers may be formed sequentially. Two of the layers are waveguide layers 420a, 420b, which are optically coupled and patterned to provide various waveguide functions.

[0061] For example, the plurality of layers may be deposited on the substrate 430 to form a layered structure comprising a first cladding layer 410a deposited on the substrate 430, a first waveguide layer 420a deposited on the first cladding layer 410a, a second cladding layer 410b deposited on the first waveguide layer 420a, a second waveguide layer 420b deposited on the second cladding layer 410b, and a third cladding layer 410c deposited on the second waveguide layer.

[0062] In a preferred example, the waveguide layers 420a, 420b may be made of silicon nitride while the cladding layers 410a, 410b, 410c are made of silicon oxide (such as, for example, silicon dioxide). These materials may be selected because they provide low optical loss in the visible to near-infrared wavelength range, as well as because they are standard materials in semiconductor foundries. However, in other examples, other materials may be used. In some examples, each cladding layer may be made of the same or different materials.

[0063] For example, the waveguide layers 420a, 420b may be made of silicon nitride, aluminium nitride, lithium niobate, aluminium oxide, tantalum oxide, or hafnium oxide. The cladding layers 410a, 410b, 410c may be made of silicon oxide, aluminium oxide, calcium fluoride, or magnesium fluoride.

[0064] In the structure shown in Figure 4, the first waveguide layer 420a is thinner than the second waveguide layer 420b. However, in other examples, the first waveguide layer 420a may be thicker than the second waveguide layer 420b (that is, in some implementations, the first waveguide layer 420a and the second waveguide layer 420b of Figure 4 may be swapped). Additionally, in yet other examples, it may be the case that the first waveguide layer 420a and the second waveguide layer 420b have the same thickness.

[0065] The second cladding layer 410b may be known as an etch stop layer, wherein the etch stop layer 410b is made of a material with a relatively low etch rate compared to the etch rate of the first 420a and second 420b waveguide layers. That is, the second cladding layer 410b may be comparatively more difficult to etch than the waveguide layers 420a, 420b, such that the waveguide layers may be etched without affecting the etch stop layer 410b.

[0066] The etch stop layer 410b may preferably be made from silicon oxide, but may also be made from aluminium oxide, hafnium oxide, calcium fluoride, or magnesium fluoride. The etch stop layer 410b may be made of the same or different material from the other cladding layers 410a, 410c. That is, the first cladding layer 410a and the third cladding layer 410c may be made of the same material which may be the same or different to the material of the etch stop layer 410b, or alternatively, the first cladding layer 410a and the third cladding layer 410c may be made of different materials which are each the same or different to the material of the etch stop layer 410b.

[0067] The cladding layers 410a, 410b, 410c may be made of a transparent material and the waveguide layers 420a, 420b may be made of a transparent material with a relatively higher refractive index than the refractive index of the first and third cladding layers 410a, 410c.

[0068] The second cladding layer (or etch stop layer) 410b may be configured to have a thickness such that the first and second waveguide layers are optically coupled, and such that the second cladding layer 410b acts as a buffer to prevent etching the first waveguide layer 420a when etching the second waveguide layer 420b.

[0069] The third cladding layer 410c may be configured to have a thickness such that optical propagation loss is prevented when further layers are fabricated (or deposited or grown) on top of the integrated photonics circuit 400 (wherein “on top” is considered to be any layer fabricated on top of the third cladding layer 410c). That is, the third cladding layer 410c may be thick enough such that the first and second waveguide layers 420a, 420b are not optically coupled with any component that may be fabricated on top of the third cladding layer 410c. The optical propagation loss is a loss in signal strength as optical waves propagate through the integrated photonics circuit. The loss may be due to the presence of optically lossy layers fabricated on top of the third cladding layer 410c. An optically lossy layer may be considered to be a layer of material through which light may be absorbed, scattered, or leaked.

[0070] Similarly, the first cladding layer 410a may be configured to have a thickness such that loss due to optically lossy layers positioned below the first cladding layer 410a is prevented.

[0071] Example thicknesses of the plurality of layers are as follows. It should be understood that the thicknesses disclosed below are merely examples and should not be construed as limiting.

[0072] The first cladding layer 410a may have a thickness of at least 2000 nm. This thickness is selected such that significant substrate loss is avoided when the plurality of layers are deposited on the substrate. The thickness of the first cladding layer 410a may be selected based on the application of the integrated photonics circuit. Generally, a benefit of the selected thicknesses of the first and second waveguide layers 420a, 420b (meaning that high confinement waveguides are provided) is that the first cladding layer 410a can be thinner than in previous examples of integrated photonics circuits. The first waveguide layer 420a and the second waveguide layer 420b each may have a thickness of between 100 nm and 1300 nm.

[0073] The second cladding layer 410b may have a thickness of between 10 nm and 200 nm. This thickness is selected to be thick enough such that the first waveguide layer 420a is protected from etching when the second waveguide layer 420b is etched but thin enough that the two waveguide layers 420a, 420b are optically coupled.

[0074] The first waveguide layer 420a, the second waveguide layer 420b, and the second cladding layer 410b may have a combined thickness of between 400 nm and 1500 nm.

[0075] The thickness of each layer of the plurality of layers is selected such that the stack meets each of the four criteria discussed above.

[0076] An example of layer thickness and material for an example layer stack is provided below, in table 1.

[0077] Figures 5a and 5b show diagrams of different stages of the process of depositing and patterning layers of the integrated photonics circuit.

[0078] Figure 5a shows an example integrated photonics circuit before the third cladding layer 410c is deposited.

[0079] As can be seen from Figure 5a, the first waveguide layer 420a and the second waveguide layer 420b are patterned before the third cladding layer 410c is deposited.

[0080] The plurality of layers may be deposited by low pressure chemical vapor deposition, LPCVD, plasma enhanced chemical vapor deposition, PECVD, atomic layer deposition, ALD, physical vapor deposition, PVD, thermal oxidation, or spin coating. Each layer may be deposited using the method best suited. For example, all of the plurality of layers may be deposited using the same method. In another example, the cladding layers may be deposited using one method, while the waveguide layers are deposited using a different method.

[0081] The first and second waveguide layers 420a, 420b, may be patterned to provide at least one of: a first waveguide, a second waveguide, a first grating coupler, and a second grating coupler.

[0082] It should be understood that various combinations of waveguides and grating couplers may be used and the above is given merely as an example and is not intended to be limiting.

[0083] For example, moving from left to right across the diagram of Figure 5a, a first waveguide 510 may be provided. The first waveguide 510 may be configured to provide high- confinement and single-mode operation for a first set of wavelengths. For example, the first set of wavelengths may be comparatively longer wavelengths. For example, the first set of wavelengths may be 1000-2000 nm. However, it should be understood that the first waveguide may be patterned to provide high-confinement and single-mode operation for any suitable set of wavelengths.

[0084] Next, a second waveguide 520 may also be provided. The second waveguide 520 may be configured to provide high-confinement and single-mode operation for a second set of wavelengths. For example, the second set of wavelengths may be comparatively shorter wavelengths. For example, the second set of wavelengths maybe 400-1000 nm. However, it should be understood that the second waveguide may be patterned to provide high- confinement and single-mode operation for any suitable set of wavelengths.

[0085] In other examples, it may be the case that more or fewer waveguides may be patterned. In some examples, a third waveguide may be provided. In other examples, a third waveguide and a fourth waveguide may be provided. In yet other examples, only one waveguide may be provided. The waveguides may be provided such that they each provide high-confinement and single-mode operation for a predefined set of wavelengths.

[0086] A first grating coupler 530 may be provided. The first grating coupler 530 may be patterned on the first waveguide layer 420a or the second waveguide layer 420b based on which layer is thinner. That is, if the first waveguide layer 420a is the thinner of the two waveguide layers, the first grating coupler 530 is patterned on the first waveguide layer 420a or, alternatively, if the second waveguide layer 420b is the thinner of the two waveguide layers, the first grating coupler 530 is patterned on the second waveguide layer 420b. That is, the grating coupler with the smallest feature sizes is fabricated on the thinnest waveguide layer of the two waveguide layers 420a, 420b. Alternatively, the grating of the first grating coupler 530 maybe patterned on both the first waveguide layer 420a and the second waveguide layer 420b, or on the thicker of the two waveguide layers 420, 420b.

[0087] Finally, a second grating coupler 540 may also be provided. A grating of the second grating coupler 540 may be patterned on the first waveguide layer or the second waveguide layer based on which layer is thicker. That is, if the first waveguide layer 420a is the thicker of the two waveguide layers, the second grating coupler 540 is patterned on the first waveguide layer 420a or, alternatively, if the second waveguide layer 420b is the thicker of the two waveguide layers, the second grating coupler 540 is patterned on the second waveguide layer 420b. When the grating of the second grating coupler 540 is patterned on the second waveguide layer 420b, an area of the first waveguide layer 420a beneath the grating may not be patterned.

[0088] In other examples, it may be the case that more or fewer grating couplers may be patterned. In some examples, a third grating coupler may be provided. In other examples, a third grating coupler and a fourth grating coupler may be provided. In yet other examples, only one or no grating coupler may be provided.

[0089] In an alternative example, the grating of the second grating coupler 540 may be patterned on both the first waveguide layer 420a and the second waveguide layer 420b. In order to pattern on both the first waveguide layer 420a and the second waveguide layer 420b, the pattern may be etched all the way through the two waveguide layers 420a, 420b and the second cladding layer 410b.

[0090] In another alternative example, each waveguide layer 420a, 420b may be patterned with a grating for the second grating coupler 540 independently. Both gratings may then be combined to form the second grating coupler 540. Advantageously, this provides freedom in the design as well as enabling high directionality in the second grating coupler 540. In more detail, the second grating coupler 540 may be patterned on the thicker of the two waveguide layers 420a, 420b to accommodate longer wavelengths of light. This is because longer wavelengths do not require as small feature sizes as shorter wavelengths and, thus, gratings configured for longer wavelengths may be patterned on a thicker waveguide layer.

[0091] Figure 5b shows the example integrated photonics circuit of Figure 5a after the third cladding layer 410c is deposited.

[0092] The third cladding layer 410c is deposited on the second waveguide layer 420b after the first waveguide layer 420a and second waveguide layer 420b are patterned such that the third cladding layer 410c covers an exposed surface of the second waveguide layer 420b. The third cladding layer 410c may be made of a silicon oxide (for example, silicon dioxide), or another material, such as aluminium oxide, hafnium oxide, calcium fluoride, or magnesium fluoride. The third cladding layer 410c may be made of the same or different material as the first cladding layer 410a and / or the second cladding layer 410b.

[0093] Surface ion traps may be fabricated on an exposed (or top) surface of the third cladding layer 410c. The surface ion traps may be fabricated using standard semiconductor fabrication techniques.

[0094] Figure 6 shows a flowchart illustrating a method of manufacturing an integrated photonics circuit such as the integrated photonics circuit shown in Figures 4, 5a and 5b.

[0095] In step S610, a plurality of layers are deposited on a substrate (or substrate layer). That is, each layer may be grown and / or deposited on a substrate; for example, the process may begin with a blank silicon wafer which acts as the substrate and upon which the plurality of layers may be formed sequentially.

[0096] The plurality of layers comprises a plurality of cladding layers 410a, 410b, 410c; and two waveguide layers 420a, 420b; wherein one of the cladding layers is sandwiched between the two waveguide layers; and wherein a thickness of the two waveguide layers and the cladding layer sandwiched between them is between 400 nm and 1500 nm.

[0097] The plurality of layers may be deposited by low pressure chemical vapor deposition, LPCVD, plasma enhanced chemical vapor deposition, PECVD, atomic layer deposition, ALD, physical vapor deposition, PVD, thermal oxidation, or spin coating. Each layer may be deposited using a best suited method. In some examples, all of the plurality of layers may be deposited using the same method. In another example, the cladding layers may be deposited using one method, while the waveguide layers are deposited using a different method.

[0098] In step S620, the two waveguide layers are patterned. The first and second waveguide layers 420a, 420b, may be patterned to provide at least one of: a first waveguide, a second waveguide, a first grating coupler, and a second grating coupler.

[0099] In step S630, an additional cladding layer (for example, the third cladding layer 410c) is deposited on an exposed surface of one of the two waveguide layers.

[0100] Figures 7 and 8 are each flowcharts which show examples of methods of manufacturing an integrated photonics circuit. Figures 7 and 8 are more specific examples of the method of manufacturing illustrated in Figure 6.

[0101] Figure 7 represents a first example of a manufacturing method for an integrated photonics circuit. The first example represents a method of manufacturing wherein the first waveguide layer 420a and the second waveguide layer 420b are patterned sequentially after both layers are deposited and before the third cladding layer 410c is deposited.

[0102] In step S710, the first cladding layer 410a is deposited. The first cladding layer 410a is deposited onto a substrate.

[0103] In step S720, the first waveguide layer 420a is deposited. The first waveguide layer 420a is deposited onto an exposed surface of the first cladding layer 410a.

[0104] In step S730, the second cladding layer 410b may be deposited. The second cladding layer 410b may be deposited onto an exposed surface of the first waveguide layer 420a.

[0105] In step S740, the second waveguide layer 420b may be deposited. The second waveguide layer 420b may be deposited onto an exposed surface of the second cladding layer 410b.

[0106] In step S750, first the second waveguide layer 420b is patterned, then the first waveguide layer 420a is patterned.

[0107] In more detail, after the layered stack is grown (or deposited or fabricated), the two waveguide layers are sequentially patterned in a subtractive process. For example, the subtractive process may use electron-beam and / or optical lithography. Thus, the second cladding layer 410b acts as an etch stop layer which ensures robustness in the manufacturing process. This is advantageous in comparison to other techniques wherein a shallow etch step might be used with a thick waveguide layer, requiring tight process control.

[0108] In step S760, the third cladding layer 410c is deposited. The third cladding layer 410c is deposited onto an exposed surface of the second waveguide layer 420b. The third cladding layer 410c is deposited subsequently to the waveguide layers being patterned.

[0109] Figure 8 represents a second example of a manufacturing method for an integrated photonics circuit. The second example represents a method of manufacturing wherein the first waveguide layer 420a is patterned after it is deposited and before the second waveguide layer 420b is deposited, and wherein the second waveguide layer 420b is patterned, independently of the first waveguide layer 420a, after it is deposited and before the third cladding layer 410c is deposited.

[0110] In step S810, a first cladding layer (for example, the first cladding layer 410a according to Figures 4, 5a, and 5b) is deposited. The first cladding layer 410a is deposited onto a substrate.

[0111] In step S820, a first waveguide layer (for example, the first waveguide layer 420a according to Figures 4, 5a, and 5b) is deposited. The first waveguide layer 420a is deposited onto an exposed surface of the first cladding layer 410a.

[0112] In step S830, the first waveguide layer 420a is patterned.

[0113] In step S840, a second cladding layer (for example, the second cladding layer 410b according to Figures 4, 5a, and 5b) may be deposited. The second cladding layer 410b may be deposited onto an exposed surface of the first waveguide layer 420a.

[0114] In step S850, a first part of a third cladding layer (for example, the third cladding layer 410c according to Figures 4, 5a, and 5b) may be deposited. That is, the third cladding layer 410c may be deposited in multiple steps. In this example, the third cladding layer 410c may be deposited in two parts; a first part and a second part.

[0115] In step S860, the first part of the third cladding layer may be planarized to the level of the second cladding layer 410b or the first waveguide layer 420a. The first part of the third cladding layer may be planarized such that a flat surface is provided for subsequent layers to be deposited onto.

[0116] It should be understood that it is not necessary for the second cladding layer 410b to be deposited after the first waveguide layer 420a is patterned. The second cladding layer 410b may be deposited immediately after the first waveguide layer 420a is deposited and before the first waveguide layer 420a is patterned. The second cladding layer 410b may alternatively be deposited after the first part of the third cladding layer 410c is deposited and planarized.

[0117] In step S870, a second waveguide layer (for example, the second waveguide layer 420b according to Figures 4, 5a, and 5b) may be deposited. The second waveguide layer 420b may be deposited onto an exposed surface of the third cladding layer 410c.

[0118] In step S880, the second waveguide layer 420b is patterned.

[0119] In step S890, a second part of the third cladding layer (for example, the third cladding layer 410c according to Figures 4, 5a, and 5b) is deposited. The second part of the third cladding layer 410c is deposited onto an exposed surface of the second waveguide layer 420b.

[0120] The plurality of layers may be deposited sequentially on top of one another. That is, the plurality of layers may be deposited such that a layered structure is fabricated, such as the structure shown in Figures 4, 5a and 5b.

[0121] It should be understood that various combinations and iterations of layers are envisioned and fall within the scope of the application. That is, more or fewer cladding layers may be included (for example, the first cladding layer 410a may be omitted), more or fewer waveguide layers may be included, and the order in which the layers are deposited may be changed.

[0122] It is possible to implement one thin layer of silicon nitride to produce single-mode waveguides and other photonic components over the entire wavelength range of interest. However, this would result disadvantageously in large footprint devices (e.g. large bend radii to get low loss) which violates the second criterion referred to above.

[0123] It would also be possible to implement a single thick layer of silicon nitride (with only a full etch step) to enable the production of compact components for longer wavelengths. However, this would make it challenging to fabricate the small feature sizes needed for shorter wavelengths (e.g. to make grating couplers for out-of-plane coupling and singlemode waveguides), given the difficulty of patterning high-aspect-ratio features. This would violate the first criterion referred to above.

[0124] Therefore, the two waveguide layers 420a, 420b of the present invention are advantageous in enabling both thin and thick waveguides, grating couplers, and other photonic components in the same integrated photonics circuit.

[0125] It would further be possible, to separate the two waveguide layers 420a, 420b vertically to prevent optical interaction between them, and it is known that waveguides can be crossed without introducing optical loss. However, this disadvantageously results in a thick total layer stack, which violates the fourth criterion.

[0126] Thus, the layer structure of the present invention is advantageous in meeting all four of the following criteria:

[0127] 1. Visible to near-infrared spectrum single-mode operation with low optical loss and efficient out-of-plane coupling;

[0128] 2. Small device footprints (necessitating strong light confinement);

[0129] 3. Robustness to fabrication variations;

[0130] 4. A thin total layer stack (to provide efficient heat transfer and to avoid stress buildup in the stack leading to cracking or excessive wafer bow).

[0131] Applications of the present invention include: quantum computing, communication, or sensing using trapped ions, neutral atoms, colour centres, quantum dots; optical atomic clocks; display technology, e.g. AR / VR technology; hyperspectral imaging; life and environmental science applications, e.g. flow cytometry, optogenetics, spectroscopic sensing, imaging.

[0132] The integrated photonics circuits of the present invention may be part of a quantum device, such as a quantum computer, atomic clock, quantum sensor or the like. The quantum device may use trapped ions to perform quantum operations.

[0133] Various improvements and modifications may be made to the above without departing from the scope of the disclosure.

Claims

CLAIMS1. An integrated photonics circuit comprising: a plurality of layers deposited sequentially on a substrate, the plurality of layers comprising: a plurality of cladding layers; and two patterned, optically coupled waveguide layers; wherein one of the cladding layers is sandwiched between the two waveguide layers; and wherein the cladding layer sandwiched between the two waveguide layers has a thickness that is configured such that: the first and second waveguide layers are optically coupled; and the sandwiched cladding layer acts as a buffer to prevent etching the first waveguide layer when etching the second waveguide layer.

2. The circuit of claim 1, wherein a combined thickness of the two waveguide layers and the cladding layer sandwiched between them is between 400 nm and 1500 nm.

3. The circuit of claim 1, wherein the plurality of layers are deposited on a first surface of the substrate to form a layered structure comprising: a first cladding layer deposited on the first surface of the substrate; a first waveguide layer deposited on the first cladding layer; a second cladding layer deposited on the first waveguide layer; a second waveguide layer deposited on the second cladding layer; and a third cladding layer deposited on the second waveguide layer.

4. The circuit of any preceding claim, wherein the waveguide layers are patterned to provide at least one of: a first waveguide, a second waveguide, a first grating coupler, and a second grating coupler.

5. The circuit of claim 4, wherein the first waveguide is configured to provide high confinement and single-mode operation for longer wavelengths; and wherein the second waveguide is configured to provide high confinement and single-mode operation for shorter wavelengths.

6. The circuit of claims 4 to 5, wherein the first grating coupler is patterned on the first waveguide layer or the second waveguide layer based on which layer is thinner.

7. The circuit of claims 4 to 5, wherein a grating of the second grating coupler is patterned on the first waveguide layer or the second waveguide layer based on which layer is thicker.

8. The circuit of claim 7, wherein when the grating is patterned on the second waveguide layer, an area of the first waveguide layer beneath the grating is not patterned.

9. The circuit of claim 3, wherein the first cladding layer and the third cladding layer are made of different materials.

10. The circuit of claim 3, wherein the second cladding layer is made of one of silicon oxide, aluminium oxide, hafnium oxide, calcium fluoride, or magnesium fluoride.

11. The circuit of any of claim 3 to 10, wherein the third cladding layer is configured to have a thickness such that loss is prevented when further layers are fabricated on the third cladding layer of the integrated photonics circuit.

12. The circuit of any of claim 3 to 11, wherein the first cladding layer is configured to have a thickness such that loss is prevented when further layers are fabricated on a second surface of the substrate.

13. The circuit of claim 3, wherein the cladding layers are made of a transparent material; and wherein the waveguide layers are made of a transparent material with a relatively higher refractive index than the refractive index of the cladding layers.

14. The circuit of claim 13, wherein the waveguide layers are made of one of silicon nitride, aluminium nitride, lithium niobate, aluminium oxide, tantalum oxide, or hafnium oxide; andwherein the cladding layers are made of one of silicon oxide, aluminium oxide, calcium fluoride, or magnesium fluoride.

15. The circuit of claim 1, wherein the circuit is part of a quantum device; and wherein the quantum device uses trapped ions.

16. The circuit of claim 1, wherein the layers are deposited by low pressure chemical vapor deposition, LPCVD, plasma enhanced chemical vapor deposition, PECVD, atomic layer deposition, ALD, physical vapor deposition, PVD, or spin coating, or thermal oxidation.

17. A method of manufacturing an integrated photonics circuit comprising: depositing a plurality of layers on a substrate; patterning the two waveguide layers; and when the waveguide layers have been patterned, depositing an additional cladding layer on an exposed surface of one of the two waveguide layers; wherein the plurality of layers includes two cladding layers, and two waveguide layers; and wherein one of the cladding layers is sandwiched between the two waveguide layers wherein the cladding layer sandwiched between the two waveguide layers has a thickness that is configured such that: the first and second waveguide layers are optically coupled; and the sandwiched cladding layer acts as a buffer to prevent etching the first waveguide layer when etching the second waveguide layer.

18. The method of manufacturing an integrated photonics circuit of claim 17, wherein the depositing comprises: depositing a first cladding layer on a substrate; depositing a first waveguide layer on the first cladding layer; depositing a second cladding layer on the first waveguide layer; depositing a second waveguide layer on the second cladding layer; and depositing a third cladding layer on the second waveguide layer.

19. The method of manufacturing an integrated photonics circuit of claim 18, wherein after the second waveguide layer is deposited: the second waveguide layer is patterned; and subsequently to the second waveguide layer being patterned, the first waveguide layer is patterned.

20. The method of manufacturing an integrated photonics circuit of claim 18, wherein the first waveguide layer is patterned after it is deposited and before the second cladding layer is deposited; and wherein the second waveguide layer is patterned, independently of the first waveguide layer, after it is deposited and before the third cladding layer is deposited.

21. The method of manufacturing an integrated photonics circuit of any of claims 18 to 20, wherein the patterning is a subtractive process.

22. The method of manufacturing an integrated photonics circuit of claim 21, wherein the patterning is performed using electron-beam and / or optical lithography.

Images