Method for manufacturing multilayer ceramic capacitor

Abstract

A method for manufacturing a multilayer ceramic capacitor 100 includes: a step for forming, on each of main surfaces of ceramic green sheets 211 obtained by using a first ceramic paste, internal electrode patterns 212 obtained by using a conductive paste and a ceramic paste layer 213 obtained by using a second ceramic paste; a step for producing an unfired layered body by layering the ceramic green sheets 211, each of which has formed thereon the internal electrode patterns 212 and the ceramic paste layer 213; a step for firing said unfired layered body; and a step for forming an external electrode on the outer surface of the fired layered body. The first ceramic paste and the second ceramic paste do not contain boron (B), lithium (Li), or zinc (Zn) which are volatile substances. The respective contents of silicon (Si) and magnesium (Mg) based on titanium (Ti) in the second ceramic paste are greater than the respective contents of Si and Mg based on Ti in the first ceramic paste.

Description

Manufacturing method for multilayer ceramic capacitors 【0001】 This invention relates to a method for manufacturing multilayer ceramic capacitors. 【0002】 Multilayer ceramic capacitors, which have a structure in which dielectric layers and internal electrode layers are alternately stacked, are manufactured, for example, by providing an outer layer on the outside of a stack of ceramic green sheets on which an internal electrode pattern is formed, and then pressing them together. In this process, a step is created between the dielectric layer and the internal electrode layer because there are parts of the ceramic green sheet on which the internal electrode pattern is not formed. 【0003】 To address the above problem, a method has been proposed to absorb the step difference by forming an internal electrode pattern on a ceramic green sheet and then forming a ceramic paste layer on the areas where the internal electrode pattern is not formed (see Patent Document 1). 【0004】Patent Document 1 discloses a multilayer ceramic electronic component comprising: a ceramic sintered body having a plurality of ceramic layers laminated together, having a first side surface and a second side surface facing each other, and a first end surface and a second end surface facing each other; a first internal electrode containing Ni formed inside the ceramic sintered body and drawn out from the first end surface; a second internal electrode containing Ni formed inside the ceramic sintered body so as to face the first internal electrode via a specific ceramic layer and drawn out from the second end surface; a first external terminal electrode formed on the first end surface of the ceramic sintered body and electrically connected to the first internal electrode; and a second external terminal electrode formed on the second end surface of the ceramic sintered body, electrically connected to the second internal electrode, and connected to a potential different from that of the first external terminal electrode. In the multilayer ceramic electronic component described in Patent Document 1, the ceramic sintered body includes, among the ceramic layers, an effective layer portion sandwiched between the first internal electrode and the second internal electrode and contributing to capacitance formation, and a side gap portion existing between the sides of the first and second internal electrodes and the first and second side surfaces of the ceramic sintered body, and between the sides of the effective layer portion and the first and second side surfaces of the ceramic sintered body, wherein at least the region of the side gap portion adjacent to the first and second internal electrodes is a Mg-rich region with a higher Mg concentration than the effective layer portion. 【0005】 Japanese Patent Publication No. 2010-103566 【0006】 When manufacturing a multilayer ceramic capacitor using the method described in Patent Document 1, if the sintering density of the portion that absorbs the step difference between the dielectric layer and the internal electrode layer is low, voids are likely to form between the edge of the internal electrode layer and the dielectric layer in the side gap portion, also known as the side margin portion. In that case, moisture such as humidity may penetrate into the void, potentially reducing the moisture resistance reliability. 【0007】Furthermore, if volatile components such as boron are included in the ceramic raw materials used to manufacture multilayer ceramic capacitors, these components may volatilize during firing, leading to variations in the composition of the resulting multilayer ceramic capacitors. As a result, the characteristics of the multilayer ceramic capacitors may also vary. 【0008】 The present invention was made to solve the above problems and aims to provide a method for manufacturing multilayer ceramic capacitors in which variations in characteristics are suppressed, the density of the side margin is high, and grain growth is suppressed. 【0009】 The present invention provides a method for manufacturing a multilayer ceramic capacitor, comprising the steps of: forming an internal electrode pattern using a conductive paste and a ceramic paste layer using a second ceramic paste on the main surface of a ceramic green sheet using a first ceramic paste; laminating the ceramic green sheets on which the internal electrode pattern and the ceramic paste layer are formed to produce an unfired laminate; firing the unfired laminate; and forming external electrodes on the outer surface of the fired laminate. Neither the first ceramic paste nor the second ceramic paste contains volatile components such as boron (B), lithium (Li), and zinc (Zn). The content of silicon (Si) and magnesium (Mg) in the second ceramic paste, relative to titanium (Ti), is greater than the content of Si and Mg in the first ceramic paste, relative to Ti. 【0010】 According to the present invention, it is possible to provide a method for manufacturing a multilayer ceramic capacitor in which variations in characteristics are suppressed, the density of the side margin is high, and grain growth is suppressed. 【0011】Figures 1A, 1B, and 1C are schematic perspective views illustrating an example of some steps in the manufacturing method of the multilayer ceramic capacitor of the present invention. Figure 2 is a schematic perspective view illustrating an example of a multilayer ceramic capacitor obtained by the manufacturing method of the present invention. Figure 3 is an example of a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line II-II. Figure 4 is an example of a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line III-III. 【0012】 The method for manufacturing the multilayer ceramic capacitor of the present invention will be described below. However, the present invention is not limited to the following embodiments, and can be appropriately modified and applied without altering the essence of the invention. Furthermore, the present invention also includes combinations of two or more of the preferred configurations described in the following embodiments. 【0013】 In this specification, terms describing relationships between elements (e.g., "perpendicular," "parallel," "orthogonal," etc.) and terms describing the shapes of elements do not represent only strict meanings, but also include a range of substantially equivalent terms, such as differences of a few percent. 【0014】 The following diagrams are schematic representations, and their dimensions, aspect ratios, and scales may differ from those of the actual product. The same reference numerals are used for identical or equivalent parts in the diagrams. Furthermore, identical elements are denoted by the same reference numerals in each diagram, and redundant explanations are omitted. 【0015】 The present invention provides a method for manufacturing a multilayer ceramic capacitor, comprising the steps of: forming an internal electrode pattern using a conductive paste and a ceramic paste layer using a second ceramic paste on the main surface of a ceramic green sheet using a first ceramic paste; stacking the ceramic green sheets on which the internal electrode pattern and the ceramic paste layer are formed to produce an unfired laminate; firing the unfired laminate; and forming external electrodes on the outer surface of the fired laminate. 【0016】 Figures 1A, 1B, and 1C are schematic perspective views illustrating an example of some steps in the manufacturing method of the multilayer ceramic capacitor of the present invention. 【0017】 Hereinafter, an example of a method for manufacturing the multilayer ceramic capacitor of the present invention will be described step by step with reference to Figures 1A, 1B, and 1C. 【0018】 (1) Prepare a ceramic green sheet using the first ceramic paste. 【0019】 The method for producing the ceramic green sheet is not particularly limited. The first ceramic paste mainly consists of a ceramic containing titanium (Ti). Preferably, the first ceramic paste further contains barium (Ba). Specifically, the first ceramic paste mainly contains a perovskite-type oxide. As the main component raw material of the first ceramic paste, for example, barium titanate (BaTiO) ３ Powders of ) compounds are used. The first ceramic paste also includes the form of a slurry. 【0020】 The first ceramic paste may further contain elements such as alkaline earth metal elements like calcium (Ca) and strontium (Sr), transition metal elements like zirconium (Zr) and hafnium (Hf), and rare earth elements (Re). 【0021】 (2) As shown in Figure 1A, an internal electrode pattern 212 is formed by printing an island-like conductive paste for internal electrodes containing conductive metal powder such as nickel (Ni) powder onto the main surface of the ceramic green sheet 211, for example by screen printing. 【0022】 (3) As shown in Figure 1B, a second ceramic paste is printed on the portion of the main surface of the ceramic green sheet 211 where the internal electrode pattern 212 is not formed, to form a ceramic paste layer 213 for eliminating steps. 【0023】 The second ceramic paste mainly comprises a ceramic containing Ti. Preferably, the second ceramic paste further contains Ba. Specifically, the second ceramic paste mainly comprises a perovskite-type oxide. For example, BaTiO is used as the main component raw material of the second ceramic paste. ３ A compound powder is used. 【0024】 The second ceramic paste may further contain elements such as alkaline earth metal elements like calcium (Ca) and strontium (Sr), transition metal elements like zirconium (Zr) and hafnium (Hf), and rare earth elements (Re). 【0025】 In the method for manufacturing a ceramic capacitor according to the present invention, it is preferable that the elements contained in the first ceramic paste and the elements contained in the second ceramic paste are the same. 【0026】 The present invention relates to a method for manufacturing a multilayer ceramic capacitor, characterized in that neither the first ceramic paste nor the second ceramic paste contains volatile components such as boron (B), lithium (Li), and zinc (Zn). In this case, it is sufficient that the first and second ceramic pastes do not contain volatile components such as B, Li, and Zn as additives, and it is permissible for trace amounts of volatile components to be inevitably mixed in as impurities. 【0027】 By using a first ceramic paste and a second ceramic paste that do not contain the volatile components B, Li, and Zn, the composition of the resulting multilayer ceramic capacitor becomes less prone to variation. As a result, variations in the characteristics of the multilayer ceramic capacitor can be suppressed. 【0028】 Furthermore, the present invention's method for manufacturing a multilayer ceramic capacitor is characterized in that the content of silicon (Si) and magnesium (Mg) in the second ceramic paste, relative to titanium (Ti), is greater than the content of Si and Mg in the first ceramic paste, relative to Ti. 【0029】 The inclusion of Si in the first or second ceramic paste improves sintering density. On the other hand, the inclusion of Mg in the first or second ceramic paste suppresses grain growth after densification. 【0030】In particular, by forming a ceramic paste layer using a second ceramic paste having a higher Si and Mg content compared to the first ceramic paste, it is possible to manufacture a multilayer ceramic capacitor with high density in the side margin area and suppressed grain growth. 【0031】 In the second ceramic paste, the Si content relative to Ti is preferably 1.9 mol% or more and 3.1 mol% or less. 【0032】 The content of Mg relative to Ti in the second ceramic paste is preferably 0.9 mol% or more and 2.6 mol% or less. For example, the content of Mg relative to Ti in the second ceramic paste may be 1.6 mol% or more and 2.6 mol% or less. 【0033】 On the other hand, the Si content in the first ceramic paste, relative to Ti, is preferably 1.0 mol% or more and 1.3 mol% or less. 【0034】 The content of Mg in the first ceramic paste, relative to Ti, is preferably 0 mol% or more and 0.1 mol% or less. The first ceramic paste may or may not contain Mg. 【0035】 If the first ceramic paste contains Mg, the ratio of the Mg content in the second ceramic paste relative to the Mg content in the first ceramic paste relative to Ti may be greater than, less than, or the same as the ratio of the Si content in the second ceramic paste relative to the Si content in the first ceramic paste relative to Ti. 【0036】Although not shown in FIG. 1B, when forming the internal electrode pattern 212 and the ceramic paste layer 213, at least a part of the second ceramic paste is made to overlap with the end portions in the width direction W of the internal electrode pattern 212, and on the main surface of the ceramic green sheet 211, a stepped region where the internal electrode pattern 212 is not formed and the second ceramic paste is not applied is present in the length direction L. It is preferable to form the internal electrode pattern 212 and the ceramic paste layer 213 in this way. 【0037】 (4) Although illustration is omitted, the ceramic green sheets 211 on which the internal electrode pattern 212 and the ceramic paste layer 213 are formed are laminated while being alternately shifted by a predetermined distance in the length direction L to produce a mother block. In addition, it is preferable to laminate a ceramic green sheet for an outer layer portion on which the internal electrode pattern 212 is not formed on the outermost layer of the mother block. Further, the mother block is preferably pressure-bonded in the lamination direction T by means such as a hydrostatic press. 【0038】 (5) As shown in FIG. 1C, the mother block is cut along a predetermined cut line CL into a predetermined size to cut out a laminated chip (unfired laminate). In FIG. 1C, for the sake of convenience, one ceramic green sheet 211 is taken out to show the cut line CL. If necessary, the laminated chip may be polished by a method such as barrel polishing to round at least one of the corner portions and ridge line portions of the laminated chip. 【0039】 In the step of cutting the mother block, when cutting the ceramic green sheet 211 in the first direction, it is preferable to cut between two adjacent internal electrode patterns 212 in a second direction orthogonal to the first direction and at the position of the stepped region described above. 【0040】 (6) The obtained laminated chip, that is, the unfired laminate is fired. The firing temperature may be a temperature at which the laminated chip is sufficiently densified. The firing treatment is, for example, mainly composed of BaTiO ３It is preferable to perform the process in an atmosphere where the compound is not reduced and the oxidation of the conductive metal is suppressed. Further, after firing, additional heat treatment may be performed at an appropriate temperature and atmosphere. 【0041】 (7) A conductive paste for an external electrode is applied to the outer surface of the fired laminate and baked to form an underlayer. If necessary, a plating layer may be formed on the surface of the underlayer. The plating layer may have a multilayer structure. Thus, an external electrode is formed. 【0042】 Thus, a multilayer ceramic capacitor is manufactured. 【0043】 FIG. 2 is a perspective view schematically showing an example of a multilayer ceramic capacitor obtained by the manufacturing method of the present invention. FIG. 3 is an example of a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 2. FIG. 4 is an example of a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 2. In FIGS. 2 to 4, the length direction of the laminate described later is indicated by L, the width direction by W, and the lamination direction by T. 【0044】 The multilayer ceramic capacitor 100 shown in FIG. 2 includes a laminate 110, a first external electrode 120, and a second external electrode 130. 【0045】 As shown in FIGS. 3 and 4, the laminate 110 includes a plurality of dielectric layers 140 and a plurality of internal electrode layers 150 laminated in the lamination direction T. 【0046】 The laminate 110 includes a first main surface 111 and a second main surface 112 that face each other in the lamination direction T, a first side surface 113 and a second side surface 114 that face each other in the width direction W orthogonal to the lamination direction T, and a first end surface 115 and a second end surface 116 that face each other in the length direction L orthogonal to the lamination direction T and the width direction W. 【0047】 At least one of the corner portions and ridge line portions of the laminate 110 may be rounded. Here, the corner portion is a portion where three surfaces of the laminate 110 intersect, and the ridge line portion is a portion where two surfaces of the laminate 110 intersect. 【0048】The first external electrode 120 is provided on the first end face 115 of the laminate 110. The first external electrode 120 may extend onto a part of the first major surface 111, the second major surface 112, the first side surface 113, and the second side surface 114 of the laminate 110. 【0049】 The second external electrode 130 is provided on the second end face 116 of the laminate 110. The second external electrode 130 may extend onto a part of the first major surface 111, the second major surface 112, the first side surface 113, and the second side surface 114 of the laminate 110. 【0050】 The dielectric layer 140 is composed of a ceramic containing titanium (Ti). The dielectric layer 140 preferably further contains barium (Ba). Specifically, the dielectric layer 140 contains a perovskite-type oxide as a main component. Also, it can be said that the dielectric layer 140 is composed of a sintered body of a perovskite-type oxide. 【0051】 The perovskite-type oxide contained as a main component in the dielectric layer 140 is, for example, barium titanate (BaTiO ３ ). BaTiO ３ exhibits a tetragonal crystal structure at room temperature and is a ferroelectric showing a high dielectric constant. Therefore, by using a BaTiO ３ -based compound as a main component, the dielectric constant of the dielectric layer 140 can be increased, and thus it becomes possible to increase the capacitance of the capacitor. 【0052】 For example, when the perovskite-type oxide is a BaTiO ３ -based compound, the BaTiO ３ -based compound may be a compound in which a part of Ba and / or Ti contained in BaTiO ３ is substituted with another element. For example, a part of Ba may be substituted with an alkaline earth metal element such as calcium (Ca) or strontium (Sr), or a part of Ti may be substituted with a transition metal element such as zirconium (Zr) or hafnium (Hf). Furthermore, BaTiO ３The molar ratio of A-site elements (Ba, Ca, Sr, etc.) to B-site elements (Ti, Zr, Hf, etc.) in a compound (hereinafter also referred to as the A / B ratio) is not strictly limited to 1:1. As long as the perovskite crystal structure is maintained, deviations in the molar ratio between A-site and B-site elements are acceptable. 【0053】 The perovskite oxide contained as the main component in the dielectric layer 140 may further contain rare earth elements (Re). Rare earth elements (Re) are a general term for elements that make up the group consisting of scandium (Sc) with atomic number 21, yttrium (Y) with atomic number 39, and lanthanum (La) with atomic number 57 to lutetium (Lu) with atomic number 71 in the periodic table. The perovskite oxide may contain one type of rare earth element (Re), or it may contain a combination of multiple types of rare earth elements (Re). The perovskite oxide contained as the main component in the dielectric layer 140 may further contain elements other than rare earth elements (Re). 【0054】 As shown in Figures 3 and 4, the internal electrode layer 150 includes a first internal electrode layer 151 electrically connected to the first external electrode 120 and a second internal electrode layer 152 electrically connected to the second external electrode 130. 【0055】 The first internal electrode layer 151 extends to the first end face 115 of the laminate 110, where it is electrically connected to the first external electrode 120. 【0056】 The second internal electrode layer 152 extends to the second end face 116 of the laminate 110, where it is electrically connected to the second external electrode 130. 【0057】 The first internal electrode layer 151 and the second internal electrode layer 152, which face each other across the dielectric layer 140, are not electrically connected. Therefore, when a voltage is applied between the first internal electrode layer 151 and the second internal electrode layer 152 via the first external electrode 120 and the second external electrode 130, charge accumulates. The accumulated charge generates capacitance, thereby enabling the device to function as a capacitive element. 【0058】As shown in Figures 3 and 4, the laminate 110 is divided into an inner layer IP, a pair of end margins EM, a pair of side margins SM, and a pair of outer layers XP. 【0059】 The inner layer IP is the portion where internal electrode layers 150 (i.e., the first internal electrode layer 151 and the second internal electrode layer 152) exposed on different end faces of the laminate 110 face each other in the lamination direction T via a dielectric layer 140. In the inner layer IP, it is preferable that the first internal electrode layer 151 and the second internal electrode layer 152 are alternately laminated via a dielectric layer 140. 【0060】 The pair of end margin portions EM are located in the longitudinal direction L on the first end face 115 side and the second end face 116 side of the inner layer portion IP, respectively, and are portions where internal electrode layers 150 exposed on the same end face of the laminate 110 (i.e., the first internal electrode layers 151 together or the second internal electrode layers 152 together) face each other in the lamination direction T without being separated by internal electrode layers 150 exposed on different end faces of the laminate 110. 【0061】 The pair of side margin portions SM are located on the first side surface 113 and the second side surface 114 sides, respectively, of the portion including the inner layer portion IP and the end margin portion EM in the width direction W, and are provided to cover the end of the internal electrode layer 150 in the width direction W. 【0062】 The outer layer XP is located on the first main surface 111 side and the second main surface 112 side of the portion including the inner layer IP, end margin EM, and side margin SM in the lamination direction T, and is provided to cover the inner electrode layer 150 closest to the first main surface 111 or the second main surface 112 of the laminate 110, respectively. 【0063】 In the multilayer ceramic capacitor 100, it is preferable that the inner layer IP, end margin EM, and side margin SM do not contain volatile components such as boron (B), lithium (Li), and zinc (Zn). 【0064】In the manufacturing process of the multilayer ceramic capacitor 100, if B, Li, and Zn are contained in the ceramic raw material, these components will volatilize during firing, which can lead to variations in the composition of the resulting multilayer ceramic capacitor 100, potentially causing variations in the characteristics of the multilayer ceramic capacitor 100. In contrast, if the volatile components B, Li, and Zn are not contained in the ceramic raw material, variations in the characteristics of the multilayer ceramic capacitor 100 can be suppressed. 【0065】 Furthermore, the inner layer IP, end margin EM, and side margin SM do not need to substantially contain the volatile components B, Li, and Zn, and it is acceptable for trace amounts of volatile components to inevitably be included as impurities, such as those that do not affect the variation in the characteristics of the multilayer ceramic capacitor 100. 【0066】 Furthermore, in the multilayer ceramic capacitor 100, it is preferable that the content of silicon (Si) and magnesium (Mg) in the ceramic contained in the end margin portion EM, relative to titanium (Ti), is greater than the content of Si and Mg in the ceramic contained in the inner layer portion IP, relative to Ti; the content of Si and Mg in the ceramic contained in the side margin portion SM, relative to Ti, is greater than the content of Si and Mg in the ceramic contained in the inner layer portion IP, relative to Ti; the content of Si and Mg in the ceramic contained in the side margin portion SM, relative to Ti, is greater than the content of Si and Mg in the ceramic contained in the end margin portion EM, relative to Ti; the content of Si in the ceramic contained in the side margin portion SM, relative to Ti, is greater than the content of Mg; and the content of Si in the ceramic contained in the end margin portion EM, relative to Ti, is greater than the content of Mg. 【0067】The presence of Si in the end margin (EM) and side margin (SM) improves sintering density, thereby enhancing moisture resistance reliability. On the other hand, the presence of Mg in the end margin (EM) and side margin (SM) suppresses grain growth after densification, thus improving high-temperature load reliability. 【0068】 In particular, by having higher Si and Mg content in the side margin portion SM compared to the end margin portion EM, it is possible to obtain a multilayer ceramic capacitor 100 with high density in the side margin portion SM and suppressed grain growth. 【0069】 The Si content in the ceramic contained in the side margin portion SM is preferably 1.4 mol% or more and 2.5 mol% or less, relative to Ti. 【0070】 In the ceramic contained in the side margin portion SM, the Mg content relative to Ti is preferably 0.4 mol% or more and 1.4 mol% or less. 【0071】 The Si content in the ceramic contained in the end margin portion EM is preferably 1.2 mol% or more and 2.1 mol% or less, relative to Ti. 【0072】 The Mg content in the ceramic contained in the end margin portion EM is preferably 0.2 mol% or more and 0.9 mol% or less, relative to Ti. 【0073】 The ratio of the Mg content in the ceramic part of the side margin part SM to the Mg content in the ceramic part of the end margin part EM, relative to the Mg content relative to Ti, may be greater than, less than, or the same as the ratio of the Si content in the ceramic part of the side margin part SM to the Si content in the ceramic part of the end margin part EM, relative to Ti. 【0074】 In the ceramic contained in the inner layer IP, the Si content relative to Ti is preferably greater than the Mg content. 【0075】 The Si content in the ceramic included in the inner layer IP is preferably 1.0 mol% or more and 1.3 mol% or less, relative to Ti. 【0076】 The Mg content in the ceramic contained in the inner layer IP is preferably 0.0 mol% or more and 0.1 mol% or less, relative to Ti. 【0077】 The content of each element in the side margin portion SM, the end margin portion EM, and the inner layer portion IP can be measured using analytical methods such as laser ablation inductively coupled plasma mass spectrometry (LA-ICP-MS) and inductively coupled plasma mass spectrometry (ICP-MS). 【0078】 Dimension of the width W of the side margin SM (in Figure 4, W) ＳＭ The lengths indicated by are not particularly limited, but are preferably 90 μm or less. On the other hand, the widthwise dimension W of the side margin portion SM is, for example, 50 μm or more. The widthwise dimension W of the side margin portion SM may be 15 μm or less. The widthwise dimension W of the side margin portion SM may be the same or different on the first side surface 113 side and the second side surface 114 side. 【0079】 Dimension L in the length direction of the end margin EM (in Figure 3, L) ＥＭ The lengths indicated by are not particularly limited, but are preferably 100 μm or less. On the other hand, the length L of the end margin portion EM is, for example, 60 μm or more. The length L of the end margin portion EM may be 15 μm or less. The length L of the end margin portion EM may be the same or different on the first end face 115 side and the second end face 116 side. 【0080】 Dimension of the stacking direction T of the outer layer XP (in Figures 3 and 4, T) ＸＰThe lengths indicated by are not particularly limited, but are preferably 90 μm or less. On the other hand, the dimensions of the outer layer XP in the lamination direction T are, for example, 70 μm or more. The dimensions of the outer layer XP in the lamination direction T may also be 15 μm or less. The dimensions of the outer layer XP in the lamination direction T may be the same or different on the first main surface 111 side and the second main surface 112 side. 【0081】 The dimensions of the laminate 110 are not particularly limited. For example, in the embodiment described later, the length L dimension of the laminate 110 is 3.2 mm and the width W dimension is 1.6 mm. 【0082】 The thickness of the dielectric layer 140 in the inner layer IP is not particularly limited, but it is preferably 0.8 μm or less for each layer. On the other hand, the thickness of the dielectric layer 140 in the inner layer IP is not particularly limited, but it is preferably 0.6 μm or more for each layer. 【0083】 The number of layers of dielectric layers 140 in the inner layer IP is, for example, 1200 or more and 1400 or less. 【0084】 The internal electrode layer 150 contains a conductive metal. Examples of conductive metals include nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), and alloys containing at least one of these metals. The internal electrode layer 150 may also contain other components besides the conductive metal. Examples of other components include ceramic components that act as co-materials. An example of a ceramic component is the BaTiO contained in the dielectric layer 140. ３ Examples include compound systems. 【0085】 The thickness of the internal electrode layer 150 in the inner layer IP is not particularly limited, but it is preferably 0.6 μm or less. On the other hand, the thickness of the internal electrode layer 150 in the inner layer IP is, for example, 0.4 μm or more. 【0086】The configuration of the first external electrode 120 and the second external electrode 130 is not particularly limited. The first external electrode 120 and the second external electrode 130 may have a laminated structure consisting of a base layer, a first plating layer, and a second plating layer, starting from the end face side of the multilayer ceramic capacitor 100. The base layer contains a metal such as nickel (Ni) or copper (Cu). The base layer may also contain ceramic powder as a co-material in addition to the metal. The first plating layer is, for example, a nickel (Ni) plating layer. The second plating layer is, for example, a tin (Sn) plating layer. A conductive resin layer may be provided between the base layer and the first plating layer. The conductive resin layer is a layer containing conductive metal particles such as copper (Cu), silver (Ag), and nickel (Ni), and resin. The first external electrode 120 and the second external electrode 130 are not limited in their form as long as they are electrically connected to the internal electrode layer 150 and function as external input / output terminals. 【0087】 The following describes how to measure the dimensions of each component. 【0088】 The thicknesses of the dielectric layer 140 and the internal electrode layer 150 in the inner layer IP are measured as follows: First, the multilayer ceramic capacitor 100 is polished to expose a cross section perpendicular to the length direction L (also called the WT cross section). The exposed cross section is observed with a scanning electron microscope. Next, the thicknesses of the dielectric layer 140 and the internal electrode layer 150 are measured along a center line along the stacking direction T that passes through the center of the exposed cross section, and along a total of five lines drawn at equal intervals on both sides of this center line. The average of the five measured values ​​for the dielectric layer 140 is taken as the thickness of the dielectric layer 140. The average of the five measured values ​​for the internal electrode layer 150 is taken as the thickness of the internal electrode layer 150. 【0089】The widthwise dimension W of the side margin portion SM is measured as follows. First, the multilayer ceramic capacitor 100 is polished to expose a cross section perpendicular to the lengthwise direction L. The exposed cross section is observed with a microscope and its dimensions are measured. The measurement positions are the upper, middle, and lower parts located on the boundary lines that divide the exposed cross section into four equal parts in the stacking direction T. The average of the measured values ​​of the side margin portion SM on the first side surface 113 at these three locations is taken as the widthwise dimension W of the side margin portion SM on the first side surface 113, and the average of the measured values ​​of the side margin portion SM on the second side surface 114 at these three locations is taken as the widthwise dimension W of the side margin portion SM on the second side surface 114. 【0090】 The length L dimension of the end margin portion EM is measured as follows. First, the multilayer ceramic capacitor 100 is polished to expose the cross section perpendicular to the width direction W (also called the LT cross section). The exposed cross section is observed with a microscope and its dimensions are measured. The measurement positions are the upper, middle, and lower parts, located on the boundary lines that divide the exposed cross section into four equal parts in the stacking direction T. The average of the measured values ​​of the end margin portion EM on the first end face 115 side at these three locations is taken as the length L dimension of the end margin portion EM on the first end face 115 side, and the average of the measured values ​​of the end margin portion EM on the second end face 116 side at these three locations is taken as the length L dimension of the end margin portion EM on the second end face 116 side. 【0091】 The dimensions of the outer layer XP in the stacking direction T are measured as follows: First, the multilayer ceramic capacitor 100 is polished to expose the cross section perpendicular to the width direction W. The exposed cross section is observed with a microscope and its dimensions are measured. The measurement position is the center of the length direction L. 【0092】 This specification discloses the following: 【0093】<1> A method for manufacturing a multilayer ceramic capacitor, comprising the steps of: forming an internal electrode pattern using a conductive paste and a ceramic paste layer using a second ceramic paste on the main surface of a ceramic green sheet using a first ceramic paste; stacking the ceramic green sheets on which the internal electrode pattern and the ceramic paste layer are formed to produce an unfired laminate; firing the unfired laminate; and forming external electrodes on the outer surface of the fired laminate, wherein neither the first ceramic paste nor the second ceramic paste contains volatile components such as boron (B), lithium (Li), and zinc (Zn); and the content of silicon (Si) and magnesium (Mg) in the second ceramic paste, relative to titanium (Ti), is greater than the content of Si and Mg in the first ceramic paste, relative to Ti. 【0094】 <2> The method for manufacturing a multilayer ceramic capacitor as described in <1>, wherein the Si content in the second ceramic paste, based on Ti, is 1.9 mol% or more and 3.1 mol% or less. 【0095】 <3> The method for manufacturing a multilayer ceramic capacitor according to <1> or <2>, wherein the content of Mg based on Ti in the second ceramic paste is 0.9 mol% or more and 2.6 mol% or less. 【0096】 <4> The method for manufacturing a multilayer ceramic capacitor according to any one of <1> to <3>, wherein the Si content in the first ceramic paste, based on Ti, is 1.0 mol% or more and 1.3 mol% or less. 【0097】 <5> The method for manufacturing a multilayer ceramic capacitor according to any one of <1> to <4>, wherein the content of Mg relative to Ti in the first ceramic paste is 0 mol% or more and 0.1 mol% or less. 【0098】<6> The method for manufacturing a multilayer ceramic capacitor according to any one of <1> to <5>, wherein the first ceramic paste and the second ceramic paste further contain barium (Ba). 【0099】 The following are examples that more specifically disclose the method for manufacturing the multilayer ceramic capacitor of the present invention. However, the present invention is not limited to these examples. 【0100】 [Fabrication of Multilayer Ceramic Capacitors] A multilayer ceramic capacitor was fabricated by performing the following steps: forming an internal electrode pattern using a conductive paste and a ceramic paste layer using a second ceramic paste on the main surface of a ceramic green sheet using a first ceramic paste; laminating the ceramic green sheet on which the internal electrode pattern and the ceramic paste layer are formed to create an unfired laminate; firing the unfired laminate; and forming external electrodes on the outer surface of the fired laminate. 【0101】 In this process, the internal electrode pattern and ceramic paste layer were formed such that at least a portion of the second ceramic paste overlapped with the widthwise edge of the internal electrode pattern, and a stepped region existed in the longitudinal direction on the main surface of the ceramic green sheet where the internal electrode pattern was not formed and the second ceramic paste was not applied. Furthermore, in the process of cutting the ceramic green sheet, when cutting the ceramic green sheet in the first direction, the cut was made between two adjacent internal electrode patterns in the second direction perpendicular to the first direction, and at the location of the stepped region described above. 【0102】 The first and second ceramic pastes can be prepared by wet mixing a ceramic material with PVB (polyvinyl butyral) resin, a plasticizer, a dispersant, and an organic solvent. The second ceramic paste can be applied using printing methods such as screen printing, inkjet printing, or gravure printing. 【0103】[Evaluation of Multilayer Ceramic Capacitors] 1. The WT cross-section (cross-section parallel to the width direction and stacking direction) at the center of the dense laminate in the side margin was observed using a scanning electron microscope (SEM), and the area of ​​voids present in the side margin was measured. The ratio of the void area to the total area of ​​the side margin (void area / total area of ​​the side margin) was defined as the porosity, and those with a porosity of less than 3% were judged as ○ (good), and those with a porosity of 3% or more were judged as × (poor). 【0104】 2. End grain diameter The WT cross section at the center of the length direction of the laminate was observed by SEM, and the grain diameter of the ceramic particles constituting the dielectric layer at the widthwise end of the inner layer (i.e., the boundary with the side margin) was measured. Similarly, the grain diameter of the ceramic particles constituting the dielectric layer at the center of the inner layer was measured. The ratio of the grain diameter at the widthwise end of the inner layer to the grain diameter at the center of the inner layer (i.e., grain diameter at the end / grain diameter at the center) was defined as the end grain diameter ratio, and those with an end grain diameter ratio of less than 1.2 were judged as ○ (good), and those with an end grain diameter ratio of 1.2 or more were judged as × (bad). 【0105】 3. High-Temperature Load Reliability (MTTF, B1 Life) Highly accelerated life testing (HALT) was performed on multilayer ceramic capacitors under the conditions of a test temperature of 150°C and a test voltage of 6.3V to determine the B1 life (the point at which the cumulative failure probability reaches 1%). Capacitors with a B1 life of more than 2.8 hours were judged as ○ (pass), and those with a B1 life of 2.8 hours or less were judged as × (fail). 【0106】 【0107】 As shown in Table 1, in Examples 1 to 4, where the content of Si and Mg relative to Ti in the second ceramic paste was greater than the content of Si and Mg relative to Ti in the first ceramic paste, the side margin area was denser, grain growth was suppressed, and a multilayer ceramic capacitor with excellent high-temperature load reliability was obtained. 【0108】100 Multilayer ceramic capacitor 110 Laminate 111 First main surface 112 Second main surface 113 First side surface 114 Second side surface 115 First end surface 116 Second end surface 120 First external electrode 130 Second external electrode 140 Dielectric layer 150 Internal electrode layer 151 First internal electrode layer 152 Second internal electrode layer 211 Ceramic green sheet 212 Internal electrode pattern 213 Ceramic paste layer EM End margin SM Side margin IP Inner layer XP Outer layer CL Cut line L Length direction T Lamination direction W Width direction

Claims

1. A method for manufacturing a multilayer ceramic capacitor, comprising the steps of: forming an internal electrode pattern using a conductive paste and a ceramic paste layer using a second ceramic paste on the main surface of a ceramic green sheet using a first ceramic paste; laminating the ceramic green sheets on which the internal electrode pattern and the ceramic paste layer are formed to produce an unfired laminate; firing the unfired laminate; and forming external electrodes on the outer surface of the fired laminate, wherein neither the first ceramic paste nor the second ceramic paste contains volatile components such as boron (B), lithium (Li), and zinc (Zn), and the respective content of silicon (Si) and magnesium (Mg) in the second ceramic paste, relative to titanium (Ti), is greater than the respective content of Si and Mg in the first ceramic paste, relative to Ti.

2. The method for manufacturing a multilayer ceramic capacitor according to claim 1, wherein the Si content in the second ceramic paste, relative to Ti, is 1.9 mol% or more and 3.1 mol% or less.

3. The method for manufacturing a multilayer ceramic capacitor according to claim 1 or 2, wherein the content of Mg in the second ceramic paste, based on Ti, is 0.9 mol% or more and 2.6 mol% or less.

4. The method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the Si content in the first ceramic paste, relative to Ti, is 1.0 mol% or more and 1.3 mol% or less.

5. The method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the content of Mg in the first ceramic paste, based on Ti, is 0 mol% or more and 0.1 mol% or less.

6. A method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the first ceramic paste and the second ceramic paste further contain barium (Ba).

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