Power conversion apparatus, motor driving apparatus, and refrigeration cycle apparatus

Abstract

A power conversion apparatus (100) is provided with a control device (5) that generates, on the basis of a voltage command value and a carrier signal, a drive signal for determining the ON time and OFF time of each of switching elements (9a, 9b, 9c) of an upper arm and switching elements (9d, 9e, 9f) of a lower arm of an inverter (3). The control device (5) changes a first time, which is a time for turning on all the three switching elements (9d, 9e, 9f) on the side on which shunt resistors (11a, 11b, 11c) provided in a current detector (4) are connected, in accordance with the modulation rate of the voltage command value, and determines the first time so that the first time does not become equal to or less than the limit value of a current detection time in the current detector (4) in a section where the modulation rate is equal to or greater than a preset first modulation rate.

Description

Power converter, motor drive system, and refrigeration cycle system 【0001】 This disclosure relates to a power conversion device equipped with an inverter that converts DC power to desired AC power and supplies it to a load, a motor drive device equipped with a power conversion device, and a refrigeration cycle device. 【0002】 Conventional power converters equipped with inverter devices use PWM (Pulse Width Modulation) control to output voltage according to the load, controlling the inverter based on the current value of the phase current flowing through each phase of the load. One method for detecting phase current is the current detection method using three shunt resistors. In this method, for example, shunt resistors are placed between the DC bus on the low potential side of the inverter and the switching elements of the lower arms of each phase, and the current flowing through the switching elements is detected as the phase current flowing through each phase of the load. In this method, when the switching elements of the lower arms are in the ON state, the current flowing through the switching elements of the lower arms can be detected by measuring the voltage drop value across the shunt resistors. 【0003】 The inverter outputs different phase voltages depending on whether the switching elements are ON or OFF. The inverter's voltage output in each state is divided into actual voltage vectors V1 to V6 and zero voltage vectors V0 and V7. When the inverter outputs voltage vectors with a desired amplitude and phase, it selects any two actual voltage vectors from V1 to V6 and controls the output time of the two selected actual voltage vectors and the output time of the zero voltage vector V0 or V7. Note that the zero voltage vector V0 is the voltage vector when all the switching elements in the lower arm are ON, and the zero voltage vector V7 is the voltage vector when all the switching elements in the lower arm are ON, so the amplitude of both voltage vectors is 0. 【0004】In order for an inverter to output an accurate voltage, it is required to accurately detect the phase current flowing through the load. Therefore, in the current detection method using three shunt resistors, current detection is performed at the time of output of a zero voltage vector that can simultaneously detect the phase current. For example, when the shunt resistor is arranged in the lower arm, in order to simultaneously detect the current of three phases with the shunt resistor, the phase current is detected at the output timing of the zero voltage vector V0. 【0005】 When increasing the output voltage of the inverter, the output time of the actual voltage vector becomes longer. On the other hand, when the output time of the actual voltage vector becomes longer, the output time of the zero voltage vector becomes shorter, making it difficult to secure the time required for current detection. And if sufficient current detection time cannot be secured, the accuracy of current detection deteriorates due to the influence of ringing or the like. In response to this problem, Patent Document 1 below discloses a technique for accurately performing current detection using three shunt resistors even when the output voltage of the inverter increases. Specifically, in Patent Document 1, in a neutral point power supply method configuration in which a neutral point where motor coils are star-connected and a low-voltage bus of the inverter are connected by a power supply such as a capacitor, the output time of the zero voltage vector is changed according to the rotational speed to secure the current detection time, and the current detection accuracy using three shunt resistors is improved. 【0006】 Japanese Patent Application Laid-Open No. 2009-118633 【0007】 However, the technique of Patent Document 1 is a method for determining whether or not to adjust the output time of the zero voltage vector according to the rotational speed, and it is necessary to perform a boosting operation when adjusting the output time of the zero voltage vector. For this reason, in the technique of Patent Document 1, the output time of the zero voltage vector is ensured more than necessary, the output time of the zero voltage vector is limited, and as a result, there is a problem that the magnitude of the output voltage of the inverter is limited. 【0008】 The present disclosure has been made in view of the above, and an object thereof is to obtain a power conversion device that can suppress the limitation of the magnitude of the output voltage of the inverter while ensuring the accuracy of current detection. 【0009】To solve the above-mentioned problems and achieve the objective, the power converter according to this disclosure is a power converter that converts DC power into desired AC power and supplies it to a load, and comprises an inverter, a current detector, and a control device. The inverter is configured by connecting three phases in parallel between a high-potential DC bus and a low-potential DC bus, each consisting of a single-phase leg in which the switching elements of the upper arm and the switching elements of the lower arm are connected in series. The current detector comprises at least two phases of shunt resistors arranged on either the side between the high-potential DC bus and the switching elements of the upper arm, or between the low-potential DC bus and the switching elements of the lower arm, and detects the phase current flowing through each phase of the load by detecting the voltage generated across the shunt resistors. The control device generates drive signals that determine the on-time and off-time of the switching elements of the upper arm and the lower arm, respectively, based on a voltage command value and a carrier signal. Furthermore, the control device changes a first time, which is the time it takes to turn on all three switching elements on the side connected to the shunt resistor, according to the modulation rate of the voltage command value. The control device determines the first time such that, in the interval where the modulation rate is equal to or greater than a preset first modulation rate, the first time does not fall below the current detection time limit of the current detector. 【0010】 The power conversion device described herein has the effect of ensuring accuracy in current detection while suppressing limitations on the magnitude of the inverter's output voltage. 【0011】1. Circuit diagram showing an example configuration of a motor drive device including a power converter according to Embodiment 1. Block diagram showing an example configuration of a control device provided in the power converter according to Embodiment 1. Diagram for explaining voltage vectors in a general spatial vector modulation scheme. Diagram for explaining the operation of the drive signal calculation unit provided in the control device according to Embodiment 1. Diagram for explaining the detection time and detection accuracy of the current flowing through the switching elements of the power converter according to Embodiment 1. Flowchart for explaining the processing flow performed in the control device according to Embodiment 1. Diagram for explaining the first example of variations of zero voltage vector output ratio change in Embodiment 1. Diagram for explaining the second example of variations of zero voltage vector output ratio change in Embodiment 1. Diagram for explaining the third example of variations of zero voltage vector output ratio change in Embodiment 1. Block diagram showing an example of hardware configuration realizing the functions of the control device according to Embodiment 1. Diagram for explaining the behavior of switching elements related to the control of the control device according to Embodiment 2. Flowchart for explaining the key points of control in the control device according to Embodiment 2. Diagram for explaining the operation when the control according to Embodiment 2 is not implemented. Diagram for explaining the operation when the control according to Embodiment 2 is implemented. Diagram showing an example configuration of an air conditioner according to Embodiment 3. 【0012】 The power converter, motor drive unit, and refrigeration cycle unit according to embodiments of this disclosure will be described in detail below with reference to the attached drawings. In the following description, the term "connection" will be used without distinguishing between physical and electrical connections. That is, the term "connection" includes both cases where components are directly connected to each other and cases where components are indirectly connected to each other through other components. In the following description, multiple components of the same type will be indicated by subscripted reference numerals, but when describing them collectively without distinguishing between them, the subscript will be omitted as appropriate. 【0013】Embodiment 1. Figure 1 is a circuit diagram showing an example configuration of a motor drive device 200 including a power converter 100 according to Embodiment 1. In Figure 1, the motor drive device 200 is configured to include a motor 8 which is a load, a power converter 100, and a DC power supply 150. The motor drive device 200 is a drive device that converts AC power supplied from an AC power source 1 into drive power for the motor 8. The DC power supply 150 converts the AC power supplied from the AC power source 1 into DC power and outputs it to the power converter 100. The power converter 100 converts the DC power supplied from the DC power supply 150 into AC power and outputs it to the motor 8. 【0014】 The DC power supply unit 150 comprises a converter 2, a reactor 6, and a capacitor 7. The converter 2 comprises four diodes 13a to 13d connected in a single-phase bridge configuration. One input terminal of the converter 2 is connected to one side of the AC power supply 1 via the reactor 6, and the other input terminal of the converter 2 is connected to the other side of the AC power supply 1. The converter 2 converts the AC voltage applied from the AC power supply 1 into a DC voltage and applies it to the power converter 100. 【0015】 Converter 2 and power converter 100 are connected by DC buses 30a and 30b. DC bus 30a is the high-potential DC bus, and DC bus 30b is the low-potential DC bus. Capacitor 7 is connected to DC buses 30a and 30b and smooths the DC voltage, which includes pulsations, output by converter 2. The DC voltage smoothed by capacitor 7 is applied to power converter 100. 【0016】 In Figure 1, the converter 2 is illustrated as a rectifier circuit composed of four diodes, but the system is not limited to this example. The converter 2 may also be composed of a boost circuit having a boosting function and at least one switching element. Furthermore, Figure 1 shows an example configuration when the AC power supply 1 is single-phase AC, but the AC power supply 1 may be three-phase AC. If the AC power supply 1 is three-phase AC, the DC power supply unit 150 is also modified to accommodate three-phase AC. 【0017】The power converter 100 comprises an inverter 3, a current detector 4, a control device 5, and voltage detectors 12a to 12c. The inverter 3 comprises switching elements 9a to 9f connected in a three-phase bridge configuration. The inverter 3 is a three-phase inverter, and the motor 8 connected to the inverter 3 is a three-phase motor. 【0018】 In inverter 3, switching elements 9a to 9c are switching elements connected to the high-potential DC bus 30a and are appropriately referred to as "upper arm switching elements". Switching elements 9d to 9f are switching elements connected to the low-potential DC bus 30b and are appropriately referred to as "lower arm switching elements". 【0019】 The switching element 9a on the upper arm and the switching element 9d on the lower arm are connected in series to form a single-phase leg. The relationship between the switching element 9b on the upper arm and the switching element 9e on the lower arm, and the relationship between the switching element 9c on the upper arm and the switching element 9f on the lower arm are similar. In other words, the inverter 3 is constructed by connecting three single-phase legs, each consisting of the switching element 9 on the upper arm and the switching element 9 on the lower arm connected in series, in parallel between the high-potential DC bus 30a and the low-potential DC bus 30b. 【0020】 Each of the switching elements 9a to 9f is equipped with freewheeling diodes 10a to 10f connected in parallel. The freewheeling diodes 10 are connected such that the cathode is on the high-potential side and the anode is on the low-potential side. Figure 1 shows the case where the switching element 9 is an IGBT (Insulated Gate Bipolar Transistor), but a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may be used instead of an IGBT. Note that, due to its structure, a MOSFET has a built-in parasitic diode. Therefore, when a MOSFET is used as the switching element 9, a configuration in which the freewheeling diodes 10 are not connected in parallel may be adopted. 【0021】The current detector 4 includes shunt resistors 11a to 11c connected between the low-potential DC bus 30b and each of the switching elements 9d to 9f on the lower arm. Each of the voltage detectors 12a to 12c detects the terminal voltage of the shunt resistor 11 generated by the current flowing through the shunt resistors 11a to 11c. The voltage detector 12 is configured with an AD (Analog Digital) converter (not shown) that detects the terminal voltage of the shunt resistor 11, converts it to a digital value, and outputs it to the control device 5. 【0022】 In the inverter 3, if all of the switching elements 9d to 9f on the lower arm are turned ON, current flows through all of the shunt resistors 11a to 11c. In the power conversion device 100 according to Embodiment 1, in order to simultaneously detect the phase current flowing through each phase of the motor 8, current detection is performed at the timing when all of the switching elements 9d to 9f on the lower arm are turned ON. 【0023】 In Figure 1, a configuration is shown in which three sets of shunt resistors 11 and voltage detectors 12 detect the current of each of the three phases. However, it is also possible to detect the current of any two of the three phases, and the current of the remaining phase can be calculated by utilizing the fact that the phase currents are balanced in three phases. Furthermore, in Figure 1, a configuration is shown in which the shunt resistors 11a to 11c are connected between the low-potential DC bus 30b and each of the switching elements 9d to 9f on the lower arm. However, the shunt resistors 11a to 11c may also be connected between the high-potential DC bus 30a and each of the switching elements 9a to 9c on the upper arm. In other words, the current detector 4 is configured to include at least two shunt resistors 11 positioned on either the side between the high-potential DC bus 30a and the switching elements 9a to 9c of the upper arm, or between the low-potential DC bus 30b and the switching elements 9d to 9f of the lower arm, and to detect the phase current flowing through each phase of the motor 8 by detecting the voltage generated across the two shunt resistors 11. 【0024】Figure 2 is a block diagram showing an example configuration of a control device 5 provided in a power converter 100 according to Embodiment 1. The control device 5 has the function of generating drive signals that determine the on-time and off-time of the switching elements 9a to 9c of the upper arm and the switching elements 9d to 9f of the lower arm, respectively, based on the voltage command value and the carrier signal. To realize this function, the control device 5 includes, as shown in Figure 2, a current calculation unit 14, a coordinate transformation unit 15, a voltage command value calculation unit 16, a phase voltage output ratio calculation unit 17, a drive signal calculation unit 18, an estimated angle calculation unit 19, and a carrier signal generation unit 20. In the following description, the leg to which the switching elements 9a and 9d are connected will be referred to as the "U phase", the leg to which the switching elements 9b and 9e are connected as the "V phase", and the leg to which the switching elements 9c and 9f are connected as the "W phase". 【0025】 The current calculation unit 14 converts the terminal voltages Vsu, Vsv, and Vsw of the shunt resistor detected by the current detector 4 into phase currents iu, iv, and iw. The carrier signal Cs output from the carrier signal generation unit 20 is used to calculate the phase currents iu, iv, and iw. The coordinate transformation unit 15 uses the motor electrical angle θ to convert the phase currents iu, iv, and iw of the three-phase fixed coordinate system into the d-axis current id and q-axis current iq of the two-phase rotating coordinate system. The motor electrical angle θ is the rotation angle of the rotor (not shown) of the motor 8, expressed in electrical angle. The motor electrical angle θ is estimated by the estimated angle calculation unit 19 and output to the coordinate transformation unit 15 and the phase voltage output ratio calculation unit 17. Alternatively, the motor electrical angle θ may be calculated based on the mechanical angle of the rotor detected by a detector such as an encoder. 【0026】The voltage command value calculation unit 16 calculates dq-axis voltage command values ​​Vd* and Vq* based on the command value N* based on the operation of the motor 8, and the d-axis current id and q-axis current iq. Examples of command values ​​N* based on the operation of the motor 8 are speed commands and torque commands. The phase voltage output ratio calculation unit 17 calculates the phase voltage output ratios DVu, DVv, and DVw based on the dq-axis voltage command values ​​Vd* and Vq*, the bus voltage Vdc which is the voltage between the DC buses 30a and 30b, and the motor electrical angle θ, according to the spatial vector modulation method described later. The phase voltage output ratios DVu, DVv, and DVw are the ratios of the time it takes to turn on the corresponding switching element 9 when outputting a desired phase voltage to the carrier period, which is one period of the carrier signal Cs. 【0027】 The drive signal calculation unit 18 calculates the drive signals Sup, Svp, Swp, Sun, Svn, and Swn based on the phase voltage output ratios DVu, DVv, and DVw, and the carrier signal Cs. For example, the drive signal calculation unit 18 compares the magnitudes of the phase voltage output ratios DVu, DVv, and DVw with the carrier signal Cs, and generates the drive signals Sup, Svp, Swp, Sun, Svn, and Swn based on the comparison result. The drive signals Sup, Svp, Swp, Sun, Svn, and Swn are PWM-modulated PWM signals. The switching elements 9 of each phase of the inverter 3 are controlled to be on and off by the drive signals Sup, Svp, Swp, Sun, Svn, and Swn. 【0028】 The operation of the phase voltage output ratio calculation unit 17 is explained below. In the circuit configuration described in Patent Document 1 mentioned above, a battery is used as the DC power supply, so the bus voltage input to the inverter is controlled to be constant. In contrast, the power conversion device 100 according to Embodiment 1 is configured such that the capacitor 7 receives the pulsating voltage output from the converter 2, so the bus voltage Vdc pulsates. In addition, the commercial power supply used as the AC power supply 1 has voltage fluctuations, and the capacitance value of the capacitor 7 is not a constant value, and pulsations that fluctuate depending on the operating state of the motor 8 are also added. For this reason, the phase voltage output ratio calculation unit 17 uses the bus voltage Vdc to calculate the phase voltage output ratios DVu, DVv, and DVw. 【0029】Figure 3 illustrates the voltage vector in a typical spatial vector modulation scheme. In the inverter 3, each phase's switching element 9 has two switching states: on and off. For the U, V, and W phases, the state where the upper arm's switching element 9 is on is defined as "1," and the state where the lower arm's switching element 9 is on is defined as "0." Here, excluding the dead time period during switching, when one arm's switching element 9a to 9c and the other arm's switching elements 9d to 9f are on, the other arm's switching element 9 is off. Therefore, the switching state of each phase leg in the inverter 3 can be represented by a combination of three state values. This combination of state values ​​is called a "voltage vector." Specifically, the output voltage vectors of inverter 3 can be represented as V0

[000] , V1

[100] , V2

[110] , V3

[010] , V4

[011] , V5

[001] , V6

[101] , and V7

[111] . Figure 3 shows these eight types of voltage vectors. The state values ​​in square brackets are represented from left to right in the order of U-phase, V-phase, and W-phase. 【0030】 Of the eight types of voltage vectors, voltage vectors V1 to V6 in which at least one of the state values ​​of each phase is different are real voltage vectors with voltage amplitude. On the other hand, voltage vectors V0 and V7 in which all the state values ​​of each phase are the same are zero voltage vectors with no amplitude. Hereinafter, voltage vectors V1 to V6 will be referred to as "real voltage vectors V1 to V6" or simply as "real voltage vectors" without any symbols, and voltage vectors V0 and V7 will be referred to as "zero voltage vectors V0 and V7" or simply as "zero voltage vectors" without any symbols. 【0031】The phase voltage output ratio calculation unit 17 controls the output times of the actual voltage vectors Vact1 and Vact2 and the zero voltage vector Vzero when it performs calculations based on the spatial vector modulation scheme using the dq-axis voltage command values ​​Vd* and Vq* calculated by the voltage command value calculation unit 16 as the output voltage vector Vout. The actual voltage vectors Vact1 and Vact2 are any two of the actual voltage vectors V1 to V6 located on either side of the output voltage vector Vout. The zero voltage vector Vzero is any one of the zero voltage vectors V0 and V7, and the output time of the zero voltage vector Vzero in one carrier period is the sum of the output time of the zero voltage vector V0 and the output time of the zero voltage vector V7. Note that the amplitude and phase of the output voltage vector Vout do not change regardless of how the output times of the zero voltage vectors V0 and V7 are set. Therefore, the ratio of the output times of the zero voltage vectors V0 and V7 can be arbitrarily changed within the range where the sum of the calculated output times of the zero voltage vectors V0 and V7 is equal. 【0032】 Generally, a modulation method in which the ratio of the output times of the zero voltage vectors V0 and V7 is set to "1:0" or "0:1" is called a "two-phase modulation method." Modulation methods other than two-phase modulation are called "three-phase modulation methods." As will be described in detail later, the power converter 100 according to Embodiment 1 basically uses a three-phase modulation method in which the ratio of the output times of the zero voltage vectors V0 and V7 is set to "1:1." 【0033】 Figure 4 is a diagram illustrating the operation of the drive signal calculation unit 18 provided in the control device 5 according to Embodiment 1. Figure 4 shows the time-varying waveform of the carrier signal Cs in the carrier period tfc, the time-varying waveforms of the drive signals Sup, Svp, Swp, Sun, Svn, Swn generated based on the phase voltage output ratios DVu, DVv, DVw calculated by the phase voltage output ratio calculation unit 17, and the transition of the voltage vector. The carrier period tfc is one period of the carrier signal Cs. Although Figure 4 shows the case where the carrier signal Cs is a single-carrier triangular wave, the carrier signal Cs may also be a double-carrier triangular wave. 【0034】For example, the drive signal Sup for the switching element 9a of the U-phase upper arm is on (=1) when the phase voltage output ratio DVu of the U-phase is greater than the carrier signal Cs, and off (=0) when it is less than DVu. On the other hand, the drive signal Sun for the switching element 9d of the U-phase lower arm is on (=1) when the phase voltage output ratio DVu of the U-phase is less than the carrier signal, and off (=0) when it is greater than DVu. The same applies to the switching elements 9 of the upper and lower arms of the V-phase and W-phase. That is, when one arm of each phase's leg is in the ON state, the other arm is in the OFF state. In practice, a leg short-circuit prevention time is provided during which the switching elements 9 of the upper and lower arms are simultaneously in the OFF state, but this is omitted in Figure 4. The leg short-circuit prevention time is called the dead time. 【0035】 As shown in Figures 3 and 4, the zero voltage vector V0 is when the switching elements 9d to 9f of each phase lower arm are in the ON state. The zero voltage vector V7 is when the switching elements 9 of each phase lower arm are in the OFF state. Even if the ratio of the output times of the zero voltage vectors V0 and V7 is changed, as long as the sum of the output time of the zero voltage vector V0 and the output time of the zero voltage vector V7 is not changed, the ON state and OFF state of the switching elements 9 of the upper and lower arms can be changed without changing the magnitude of the output voltage vector Vout. 【0036】 Figure 5 is a diagram illustrating the detection time and detection accuracy of the current flowing through the switching element 9 of the power converter 100 according to Embodiment 1. As an example, Figure 5 shows the time-varying waveform of the terminal voltage Vsu (= -iu × Rsu) generated by the current flowing through the U-phase shunt resistor 11a. iu is the phase current flowing through the switching element 9d of the lower U-phase arm, and since the direction of flow from the inverter 3 to the motor 8 is considered positive, the phase current iu is denoted by a "-" sign. 【0037】When the switching element 9d of the lower arm is in the off state, the phase current iu is supplied through the switching element 9a of the upper arm. The shunt resistor 11a is connected between the switching element 9d of the lower arm and the DC bus 30b on the low potential side. Therefore, no current flows through the shunt resistor 11a, and the terminal voltage Vsu of the shunt resistor 11a becomes 0V, making it impossible to detect the phase current iu. On the other hand, when the switching element 9d of the lower arm is in the on state, the terminal voltage Vsu of the shunt resistor 11a is "-iu × Rsu", and the phase current iu can be detected by calculating the phase current iu from the terminal voltage Vsu and the shunt resistance value Rsu. 【0038】 As shown in Figure 4, the waveform of the drive signal Sup is a pulsed voltage waveform. Therefore, as shown in Figure 5, the voltage Vsu across the terminals of the shunt resistor 11a exhibits a phenomenon called ringing, where the voltage waveform oscillates due to the influence of parasitic capacitance and parasitic inductance of the circuit, occurring at the rising and falling ends of the voltage. To eliminate the effect of error voltage due to ringing, the control device 5 does not detect current at the rising end, but detects the phase current iu by performing AD conversion on the voltage value of the terminal voltage Vsu after the ringing has subsided. In Figure 5, td indicates the time from the point where the voltage waveform rises due to the input of the drive signal Sup to the point where AD conversion is performed for current detection. Since current detection cannot be performed during this td period, td can be said to represent the limit value of the current detection time. Note that although the current detection of the U phase has been explained here, the same applies to the V phase and W phase. 【0039】To perform high-precision motor control, it is desirable to control all three phases using the same current value at the same time. For this reason, the power converter 100 according to Embodiment 1 simultaneously detects the phase currents iu, iv, and iw flowing through each phase of the motor 8. As described above, the power converter 100 according to Embodiment 1 simultaneously detects the phase currents iu, iv, and iw flowing through each phase of the motor 8, and therefore performs current detection at the timing when all of the switching elements 9d to 9f of the lower arm are turned on, that is, at the timing when the zero voltage vector V0 is output. On the other hand, as the output voltage vector Vout increases, the output time of the actual voltage vectors V1 to V6 increases, and the output time of the zero voltage vector V0 decreases. When the output time of the zero voltage vector V0 decreases and approaches the current detection time limit td mentioned above, the accuracy of current detection deteriorates. Furthermore, when the output time of the zero voltage vector V0 falls below the current detection time limit td, it becomes difficult to ensure the detection accuracy of the phase currents iu, iv, and iw. 【0040】 Therefore, the control device 5 of Embodiment 1 performs the control shown below. Figure 6 is a flowchart illustrating the processing flow performed in the control device 5 according to Embodiment 1. 【0041】 The phase voltage output ratio calculation unit 17 calculates the modulation rate M based on the dq-axis voltage command values ​​Vd*, Vq* and the bus voltage Vdc (step S10). In this paper, the modulation rate M is defined as the ratio of the output voltage to the voltage amplitude that the inverter 3 can output as a sinusoidal wave of the three-phase line voltage. Since the modulation rate M is calculated using the amplitude of the output voltage vector Vout calculated by the dq-axis voltage command values ​​Vd*, Vq* and the detected bus voltage Vdc, it changes due to pulsations in the bus voltage Vdc, torque pulsations of the motor 8, etc. 【0042】 The control device 5 compares the modulation rate M calculated in step S10 with a preset modulation rate M0 (step S11). In this paper, the modulation rate M0 is appropriately referred to as the "first modulation rate". 【0043】When the modulation rate M is less than the modulation rate M0 (step S11, No), the control device 5 determines DV0 and DV7 such that the value of the zero-voltage vector output ratio DV7 / DV0, which is the ratio of DV7 to DV0, becomes 1 (step S12). Here, DV0 is the ratio of the output time of the zero-voltage vector V0 to the carrier period tfc, that is, the ratio of the time when all the switching elements 9d to 9f of the lower arm are turned on to the carrier period tfc. Also, DV7 is the ratio of the output time of the zero-voltage vector V7 to the carrier period tfc, that is, the ratio of the time when all the switching elements 9a to 9c of the upper arm are turned on to the carrier period tfc. In this article, DV0 is appropriately referred to as the "first output time ratio", and DV7 is appropriately referred to as the "second output time ratio". Also, in this article, the time when all the switching elements 9a to 9c of the upper arm are turned on is appropriately referred to as the "first time", and the time when all the switching elements 9d to 9f of the lower arm are turned on is appropriately referred to as the "second time". After the process of step S12 is completed, the process proceeds to step S14. 【0044】 Also, in step S11, when the modulation rate M is greater than or equal to the modulation rate M0 (step S11, Yes), the control device 5 determines the first output time ratio DV0 and the second output time ratio DV7 such that the value of the zero-voltage vector output ratio DV7 / DV0 becomes a value other than 1 (step S13). After the process of step S13 is completed, the process proceeds to step S14. 【0045】 The control device 5 calculates the phase voltage output time ratios DVu, Dvv, and Dvw based on the first output time ratio DV0 and the second output time ratio DV7 determined in step S12 or step S13 (step S14). After the process of step S14, the processing flow of FIG. 6 ends. Note that the processing flow of FIG. 6 is started and executed each time the modulation rate M is changed. 【0046】 FIG. 7 is a diagram for explaining the first example of the variation of the zero-voltage vector output ratio change in the first embodiment. On the upper side of FIG. 7, the change in the first output time ratio DV0 with respect to the modulation rate M is shown, and on the lower side of FIG. 7, the change in the second output time ratio DV7 with respect to the modulation rate M is shown. 【0047】 Figure 7 shows an example of setting the modulation ratio M0 shown in Figure 6 to M1. Here, the modulation ratio M1 is the modulation ratio when the first output ratio DV0 and the second output ratio DV7 become the ratio td / tfc of the current detection time limit value td to the carrier period tfc, that is, when DV0 = DV7 = td / tfc. 【0048】 In Figure 7, the slope of the straight line of the first output ratio DV0 up to the modulation ratio M1 is equal to the slope of the straight line of the second output ratio DV7, which corresponds to setting the zero voltage vector output ratio DV7 / DV0 to DV7 / DV0 = 1 in step S12 of the flowchart in Figure 6. That is, in the first example, in the section where the modulation ratio M is from 0 to M1, the control device 5 decreases the first output ratio DV0 in accordance with the increase of the modulation ratio M, and decreases the second output ratio DV7 so that the decrease rate of decreasing the first output ratio DV0 is equal to the decrease rate of decreasing the second output ratio DV7. 【0049】 Also, in the first example, in the section where the modulation ratio M is M1 or more, the control device 5 sets the first output ratio DV0 to a constant value and decreases the second output ratio DV7 in accordance with the increase of the modulation ratio M. This corresponds to setting the zero voltage vector output ratio DV7 / DV0 to DV7 / DV0 ≠ 1 in step S13 of the flowchart in Figure 6. 【0050】If the first output ratio DV0 falls below the ratio td / tfc, it becomes difficult to ensure the detection accuracy of the phase currents iu, iv, and iw. Therefore, after the modulation rate M becomes M1 = td / tfc, the first output ratio DV0 is kept at a constant value so as not to fall below the ratio td / tfc. In Figure 7, M2 is the modulation rate at which the second output ratio DV7 becomes 0. In the interval where the modulation rate M is M1 or greater and M2 or less, the control device 5 maintains the first output ratio DV0 at a constant value of the ratio td / tfc, while decreasing the second output ratio DV7 as the modulation rate M increases. In order to ensure the detection accuracy of the phase currents iu, iv, and iw while maintaining the zero voltage vector output ratio DV7 / DV0 = 1, the upper limit of the modulation rate M becomes the modulation rate M1. In contrast, as shown in Figure 7, by maintaining the first output ratio DV0 at the ratio td / tfc while decreasing the second output ratio DV7, the upper limit of the modulation rate M can be expanded to the modulation rate M2. 【0051】 Figure 7 shows an example where the shunt resistor 11 is placed between the low-potential DC bus 30b and the switching element 9 on the lower arm. However, if the shunt resistor 11 is placed between the high-potential DC bus 30a and the switching element 9 on the upper arm, current detection is performed when the zero voltage vector V7 is output, so the relationship between the first output ratio DV0 and the second output ratio DV7 should be reversed. That is, in the section where the modulation rate M is M1 or higher and M2 or lower, the control device 5 maintains the second output ratio DV7 at a constant ratio td / tfc, while decreasing the first output ratio DV0 as the modulation rate M increases. 【0052】 Figure 8 illustrates a second example of the variation in changing the zero voltage vector output ratio in Embodiment 1. Similar to Figure 7, the upper part of Figure 8 shows the change in the first output ratio DV0 with respect to the modulation rate M, and the lower part of Figure 8 shows the change in the second output ratio DV7 with respect to the modulation rate M. 【0053】In Figure 8, the position of modulation index M1 is the same as in Figure 7. Also, in the interval from modulation index M 0 to M1, the rate of decrease for the first output ratio DV0 and the rate of decrease for the second output ratio DV7 are equal, just as in Figure 7. On the other hand, in Figure 8, even in the interval from modulation index M1 to M2, the rate of decrease for the first output ratio DV0 and the rate of decrease for the second output ratio DV7 are equal. Therefore, in the second example shown in Figure 8, the rate of decrease for the first output ratio DV0 and the rate of decrease for the second output ratio DV7 are equal in the entire interval from modulation index M 0 to M2. 【0054】 To achieve the control shown in Figure 8, the phase voltage output ratio calculation unit 17 determines a shift amount ΔD at modulation rate M1 such that the first output ratio DV0 at modulation rate M2 is DV0 = td / tfc. When the modulation rate M reaches modulation rate M1, the phase voltage output ratio calculation unit 17 increases the first output ratio DV0 by the shift amount ΔD, and conversely decreases the second output ratio DV7 by the shift amount ΔD. 【0055】 In the second example shown in Figure 8, the rate of reduction for the first output ratio DV0 and the rate of reduction for the second output ratio DV7 are equal throughout the entire interval between modulation rate M 0 and M2. Therefore, even if the modulation rate M changes, it is not necessary to calculate the reduction rates for both individually, which has the advantage of reducing the computational load compared to the first example shown in Figure 7. 【0056】 Furthermore, in the second example shown in Figure 8, the first and second output ratios DV0 and DV7 are modified so that the sum of the first and second output ratios DV0 remains unchanged throughout the entire interval where the modulation rate M is between 0 and M2. If the sum of the first and second output ratios DV0 and DV7 does not change, the magnitudes of the actual voltage vectors Vact1 and Vact2 also remain unchanged, which has the advantage of suppressing the occurrence of voltage errors. 【0057】Figure 9 illustrates a third example of the variation in changing the zero voltage vector output ratio in Embodiment 1. Similar to Figures 7 and 8, the upper part of Figure 9 shows the change in the first output ratio DV0 with respect to the modulation rate M, and the lower part of Figure 9 shows the change in the second output ratio DV7 with respect to the modulation rate M. 【0058】 Figure 9 shows an example where the modulation rate M0 shown in Figure 6 is set to 0. When the modulation rate M0 = 0, the determination result in step S11 in Figure 6 is always "Yes". Therefore, the process in step S12 is not performed, and the process in step S13 is always performed. In Figure 9, the reduction rate that reduces the first output ratio DV0 and the reduction rate that reduces the second output ratio DV7 are equal throughout the entire interval from modulation rate M 0 to M2, just as in Figure 8. Therefore, in the third example, as in the second example, two advantages can be enjoyed: the computational load is reduced and the occurrence of voltage errors can be suppressed. In addition, in the third example, since control switching is unnecessary, the burden on the control system can be reduced. 【0059】 Furthermore, in Figure 9, unlike Figure 8, the first output ratio DV0 and the second output ratio DV7 change continuously throughout the entire interval from modulation rate M 0 to M2. In the third example, unlike the second example, the first output ratio DV0 and the second output ratio DV7 do not change abruptly, thus enabling smooth control. 【0060】 Figure 10 is a block diagram showing an example of a hardware configuration that realizes the functions of the control device 5 according to Embodiment 1. In order to realize some or all of the functions of the control device 5, the configuration can include a processor 91 that performs calculations and a memory 92 in which the program read by the processor 91 is stored, as shown in Figure 10. 【0061】The processor 91 is an example of a calculation means. The processor 91 may be a calculation means referred to as a microprocessor, microcomputer, CPU (Central Processing Unit), or DSP (Digital Signal Processor). The memory 92 may also include examples of non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (Registered Trademark) (Electrically EPROM), magnetic disks, flexible disks, optical disks, compact disks, minidiscs, and DVDs (Digital Versatile Discs). 【0062】 Memory 92 holds a program that executes the functions of the control device 5. The processor 91 receives and stores necessary information in memory 92, executes the program stored in memory 92, and references the data and tables stored in memory 92 to perform the processing by the control device 5 described above. The calculation results of the processor 91 can be stored in memory 92. 【0063】 As described above, the control device provided in the power converter according to Embodiment 1 changes a first time, which is the time it takes to turn on all three switching elements on the side connected to the shunt resistor, according to the modulation rate of the voltage command value, and determines the first time such that in the interval where the modulation rate is above a preset first modulation rate, the first time does not fall below the limit value of the current detection time in the current detector. According to the power converter according to Embodiment 1, even in the interval where the modulation rate is above the first modulation rate, the first time for turning on all three switching elements on the side connected to the shunt resistor does not fall below the limit value of the current detection time, so that the accuracy of current detection is ensured while suppressing the limitation of the output voltage of the inverter. 【0064】The control device can determine the first and second output time ratios such that the first output time ratio, which is the ratio of the first time to the carrier period during which all three switching elements on the side to which the shunt resistor is connected are turned on, and the second output time ratio, which is the ratio of the second time to the carrier period during which all three switching elements on the side to which the shunt resistor is not connected are turned on, are in a 1:1 ratio. The control device may also set the first output time ratio to a constant value in the interval where the modulation rate is equal to or greater than the first modulation rate, and decrease the second output time ratio as the modulation rate increases. 【0065】 The control device may, in the interval where the modulation rate is equal to or greater than the first modulation rate, decrease the first output ratio in accordance with the increase in the modulation rate, and also decrease the second output ratio so that the rate at which the first output ratio is decreased is equal to the rate at which the second output ratio is decreased. When the modulation rate reaches the first modulation rate, the control device can change the second output ratio so that the sum of the first output ratio and the second output ratio does not change, by discretely changing the first output ratio. 【0066】 The control device may set the value of the first modulation rate to 0, and when it reduces the first output time ratio, which is the ratio of the first time to the carrier period during which all three switching elements on the side to which the shunt resistor is connected are turned on, and the second output time ratio, which is the ratio of the second time to the carrier period during which all three switching elements on the side to which the shunt resistor is not connected are turned on, as the modulation rate increases, it may determine the first output time ratio and the second output time ratio such that the rate at which the first output time ratio is reduced and the rate at which the second output time ratio is reduced are equal. 【0067】Embodiment 2. In Embodiment 1, the zero voltage vector output ratio DV7 / DV0 was changed based on a preset modulation rate M0, and the first output ratio DV0 and the second output ratio DV7 were changed in accordance with the change in modulation rate M, thereby changing the output time of the zero voltage vectors V0 and V7. This control suppressed the limitation of the output voltage of the inverter 3 while ensuring the accuracy of current detection by the shunt resistor 11. In Embodiment 2, the output time of the zero voltage vectors V0 and V7 was changed in accordance with the on time of the drive signals Sup, Svp, Swp, Sun, Svn, and Swn. This control suppressed the output voltage error of the inverter 3 that may occur due to the response of the switching element 9. 【0068】 Figure 11 is a diagram illustrating the behavior of a switching element related to the control of the control device 5 according to Embodiment 2. The upper part of Figure 11 shows, as an example, the waveform of the drive signal Sup generated by the drive signal calculation unit 18. The lower part of Figure 11 shows the waveforms of the collector current Ic and the collector-emitter voltage Vce when the switching element 9 is driven by the drive signal Sup shown in the upper part. For the switching element 9 to perform switching operation in response to the drive signal Sup, a delay time occurs both when the drive signal Sup rises and when the drive signal Sup falls. This delay time is generally known as the turn-on time and the turn-off time. The lower part of Figure 11 shows the turn-on time ton and the turn-off time toff. 【0069】 Generally, when a narrow drive signal with an off time shorter than the turn-off time is input to a switching element, the current flowing through the switching element cannot be interrupted, potentially causing a leg short circuit between the upper and lower arm switching elements by driving the switching element on the opposite arm. For this reason, as mentioned above, a short-circuit prevention time called a dead time is provided for drive signals with a narrow off time to prevent the generation of pulses with a pulse width shorter than the turn-off time. 【0070】Furthermore, generally, when a narrow drive signal with an on-time shorter than the turn-on time is input to a switching element, the output voltage may be lower than the voltage that was originally intended to be output, or the output may not respond at all. In these cases, an error occurs in the inverter's output voltage. This error in the inverter's output voltage can negatively affect the stability of motor control. 【0071】 Therefore, the control device 5 according to Embodiment 2 performs the control shown below. Figure 12 is a flowchart illustrating the key points of the control in the control device 5 according to Embodiment 2. 【0072】 First, the drive signal calculation unit 18 calculates the drive signals Sup, Sun, Svp, Svn, Swp, and Swn using the method described above (step S20). The phase voltage output ratios DVu, DVv, and DVw used when generating the drive signals Sup, Sun, Svp, Svn, Swp, and Swn are calculated by the phase voltage output ratio calculation unit 17, as described in Embodiment 1. 【0073】 The drive signal calculation unit 18 determines whether the on-time of at least one of the drive signals Sup, Svp, and Swp for the switching elements 9a, 9b, and 9c of each phase upper arm is longer than the turn-on time ton (step S21). Note that the control in Embodiment 2 is based on the control in Embodiment 1. In Embodiment 1, control is performed to ensure current detection time, so the on-times of the drive signals Sun, Svn, and Swn that drive the switching elements 9d, 9e, and 9f of each phase lower arm are controlled to be longer than the turn-on time. For this reason, the determination process corresponding to step S21 is not performed for the drive signals Sun, Svn, and Swn. 【0074】 If the on-time of at least one of the drive signals Sup, Svp, and Swp is longer than the turn-on time ton (step S21, Yes), the processing flow in Figure 12 is terminated. Note that the processing flow in Figure 12 is started and executed each time the calculations for the drive signals Sup, Svp, Swp, Sun, Svn, and Swn are performed. 【0075】If the on-time of at least one of the drive signals Sup, Svp, and Swp is less than or equal to the turn-on time ton (step S21, No), the control device 5 changes the output times of the zero voltage vectors V0 and V7 (step S22). The process in step S22 is explained below. If the determination in step S21 is negative, the output time of the zero voltage vector V7 is basically changed. However, as explained in Embodiment 1, if the output time of the zero voltage vector V7 is changed so that the sum of the first output time ratio DV0 and the second output time ratio DV7 does not change, the output time of the zero voltage vector V0 will inevitably also be changed. Therefore, in step S22, the process changes not only the output time of the zero voltage vector V7 but also the output time of the zero voltage vector V0. 【0076】 Figure 13 is a diagram illustrating the operation when the control according to Embodiment 2 is not implemented. Figure 14 is a diagram illustrating the operation when the control according to Embodiment 2 is implemented. Figures 13 and 14 are examples of operating waveforms when the on-time of the drive signal Sup is less than or equal to the turn-on time ton, and show the time-varying waveform of the carrier signal Cs, the time-varying waveforms of the drive signals Sup, Svp, Swp, Sun, Svn, Swn, and the transition of the output time of the voltage vector. Note that the short-circuit prevention time is indicated by hatching in the output time of the voltage vector. 【0077】 When the inverter 3 is controlled at a high modulation rate, one of the phase voltage output ratios DVu, DVv, and DVw approaches the upper or lower limit of the carrier signal Cs. Figures 13 and 14 show an example where the U-phase voltage output ratio DVu is close to the lower limit of the carrier signal Cs. In such an example, the drive signal Sup generated by the magnitude relationship between the U-phase voltage output ratio DVu and the carrier signal Cs has a shorter on-time, which is shorter than the turn-on time of the switching element 9. Figure 13 shows how a narrow-width drive signal Sup is generated such that its on-time is shorter than the turn-on time of the switching element 9. 【0078】When control based on the flowchart in Figure 12, as described above, is implemented, the output time of the zero voltage vector V7 becomes 0, and the narrow-width drive signal Sup disappears. As a result, the drive signal Sup becomes a permanently off signal, and the zero voltage vector V7 also disappears. The period of the zero voltage vector V7 is changed to a short-circuit prevention time, and the period that was the zero voltage vector V7 is distributed to the zero voltage vector V0, widening the width of the zero voltage vector V0. As mentioned above, the sum of the output time of the zero voltage vector V0 and the output time of the zero voltage vector V7 remains unchanged before and after the control. Also, since the sum of the output times of the zero voltage vectors V0 and V7 remains unchanged, the output times of the actual voltage vectors V4 and V5 also remain unchanged. This makes it possible to suppress the output voltage error of the inverter 3 that may occur due to the response of the switching element 9. 【0079】 As described above, the control device provided in the power converter according to Embodiment 2 changes the second time, which is the time it takes to turn on all three switching elements on the side not connected to the shunt resistor, based on the on time of the drive signal, so that the sum of the first time and the second time remains unchanged. According to the power converter according to Embodiment 2, the second time is changed so that the output time of the actual voltage vector remains constant, making it possible to suppress the output voltage error of the inverter that may occur due to the response of the switching elements. In addition, if the on time of the drive signal is shorter than the turn-on time of the switching elements, the control device basically changes the on time of the drive signal to the off time. However, if the on time of the drive signal is slightly shorter than the turn-on time of the switching elements, the on time of the drive signal may be changed so that the on time of the drive signal is longer than the turn-on time of the switching elements. Even in this way, it is possible to avoid the generation of a narrow-width drive signal. 【0080】 Embodiment 3. Figure 15 shows an example of the configuration of an air conditioner 300 according to Embodiment 3. The air conditioner 300 is an example of a refrigeration cycle device and includes the power converter 100 and motor drive device 200 described in Embodiments 1 and 2. 【0081】The air conditioner 300 comprises a compressor 301, a four-way valve 302, an outdoor heat exchanger 303, an expansion mechanism 304, and an indoor heat exchanger 305. These components—compressor 301, four-way valve 302, outdoor heat exchanger 303, expansion mechanism 304, and indoor heat exchanger 305—are connected via a refrigerant pipe 306 to form a refrigeration cycle. 【0082】 The compressor 301 comprises a compression mechanism 309 for compressing the refrigerant and a motor 310 for operating the compression mechanism 309. The motor drive unit 200 operates the compression mechanism 309 by rotating the motor 310, thereby compressing the refrigerant and circulating it within the refrigeration cycle. 【0083】 The air conditioner 300 circulates air with respect to the outdoor heat exchanger 303 using an outdoor fan 307 to perform heat exchange of the air. The air conditioner 300 also circulates air with respect to the indoor heat exchanger 305 using an indoor fan 308 to perform heat exchange of the air. 【0084】 The outdoor fan 307 is equipped with a power converter 101 and a drive unit 201 as a drive source for blowing air, and the indoor fan 308 is equipped with a power converter 102 and a drive unit 202 as a drive source for blowing air. Here, the power converter 101 and the power converter 102 can be configured as power converters equipped with the technology described in Embodiment 1 and Embodiment 2. 【0085】 In the air conditioner 300 according to Embodiment 3, at least one of the power converter 100, power converter 101, and power converter 102 is configured as a power converter equipped with the technology described in Embodiments 1 and 2, so that the effects obtained in Embodiments 1 and 2 can be enjoyed. As a result, the air conditioner 300 according to Embodiment 3 can obtain effects such as an expanded operating range and improved cooling and heating capacity. 【0086】In Embodiment 3, an example was shown in which the power converter 100 and motor drive unit 200 described in Embodiments 1 and 2 were applied to an air conditioner 300. However, the power converter 100 and motor drive unit 200 described in Embodiments 1 and 2 can also be applied to products equipped with a refrigeration cycle, such as refrigerators, freezers, and heat pump water heaters. 【0087】 Furthermore, the configurations shown in the above embodiments are merely examples, and it is possible to combine them with other known technologies, combine different embodiments, and omit or modify parts of the configuration without departing from the gist of the invention. 【0088】 1 AC power supply, 2 converter, 3 inverter, 4 current detector, 5 control device, 6 reactor, 7 capacitor, 8, 310 motor, 9, 9a, 9b, 9c, 9d, 9e, 9f switching element, 10, 10a, 10b, 10c, 10d, 10e, 10f freewheeling diode, 11, 11a, 11b, 11c shunt resistor, 12, 12a, 12b, 12c voltage detector, 13a, 13b, 13c, 13d diode, 14 current calculation unit, 15 coordinate transformation unit, 16 voltage command value calculation unit, 17 phase voltage output ratio calculation unit, 18 drive signal calculation unit, 19 estimated angle calculation unit, 20 carrier signal generation unit, 30a, 30b DC bus, 91 processor, 92 memory, 100, 101, 102 Power converter, 150 DC power supply, 200 Motor drive unit, 201, 202 Drive unit, 300 Air conditioner, 301 Compressor, 302 Four-way valve, 303 Outdoor heat exchanger, 304 Expansion mechanism, 305 Indoor heat exchanger, 306 Refrigerant pipe, 307 Outdoor fan, 308 Indoor fan, 309 Compression mechanism.

Claims

1. A power conversion device for converting DC power to desired AC power and supplying it to a load, comprising: an inverter configured by connecting three phases in parallel between a high-potential DC bus and a low-potential DC bus, each consisting of a single-phase leg in which the switching elements of an upper arm and a lower arm are connected in series; a current detector that detects the phase current flowing through each phase of the load by detecting the voltage generated across the shunt resistors, with at least two phases of shunt resistors positioned on either the high-potential DC bus and the switching elements of the upper arm, or the low-potential DC bus and the switching elements of the lower arm; and a control device that generates drive signals to determine the on-time and off-time of the switching elements of the upper arm and the lower arm, respectively, based on a voltage command value and a carrier signal. The control device changes a first time, which is the time for turning on all three switching elements on the side to which the shunt resistor is connected, according to the modulation rate of the voltage command value, and determines the first time such that the first time does not fall below the limit value of the current detection time in the current detector in the interval where the modulation rate is equal to or greater than a preset first modulation rate.

2. In a section where the modulation rate is less than the first modulation rate, the control device determines the first output time ratio and the second output time ratio such that the ratio of the first time, which is the ratio of the time to which all three switching elements on the side to which the shunt resistor is connected, is turned on to the carrier period, which is one period of the carrier signal, and the ratio of the second time, which is the ratio of the time to which all three switching elements on the side to which the shunt resistor is not connected, is turned on to the carrier period, in a 1:1 ratio.

3. In a section where the modulation rate is equal to or greater than the first modulation rate, the control device sets the first output ratio to a constant value and decreases the second output ratio in accordance with the increase in the modulation rate, as described in claim 2.

4. In a section where the modulation rate is equal to or greater than the first modulation rate, the control device reduces the first output ratio in accordance with the increase in the modulation rate, and reduces the second output ratio such that the rate of reduction for reducing the first output ratio is equal to the rate of reduction for reducing the second output ratio, as described in claim 2.

5. The power conversion device according to claim 4, wherein the control device discretely changes the first output ratio when the modulation rate reaches the first modulation rate, and changes the second output ratio so that the sum of the first output ratio and the second output ratio does not change.

6. The power conversion device according to claim 1, wherein the control device sets the value of the first modulation rate to 0, and when the first output time ratio, which is the ratio of the first time to which all three switching elements on the side to which the shunt resistor is connected are turned on, to the carrier period, which is one period of the carrier signal, and the second output time ratio, which is the ratio of the second time to which all three switching elements on the side to which the shunt resistor is not connected are turned on, are reduced in accordance with the increase in the modulation rate, the control device determines the first output time ratio and the second output time ratio such that the rate at which the first output time ratio is reduced and the rate at which the second output time ratio is reduced are equal.

7. The power conversion device according to claim 1, wherein the control device changes a second time, which is the time it takes to turn on all three switching elements on the side not connected to the shunt resistor, based on the ON time of the drive signal, such that the sum of the first time and the second time remains unchanged.

8. The power conversion device according to claim 7, wherein the control device changes the on time of the drive signal to an off time if the on time of the drive signal is shorter than the turn-on time of the switching element, or changes the on time so that the on time of the drive signal is longer than the turn-on time of the switching element.

9. A motor drive device comprising a power conversion device according to any one of claims 1 to 8.

10. A refrigeration cycle apparatus comprising a power conversion device according to any one of claims 1 to 8.

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