Multilayer ceramic capacitor
The multilayer ceramic capacitor design with a first resin electrode layer and plating layer addresses stress-induced cracking by buffering external electrode stress, enhancing crack resistance and moisture resistance.
WO2026126341A1PCT designated stage Publication Date: 2026-06-18MURATA MFG CO LTD
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- MURATA MFG CO LTD
- Filing Date
- 2024-12-10
- Publication Date
- 2026-06-18
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Figure JP2024043649_18062026_PF_FP_ABST
Abstract
Provided is a two-terminal multilayer ceramic capacitor in which crack formation can be suppressed. An internal electrode has a first internal electrode that is connected to a first external electrode 3A and is not connected to a second external electrode 3B, and a second internal electrode that is connected to the second external electrode 3B and is not connected to the first external electrode 3A. The first external electrode 3A has: a first base electrode layer 31A of the first external electrode disposed on a first surface F1; a second base electrode layer 32A of the first external electrode disposed on the first surface F1; a first resin electrode layer 34A disposed over the first base electrode layer 31A of the first external electrode, the first surface F1, and the second base electrode layer 32A of the first external electrode; and a first plating layer 36A disposed on the first resin electrode layer 34A. The first surface F1 has a first region 21, which is the region between the region where the first base electrode layer 31A of the first external electrode is disposed and the region where the second base electrode layer 32A of the first external electrode is disposed, and which is the region where the first resin electrode layer 34A is disposed. The first region 21 overlaps, in a lamination direction T, the central part in a second direction W of a multilayer body 2.
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