Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component capable of ensuring mechanical strength of the multilayer ceramic electronic component while ensuring adhesion to mold resin.　A multilayer ceramic electronic component 10 according to the present invention comprises: a multilayer body 12 that includes a plurality of laminated ceramic layers 14 and a plurality of internal electrode layers 16 laminated on the ceramic layers 14, and has a first main surface 12a and a second main surface 12b opposing each other in a lamination direction, a first surface 12c and a second surface 12d opposing each other in a first direction orthogonal to the lamination direction, and a third surface 12e and a fourth surface 12f opposing each other in a second direction orthogonal to the lamination direction and the first direction; and at least four external electrodes 30 that are disposed so as to cover the multilayer body 12 and are connected to the internal electrode layers 16. The first surface 12c to the fourth surface 12f have uncovered regions 40 that are not covered with the external electrodes 30, and the surface roughness of the uncovered regions 40 is higher than the surface roughness of the first main surface 12a.

Description

Multilayer ceramic electronic component 【0001】 This invention relates to a multilayer ceramic electronic component. 【0002】 Recently, centered around mobile device products, the low-impedance of electronic circuit lines has been accelerating, and the miniaturization and high capacitance of multilayer ceramic capacitors for decoupling applications have been progressing. Regarding the miniaturization of multilayer ceramic capacitors, from the perspective of mountability, which is one of the necessary functions of multilayer ceramic capacitors, a decrease in the adhesion between the chip and the substrate due to a reduction in the bonding area between the mounting land and the chip has become one of the concerns. To compensate for this, the use of resin molding in small multilayer ceramic capacitors is increasing. The effect of improving the adhesion by this resin molding is an effect obtained through the adhesion between the laminate and the resin, and if the adhesion cannot be obtained, the effect cannot be obtained. In particular, when many external electrodes are arranged on the laminate, it is often difficult to obtain the adhesion. 【0003】 As a multilayer ceramic capacitor with many external electrodes arranged, for example, there is a through-type multilayer ceramic capacitor. This through-type multilayer ceramic capacitor generally includes a ceramic substrate (laminate) having an outer surface composed of a first and a second main surface facing each other, a first and a second side surface facing each other, and a first and a second end surface facing each other. Inside the ceramic substrate, a plurality of first internal electrodes and second internal electrodes are alternately arranged in the stacking direction. And both ends of the first internal electrode are led out to the first end surface and the second end surface, and are respectively connected to the first external electrode and the second external electrode. Also, both ends of the second internal electrode are led out to the first side surface and the second side surface, and are respectively connected to the third external electrode and the fourth external electrode. 【0004】 Japanese Patent Application Laid-Open No. 2003-022932 【0005】For such multilayer ceramic capacitors, it is necessary to increase the surface roughness of the laminate in order to improve the adhesion between the resin and the laminate. However, simply increasing the surface roughness of the laminate tends to create localized stress concentration on the surface of the laminate, which can cause failures such as bending cracks due to mechanical stress in multilayer ceramic capacitors. 【0006】 Therefore, the main objective of this invention is to provide a multilayer ceramic electronic component that ensures adhesion to the mold resin while also ensuring the mechanical strength of the multilayer ceramic electronic component. 【0007】 The multilayer ceramic electronic component according to this invention comprises a laminate having a plurality of stacked ceramic layers and a plurality of internal electrode layers stacked on the ceramic layers, the laminate having a first main surface and a second main surface facing each other in the stacking direction, a first surface and a second surface facing each other in a first direction perpendicular to the stacking direction, and a third surface and a fourth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, and at least four or more external electrodes arranged to cover the laminate and connected to the internal electrode layers, wherein the first to fourth surfaces have uncovered regions that do not cover the external electrodes, and the surface roughness of the uncovered regions is rougher than the surface roughness of the first main surface. 【0008】According to the multilayer ceramic electronic component of this invention, the first to fourth surfaces have uncoated regions that do not cover the external electrodes, and the surface roughness of the uncoated regions is rougher than the surface roughness of the first main surface. Therefore, in the multilayer ceramic electronic component, cracks caused by external stress on the mounting surface are suppressed, while adhesion with the molding resin on the side surfaces of the multilayer ceramic electronic component excluding the main surface is ensured, and stable bonding strength after mounting can be ensured. In other words, since the adhesion between the resin molding the multilayer ceramic electronic component and the multilayer ceramic electronic component is improved, bonding strength between the multilayer ceramic electronic component and the mounting substrate after mounting can be ensured. Furthermore, since peeling of the resin molding the multilayer ceramic electronic component starts in the uncoated regions, adhesion can be further improved by making the surface roughness of the uncoated regions greater than the surface roughness of the first main surface. 【0009】 According to this invention, it is possible to provide a multilayer ceramic electronic component that ensures adhesion to the mold resin while also ensuring the mechanical strength of the multilayer ceramic electronic component. 【0010】 The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings. 【0011】This diagram shows an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the first embodiment of this invention, where (a) is an external perspective view from one direction and (b) is an external perspective view from the other direction. This is a top view showing an example of a multilayer ceramic capacitor according to the first embodiment of this invention. This is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of this invention. This is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of this invention. This is a cross-sectional view along line V-V in Figure 1. This is a cross-sectional view along line VI-VI in Figure 1. This is a cross-sectional view along line VII-VII in Figure 4. This is a cross-sectional view along line VIII-VIII in Figure 4. This is a diagram illustrating a method for manufacturing a multilayer ceramic capacitor according to the present invention. This diagram shows an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the second embodiment of this invention, where (a) is an external perspective view from one direction and (b) is an external perspective view from the other direction. This is a top view showing an example of a multilayer ceramic capacitor according to the second embodiment of this invention. This is a front view showing an example of a multilayer ceramic capacitor according to the second embodiment of this invention. This is a side view showing an example of a multilayer ceramic capacitor according to the second embodiment of this invention. This shows an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the third embodiment of this invention, where (a) is an external perspective view from one direction and (b) is an external perspective view from the other direction. This is a top view showing an example of a multilayer ceramic capacitor according to the third embodiment of this invention. This is a front view showing an example of a multilayer ceramic capacitor according to the third embodiment of this invention. This is a side view showing an example of a multilayer ceramic capacitor according to the third embodiment of this invention. This shows an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the fourth embodiment of this invention, where (a) is an external perspective view from one direction and (b) is an external perspective view from the other direction. This is a top view showing an example of a multilayer ceramic capacitor according to the fourth embodiment of this invention. This is a front view showing an example of a multilayer ceramic capacitor according to the fourth embodiment of this invention. This is a side view showing an example of a multilayer ceramic capacitor according to the fourth embodiment of this invention. 【0012】 1. Multilayer Ceramic Capacitor As an example of a multilayer ceramic electronic component according to an embodiment of this invention, a multilayer ceramic capacitor will be described. The multilayer ceramic capacitor 10 is a through-type multilayer ceramic capacitor (a three-terminal type multilayer ceramic capacitor). 【0013】 Figure 1 shows an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the first embodiment of the present invention, where (a) is an external perspective view from one direction and (b) is an external perspective view from the other direction. Figure 2 is a top view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 3 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 4 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 5 is a cross-sectional view taken along line V-V in Figure 1. Figure 6 is a cross-sectional view taken along line VI-VI in Figure 1. Figure 7 is a cross-sectional view taken along line VII-VII in Figure 4. Figure 8 is a cross-sectional view taken along line VIII-VIII in Figure 4. 【0014】 As shown in Figures 1 to 8, the multilayer ceramic capacitor 10 includes, for example, a laminate 12 and an external electrode 30. 【0015】 The laminate 12 has a plurality of stacked ceramic layers 14 and a plurality of internal electrode layers 16 stacked on the ceramic layers 14. The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b. Details of the first internal electrode layer 16a and the second internal electrode layer 16b will be described later. 【0016】 The laminate 12 has a first main surface 12a and a second main surface 12b facing the stacking direction x, a first surface 12c and a second surface 12d facing a first direction y perpendicular to the stacking direction x, and a third surface 12e and a fourth surface 12f facing a second direction z perpendicular to the stacking direction x and the first direction y. 【0017】The laminate 12 has a rectangular parallelepiped shape, and it is preferable that the corners and edges of the laminate 12 are rounded. The corners are the parts where three faces of the laminate 12 intersect, and the edges are the parts where two faces of the laminate 12 intersect. In addition, some or all of the first main surface 12a and the second main surface 12b, the first surface 12c and the second surface 12d, and the third surface 12e and the fourth surface 12f may have irregularities or other features formed on them. 【0018】 The first main surface 12a or the second main surface 12b is preferably the substrate mounting surface. The surface roughness Ra1 of the first main surface 12a or the second main surface 12b is preferably 0.053 μm or more and 0.115 μm or less. 【0019】 Here, the dimension of the laminate 12 in the first direction y is denoted as the l dimension, the dimension of the laminate 12 in the second direction z is denoted as the w dimension, and the dimension of the laminate 12 in the stacking direction x is denoted as the t dimension. It is preferable that the t dimension of the laminate 12 is shorter than the w dimension. It is preferable that the l dimension of the laminate 12 is longer than the w dimension. It is preferable that the l dimension of the laminate 12 is 0.01 mm or more and 0.70 mm or less. It is preferable that the w dimension of the laminate 12 is 0.05 mm or more and 0.40 mm or less. 【0020】 The laminate 12 includes a volume-forming portion 18, a first outer layer portion 20a located on the side of the first main surface 12a, and a second outer layer portion 20b located on the side of the second main surface 12b, which are arranged to sandwich the volume-forming portion 18 in the stacking direction x. 【0021】 In the capacitance forming section 18, a first internal electrode layer 16a and a second internal electrode layer 16b are alternately stacked via a ceramic layer 14. 【0022】The first outer layer 20a is located on the side of the first main surface 12a of the laminate 12 and is an aggregate of multiple ceramic layers 14 located between the first main surface 12a and the volume-forming portion 18 closest to the first main surface 12a. The second outer layer 20b is located on the side of the second main surface 12b of the laminate 12 and is an aggregate of multiple ceramic layers 14 located between the second main surface 12b and the volume-forming portion 18 closest to the second main surface 12b. Furthermore, the region sandwiched between the first outer layer 20a and the second outer layer 20b is the volume-forming portion 18. 【0023】 The volume-forming section 18 is positioned in the center in the stacking direction x. More specifically, in the stacking direction x connecting the first main surface 12a and the second main surface 12b, the center position of the laminate 12 and the center position of the volume-forming section 18 are approximately the same. 【0024】 As shown in Figure 6, the laminate 12 is located between the volume-forming portion 18 and the third surface 12e, and between the volume-forming portion 18 and the fourth surface 12f, and has side portions (W gaps) 22a and 22b of the laminate 12, including the first extension portion 27a and the second extension portion 27b of the second internal electrode layer 16b. 【0025】 Furthermore, as shown in Figure 5, the laminate 12 is located between the volume-forming portion 18 and the first surface 12c, and between the volume-forming portion 18 and the second surface 12d, and has ends (L-gap) 24a, 24b of the laminate 12 that include the first lead-out portion 26a and the second lead-out portion 26b of the first internal electrode layer 16a. 【0026】 The ceramic layer 14 can be made of a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the ceramic material. Alternatively, a material may be used in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds are added to the main components. 【0027】Furthermore, when a piezoelectric ceramic material is used for the ceramic layer 14, the multilayer ceramic electronic component functions as a piezoelectric component. Specific examples of piezoelectric ceramic materials include, for example, PZT (lead zirconate titanate) ceramic materials. Also, when a semiconductor ceramic material is used for the ceramic layer 14, the multilayer ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include, for example, spinel ceramic materials. Furthermore, when a magnetic ceramic material is used for the ceramic layer 14, the multilayer ceramic electronic component functions as an inductor element. When functioning as an inductor element, the internal electrode layer 16 becomes a coil-shaped conductor. Specific examples of magnetic ceramic materials include, for example, ferrite ceramic materials. 【0028】 The thickness of the ceramic layer 14 is preferably 0.10 μm or more and 5.00 μm or less. Furthermore, the number of laminated ceramic layers 14 is preferably 6 or more and 802 or less. Note that this number of ceramic layers 14 is the sum of the number of ceramic layers 14 in the volume forming section 18 and the number of ceramic layers 14 in the first outer layer section 20a and the second outer layer section 20b. 【0029】 (Internal electrode layer) The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b. 【0030】 The first internal electrode layer 16a is arranged on a plurality of ceramic layers 14. The first internal electrode layer 16a is also drawn out to a first surface 12c and a second surface 12d. 【0031】More specifically, as shown in Figure 7, the first internal electrode layer 16a extends between the first surface 12c and the second surface 12d of the laminate 12 and has a first opposing portion 25a located in its central part, a first leading portion 26a extending from the first opposing portion 25a and leading out to the first surface 12c of the laminate 12, and a second leading portion 26b extending from the first opposing portion 25a and leading out to the second surface 12d of the laminate 12. The first opposing portion 25a is located in the central part of the ceramic layer 14. The first leading portion 26a is exposed to the first surface 12c of the laminate 12, and the second leading portion 26b is exposed to the second surface 12d of the laminate 12. Therefore, the first internal electrode layer 16a is not exposed to the third surface 12e and the fourth surface 12f of the laminate 12. 【0032】 The shape of the first internal electrode layer 16a is not particularly limited, but it is preferably rectangular in plan view. The shapes of the first opposing portion 25a, the first leading portion 26a, and the second leading portion 26b of the first internal electrode layer 16a are also not particularly limited, but they are preferably rectangular in plan view. However, the corners may be rounded. 【0033】 The second internal electrode layer 16b is arranged on a plurality of ceramic layers 14. The second internal electrode layer 16b is also drawn out to the third surface 12e and the fourth surface 12f. The second internal electrode layer 16b is arranged on a ceramic layer 14 that is different from the ceramic layer 14 on which the first internal electrode layer 16a is arranged. 【0034】More specifically, as shown in Figure 8, the second internal electrode layer 16b extends between the third surface 12e and the fourth surface 12f of the laminate 12 and has a second opposing portion 25b located in its central part, a first extension portion 27a extending from the second opposing portion 25b and drawn out to the third surface 12e, and a second extension portion 27b extending from the second opposing portion 25b and drawn out to the fourth surface 12f. The second opposing portion 25b is formed in a rectangular shape so as to extend in the direction of the first surface 12c and in the direction of the second surface 12d. The second opposing portion 25b is located in the central part of the ceramic layer 14. The first extension portion 27a is exposed to the third surface 12e of the laminate 12, and the second extension portion 27b is exposed to the fourth surface 12f of the laminate 12. Therefore, the second internal electrode layer 16b is not exposed to the first surface 12c and the second surface 12d of the laminate 12. 【0035】 The shapes of the second opposing portion 25b, the first extension portion 27a, and the second extension portion 27b of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded. 【0036】 The first opposing portion 25a of the first internal electrode layer 16a and the second opposing portion 25b of the second internal electrode layer 16b are facing each other. In this embodiment, the first opposing portion 25a of the first internal electrode layer 16a and the second opposing portion 25b of the second internal electrode layer 16b face each other via the ceramic layer 14, thereby forming capacitance and exhibiting capacitor characteristics. 【0037】 The number of first internal electrode layers 16a is not particularly limited, but is preferably, for example, 2 to 400. Similarly, the number of second internal electrode layers 16b is not particularly limited, but is preferably, for example, 2 to 400. Therefore, the total number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 4 to 800. 【0038】The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.10 μm or more and 2.00 μm or less. The thickness of the second internal electrode layer 16b is also not particularly limited, but is preferably, for example, 0.10 μm or more and 2.00 μm or less. 【0039】 The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys. 【0040】 By including a Sn layer between the first internal electrode layer 16a and the second internal electrode layer 16b and the ceramic layer 14, electric field concentration at the interface between the internal electrode layer and the ceramic layer can be mitigated, leading to improved high-temperature load reliability. 【0041】 (External electrodes) External electrodes 30 are arranged on the first surface 12c and the second surface 12d, as well as the third surface 12e and the fourth surface 12f of the laminate 12. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d. 【0042】 The first external electrode 30a is positioned on the first surface 12c. The first external electrode 30a is also connected to the first internal electrode layer 16a. Furthermore, it may also be positioned on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the third surface 12e, and a portion of the fourth surface 12f. 【0043】 The second external electrode 30b is positioned on the second surface 12d. The second external electrode 30b is also connected to the first internal electrode layer 16a. Furthermore, it may also be positioned on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the third surface 12e, and a portion of the fourth surface 12f. 【0044】The third external electrode 30c is disposed on the third surface 12e. The third external electrode 30c is connected to the second internal electrode layer 16b. Further, the third external electrode 30c may include a first covering portion 30c1 that covers the second internal electrode layer 16b exposed on the third surface 12e, a first folded-back portion 30c2 formed in parallel with the second internal electrode layer 16b on the first main surface 12a, and a second folded-back portion 30c3 formed in parallel with the second internal electrode layer 16b on the second main surface 12b. By having the second folded-back portion 30c3, the electrical connection reliability with the mounting substrate can be further maintained. 【0045】 The fourth external electrode 30d is disposed on the fourth surface 12f. The fourth external electrode 30d is connected to the second internal electrode layer 16b. Further, the fourth external electrode 30d may include a second covering portion 30d1 that covers the second internal electrode layer 16b exposed on the fourth surface 12f, a third folded-back portion 30d2 formed in parallel with the second internal electrode layer 16b on the first main surface 12a, and a fourth folded-back portion 30d3 formed in parallel with the second internal electrode layer 16b on the second main surface 12b. By having the fourth folded-back portion 30d3, the electrical connection reliability with the mounting substrate can be further maintained. 【0046】 The first surface 12c to the fourth surface 12f have an uncovered region 40 that is not covered by the external electrode 30. The surface roughness Ra2 of the uncovered region 40 is greater than the surface roughness Ra1 of the first main surface 12a or the second main surface 12b. Preferably, the surface roughness Ra2 of the uncovered region 40 is 10% greater than the surface roughness Ra1 of the first main surface 12a or the second main surface 12b. Preferably, the surface roughness Ra2 of the uncovered region 40 is 0.0535 μm or more. 【0047】The surface roughness Ra1 of the first main surface 12a is obtained by scanning the center of the surface of the first main surface 12a along the first direction y using a shape analysis laser microscope (VK-X1000 manufactured by Keyence Corporation) and measuring the maximum height (Ra1). The surface roughness Ra2 of the non-coated region 40 can be obtained by scanning the center of the surface of the non-coated region 40 located on the third surface 12e along the first direction y and measuring the maximum height (Ra2). 【0048】 The external electrode 30 includes a base electrode layer 32 disposed on the surface of the laminate 12 and a plating layer 34 disposed so as to cover the base electrode layer 32. 【0049】 The base electrode layer 32 has a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d. 【0050】 The plating layer 34 has a first plating layer 34a, a second plating layer 34b, a third plating layer 34c, and a fourth plating layer 34d. 【0051】 In other words, the first external electrode 30a has the first base electrode layer 32a and the first plating layer 34a. The second external electrode 30b has the second base electrode layer 32b and the second plating layer 34b. The third external electrode 30c has the third base electrode layer 32c and the third plating layer 34c. The fourth external electrode 30d has the fourth base electrode layer 32d and the fourth plating layer 34d. 【0052】 The first base electrode layer 32a is disposed on the surface of the first surface 12c of the laminate 12 and is formed so as to extend from the first surface 12c and cover a part of each of the first main surface 12a, the second main surface 12b, the third surface 12e, and the fourth surface 12f. The second base electrode layer 32b is disposed on the surface of the second surface 12d of the laminate 12 and is formed so as to extend from the second surface 12d and cover a part of each of the first main surface 12a, the second main surface 12b, the third surface 12e, and the fourth surface 12f. Note that the first base electrode layer 32a may be disposed only on the surface of the first surface 12c of the laminate 12, or the second base electrode layer 32b may be disposed only on the surface of the second surface 12d of the laminate 12. 【0053】 The third base electrode layer 32c is placed on the surface of the third surface 12e of the laminate 12 and is formed to extend from the third surface 12e and cover the second main surface 12b. The fourth base electrode layer 32d is placed on the surface of the fourth surface 12f of the laminate 12 and is formed to extend from the fourth surface 12f and cover the second main surface 12b. 【0054】 The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. The configurations when the base electrode layer 32 is the baked layer, conductive resin layer, or thin film layer will be described below. 【0055】 (In the case of a baked layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it. The baked layer may be obtained by simultaneously firing the laminate chip having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the laminate chip, or by firing the laminate chip having the internal electrode layer 16 and the ceramic layer 14 to obtain the laminate 12, and then applying the conductive paste to the laminate 12 and baking it. Furthermore, when firing a laminated chip having an internal electrode layer 16 and a ceramic layer 14 and a conductive paste applied to the laminated chip simultaneously, it is preferable to form the firing layer by firing a material to which a dielectric material has been added instead of a glass component. 【0056】 The thickness of the first base electrode layer 32a located on the first surface 12c in the first direction y connecting the first surface 12c and the second surface 12d at the center of the lamination direction x is preferably 5 μm or more and 50 μm or less. Similarly, the thickness of the second base electrode layer 32b located on the second surface 12d in the first direction y connecting the first surface 12c and the second surface 12d at the center of the lamination direction x is preferably 5 μm or more and 50 μm or less. 【0057】When the first base electrode layer 32a is provided on a part of the first main surface 12a and a part of the second main surface 12b, and a part of the third surface 12e and a part of the fourth surface 12f, the thickness in the stacking direction x connecting the first main surface 12a and the second main surface 12b at the center of the first direction y connecting the first surface 12c and the second surface 12d of the first base electrode layer 32a located on the first main surface 12a and the second main surface 12b is preferably, for example, 1 μm or more and 25 μm or less. Furthermore, the thickness in the second direction z connecting the third surface 12e and the fourth surface 12f at the center of the first direction y connecting the first surface 12c and the second surface 12d of the first base electrode layer 32a located on the third surface 12e and the fourth surface 12f is preferably, for example, 1 μm or more and 25 μm or less. 【0058】 Furthermore, when a second base electrode layer 32b is provided on a part of the first main surface 12a and a part of the second main surface 12b, and a part of the third surface 12e and a part of the fourth surface 12f, the thickness of the second base electrode layer 32b located on the first main surface 12a and the second main surface 12b in the stacking direction x connecting the first main surface 12a and the second main surface 12b at the center of the first direction y connecting the first surface 12c and the second surface 12d is preferably, for example, 1 μm or more and 25 μm or less. Moreover, the thickness of the second base electrode layer 32b located on the third surface 12e and the fourth surface 12f in the second direction z connecting the third surface 12e and the fourth surface 12f at the center of the first direction y connecting the first surface 12c and the second surface 12d is preferably, for example, 1 μm or more and 25 μm or less. 【0059】 The thickness in the second direction z connecting the third surface 12e and the fourth surface 12f at the center of the first direction y connecting the first surface 12c and the second surface 12d of the third base electrode layer 32c, located on the third surface 12e, is preferably 1 μm or more and 50 μm or less. Furthermore, the thickness in the second direction z connecting the third surface 12e and the fourth surface 12f at the center of the first direction y connecting the first surface 12c and the second surface 12d of the fourth base electrode layer 32d, located on the fourth surface 12f, is preferably 1 μm or more and 50 μm or less. 【0060】The thickness of the third base electrode layer 32c located on the second main surface 12b in the lamination direction x connecting the first main surface 12a and the second main surface 12b at the center of the first direction y connecting the first surface 12c and the second surface 12d is preferably, for example, 1 μm or more and 25 μm or less. Similarly, the thickness of the fourth base electrode layer 32d located on the second main surface 12b in the lamination direction x connecting the first main surface 12a and the second main surface 12b at the center of the first direction y connecting the first surface 12c and the second surface 12d is preferably, for example, 1 μm or more and 25 μm or less. 【0061】 (In the case of a conductive resin layer) The conductive resin layer may be arranged on top of the baking layer so as to cover the baking layer, or it may be arranged directly on the laminate 12 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover a part of the baking layer. In addition, there may be multiple conductive resin layers. 【0062】 The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer made of, for example, a plated film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10. 【0063】 The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag. 【0064】Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Alternatively, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. 【0065】 The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer. 【0066】 The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders. 【0067】 As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. 【0068】 Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin. 【0069】 The thickest part of the conductive resin layer is preferably, for example, 1 μm or more and 50 μm or less. 【0070】 (In the case of a thin film layer) When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited. 【0071】 The plating layer 34 is positioned to cover the underlying electrode layer 32. 【0072】The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. 【0073】 The plating layer 34 may be formed from multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of Ni plating and Sn plating. The Ni plating layer is used to prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting. The thickness of each layer of the plating layer 34 is preferably 1 μm or more and 10 μm or less. 【0074】 Furthermore, the external electrode 30 may be formed using only the plating layer without providing the underlayer electrode layer 32. Although not shown in the figures, a structure in which the plating layer is provided without the underlayer electrode layer 32 will be described below. 【0075】 The first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d, or each of them, may have a plating layer directly formed on the surface of the laminate 12 without providing an underlay electrode layer 32. That is, the multilayer ceramic capacitor 10 may have a structure that includes a plating layer electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. In such a case, the plating layer may be formed after a catalyst is placed on the surface of the laminate 12 as a pretreatment. 【0076】 Furthermore, if the plating layer is formed directly on the laminate 12 without providing the underlay electrode layer 32, the reduction in the thickness of the underlay electrode layer 32 can be converted into a lower profile, i.e., a thinner design, or into the thickness of the laminate 12, i.e., the thickness of the capacitance forming section 18, thereby improving the design flexibility of the thin chip. 【0077】The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 12 and an upper plating electrode formed on the surface of the lower plating electrode. The lower plating electrode and the upper plating electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower plating electrode is preferably formed using Ni, which has solder barrier properties, and the upper plating electrode is preferably formed using Sn or Au, which has good solder wettability. 【0078】 Furthermore, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower plated electrode be formed using Cu, which has good bonding properties with Ni. The upper plated electrode may be formed as needed, and the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d may each consist only of the lower plated electrode. The plating layer may have the upper plated electrode as the outermost layer, or other plated electrodes may be formed on the surface of the upper plated electrode. 【0079】 In this case, when the external electrode 30 is formed using only the plating layer without providing the underlayer electrode layer 32, it is preferable that the thickness of each plating layer placed without the underlayer electrode layer 32 is 1 μm or more and 20 μm or less. 【0080】 Furthermore, it is preferable that the plating layer does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more. 【0081】 The dimension in the first direction y of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrodes 30, is defined as dimension L. Dimension L is preferably 0.10 mm or more and 0.70 mm or less. The dimension in the stacking direction x of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrodes 30, is defined as dimension T. Dimension T is preferably 0.05 mm or more and 1.00 mm or less. The dimension in the second direction z of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrodes 30, is defined as dimension W. Dimension W is preferably 0.05 mm or more and 0.40 mm or less. 【0082】 The multilayer ceramic capacitor 10 shown in Figure 1 has uncovered regions 40 on the first surface 12c to the fourth surface 12f that do not cover the external electrodes 30. The surface roughness Ra2 of the uncovered regions 40 is rougher than the surface roughness Ra1 of the first main surface 12a. Therefore, in a small multilayer ceramic capacitor 10, cracks caused by external stress on the mounting surface are suppressed, while ensuring good adhesion with the molding resin on the side surfaces of the multilayer ceramic capacitor 10 excluding the main surface, thereby ensuring stable adhesion after mounting. On the other hand, by making the main surface side of the laminate 12 smooth, stress concentration on the laminate 12 is suppressed when external stress is applied, and mechanical strength can be ensured at a certain level. In other words, the adhesion between the resin molding the multilayer ceramic capacitor 10 and the multilayer ceramic capacitor 10 is improved, so that the adhesion between the multilayer ceramic capacitor 10 and the mounting substrate after mounting can be ensured. Furthermore, since the peeling of the resin used to mold the multilayer ceramic capacitor 10 originates in the uncoated area 40, the adhesion can be further improved by making the surface roughness Ra2 of the uncoated area 40 greater than the surface roughness Ra1 of the first main surface 12a. 【0083】 2. Method for Manufacturing a Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described. 【0084】 First, a dielectric sheet for the ceramic layer and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known substances. 【0085】 A conductive paste for the internal electrode layer is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer formed on it, and a dielectric sheet with the pattern for the second internal electrode layer formed on it. 【0086】More specifically, a gravure plate can be prepared for printing the first internal electrode layer and the second internal electrode layer, and the patterns for each internal electrode layer can be printed using a gravure printing machine. 【0087】 Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second outer layer portion 20b on the second main surface 12b side. Then, the portion that will become the capacitance forming portion 18 formed by the above process is stacked on top of the portion that will become the second outer layer portion 20b. Next, the portion that will become the current-carrying portion 21 constituting the first outer layer portion 20a formed by the above process is stacked on top of the portion that will become the capacitance forming portion 18. Then, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the portion that will become the current-carrying portion 21 to form the first outer layer portion 20a on the first main surface 12a side. This completes the production of the laminated sheet. 【0088】 Next, the laminated sheets are pressed in the lamination direction using means such as hydrostatic pressing to produce a laminated block. 【0089】 Next, the laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods. 【0090】 The laminated chips that have been cut out are then fired to produce the laminated body 12. The firing temperature depends on the materials of the ceramic layer 14 and the internal electrode layer 16, but is preferably between 900°C and 1400°C. 【0091】 Next, the third and fourth surfaces are subjected to the following procedures in order to achieve the surface roughness of the present invention. 【0092】 First, the fired laminate 12 is mirror-polished using a barrel or the like. Then, as shown in Figure 9, the fired laminate is placed into a sprinkling pallet 50 which has a cavity hole 52 that accommodates only the third surface 12e or the fourth surface 12f of the laminate 12. After that, the third surface 12e is roughened by sandblasting. 【0093】Next, after the sandblasting of the third surface 12e is completed, the laminate 12 is transferred to another transfer pallet 50, and the fourth surface 12f is roughened by sandblasting. 【0094】 (Underlayment electrode layer) Next, a third underlayment electrode layer 32c of the third external electrode 30c is formed on the third surface 12e of the laminate 12 obtained by firing, and a fourth underlayment electrode layer 32d of the fourth external electrode 30d is formed on the fourth surface 12f of the laminate 12. 【0095】 When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed of a baked layer. 【0096】 Here, various methods can be used for forming the baked layer. For example, a method can be used in which the orientation of the laminate 12 is aligned using a camera or magnet so that the third surface 12e or the fourth surface 12f is facing downwards, and then the laminate 12 is held with a holding jig, and conductive paste is extruded and applied through slits or holes. In this method, by increasing the amount of conductive paste extruded, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed not only on the third surface 12e and the fourth surface 12f, but also on a part of the first main surface 12a and a part of the second main surface 12b. 【0097】 Next, a first base electrode layer 32a of the first external electrode 30a is formed on the first surface 12c of the laminate 12 obtained by firing, and a second base electrode layer 32b of the second external electrode 30b is formed on the second surface 12d of the laminate 12. In this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are formed using the DIP method so as to extend not only to the first surface 12c and the second surface 12d, but also to a part of the first main surface 12a, a part of the second main surface 12b, a part of the third surface 12e, and a part of the fourth surface 12f. 【0098】The baking process may involve baking the first base electrode layer 32a of the first external electrode 30a, the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d simultaneously, or the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d separately. 【0099】 (Conductive resin layer) When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baked layer. 【0100】 The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baking layer or the laminate 12, and then performing heat treatment at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, in order to prevent the scattering of resin and to prevent oxidation of various metal components, it is preferable to keep the oxygen concentration below 100 ppm. 【0101】 Furthermore, the conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 with a baked layer, for example, by extruding the conductive resin paste through a slit. 【0102】 (Thin film layer) When the base electrode layer 32 is formed as a thin film layer, masking can be performed and the base electrode layer 32 can be formed in the area where the external electrode 30 is to be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer shall be a layer of 1 μm or less in thickness in which metal particles are deposited. 【0103】 (Plating layer) Furthermore, the external electrode 30 may be formed using only the plating layer without providing the underlayer electrode layer 32. In that case, it can be formed by the following method. 【0104】 Plating is applied to the first surface 12c and the second surface 12d of the laminate 12 to form a lower layer plated electrode on the exposed portion of the first internal electrode layer 16a. Similarly, plating is applied to the third surface 12e and the fourth surface 12f of the laminate 12 to form a lower layer plated electrode on the exposed portion of the second internal electrode layer 16b. When performing the plating, either electrolytic plating or electroless plating may be used, but electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. As for the plating method, barrel plating is preferred. Also, if necessary, the upper layer plated electrode formed on the surface of the lower layer plated electrode may be formed in the same manner. 【0105】 Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or it may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer is formed on the base electrode layer 32 as the lower plating layer, and a Sn plating layer is formed as the upper plating layer. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating requires pretreatment with a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred. 【0106】 As described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured. 【0107】 3. Second Embodiment An example of a multilayer ceramic capacitor 110 according to a second embodiment of the present invention will be described. 【0108】Figure 10 shows an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the second embodiment of the present invention, where (a) is an external perspective view from one direction and (b) is an external perspective view from the other direction. Figure 11 is a top view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. Figure 12 is a front view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. Figure 13 is a side view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. 【0109】 The multilayer ceramic capacitor 110 comprises a laminate 112 and a plurality of external electrodes 130. 【0110】 The laminate 112 has a first main surface 112a and a second main surface 112b facing the stacking direction x, a first surface 112c and a second surface 112d facing a first direction y perpendicular to the stacking direction x, and a third surface 112e and a fourth surface 112f facing a second direction z perpendicular to the stacking direction x and the first direction y. 【0111】 Furthermore, the surface roughness Ra1 of the first main surface 112a or the second main surface 112b is preferably 0.053 μm or more and 0.115 μm or less. 【0112】 (External electrodes) External electrodes 130 are arranged on the third surface 112e side and the fourth surface 112f side of the laminate 112. The external electrodes 130 have a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d. 【0113】 The first external electrode 130a and the second external electrode 130b are arranged on the third surface 112e of the laminate 112 in a first direction y. The first external electrode group 130A is formed by the first external electrode 130a and the second external electrode 130b, and the first external electrode group 130A is isolated at a predetermined interval in the first direction y on the third surface 112e side of the laminate 112. Parts of the first external electrode 130a and the second external electrode 130b may be arranged on parts of the first main surface 112a and parts of the second main surface 112b. 【0114】The third external electrode 130c and the fourth external electrode 130d are arranged on the fourth surface 112f of the laminate 112 in the first direction y. The third external electrode 130c and the fourth external electrode 130d constitute the second external electrode group 130B, and the second external electrode group 130B is isolated at a predetermined interval in the first direction y on the fourth surface 112f side of the laminate 112. Parts of the third external electrode 130c and the fourth external electrode 130d may be arranged on parts of the first main surface 112a and parts of the second main surface 112b. 【0115】 The first surface 112c to the fourth surface 112f have an uncoated area 140 that is not covered by the external electrode 130. The surface roughness Ra2 of the uncoated area 140 is greater than the surface roughness Ra1 of the first main surface 112a or the second main surface 112b. Preferably, the surface roughness Ra2 of the uncoated area 140 is 10% greater than the surface roughness Ra1 of the first main surface 112a or the second main surface 112b. Preferably, the surface roughness Ra2 of the uncoated area 140 is 0.0535 μm or greater. 【0116】 The multilayer ceramic capacitor 110 according to the second embodiment shown in Figure 10 provides the same effects as the multilayer ceramic capacitor 10 described above. 【0117】 4. Third Embodiment An example of a multilayer ceramic capacitor 210 according to the third embodiment of this invention will be described. 【0118】 Figure 14 shows an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the third embodiment of the present invention, where (a) is an external perspective view from one direction and (b) is an external perspective view from the other direction. Figure 15 is a top view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 16 is a front view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 17 is a side view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. 【0119】 The multilayer ceramic capacitor 210 comprises a laminate 212 and a plurality of external electrodes 230. 【0120】 The laminate 212 has a first main surface 212a and a second main surface 212b facing the stacking direction x, a first surface 212c and a second surface 212d facing a first direction y perpendicular to the stacking direction x, and a third surface 212e and a fourth surface 212f facing a second direction z perpendicular to the stacking direction x and the first direction y. 【0121】 (External electrodes) External electrodes 230 are arranged on the third surface 212e side and the fourth surface 212f side of the laminate 212. The external electrodes 230 have a first external electrode 230a, a second external electrode 230b, a third external electrode 230c, and a fourth external electrode 230d. 【0122】 The first external electrode 230a, the second external electrode 230b, and the third external electrode 230c are arranged on the third surface 212e of the laminate 212 in a first direction y. The first external electrode group 230A is formed by the first external electrode 230a, the second external electrode 230b, and the third external electrode 230c, and the first external electrode group 230A is isolated at equal intervals in the first direction y on the third surface 212e side of the laminate 212. The first external electrode 230a may be arranged on a part of the first main surface 212a, a part of the second main surface 212b, and a part of the first surface 212c. The second external electrode 230b may be arranged on a part of the first main surface 212a and a part of the second main surface 212b. The third external electrode 230c may be positioned on a portion of the first main surface 212a, a portion of the second main surface 212b, and a portion of the second surface 212d. 【0123】The fourth external electrode 230d, the fifth external electrode 230e, and the sixth external electrode 230f are arranged on the fourth surface 212f of the laminate 212 in a first direction y. The fourth external electrode 230d, the fifth external electrode 230e, and the sixth external electrode 230f constitute the second external electrode group 230B, and the second external electrode group 230B is isolated at equal intervals in the first direction y on the fourth surface 212f side of the laminate 212. The fourth external electrode 230d may be arranged on a part of the first main surface 212a, a part of the second main surface 212b, and a part of the first surface 212c. The fifth external electrode 230e may be arranged on a part of the first main surface 212a and a part of the second main surface 212b. The sixth external electrode 230f may be positioned on a portion of the first main surface 212a, a portion of the second main surface 212b, and a portion of the second surface 212d. 【0124】 The first surface 212c to the fourth surface 212f have an uncoated region 240 that is not covered by the external electrode 230. The surface roughness of the uncoated region 240 is greater than the surface roughness of the first main surface 212a or the second main surface 212b. Preferably, the surface roughness of the uncoated region 240 is 10% greater than the surface roughness of the first main surface 212a or the second main surface 212b. Preferably, the surface roughness of the uncoated region 240 is 0.0535 μm or more. Also, preferably, the surface roughness of the first main surface 212a or the second main surface 212b is 0.053 μm or more and 0.115 μm or less. 【0125】 The multilayer ceramic capacitor 210 according to the third embodiment shown in Figure 14 provides the same effects as the multilayer ceramic capacitor 10 described above. 【0126】 5. Fourth Embodiment An example of a multilayer ceramic capacitor 310 according to the fourth embodiment of this invention will be described. 【0127】Figure 18 shows an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the fourth embodiment of the present invention, where (a) is an external perspective view from one direction and (b) is an external perspective view from the other direction. Figure 19 is a top view showing an example of a multilayer ceramic capacitor according to the fourth embodiment of the present invention. Figure 20 is a front view showing an example of a multilayer ceramic capacitor according to the fourth embodiment of the present invention. Figure 21 is a side view showing an example of a multilayer ceramic capacitor according to the fourth embodiment of the present invention. 【0128】 The multilayer ceramic capacitor 310 comprises a laminated body 312 and a plurality of external electrodes 330. 【0129】 The laminate 312 has a first main surface 312a and a second main surface 312b facing the stacking direction x, a first surface 312c and a second surface 312d facing a first direction y perpendicular to the stacking direction x, and a third surface 312e and a fourth surface 312f facing a second direction z perpendicular to the stacking direction x and the first direction y. 【0130】 The surface roughness Ra1 of the first main surface 312a or the second main surface 312b is preferably 0.053 μm or more and 0.115 μm or less. 【0131】 (External electrodes) External electrodes 330 are arranged on the third surface 312e side and the fourth surface 312f side of the laminate 312. The external electrodes 330 have a first external electrode 330a, a second external electrode 330b, a third external electrode 330c, and a fourth external electrode 330d. 【0132】The first external electrode 330a, the second external electrode 330b, the third external electrode 330c, and the fourth external electrode 330d are arranged on the third surface 312e of the laminate 312 in a first direction y. The first external electrode group 330A is formed by the first external electrode 330a, the second external electrode 330b, the third external electrode 330c, and the fourth external electrode 330d, and the first external electrode group 330A is isolated at equal intervals in the first direction y on the third surface 312e side of the laminate 312. The first external electrode 330a, the second external electrode 330b, the third external electrode 330c, and the fourth external electrode 330d may be arranged on a part of the first main surface 312a and a part of the second main surface 312b. 【0133】 The fifth external electrode 330e, the sixth external electrode 330f, the seventh external electrode 330g, and the eighth external electrode 330h are arranged on the fourth surface 212f of the laminate 212 in the first direction y. The fifth external electrode 330e, the sixth external electrode 330f, the seventh external electrode 330g, and the eighth external electrode 330h constitute the second external electrode group 330B, and the second external electrode group 330B is isolated at equal intervals in the first direction y on the fourth surface 312f side of the laminate 312. The fifth external electrode 330e, the sixth external electrode 330f, the seventh external electrode 330g, and the eighth external electrode 330h may be arranged on a part of the first main surface 312a and a part of the second main surface 312b. 【0134】 The first surface 312c to the fourth surface 312f have an uncoated region 340 that is not covered by the external electrode 330. The surface roughness Ra2 of the uncoated region 340 is greater than the surface roughness Ra1 of the first main surface 312a or the second main surface 312b. Preferably, the surface roughness Ra2 of the uncoated region 340 is 10% greater than the surface roughness Ra1 of the first main surface 312a or the second main surface 312b. Preferably, the surface roughness Ra2 of the uncoated region 340 is 0.0535 μm or greater. 【0135】 The multilayer ceramic capacitor 310 according to the fourth embodiment shown in Figure 18 provides the same effects as the multilayer ceramic capacitor 10 described above. 【0136】6. Experimental Examples Next, in order to confirm the effect of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitors were manufactured as experimental samples, and each sample was evaluated by substrate bending resistance tests and adhesion strength tests. 【0137】 (1) Specifications of the multilayer ceramic capacitors prepared as samples for the experimental example Multilayer ceramic capacitors provided in the multilayer ceramic electronic components that are comparative examples and examples 1 to 8 were prepared using the manufacturing method according to the above embodiment.・Structure of multilayer ceramic capacitor: 3 terminals (see Figure 1) ・Dimensions of multilayer ceramic capacitor (L): 0.67 mm ・Dimensions of multilayer ceramic capacitor (W): 0.37 mm ・Dimensions of multilayer ceramic capacitor (T): 0.33 mm ・Structure of internal electrodes ・Dielectric thickness of capacitance forming part: 0.65 μm ・Thickness of first and second internal electrode layers: 0.45 μm ・Number of first internal electrode layers: 125 layers ・Number of second internal electrode layers: 125 layers ・Thickness of first and second outer layers: 22 μm ・L gap dimension: 50 μm ・W gap dimension: 50 μm ・Structure of external electrodes ・First and second external electrodes ・Underlay electrode layer: Baked layer containing conductive metal (Cu) and glass component ・Plating layer: Two-layer structure of Ni plating layer and Sn plating layer ・Third and fourth external electrodes ・Underlay electrode layer: Baked layer containing conductive metal (Cu) and glass component ・Plating layer : Two-layer structure consisting of a Ni plating layer and a Sn plating layer 【0138】 (2) Method for measuring the surface roughness of the first main surface and the uncoated area The surface roughness Ra1 of the first main surface was determined by scanning the center of the surface of the first main surface along the first direction y using a shape analysis laser microscope (VK-X1000 manufactured by Keyence Corporation) and measuring the maximum height (Ra1). The surface roughness Ra2 of the uncoated area was determined by scanning the center of the surface of the uncoated area located on the third surface along the first direction y and measuring the maximum height (Ra2). 【0139】(3) Multilayer ceramic capacitors, which are to be used as test samples for substrate bending resistance, were prepared, and the prepared multilayer ceramic capacitor samples were mounted on a 1.6 mm thick JIS substrate (glass epoxy substrate) using solder paste. Then, the substrate was bent by pressing a metal push rod with a 5 ± 0.1 mm rounded tip from the substrate side where no samples were mounted, thereby applying mechanical stress to the substrate. The holding time was set to 5 seconds, and the deflection amount was set to 5 mm. After the substrate bending resistance test, the cross-section of the multilayer ceramic capacitor samples was polished, and the number of cracks that occurred in the exposed cross-section was checked. Ten samples were prepared for each test. The judging criteria were that if one or fewer cracks occurred out of 10 samples, it was judged as good, and if two or more cracks occurred out of 10 samples, it was judged as poor. 【0140】 (4) A multilayer ceramic capacitor, which is to be used as a test specimen for adhesion strength, was prepared, and the prepared multilayer ceramic capacitor specimen was mounted on a 1.6 mm thick JIS substrate (glass epoxy substrate) using solder paste. Then, the surfaces of the specimen other than the mounting surface of the multilayer ceramic capacitor were covered with resin mold. Adhesive tape was then applied to the surfaces of the resin mold corresponding to the third surface, first main surface, and fourth surface of the multilayer ceramic capacitor, and the tape was peeled off at a constant speed of 5 mm / sec. Twenty specimens were prepared for each test. The criterion for judgment was that if the number of resin molds that peeled off was 2 or less out of 20 specimens, it was judged as good, and if it peeled off was 3 or more out of 20 specimens, it was judged as poor. 【0141】 (5) Results Table 1 shows the test results of the substrate bending resistance test and tape peeling test when the surface roughness Ra1 of the first main surface and the surface roughness Ra2 of the uncoated area are changed, respectively. 【0142】 【0143】According to Table 1, in each of the samples from Examples 1 to 11, the surface roughness Ra2 of the uncoated area was rougher than the surface roughness Ra1 of the first main surface, resulting in good results in the tape peel test. Furthermore, in Examples 1, 3, 5, 7, 9, and 11, the surface roughness Ra2 of the uncoated area was 10% greater than the surface roughness Ra1 of the first main surface, resulting in even better results in the tape peel test. 【0144】 On the other hand, in the comparative example sample, the surface roughness Ra1 of the first main surface was rougher than the surface roughness Ra2 of the uncoated area, resulting in 6 defective samples out of 20 in the tape peel test. 【0145】 From the above results, it was confirmed that in the multilayer ceramic capacitor samples according to Examples 1 to 11, the surface roughness Ra2 of the uncoated area is rougher than the surface roughness Ra1 of the first main surface, so that cracks caused by external stress on the mounting surface are suppressed, adhesion with the molding resin on the side surface of the multilayer ceramic capacitor is ensured, and stable fixing force after mounting can be ensured. Furthermore, it was confirmed that when the surface roughness Ra1 of the first main surface is greater than 0.115 μm, localized stress concentration on the surface of the laminate is more likely to occur, and deflection cracks begin to occur. 【0146】 Furthermore, it was confirmed that by making the first main surface smooth, stress concentration on the laminate when external stress occurs can be suppressed, thereby ensuring a certain level of mechanical strength. On the other hand, by making the surface roughness Ra2 of the uncoated area rougher by a certain amount, the adhesion between the mold resin and the laminate can be improved, and the bonding force to the substrate after mounting can be ensured. In addition, since the peeling of the mold resin starts in the uncoated area, it was confirmed that the adhesion can be further improved by making the surface roughness Ra2 of the uncoated area greater than the surface roughness Ra1 of the first main surface. 【0147】As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. That is, without departing from the scope of the technical idea and objectives of the present invention, various modifications can be made to the embodiments described above in terms of mechanism, shape, material, quantity, position or arrangement, etc., and these are included in the present invention. 【0148】10, 110, 210, 310 Multilayer ceramic capacitor 12, 112, 212, 312 Laminate 12a, 112a, 212a, 312a First main surface 12b, 112b, 212b, 312b Second main surface 12c, 112c, 212c, 312c First surface 12d, 112d, 212d, 312d Second surface 12e, 112e, 212e, 312e Third surface 12f, 112f, 212f, 312f Fourth surface 14 Ceramic layer 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18 Capacitance forming section 20a First outer layer 20b Second outer layer 22a, 22b W gap 24a,24b L-gap 25a First opposing part 25b Second opposing part 26a First lead-out part 26b Second lead-out part 27a First extension part 27b Second extension part 30, 130, 230, 330 External electrodes 30a, 130a, 230a, 330a First external electrodes 30b, 130b, 230b, 330b Second external electrodes 30c, 130c, 230c, 330c Third external electrodes 30d, 130d, 230d, 330d Fourth external electrodes 230e, 330e Fifth external electrodes 230f, 330f Sixth external electrode 330g Seventh external electrode 330h Eighth external electrode 130A, 230A, 330A 40, 140, 240, 340 Uncoated area 50 Spreading pallet 52 Cavity hole x Lamination direction y First direction z Second direction L Dimension of multilayer ceramic capacitor in the first direction W Dimensions of the multilayer ceramic capacitor in the second direction T Dimensions of the multilayer ceramic capacitor in the stacking direction l Dimensions of the stack in the first direction w Dimensions of the stack in the second direction t Dimensions of the stack in the stacking direction

Claims

1. A multilayer ceramic electronic component comprising: a laminate including a plurality of stacked ceramic layers and a plurality of internal electrode layers stacked on the ceramic layers, the laminate having a first main surface and a second main surface facing each other in the stacking direction, a first surface and a second surface facing each other in a first direction perpendicular to the stacking direction, and a third surface and a fourth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; and at least four or more external electrodes arranged to cover the laminate and connected to the internal electrode layers, wherein the first to fourth surfaces have uncovered regions that do not cover the external electrodes, and the surface roughness of the uncovered regions is rougher than the surface roughness of the first main surface.

2. The multilayer ceramic electronic component according to claim 1, wherein the surface roughness of the uncoated region is 10% greater than the surface roughness of the first main surface.

3. The multilayer ceramic electronic component according to claim 1 or claim 2, wherein the surface roughness of the uncoated region is 0.0535 μm or more.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the surface roughness of the first main surface is 0.053 μm or more and 0.115 μm or less.

5. The multilayer ceramic electronic component according to any one of claims 1 to 4, wherein the length in the stacking direction including the laminate and the external electrode is shorter than the length in the second direction including the laminate and the external electrode.

6. The multilayer ceramic electronic component according to any one of claims 1 to 5, wherein the length in the first direction including the laminate and the external electrode is longer than the length in the second direction including the laminate and the external electrode.

7. The multilayer ceramic electronic component according to any one of claims 1 to 6, wherein the length in the first direction including the laminate and the external electrode is 0.10 mm or more and 0.70 mm or less, and the length in the second direction including the laminate and the external electrode is 0.05 mm or more and 0.40 mm or less.

8. The multilayer ceramic electronic component according to any one of claims 1 to 7, wherein the first main surface or the second main surface is a substrate mounting surface.

9. The multilayer ceramic electronic component according to any one of claims 1 to 8, wherein the external electrodes include a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode, the first external electrode and the second external electrode being arranged in a first direction on the third surface of the laminate, and the third external electrode and the fourth external electrode being arranged in a first direction on the fourth surface of the laminate.

10. The multilayer ceramic electronic component according to any one of claims 1 to 8, wherein the external electrodes include a first external electrode, a second external electrode, a third external electrode, a fourth external electrode, a fifth external electrode, and a sixth external electrode, the first to third external electrodes being arranged in a first direction on the third surface of the laminate, and the fourth to sixth external electrodes being arranged in a first direction on the fourth surface of the laminate.

11. The multilayer ceramic electronic component according to any one of claims 1 to 8, wherein the external electrodes include a first external electrode, a second external electrode, a third external electrode, a fourth external electrode, a fifth external electrode, a sixth external electrode, a seventh external electrode, and an eighth external electrode, wherein the first to fourth external electrodes are arranged in the first direction on the third surface of the laminate, and the fifth to eighth external electrodes are arranged in the first direction on the fourth surface of the laminate.

Images