Method for manufacturing semiconductor device

Abstract

This method for manufacturing a semiconductor device includes: a pad formation step for forming a connection electrode pad, an inspection electrode pad, and an electrode pad connection portion on a first substrate; an inspection step for performing an electrical inspection by bringing an inspection probe into contact with the inspection electrode pad after the pad formation step; a removal step for removing at least the region of the inspection electrode pad that came into contact with the inspection probe in the inspection step after the inspection step; a connection step for electrically connecting the connection electrode pad to a second element via a bump after the removal step; and a coating step for coating at least the bump with a coating having an insulating property after the removal step.

Description

Method of manufacturing a semiconductor device 【0001】 One aspect of the present disclosure relates to a method of manufacturing a semiconductor device. 【0002】 For example, in the manufacturing process of the semiconductor device described in Patent Document 1, inspection is performed by bringing a probe into contact with an electrode pad. Since this inspection is performed by pressing the probe against the electrode, raised needle marks remain on the surface of the electrode after inspection. In the semiconductor device described in Patent Document 1, an inspection electrode is formed inside an opening formed in a semiconductor substrate, thereby preventing the needle marks from protruding from the surface of the semiconductor substrate. 【0003】 Japanese Patent Application Laid-Open No. 2014-86596 【0004】 The method of manufacturing a semiconductor device as described above is required to enhance reliability. Therefore, one aspect of the present disclosure aims to provide a method of manufacturing a semiconductor device with enhanced reliability. 【0005】 A method of manufacturing a semiconductor device according to one aspect of the present disclosure is [1] "a method of manufacturing a semiconductor device in which a first element having a first substrate and a second element having a second substrate are connected to each other, comprising: a pad forming step of forming a connection electrode pad, an inspection electrode pad, and an electrode pad connection portion for electrically connecting the connection electrode pad to the inspection electrode pad on the first substrate; an inspection step of performing an electrical inspection by bringing an inspection probe into contact with the inspection electrode pad after the pad forming step; a removal step of removing at least a region where the inspection probe has contacted in the inspection step in the inspection electrode pad after the inspection step; a connection step of electrically connecting the connection electrode pad to the second element via an electrical connection portion after the removal step; and a coating step of coating at least the electrical connection portion with a coating portion having insulating properties after the removal step." 【0006】In this semiconductor device manufacturing method, the electrical connection portion connecting the electrode pads for connecting the first element to the second element is covered with an insulating coating. This allows the exposed conductor portion to be covered by the coating, thereby improving reliability. On the other hand, when performing electrical testing by contacting the electrode pad with an inspection probe, as in this semiconductor device manufacturing method, raised needle marks (irregularities) remain on the surface of the electrode pad after testing. In such cases, if the coating is simply provided on the electrode pad, the coating may not adhere well due to the protrusions of the needle marks, or voids may be created due to the depressions of the needle marks, potentially reducing reliability. In contrast, in this semiconductor device manufacturing method, at least the area of ​​the inspection electrode pad that was in contact with the inspection probe during the inspection process is removed during the removal process. This suppresses the occurrence of the above-mentioned problems, allowing the electrical connection portion to be well covered by the coating, thereby improving reliability. 【0007】 A method for manufacturing a semiconductor device relating to one aspect of this disclosure may also be [2] "a method for manufacturing a semiconductor device according to [1], further comprising the step of forming an insulating layer on the connecting electrode pad before the removal step." In this case, exposure of the connecting electrode pad can be suppressed, and deterioration of the connecting electrode pad due to oxidation, etc., can be suppressed. In addition, adverse effects on the connecting electrode pad due to unnecessary etching in the removal step can be suppressed. 【0008】 A method for manufacturing a semiconductor device relating to one aspect of this disclosure may be [3] "a method for manufacturing a semiconductor device according to [1] or [2], wherein the entire inspection electrode pad is removed in the removal step." In this case, needle marks caused by contact with the inspection probe can be reliably removed. 【0009】A method for manufacturing a semiconductor device relating to one aspect of the present disclosure may be [4] "a method for manufacturing a semiconductor device according to any one of [1] to [3], wherein in the connection step, the first element and the second element are joined to each other by the electrical connection portion such that the first substrate and the second substrate face each other via the electrical connection portion." When the first element and the second element are joined in this manner, the flatness of the joining surface is particularly important. This method for manufacturing a semiconductor device can be suitably applied in such cases. 【0010】 A method for manufacturing a semiconductor device relating to one aspect of the present disclosure may be [5] "a method for manufacturing a semiconductor device according to any one of [1] to [4], wherein in the connection step, the electrical connection portion is provided at a position that does not overlap with the area removed in the removal step on the inspection electrode pad when viewed from a direction perpendicular to the main surface of the first substrate." In this case, for example, it is not necessary to remove the electrode pad connection portion or the insulating layer in order to bring the electrical connection portion into contact with the connection electrode pad, thus simplifying the process. Also, in the position that overlaps with the area removed in the removal step, there is a possibility that irregularities have been formed on the connection electrode pad by the removal step. By providing the electrical connection portion at a position that does not overlap with the area removed in the removal step, the electrical connection portion can be reliably provided on a flat surface. 【0011】 A method for manufacturing a semiconductor device according to one aspect of the present disclosure may be [6] "In the coating step, the coating portion is provided between the first element and the second element, and is a method for manufacturing a semiconductor device according to any one of [1] to [5]." In this case, both the exposed conductor portion of the first element and the exposed conductor portion of the second element can be covered by the coating portion. 【0012】 A method for manufacturing a semiconductor device relating to one aspect of this disclosure may be [7] "a method for manufacturing a semiconductor device according to any one of [1] to [6], wherein in the coating step, at least a part of the electrode pad connection portion is covered by the coating portion." In this case, reliability can be further enhanced. In addition, the occurrence of short circuits via the electrode pad connection portion can be suppressed. 【0013】A method for manufacturing a semiconductor device relating to one aspect of the present disclosure may be [8] "a method for manufacturing a semiconductor device according to any one of [1] to [7], wherein in the pad formation step, the inspection electrode pad is formed such that, when viewed from a direction perpendicular to the main surface of the first substrate, at least a portion of the inspection electrode pad overlaps with the connecting electrode pad." In this case, since at least a portion of the inspection electrode pad overlaps with the connecting electrode pad, an increase in the area of ​​the first substrate can be suppressed. 【0014】 A method for manufacturing a semiconductor device relating to one aspect of the present disclosure may be [9] "the method for manufacturing a semiconductor device according to [8], wherein in the pad forming step, the inspection electrode pad is formed such that, when viewed from a direction perpendicular to the main surface of the first substrate, a part of the inspection electrode pad is located outside the connecting electrode pad." In this case, while securing the area of ​​the inspection electrode pad, a wide area of ​​the opening region for connecting the electrical connection portion in the connecting electrode pad can be secured. Furthermore, for example, by bringing an inspection probe into contact with the inspection electrode pad at the outer part and performing the inspection, it is possible to suppress the effect of stress from the inspection probe on the connecting electrode pad. 【0015】 A method for manufacturing a semiconductor device relating to one aspect of this disclosure may be

[10] "a method for manufacturing a semiconductor device according to [8] or [9], wherein the etching rate of the metal material constituting the electrode pad connection portion is lower than the etching rate of the metal material constituting the inspection electrode pad." In this case, when removing the inspection electrode pad in the removal step, the electrode pad connection portion can function as a stopper to protect the connecting electrode pad. 【0016】 A method for manufacturing a semiconductor device relating to one aspect of the present disclosure may be

[11] "a method for manufacturing a semiconductor device according to any one of [8] to

[10] , wherein the electrode pad connection portion formed in the pad formation step has a recess on the surface opposite to the first substrate, and in the coating step, the coating portion fits into the recess." In this case, it is possible to suppress the space within the recess from becoming a void, and to suppress connection failures and the like caused by voids. 【0017】 A method for manufacturing a semiconductor device relating to one aspect of the present disclosure may be

[12] "a method for manufacturing a semiconductor device according to any one of [1] to [7], wherein in the pad forming step, the inspection electrode pad is formed such that it does not overlap with the connecting electrode pad when viewed from a direction perpendicular to the main surface of the first substrate." In this case, since the inspection electrode pad does not overlap with the connecting electrode pad, an increase in the thickness of the first element can be suppressed. 【0018】 A method for manufacturing a semiconductor device relating to one aspect of the present disclosure may be

[13] "a method for manufacturing a semiconductor device according to

[12] , further comprising the step of forming an insulating layer over the connecting electrode pad, the inspection electrode pad and the electrode pad connection portion after the pad forming step and before the removal step, wherein in the removal step, a recess is formed in the insulating layer when at least the area of ​​the inspection electrode pad that the inspection probe contacted in the inspection step is removed, and in the coating step, the coating portion fits into the recess." In this case, it is possible to suppress the space within the recess from becoming a void, and to suppress connection failures and the like caused by voids. 【0019】 A method for manufacturing a semiconductor device relating to one aspect of the present disclosure may be

[14] "a method for manufacturing a semiconductor device according to

[13] , wherein in the removal step, at least a portion of the electrode pad connection is removed when at least the area in the inspection step that the inspection probe has contacted in the inspection step is removed, thereby forming the recess in the insulating layer." In this case, it is possible to suppress the space within the recess from becoming a void, and to suppress connection failures and the like caused by voids. 【0020】A method for manufacturing a semiconductor device relating to one aspect of the present disclosure may be

[15] "a method for manufacturing a semiconductor device according to

[13] or

[14] , wherein in the removal step, when at least the area in the inspection electrode pad that the inspection probe contacted in the inspection step is removed, the recess is formed in the insulating layer in a portion adjacent to the area in the inspection electrode pad that was removed in the removal step." In this case, it is possible to suppress the space within the recess from becoming a void, and to suppress connection failures and the like caused by voids. 【0021】 According to one aspect of this disclosure, it becomes possible to provide a method for manufacturing a semiconductor device with enhanced reliability. 【0022】This is a cross-sectional view of a semiconductor device according to an embodiment. (a), (b), and (c) are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to an embodiment. This is a plan view of a connecting electrode pad, an inspection electrode pad, and an electrode pad connection part. (a), (b), and (c) are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to an embodiment. (a) and (b) are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to an embodiment. (a) and (b) are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to an embodiment. This is a cross-sectional view for illustrating a method for manufacturing a semiconductor device according to a first modification. (a) and (b) are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to a first modification. This is a plan view of a connecting electrode pad, an inspection electrode pad, and an electrode pad connection part according to a second modification. (a), (b), and (c) are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to a second modification. (a), (b), and (c) are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to a second modification. (a) and (b) are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to a second modification. (a), (b), and (c) are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to a third modification. (a), (b), and (c) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third modified example. (a) and (b) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third modified example. A cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fourth modified example. A cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment. A cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fifth modified example. 【0023】 Hereinafter, embodiments relating to one aspect of this disclosure will be described in detail with reference to the drawings. In the following description, the same or equivalent elements will be denoted by the same reference numerals, and redundant descriptions will be omitted. 【0024】As shown in Figure 1, the semiconductor device 1 according to this embodiment comprises a first element 10 and a second element 20, with the first element 10 and the second element 20 connected to each other. In this example, each of the first element 10 and the second element 20 is a semiconductor chip, the first element 10 is a CCD (Charge Coupled Device) chip, and the second element 20 is a CMOS (Complementary Metal-Oxide-Semiconductor) chip. The semiconductor device 1 in this example is a semiconductor imaging device that detects light L incident from the upper side in Figure 1. 【0025】 The first element 10 has a first substrate 11. The first substrate 11 is formed in the shape of a rectangular plate from, for example, a semiconductor material, and has main surfaces 11a and 11b. The main surface 11b is the light incident surface to which the light L to be detected is incident. In this example, the first substrate 11 is a silicon substrate. An insulating layer 12 is formed on the main surface 11a of the first substrate 11. The insulating layer 12 is formed from, for example, boron phosphorus glass (BPSG). Various element parts 13 that constitute the CCD chip are formed within the insulating layer 12. The element part 13 includes, for example, a plurality of polysilicon electrodes 13a and contact parts 13b electrically connected to the polysilicon electrodes 13a. Note that although the element part 13 is shown in a simplified form in Figure 1, the element part 13 is actually more complex than shown. The same applies to the element part 23 of the second element 20, which will be described later. 【0026】A connecting electrode pad 14 is formed on the surface 12a of the insulating layer 12 opposite to the first substrate 11 (the lower side in Figure 1). The connecting electrode pad 14 is electrically connected to the contact portion 13b. An insulating layer 15 is formed on the surface 12a of the insulating layer 12 so as to cover the connecting electrode pad 14. The insulating layer 15 is made of, for example, silicon nitride (SiN). An electrode pad connection portion 16 is formed on the surface 15a of the insulating layer 15 opposite to the first substrate 11 (the lower side in Figure 1). A through hole 15b is formed in the insulating layer 15, and the electrode pad connection portion 16 is electrically connected to the connecting electrode pad 14 through the through hole 15b. A recess 16b is formed on the surface 16a of the electrode pad connection portion 16 opposite to the first substrate 11 (the lower side in Figure 1). 【0027】 The second element 20 has a second substrate 21. The second substrate 21 is formed in the shape of a rectangular plate from, for example, a semiconductor material. In this example, the second substrate 21 is a silicon substrate. An insulating layer 22 is formed on the main surface 21a of the second substrate 21. The insulating layer 22 is formed from, for example, boron phosphorus glass (BPSG). Various element parts 23 that constitute a CMOS chip are formed within the insulating layer 22. The element part 23 includes, for example, an electrode 23a and a plurality of contact parts 23b electrically connected to the electrode 23a. 【0028】 A connecting electrode pad 24 is formed on the surface 22a of the insulating layer 22 opposite to the second substrate 21 (the upper side in Figure 1). The connecting electrode pad 24 is electrically connected to the contact portion 23b. An insulating layer 25 is formed on the surface 22a of the insulating layer 22 so as to cover the connecting electrode pad 24. The insulating layer 25 is made of, for example, silicon nitride (SiN). 【0029】The first element 10 and the second element 20 are electrically connected to and joined to each other by bumps 17 and 27 (electrical connection points). In other words, the first element 10 and the second element 20 are bump-bonded. More specifically, an opening 15c is formed in the insulating layer 15 of the first element 10 to expose a connecting electrode pad 14, and the bump 17 is joined to the connecting electrode pad 14 at the opening 15c. Similarly, an opening 25c is formed in the insulating layer 25 of the second element 20 to expose a connecting electrode pad 24, and the bump 27 is joined to the connecting electrode pad 24 at the opening 25c. The bumps 17 and 27 are joined (integrated) to each other, for example, by melting and solidifying. 【0030】 As shown in Figure 1, the first element 10 and the second element 20 are joined to each other by bumps 17 and 27 such that the first substrate 11 and the second substrate 21 face each other via bumps 17 and 27. The first substrate 11 and the second substrate 21 are arranged so as to be aligned in a direction perpendicular to the main surfaces 11a and 11b of the first substrate 11 (the direction of light incidence, the up and down direction in Figure 1). 【0031】 An insulating covering portion 30 is provided between the first element 10 and the second element 20. In this example, the covering portion 30 has insulating layers 31 and 32 and an underfill portion 33. The insulating layer 31 is formed on the surface 15a of the insulating layer 15 so as to cover the electrode pad connection portion 16. The insulating layer 31 extends into the entire recess 16b formed on the surface 16a of the electrode pad connection portion 16. The insulating layer 32 is formed on the surface 25a of the insulating layer 25 opposite to the second substrate 21 (upper side in Figure 1). The insulating layers 31 and 32 are made of, for example, silicon oxide film (SiO ２ The underfill portion 33 is formed by the insulating layers 31 and 32. The underfill portion 33 is formed by, for example, an insulating resin material. The insulating layers 31 and 32 and the underfill portion 33 cover the bumps 17 and 27 (electrical connection parts) so that they are not exposed to the outside. 【0032】A method for manufacturing a semiconductor device according to an embodiment will be described with reference to Figures 2 to 6. Figures 2 to 4 are diagrams illustrating the process of preparing the first element 10, and Figure 5 is a diagram illustrating the process of preparing the second element 20. The process of preparing the first element 10 and the process of preparing the second element 20 may be performed either first or in parallel. First, the process of preparing the first element 10 will be described with reference to Figures 2 to 4. 【0033】 First, a first substrate 11 on which an insulating layer 12 is formed is prepared (Figure 2(a)). An element portion 13 is formed within the insulating layer 12. Next, a connecting electrode pad 14, an inspection electrode pad 18, and an electrode pad connection portion 16 are formed on the first substrate 11 (Figure 2, pad formation process). More specifically, in the pad formation process, first, the connecting electrode pad 14 is formed on the surface 12a of the insulating layer 12 on the first substrate 11 (Figure 2(a)). Thus, forming element B (connecting electrode pad 14 in this example) on element A (first substrate 11 in this example) includes not only directly forming element B on element A, but also forming element B on element A via another element (insulating layer 12 in this example). Next, an insulating layer 15 is formed on the surface 12a of the insulating layer 12 so as to cover the connecting electrode pad 14 (Figure 2(b)). Next, the electrode pad connection portion 16 is formed on the surface 15a of the insulating layer 15. In this process, a through-hole 15b is formed in the insulating layer 15, and the electrode pad connection portion 16 is electrically connected to the connecting electrode pad 14 through the through-hole 15b. As the electrode pad connection portion 16 enters the through-hole 15b, a recess 16b is formed on the surface 16a of the electrode pad connection portion 16. Next, an inspection electrode pad 18 is formed on the electrode pad connection portion 16. In this process, as the inspection electrode pad 18 enters the recess 16b, a recess 18b is formed on the surface 18a of the inspection electrode pad 18. The inspection electrode pad 18 is electrically connected to the connecting electrode pad 14 via the electrode pad connection portion 16. 【0034】Figure 3 is a plan view of the connecting electrode pad 14, the inspection electrode pad 18, and the electrode pad connection portion 16. As shown in Figure 3, the connecting electrode pad 14 is formed in a square shape, for example, when viewed from a direction perpendicular to the main surfaces 11a and 11b of the first substrate 11 in a plan view. The inspection electrode pad 18 and the electrode pad connection portion 16 are formed in a rectangular shape, for example, in a plan view. In this example, the inspection electrode pad 18 is formed on the electrode pad connection portion 16. The inspection electrode pad 18 has an overlapping portion 18x that overlaps with the connecting electrode pad 14 in a plan view, and an outer portion 18y that is located outside the connecting electrode pad 14 in a plan view. That is, the inspection electrode pad 18 is formed such that, in a plan view, at least a part of the inspection electrode pad 18 (not the whole in this example) overlaps with the connecting electrode pad 14, and the outer portion 18y (the other part) is located outside the connecting electrode pad 14. The etching rate of the metal material constituting the electrode pad connection portion 16 is lower than that of the metal material constituting the inspection electrode pad 18. Furthermore, the hardness (Vickers hardness) of the electrode pad connection portion 16 is higher than that of the inspection electrode pad 18 (the electrode pad connection portion 16 is harder than the inspection electrode pad 18). Preferably, the Vickers hardness of the electrode pad connection portion 16 is, for example, 50 or more higher than that of the inspection electrode pad 18. The electrode pad connection portion 16 is formed from, for example, W, Ti, Ta, or nitrides thereof, while the inspection electrode pad 18 is formed from, for example, Al, Cu, or alloys thereof. 【0035】Following the pad formation process, an inspection probe P is brought into contact with the inspection electrode pad 18 to perform an electrical inspection (Figure 4(a), inspection process). In the inspection process, a needle-shaped inspection probe P is electrically connected to the inspection electrode pad 18 to perform an electrical inspection and determine whether the first element 10 passes or fails. As shown in Figure 4(a), in the inspection process, when the inspection probe P is pressed against the inspection electrode pad 18, a part of the inspection electrode pad 18 is pushed out and raised, and raised needle marks N (irregularities) remain on the surface 18a of the inspection electrode pad 18 after the inspection. In the example of Figure 4(a), the inspection probe P is in contact with the overlapping portion 18x of the inspection electrode pad 18, but the inspection probe P may also be in contact with the outer portion 18y of the inspection electrode pad 18. In this case, it is possible to suppress the stress from the inspection probe P from affecting the connecting electrode pad 14. 【0036】 Following the inspection process, at least the area of ​​the inspection electrode pad 18 that the inspection probe P contacted during the inspection process is removed (Figure 4(b), removal process). In this example, the entire inspection electrode pad 18 is removed. This exposes the electrode pad connection portion 16. The inspection electrode pad 18 is removed, for example, by wet etching. In the removal process, the etching rate of the metal material constituting the electrode pad connection portion 16 is lower than that of the metal material constituting the inspection electrode pad 18, so that the electrode pad connection portion 16 functions as a stopper to protect the connecting electrode pad 14 during etching. 【0037】Following the removal process, a bump 17 (electrical connection portion) is formed on the first substrate 11 (Figure 4(c), electrical connection portion formation process). In the electrical connection portion formation process, an insulating layer 31 is formed on the surface 15a of the insulating layer 15 so as to cover the electrode pad connection portion 16. At this time, the insulating layer 31 fits into a recess 16b formed on the surface 16a of the electrode pad connection portion 16. Subsequently, an opening 15c is formed in the insulating layer 15 and an opening 31a is formed in the insulating layer 31 so as to expose the connecting electrode pad 14, and a bump 17 is formed within the openings 15c and 31a so as to contact the connecting electrode pad 14. As shown in Figure 4(c), the bump 17 is provided in a position that does not overlap with the area removed in the removal process of the inspection electrode pad 18 (in this example, the entire inspection electrode pad 18) in a plan view. 【0038】 The process of preparing the second element 20 will be explained with reference to Figure 5. First, a second substrate 21 on which an insulating layer 22 is formed is prepared (Figure 5(a)). The element portion 23 is formed within the insulating layer 22. Next, a connecting electrode pad 24 is formed on the surface 22a of the insulating layer 22 on the second substrate 21 (Figure 5(a)). Next, an insulating layer 25 is formed on the surface 22a of the insulating layer 22 so as to cover the connecting electrode pad 24 (Figure 5(a)). Next, an insulating layer 32 is formed on the surface 25a of the insulating layer 25 (Figure 5(a)). Next, a bump 27 (electrical connection portion) is formed on the second substrate 21 (Figure 5(b), electrical connection portion formation process). In the electrical connection portion formation process, an opening 25c is formed in the insulating layer 25 so as to expose the connecting electrode pad 24, and an opening 32a is formed in the insulating layer 32, and a bump 27 is formed within the openings 25c and 32a so as to contact the connecting electrode pad 24. 【0039】Following the steps of preparing the first element 10 shown in Figures 2 to 4 and the second element 20 shown in Figure 5, the connection step shown in Figure 6(a) is carried out. In the connection step, the connection electrode pad 14 of the first element 10 is electrically connected to the connection electrode pad 24 of the second element 20 via the bumps 17 and 27. In the connection step, the bumps 17 and 27 are joined (integrated) with each other and joined to the connection electrode pads 14 and 24 by heating, melting, and solidifying them, for example. In the connection step, the first element 10 and the second element 20, and the first substrate 11 and the second substrate 21 are joined to each other by the bumps 17 and 27 so that they face each other via the bumps 17 and 27. 【0040】 Following the connection process, the coating process shown in Figure 6(b) is carried out. In the coating process, the bumps 17 and 27 are covered by the coating portion 30. In this example, the bumps 17 and 27 are covered by the insulating layers 31 and 32 and the underfill portion 33 by forming an underfill portion 33 between the insulating layers 31 and 32. The process of forming the insulating layer 31 on the insulating layer 15 and the process of forming the insulating layer 32 on the insulating layer 25 described above can also be considered as part of the coating process. In the coating process, the coating portion 30, including the insulating layers 31 and 32 and the underfill portion 33, is provided between the first element 10 and the second element 20. By the above process, the semiconductor device 1 is obtained. [Operation and Effects] 【0041】In the manufacturing method of the semiconductor device according to the embodiment, the bumps 17 and 27 (electrical connection portions) that connect the connection electrode pads 14 of the first element 10 to the second element 20 are covered by the covering portion 30 having insulating properties. Thereby, the exposed conductor portion (wiring portion) can be covered by the covering portion 30, and the reliability can be enhanced. On the other hand, when performing an electrical inspection by bringing a test probe into contact with an electrode pad as in the manufacturing method of the semiconductor device according to the embodiment, the needle marks N (concavities and convexities) raised on the surface of the electrode pad after the inspection remain. In such a case, for example, if the covering portion 30 is simply provided on the electrode pad, the covering portion 30 may not be well adhered due to the convex portions of the needle marks N, or voids may occur due to the concave portions of the needle marks N, and there is a possibility that the reliability may decrease. In contrast, in the manufacturing method of the semiconductor device according to the embodiment, in the removing step, at least the region where the test probe P has contacted in the inspection step in the inspection electrode pad 18 is removed. Thereby, the occurrence of the above-described situation can be suppressed, and the bumps 17 and 27 can be well covered by the covering portion 30, and the reliability can be enhanced. 【0042】 Before the removing step, a step of forming an insulating layer 15 on the connection electrode pad 14 is performed. Thereby, the exposure of the connection electrode pad 14 can be suppressed, and the deterioration of the connection electrode pad 14 due to oxidation or the like can be suppressed. Also, it is possible to suppress the adverse effect on the connection electrode pad 14 due to unnecessary etching in the removing step. 【0043】 In the removing step, the entire inspection electrode pad 18 is removed. Thereby, the needle marks N caused by the contact of the test probe P can be surely removed. 【0044】 In the connecting step, the first element 10 and the second element 20 are joined to each other by the bumps 17 and 27 such that the first substrate 11 and the second substrate 21 face each other via the bumps 17 and 27. When the first element 10 and the second element 20 are joined in this way, the flatness of the joining surface becomes particularly important. The manufacturing method of the semiconductor device according to the embodiment can be suitably applied in such a case. 【0045】In the connection process, the bumps 17 and 27 are provided at positions that do not overlap with the area removed in the removal process of the inspection electrode pads 18 when viewed in plan view (when viewed from a direction perpendicular to the main surfaces 11a and 11b of the first substrate 11). As a result, for example, there is no need to remove the electrode pad connection portion 16 or the insulating layer 31 in order to bring the bump 17 into contact with the connection electrode pad 14, so the process can be simplified. Also, there is a possibility that unevenness is formed on the connection electrode pad 14 by the removal process at positions overlapping the area removed in the removal process. By providing the bump 17 at a position that does not overlap with the area removed in the removal process, the bump 17 can be surely provided on a flat surface. 【0046】 In the coating process, the coating portion 30 is provided between the first element 10 and the second element 20. As a result, both the exposed conductor portion in the first element 10 and the exposed conductor portion in the second element 20 can be coated by the coating portion 30. 【0047】 In the pad forming process, the inspection electrode pad 18 is formed such that the overlapping portion 18x of the inspection electrode pad 18 overlaps with the connection electrode pad 14 when viewed in plan view. As a result, since the overlapping portion 18x of the inspection electrode pad 18 overlaps with the connection electrode pad 14, an increase in the area of the first substrate 11 can be suppressed. 【0048】 In the pad forming process, the inspection electrode pad 18 is formed such that the outer portion 18y of the inspection electrode pad 18 is located outside the connection electrode pad 14 when viewed in plan view. As a result, while securing the area of the inspection electrode pad 18, a wide area for the opening region for connecting the bump 17 in the connection electrode pad 14 can be secured. Also, for example, by bringing the inspection probe P into contact with the inspection electrode pad 18 at the outer portion 18y to perform inspection, it is possible to suppress the stress from the inspection probe P from affecting the connection electrode pad 14. 【0049】In the coating process, at least a portion of the electrode pad connection portion 16 is covered by the coating portion 30 (insulating layer 31). This further enhances reliability. It also suppresses the occurrence of short circuits through the electrode pad connection portion 16. 【0050】 The etching rate of the metal material constituting the electrode pad connection portion 16 is lower than that of the metal material constituting the inspection electrode pad 18. This allows the electrode pad connection portion 16 to function as a stopper to protect the connecting electrode pad 14 when the inspection electrode pad 18 is removed during the removal process. Furthermore, the electrode pad connection portion 16 is harder than the inspection electrode pad 18. This makes it difficult for the inspection probe P to penetrate the inspection electrode pad 18 during the inspection process, thus preventing the formation of needle marks on the electrode pad connection portion 16. 【0051】 In the pad formation process, the electrode pad connection portion 16 formed has a recess 16b on the surface 16a opposite to the first substrate 11, and in the coating process, the coating portion 30 (insulating layer 31) fits into the recess 16b. This suppresses the formation of a void in the space within the recess 16b, thereby suppressing connection failures caused by voids. [Modified example] 【0052】 In the first modified example shown in Figures 7 and 8, the first element 10 and the second element 20 are wire-bonded. In the first modified example, the second element 20 is made up of a second substrate 21. A connecting electrode 28 is formed on the main surface 21a of the second substrate 21. In the first modified example as well, the first substrate 11 and the second substrate 21 are arranged side by side in a direction perpendicular to the main surfaces 11a and 11b of the first substrate 11 (Figure 8(b)). 【0053】The step of preparing the first element 10 in the first modified example differs from the same step in the above embodiment in that the bump 17 is not formed (Figure 7). In the connection step of the first modified example, the connection electrode pad 14 of the first element 10 is electrically connected to the connection electrode 28 of the second element 20 by a wire W (electrical connection part) (Figure 8(a)). Also, the main surface 11b of the first substrate 11 is die-bonded to the main surface 21a of the second substrate 21 by a connection member 40, for example, which is a conductive resin. In the coating step of the first modified example, the entire wire W and the entire first element 10 are coated with molded resin 34 (Figure 8(b)). The molded resin 34, together with the insulating layer 31, constitutes the coating part 30. In the first modified example, a part of the electrode pad connection part 16 (the part exposed from the insulating layer 15) is covered by the molded resin 34. Even with this first modified example, reliability can be improved in the same way as in the above embodiment. Furthermore, since at least a portion of the electrode pad connection portion 16 is covered by the molded resin 34 (covering portion 30), reliability can be further enhanced. 【0054】 A method for manufacturing a semiconductor device according to a second modification will be described with reference to Figures 9 to 12. In the second modification, as shown in Figures 9 and 10(a), a connecting electrode pad 14, an inspection electrode pad 18, and an electrode pad connection portion 16 are formed in a planar shape on the main surface 11a of the first substrate 11. That is, the planar connecting electrode pad 14, inspection electrode pad 18, and electrode pad connection portion 16 are formed to be aligned on the main surface 11a. In other words, the inspection electrode pad 18 is formed so as not to overlap with the connecting electrode pad 14 in a plan view. As shown in Figure 9, the connecting electrode pad 14 is formed in a square shape, for example, in a plan view. The inspection electrode pad 18 is formed in a rectangular shape, for example, in a plan view. The electrode pad connection portion 16 is formed in a rectangular shape, for example, with a width narrower than the connecting electrode pad 14 and the inspection electrode pad 18 in a plan view, and electrically connects the connecting electrode pad 14 to the inspection electrode pad 18. The cross-sectional area of ​​the electrode pad connection portion 16 in a section perpendicular to the extending direction of the electrode pad connection portion 16 is smaller than the cross-sectional area of ​​the connecting electrode pad 14 and the inspection electrode pad 18 in a section perpendicular to the extending direction. 【0055】Figures 10 to 12 are diagrams illustrating a method for manufacturing a semiconductor device according to a second modified example. Figures 10 to 12 show cross-sections corresponding to the line A-A in Figure 9. The following describes the process of preparing the first element 10, but the process of preparing the second element 20 of the second modified example is the same as in the above embodiment. 【0056】 First, a connecting electrode pad 14, an inspection electrode pad 18, and an electrode pad connection portion 16 are formed on the first substrate 11 (Figure 10(a), pad formation process). Next, an insulating layer 15 is formed on the surface 12a of the insulating layer 12 so as to cover the connecting electrode pad 14, the inspection electrode pad 18, and the electrode pad connection portion 16 (over the connecting electrode pad 14, the inspection electrode pad 18, and the electrode pad connection portion 16) (Figure 10(b)). Subsequently, an opening 15d is formed in the insulating layer 15, exposing the inspection electrode pad 18 through the opening 15d (Figure 10(c)). In this example, in a plan view, the opening 15d is slightly larger than the inspection electrode pad 18, and the entire inspection electrode pad 18 is exposed through the opening 15d. 【0057】 Following the pad formation process, an inspection probe P is brought into contact with the inspection electrode pad 18 to perform an electrical inspection (Figure 11(a), inspection process). Following the inspection process, at least the area of ​​the inspection electrode pad 18 that was in contact with the inspection probe P during the inspection process is removed (Figure 11(b), removal process). As shown in Figure 11(b), in the removal process of the second modified example, the entire inspection electrode pad 18 is removed. At this time, a part of the electrode pad connection portion 16 (the connection portion with the inspection electrode pad 18) is removed by side etching. As a result, a recess 15e is formed in the insulating layer 15, as shown in Figure 11(b). 【0058】Following the removal process, bumps 17 (electrical connection parts) are formed on the first substrate 11 (Figure 11(c), electrical connection part formation process). Following the process of preparing the first element 10 and the process of preparing the second element 20, the connection electrode pads 14 of the first element 10 are electrically connected to the connection electrode pads 24 of the second element 20 via the bumps 17 and 27 (Figure 12(a), connection process). Following the connection process, the bumps 17 and 27 are covered with the covering part 30 (Figure 12(b), covering process). In the covering process, the insulating layer 31 (covering part 30) penetrates at least a portion of the recess 15e of the insulating layer 15 (Figure 11(c)). In this example, the insulating layer 31 penetrates a portion of the recess 15e. By the above steps, the semiconductor device 1 is obtained. 【0059】 The reliability can be improved in the second modification in the same way as in the above embodiment. In the pad formation step of the second modification, the inspection electrode pad 18 is formed so as not to overlap with the connection electrode pad 14 in a plan view. This makes it possible to suppress an increase in the thickness of the first element 10. In the coating step, the insulating layer 31 (coating portion 30) fits into the recess 15e of the insulating layer 15. This makes it possible to suppress the space within the recess 15e from becoming a void, and thus suppress connection failures caused by voids. 【0060】 A third modified example of a semiconductor device manufacturing method will be described with reference to Figures 13 to 15. Figures 13 to 15 show cross-sections corresponding to the line B-B in Figure 9. The third modified example differs from the second modified example in that, as shown in Figure 13(c), the opening 15d is slightly smaller than the inspection electrode pad 18 in a plan view, and only a portion of the central side of the inspection electrode pad 18 is exposed from the opening 15d. As shown in Figure 14(b), in the removal step of the third modified example, a recess 15e is formed in the insulating layer 15 by side etching in the portion adjacent to the inspection electrode pad 18 (the area removed in the removal step of the inspection electrode pad 18). In this example, an annular recess 15e is formed so as to surround the area where the inspection electrode pad 18 is placed in a plan view. In the coating step, the insulating layer 31 (coating portion 30) penetrates at least a portion of the recess 15e of the insulating layer 15 (Figure 14(c)). 【0061】The third modification also allows for improved reliability, similar to the above embodiment. In the coating process, the insulating layer 31 (coating portion 30) fits into the recess 15e of the insulating layer 15. This prevents the space within the recess 15e from becoming a void, thereby suppressing connection failures and other problems caused by voids. 【0062】 Figure 16 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fourth modification. The fourth modification differs from the second modification in that the first element 10 and the second element 20 are wire-bonded instead of bump-bonded. Reliability can be improved by the fourth modification as well as by the above embodiment. 【0063】 Figure 17 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment, and Figure 18 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fifth modified example. As described above, as shown in Figure 17, in the method for manufacturing a semiconductor device according to an embodiment, a connecting electrode pad 14 and an insulating layer 15 are formed on a first substrate 11 (insulating layer 12), an electrode pad connection portion 16 is formed on the connecting electrode pad 14 and the insulating layer 15, an inspection electrode pad 18 is formed on the electrode pad connection portion 16, an inspection process is performed using an inspection probe P, and the area of ​​the inspection electrode pad 18 that was in contact with the inspection probe P during the inspection process is removed. 【0064】 As shown in the fifth modified example in Figure 18, a connecting electrode pad 14 and an inspection electrode pad 18 may be formed on the electrode pad connection portion 16. In the semiconductor device manufacturing method according to the fifth modified example, an electrode pad connection portion 16 is formed on the first substrate 11 (insulating layer 12), and a connecting electrode pad 14 and an inspection electrode pad 18 are formed on the electrode pad connection portion 16. Subsequently, an insulating layer 15 is formed to cover the connecting electrode pad 14 and the inspection electrode pad 18. Subsequently, an opening 15f is formed in the insulating layer 15, and the inspection electrode pad 18 is exposed through the opening 15f. Subsequently, an inspection probe P is brought into contact with the inspection electrode pad 18 to perform an electrical inspection. Subsequently, the area of ​​the inspection electrode pad 18 that was in contact with the inspection probe P during the inspection process is removed. Reliability can be improved in the same way as in the above embodiment by the fifth modified example. 【0065】 This disclosure is not limited to the embodiments and modifications described above. For example, the materials and shapes of each component are not limited to those described above, but can be made from a variety of materials and shapes. 【0066】 In the removal process of the above embodiment and its modifications, the entire inspection electrode pad 18 was removed. However, it is sufficient that at least the area of ​​the inspection electrode pad 18 that the inspection probe P contacted during the inspection process is removed, and only a portion of the inspection electrode pad 18 may be removed. In the above embodiment, one of the insulating layers 31 and 32 may be omitted. The covering portion 30 may consist only of the insulating layers 31 and 32, and the underfill portion 33 may be omitted. The connection process and the covering process may be carried out in parallel. For example, the connection process and the covering process may be carried out so that the covering process is completed when the connection process is completed. 【0067】 In the above embodiments and modifications, the first element 10 and the second element 20 are described as being connected to each other in a chip state, but the first element 10 and the second element 20 may be connected to each other when at least one of the first element 10 and the second element 20 is in a wafer state. The pad formation process, inspection process and removal process in the above embodiments and modifications may be performed on the first element 10 (first substrate 11) in a wafer state. The semiconductor device 1 may be configured to detect light incident from the second substrate 21 side. The semiconductor device 1 is not limited to an imaging device, but may be other semiconductor devices such as a magnetic sensor. 【0068】 1... Semiconductor device, 10... First element, 20... Second element, 11... First substrate, 11a, 11b... Main surface, 15... Insulating layer, 21... Second substrate, 14... Connecting electrode pad, 15e... Recess, 16b... Recess, 16... Electrode pad connection part, 16a... Surface, 17, 27... Bump (electrical connection part), 18... Inspection electrode pad, 30... Covering part, P... Inspection probe, W... Wire (electrical connection part).

Claims

1. A method for manufacturing a semiconductor device comprising: a pad forming step of forming a connecting electrode pad, an inspection electrode pad, and an electrode pad connection portion for electrically connecting the connecting electrode pad to the inspection electrode pad on the first substrate; an inspection step of performing an electrical inspection by bringing an inspection probe into contact with the inspection electrode pad after the pad forming step; a removal step of removing at least the area on the inspection electrode pad that was in contact with the inspection probe in the inspection step after the inspection step; a connection step of electrically connecting the connecting electrode pad to the second element via an electrical connection portion after the removal step; and a coating step of covering at least the electrical connection portion with an insulating coating portion after the removal step.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming an insulating layer on the connecting electrode pad before the removal step.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the entire inspection electrode pad is removed in the removal step.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein in the connection step, the first element and the second element are joined to each other by the electrical connection portion such that the first substrate and the second substrate face each other via the electrical connection portion.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein in the connection step, the electrical connection portion is provided in a position that does not overlap with the area removed in the removal step on the inspection electrode pad when viewed from a direction perpendicular to the main surface of the first substrate.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein in the coating step, the coating portion is provided between the first element and the second element.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein in the coating step, at least a portion of the electrode pad connection portion is covered by the coating portion.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein in the pad forming step, the inspection electrode pad is formed such that, when viewed from a direction perpendicular to the main surface of the first substrate, at least a portion of the inspection electrode pad overlaps with the connecting electrode pad.

9. The method for manufacturing a semiconductor device according to claim 8, wherein in the pad forming step, the inspection electrode pad is formed such that, when viewed from a direction perpendicular to the main surface of the first substrate, a portion of the inspection electrode pad is located outside the connecting electrode pad.

10. The method for manufacturing a semiconductor device according to claim 8 or 9, wherein the etching rate of the metal material constituting the electrode pad connection portion is lower than the etching rate of the metal material constituting the inspection electrode pad.

11. The method for manufacturing a semiconductor device according to any one of claims 8 to 10, wherein the electrode pad connection portion formed in the pad forming step has a recess on the surface opposite to the first substrate, and in the coating step, the coating portion fits into the recess.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein in the pad forming step, the inspection electrode pad is formed such that it does not overlap with the connecting electrode pad when viewed from a direction perpendicular to the main surface of the first substrate.

13. A method for manufacturing a semiconductor device according to claim 12, further comprising the step of forming an insulating layer over the connecting electrode pad, the inspection electrode pad and the electrode pad connection portion after the pad forming step and before the removal step, wherein in the removal step, a recess is formed in the insulating layer when at least the area of ​​the inspection electrode pad that has been in contact with the inspection probe in the inspection step is removed, and in the coating step, the coating portion fits into the recess.

14. The method for manufacturing a semiconductor device according to claim 13, wherein in the removal step, when at least the area of ​​the inspection electrode pad that the inspection probe contacted in the inspection step is removed, at least a part of the electrode pad connection portion is removed, thereby forming the recess in the insulating layer.

15. The method for manufacturing a semiconductor device according to claim 13 or 14, wherein in the removal step, when at least the area of ​​the inspection electrode pad that the inspection probe contacted in the inspection step is removed, the recess is formed in the insulating layer in a portion adjacent to the area of ​​the inspection electrode pad that was removed in the removal step.

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