Reference voltage generation circuit and reference voltage generation method

Abstract

A reference voltage generation circuit (4) comprises: a transistor-characteristic voltage generation circuit (10) that comprises, inter alia, a transistor element group (NPN bipolar transistors (Q1 and Q2)) constituted by two types of transistor elements having different conduction current densities, and that generates a transistor-characteristic voltage (band gap reference voltage (Vbgr)); and a stress-compensation current generation circuit (20) that generates a stress-compensation current (Icompout) of which the direction and / or magnitude is changed on the basis of the direction and / or magnitude of stress applied to a semiconductor substrate. The transistor-characteristic voltage generation circuit (10) generates a voltage corresponding to the stress-compensation current by using a voltage drop caused by the stress-compensation current of a resistance element (R1a), and generates a reference voltage (Vref) by adding the voltage drop to or subtracting the voltage drop from the transistor-characteristic voltage.

Description

Reference Voltage Generation Circuit and Reference Voltage Generation Method 【0001】 The present disclosure relates to a reference voltage generation circuit and a reference voltage generation method using a semiconductor bandgap voltage. 【0002】 Lithium-ion batteries are used in various applications as secondary batteries with high energy density. In particular, in electric vehicles that require a large capacity, they are used as lithium-ion battery packs composed of a plurality of battery cells combined in series or in parallel. 【0003】 An electric vehicle is equipped with a battery management system that controls the charging and discharging of a lithium-ion battery pack. As one of the functions of the battery management system, there is an estimation of the state of charge (SOC) of each battery cell. For this estimation of the state of charge, highly accurate voltage measurement is required, and the highly accurate voltage measurement must be maintained for a period of about 20 years, which is the product life cycle of an electric vehicle. 【0004】 The voltage measurement of a lithium-ion battery pack is performed by an AD converter (Analog to Digital converter) installed inside a battery monitoring IC of the battery management system. Generally, the AD converter is supplied with a predetermined reference voltage having a certain voltage value from a reference voltage generation circuit separately installed inside the battery monitoring IC, and this reference voltage determines the measurement accuracy of the voltage measurement of the lithium-ion battery pack. To achieve highly accurate voltage measurement, it is necessary to be supplied stably regardless of temperature, and it is also necessary to be supplied stably over the product life cycle. 【0005】 In order to stably supply a predetermined reference voltage regardless of temperature, a reference voltage generation circuit using a semiconductor bandgap voltage is known. Generally, a reference voltage generation circuit using a semiconductor bandgap voltage has two types of transistor elements with different conduction current densities inside, and outputs a transistor characteristic voltage generated based on the difference in conduction current density as a reference voltage. 【0006】Incidentally, semiconductor substrates are generally sealed with a molding material such as epoxy resin and shipped as IC chip products. At that time, a stress of a certain direction and magnitude is applied to the semiconductor substrate due to the sealing with the molding material, and it is known that at least one of the direction and magnitude of this stress changes due to the thermal deformation of the molding material. In the following description of this specification, we will mainly deal with expansion and compression as directions of stress, and will simply refer to these as stresses, but it is known that shear stress is another type of stress that can be applied to semiconductor substrates. 【0007】 In general, it is known that in transistor elements manufactured on semiconductor substrates, the current values ​​at each terminal change in response to the presence or absence of stress in the molding material mentioned above. When the current values ​​at each terminal change, even a reference voltage generation circuit that previously supplied a stable reference voltage regardless of temperature under a certain stress application state will change to output a reference voltage that is not stable with respect to temperature. 【0008】 Regarding the change in the reference voltage in response to the presence or absence of stress and its changes, a reference voltage generation circuit such as the one disclosed in Patent Document 1 has been proposed. Specifically, this method involves combining a transistor characteristic voltage generation circuit having two types of NPN bipolar transistors as transistor elements with a transistor characteristic voltage generation circuit having two types of PNP bipolar transistors as transistor elements to create a reference voltage generation circuit. In this reference voltage generation circuit, the transistor characteristic voltages of both transistor characteristic voltage generation circuits are added together and output as a reference voltage. Even when there is a change in the stress application state, the changes in the two transistor characteristic voltages are in opposite directions, and by canceling out the changes in both, a stable reference voltage can be obtained regardless of temperature. 【0009】 U.S. Patent Application Publication No. 2014 / 0285175 【0010】RCJaeger, et al., "Characterization of residual stress levels in complementary bipolar junction transistors on (100) silicon", IEEE Bipolar / BiCMOS Circuits and Technology Meeting, pp16-28, Oct., 2015 【0011】 However, if we consider, for example, the change in terminal current with respect to stress of an NPN bipolar transistor shown in Fig. 3 of Non-Patent Document 1 and the change in terminal current with respect to stress of a PNP bipolar transistor shown in Fig. 4, the characteristics of these two transistors may not be inverse. This is because the design values ​​for the physical structure of bipolar transistors and the dimensions of the terminal parts differ according to the design rules of each manufacturing plant. Furthermore, due to manufacturing variations in bipolar transistors, differences in the characteristic changes with respect to stress occur between NPN bipolar transistors and PNP bipolar transistors even for individual IC chips. Due to these circumstances, it is difficult to obtain a stable reference voltage regardless of temperature for all individual IC chips in mass production using the solution disclosed in Patent Document 1. 【0012】 Therefore, the present disclosure aims to provide a reference voltage generation circuit and a reference voltage generation method that output a more stable reference voltage regardless of the stress and temperature experienced by the semiconductor substrate than conventional methods. 【0013】To achieve the above objective, a reference voltage generation circuit according to one embodiment of the present disclosure is a reference voltage generation circuit formed on a semiconductor substrate and generating a reference voltage, comprising a group of transistor elements composed of two types of transistor elements with different conduction current densities and a group of resistor elements, and a transistor characteristic voltage generation circuit that generates a transistor characteristic voltage based on the difference in conduction current densities of the two types of transistor elements with different conduction current densities, and a stress compensation current generation circuit comprising a stress sensing transistor element having the same structure and material as the transistor elements constituting the group of transistor elements, and generating a stress compensation current whose direction and magnitude are changed based on at least one of the direction and magnitude of the stress applied to the semiconductor substrate, wherein the transistor characteristic voltage generation circuit generates a voltage corresponding to the stress compensation current by a voltage drop of at least a portion of the constituent elements of the transistor characteristic voltage generation circuit, and generates a reference voltage by adding or subtracting the voltage drop to the transistor characteristic voltage. 【0014】 To achieve the above objective, a reference voltage generation method according to one embodiment of the present disclosure is a method for generating a reference voltage using a circuit formed on a semiconductor substrate, comprising: a transistor characteristic voltage generation step of generating a transistor characteristic voltage based on the difference in conduction current density of two types of transistor elements having different conduction current densities; and a stress compensation current generation step of generating a stress compensation current using a stress-sensing transistor element manufactured in the same process as the two types of transistor elements, in which at least one of the direction and magnitude of the stress applied to the semiconductor substrate is changed, wherein in the transistor characteristic voltage generation step, a voltage corresponding to the stress compensation current is generated by a voltage drop of at least a portion of the constituent elements of the circuit that generates the transistor characteristic voltage, and the reference voltage is generated by adding or subtracting the voltage drop to the transistor characteristic voltage. 【0015】 This disclosure provides a reference voltage generation circuit and a reference voltage generation method that output a more stable reference voltage regardless of the stress and temperature experienced by the semiconductor substrate than conventional methods. 【0016】Figure 1 is a circuit diagram showing the configuration of a reference voltage generation circuit according to a reference example utilizing the bandgap voltage of a semiconductor. Figure 2 is a circuit diagram showing the configuration of a reference voltage generation circuit according to an embodiment utilizing the bandgap voltage of a semiconductor. Figure 3 is a circuit diagram showing a detailed configuration example of the current DAC circuit shown in Figure 2. Figure 4 is a flowchart showing the procedure of the reference voltage generation method according to the embodiment. 【0017】 The following will describe in detail, with reference to the examples and embodiments of this disclosure, using the drawings. The examples and embodiments described below are all specific examples of the examples and embodiments of this disclosure. The numerical values, types of circuit elements, performance and connection configurations, signals, steps, and step order shown in the following examples and embodiments are examples only and are not intended to limit this disclosure. Furthermore, the figures are not necessarily strictly illustrative. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified. "Connection" refers to an electrical connection, including not only cases where two circuit elements are directly connected, but also cases where two circuit elements are indirectly connected with another circuit element inserted between them. Furthermore, the reference numerals associated with circuit elements and signals may, depending on the context, be used as identifiers for circuit elements and signals, or as identifiers for characteristic values ​​of circuit elements and signals. For example, the resistance value of resistor R1a is denoted as resistance value R1a. 【0018】 Furthermore, "equivalent" means substantially the same size, and does not need to be exactly the same. Similarly, "identical structure and material" means substantially the same structure and material, for example, those manufactured using the same process in semiconductor manufacturing. 【0019】 To understand the features of this invention, we will first describe in more detail below the reference voltage generation circuit that utilizes the bandgap voltage of a semiconductor. 【0020】Figure 1 is a circuit diagram showing the configuration of a reference voltage generation circuit 2, which is a reference example utilizing the bandgap voltage of a semiconductor. The reference voltage generation circuit 2 consists only of a transistor characteristic voltage generation circuit 10 that utilizes the bandgap voltage of a semiconductor. The transistor characteristic voltage generation circuit 10 is placed between the power line and the ground line and includes diode-connected NPN bipolar transistors Q1 and Q2, resistors R1a, R1b, R1c and R2, an error amplifier Amp, and a pMOS (p-channel Metal Oxide Semiconductor) transistor Q3. 【0021】 In the following, we will assume that the resistors R1b and R1c have the same resistance value and are independent of temperature, and that the NPN bipolar transistors Q1 and Q2 are manufactured in the same process and have an emitter area ratio of 1:N. We will take up reference voltage generation circuit 2 as an example of the basic configuration of a reference voltage generation circuit and explain its operating principle. Specifically, we will explain the principle by which the reference voltage Vref0 [V] generated by reference voltage generation circuit 2 has a stable voltage value regardless of temperature. 【0022】 In the reference voltage generation circuit 2, the NPN bipolar transistors Q1 and Q2 are connected at their base and collector terminals, in a so-called diode connection. The NPN bipolar transistors Q1 and Q2 are an example of a group of transistor elements composed of two types of transistor elements with different conduction current densities. In addition, as long as the above-mentioned 1:N emitter area ratio is maintained, each of the NPN bipolar transistors Q1 and Q2 may be composed of multiple NPN bipolar transistors connected in parallel. 【0023】Furthermore, the error amplifier Amp outputs a bias voltage Vampout to the gate terminal of pMOS transistor Q3 so that nodes Vinp and Vinn, which are connected to the differential input of the error amplifier Amp, are adjusted to the same potential by a virtual short circuit of the error amplifier Amp. Since resistors R1b and R1c have the same resistance value, the collector currents of NPN bipolar transistors Q1 and Q2 are the same, and this value is defined as the bias current value Ibias [A]. In Figure 1, the bias current value Ibias [A] is illustrated by a single black arrow. Where two black arrows are placed side by side, it means twice the bias current value Ibias [A]. However, in this case, the base currents of NPN bipolar transistors Q1 and Q2 can be ignored. The same applies hereafter. 【0024】 Here, the collector current of a bipolar transistor is an example of the conduction current of a transistor element. Other examples of conduction currents include the drain current of a MOS transistor element. 【0025】 Generally, the temperature dependence of the voltage Vbe [V] between the base terminal and emitter terminal of an NPN bipolar transistor when a current proportional to absolute temperature, known as a PTAT (Proportional To Absolute Temperature) current, is conducted in addition to the collector current is known to be expressed by the following equation 1. 【0026】 【0027】 Here, T [K] is the absolute temperature, Tr [K] is an arbitrary reference temperature (constant), and Vg0 [V] is the bandgap voltage of the semiconductor substrate material (e.g., Si) at an absolute temperature of 0 [K]. However, in Equation 1, quadratic or higher terms relating to the absolute temperature T [K] are considered relatively small and ignored. Note that the argument expression Vbe(T) on the left side of Equation 1 represents the dependence of the voltage Vbe [V] between the base terminal and emitter terminal of an NPN bipolar transistor on the absolute temperature T [K], but the argument part is omitted in this text. Similarly, in the formulas described herein, the argument expression in parentheses represents the dependence of the argument variable on its parameter. 【0028】Furthermore, it is generally known that the relationship between the voltage Vbe between the base terminal and emitter terminal of an NPN bipolar transistor and the collector current can be expressed by the following equation 2. 【0029】 【0030】 Here, Ic [A] is the collector current of a typical NPN bipolar transistor, Is [A] is the reverse saturation current of a typical NPN bipolar transistor, kB [J / K] is the Boltzmann constant, and q [C] is the elementary charge. 【0031】 Now, in the reference voltage generation circuit 2, the bias current value Ibias [A], which is the magnitude of the current flowing through each branch of the NPN bipolar transistors Q1 and Q2, is obtained by dividing the voltage across the resistor R2 by the resistance value R2 [Ω]. At this time, considering that nodes Vinp and Vinn are adjusted to the same potential by the virtual short circuit of the error amplifier Amp, and taking into account the above equation 2, it can be expressed as shown in the following equation 3. 【0032】 【0033】Here, Vbex [V] (where x is either 1 or 2 corresponding to NPN bipolar transistors Q1 and Q2, and so on) is the voltage between the base terminal and emitter terminal of NPN bipolar transistors Q1 and Q2, and Isx [V] is the reverse saturation current of NPN bipolar transistors Q1 and Q2. The derivation of the final equation of Equation 3 takes advantage of the assumption that the reverse saturation current of an NPN bipolar transistor is directly proportional to the emitter area, and that NPN bipolar transistors Q1 and Q2 have an emitter area ratio of 1:N, that is, the ratio of their respective reverse saturation currents Is1 [A] and Is2 [A] is 1:N. Furthermore, focusing on the final equation of Equation 3, it can be seen that the parts other than the absolute temperature T [K] are constants, and the bias current value Ibias [A] in the reference voltage generation circuit 2 is, in principle, a current that does not depend on anything other than the absolute temperature T [K], i.e., the PTAT current. If the base currents of NPN bipolar transistors Q1 and Q2 are ignored, the bias current value Ibias [A] becomes the collector current value of NPN bipolar transistors Q1 and Q2, and in this case, equation 1 holds true. 【0034】 At this time, the reference voltage Vref0 [V] output from the reference voltage generation circuit 2 is obtained by adding the voltage Vbe1 [V] between the base terminal and emitter terminal of the NPN bipolar transistor Q1 to the voltage across both resistors R1a and R1b, and is expressed as shown in Equation 4 below using the bias current value Ibias [A]. 【0035】 【0036】 However, the resistance value R1 [Ω] in Equation 4 is expressed as shown in Equation 5 below, using the resistance value R1a [Ω] of resistor element R1a and the resistance value R1b [Ω] of resistor element R1b. 【0037】 【0038】 By transforming the above equation 4 considering equations 1, 2, and 3, the reference voltage Vref0 [V] output from the reference voltage generation circuit 2 is ultimately expressed in the following equation 6. 【0039】 【0040】The first term of the final formula of Equation 6 is a constant value independent of temperature. Considering that the part multiplied by the absolute temperature T [K] in the second term is a value independent of temperature, the output reference voltage Vref0 [V] becomes a straight line with a constant slope with respect to the absolute temperature T [K]. In particular, when either the resistance value R1 (that is, the resistance values of the resistance elements R1a and R1b (and R1c paired with R1b)) or the resistance value R2 can be adjusted, this adjustment function can be used to make the part multiplied by the absolute temperature T [K] in the second term of the final formula of Equation 6 zero. At this time, the reference voltage Vref0 [V] can be the bandgap voltage Vg0 [V] itself at 0 [K] of the semiconductor substrate material, and it will have a stable voltage value independent of the absolute temperature T [K]. 【0041】 Next, the influence on the reference voltage output from the transistor characteristic voltage generation circuit 10 inside the reference voltage generation circuit 2 due to the stress application state to the semiconductor substrate will be described in more detail. 【0042】For example, in the NPN bipolar transistors Q1 and Q2 inside the transistor characteristic voltage generation circuit 10 of the reference voltage generation circuit 2, as described above, the bias current value Ibias [A] coincides with the collector current, and it is suggested from Equation 3 that this has a constant value in principle regardless of the stress application state. Therefore, it is considered that the reverse saturation currents Is1 [A] and Is2 [A] change. Also, since the NPN bipolar transistors Q1 and Q2 are manufactured in the same process, it is considered that for the same stress, the reverse saturation currents Is1 [A] and Is2 [A] change at the same rate. At this time, focusing on the final equation of Equation 6, it can be seen that the reference voltage Vref0 [V] changes because the part multiplied by the absolute temperature T [K] in the second term changes with the change in the stress application state. In particular, using the adjustment function of either the resistance value R1 (that is, the resistance values of the resistance elements R1a and R1b (and R1c paired with R1b)) or the resistance value R2 as described above, in an IC chip where the part multiplied by the absolute temperature T [K] in the second term of the final equation of Equation 6 is adjusted to 0, when there is a change in the stress application state to the semiconductor substrate due to, for example, before and after the sealing process or deformation of the molding material after the sealing process, the part multiplied by the absolute temperature T [K] in the second term of the final equation of Equation 6 has a value different from 0, and thus the reference voltage Vref0 [V] changes to have a voltage value dependent on the absolute temperature T [K]. 【0043】 Let the stress applied to the semiconductor substrate be σ [N], and let Δ be the rate of change of the reverse saturation current when the stress σ [N] is applied to the NPN bipolar transistor Q1. Then, the bandgap reference voltage Vbgr [V] generated only by the operation of the transistor characteristic voltage generation circuit 10 when the stress σ is applied can be transformed as shown in Equation 7 below. 【0044】 【0045】 Is1_0 [A] in Equation 7 is the value of the reverse saturation current of the NPN bipolar transistor Q1 when the stress σ [N] is 0. However, in the derivation of the final equation of Equation 7, it is assumed that a certain real number a is sufficiently smaller than 1, and the following approximate equation of Equation 8 is used. 【0046】 【0047】 Furthermore, Vbgr[V] in Equation 7 is derived from the fact that Is1[A] in Vref0[V] in Equation 6 increased by the rate of change Δ. 【0048】 Focusing on the final equation of Equation 7, we can see that the first term on the right-hand side can be decomposed into the voltage generated by the transistor characteristic voltage generation circuit 10 represented by Equation 6 and the shift voltage due to stress σ in the second term. In this case, it can be seen that the shift voltage due to stress σ is approximately proportional to the rate of change Δ of the reverse saturation current Is1 [A] of the NPN bipolar transistor Q1. 【0049】 Next, as a typical embodiment of the present invention, the operating principle of the reference voltage generation circuit 4 will be explained with reference to Figure 2. Figure 2 is a circuit diagram showing the configuration of the reference voltage generation circuit 4 according to an embodiment that utilizes the bandgap voltage of a semiconductor. The reference voltage generation circuit 4 is a circuit formed on a semiconductor substrate (not shown) that generates a reference voltage Vref, and in addition to the transistor characteristic voltage generation circuit 10 shown in Figure 1, it includes a stress compensation current generation circuit 20 arranged between the power line and the ground line. The semiconductor substrate on which the transistor characteristic voltage generation circuit 10 and the stress compensation current generation circuit 20 are formed is sealed with a molding material such as epoxy resin, for example, and shipped as an IC chip product. 【0050】 The reference voltage generation circuit 4 has the same transistor characteristic voltage generation circuit 10 as the reference voltage generation circuit 2 in the reference example, and also incorporates a stress compensation current generation circuit 20. 【0051】 The stress compensation current generation circuit 20 includes an NPN bipolar transistor Qsense that multiplies the input current Icompin by a current gain, nMOS (n-channel MOS) transistors Q21a and Q21b that constitute a current mirror circuit, and a current DAC circuit 22, and outputs a stress compensation current Icompout[A] whose direction and magnitude are changed based on at least one of the direction and magnitude of the stress applied to the semiconductor substrate. The input current Icompin may be an internal current generated by a current source provided in the stress compensation current generation circuit 20, or it may be a current input from an externally provided current source. 【0052】 The stress compensation current Icomput[A] is shown by a thin black arrow in Figure 2, and is energized only through the resistor R1a inside the transistor characteristic voltage generation circuit 10. In other words, the stress compensation current Icomput[A] supplied from the stress compensation current generation circuit 20 is added to the current flowing through the pMOS transistor Q3 (magnitude 2 * Ibias; "*" indicates multiplication), and the resulting combined current flows through the resistor R1a. Subsequently, of this combined current, the portion corresponding to the stress compensation current Icomput[A] is diverted to the current mirror circuit (nMOS transistors Q21a and Q21b) of the stress compensation current generation circuit 20, while the remaining 2 * Ibias portion flows to the respective branches of the NPN bipolar transistors Q1 and Q2. 【0053】 As a result, in the resistive element R1a, in addition to the voltage drop 2 * Ibias * R1a [V] generated as a result of the operation of the transistor characteristic voltage generation circuit 10 alone, the voltage drop Vcomput [V] due to the stress compensation current Icomput [A] is added, resulting in the total voltage drop of the resistive element R1a. That is, the output reference voltage Vref [V] is the value obtained by adding the voltage drop Vcomput [V] due to the stress compensation current Icomput [A] of the resistive element R1a to the bandgap reference voltage Vbgr [V] generated as a result of the operation of the transistor characteristic voltage generation circuit 10 alone. At this time, the voltage drop Vcomput [V] is configured to change due to the stress applied to the semiconductor substrate so as to cancel out the deviation of the generated bandgap reference voltage Vbgr [V] due to the stress applied to the semiconductor substrate. 【0054】 The stress compensation current generation circuit 20 is configured as follows, as shown in Figure 2. 【0055】The stress compensation current generation circuit 20 has an NPN bipolar transistor Qsense, which is an example of a stress-sensing transistor element manufactured using the same process (here, the same structure and materials) as the NPN bipolar transistors Q1 and Q2 inside the transistor characteristic voltage generation circuit 10. The stress compensation current generation circuit 20 takes an arbitrary input current Icompin [A], multiplies it by the current gain of the NPN bipolar transistor Qsense, and then multiplies it by a real number k by the current DAC circuit 22 to output a stress compensation current Icompout [A]. 【0056】 Figure 3 is a circuit diagram showing a detailed configuration example of the current DAC circuit 22 shown in Figure 2. The current DAC circuit 22 has a first output section 22a and a second output section 22b, which have the same circuit configuration to generate stress-compensated currents Icomput (I_out1 and I_out2, respectively). The first output section 22a and the second output section 22b are each composed of pMOS transistors Q23a to Q23d that constitute a current mirror circuit and pMOS transistors Q24a to Q24c as gates controlled by a digital signal D_in<m-1:0>. It is desirable that the pMOS transistors Q23a to Q23c mirror the drain current of pMOS transistor Q23d with weights that are powers of 2. For example, the drain currents of pMOS transistors Q23a, ..., Q23b, and Q23c are 1 [times], ..., 2^-(m-2) [times], and 2^-(m-1) [times] of the drain current of pMOS transistor Q23d, respectively (where "^" represents exponentiation). In this case, the ratio k of the output currents I_out1 and I_out2 with respect to the input current I_in of the current DAC circuit 22 is determined by the digital signal D_in<m-1:0> and is expressed by the following equation 9. However, the bar symbol above D_in<m-1> etc. in equation 9 represents the inversion of the digital value 0 or 1. 【0057】 【0058】 The current DAC circuit 22 multiplies the input current I_in by a real number k (where k is a real number greater than or equal to zero) and outputs it as a stress-compensated current Icomput (I_out1 and I_out2). 【0059】 In this case, it is desirable that the real number k is variable, and may be made variable by controlling an external digital signal D_in<m-1:0> (where m is a positive integer) from a non-volatile memory (not shown). The non-volatile memory may be a component provided in the stress compensation current generation circuit 20. 【0060】 In this case, the current gain Qsense of an NPN bipolar transistor is an example of an equivalent circuit model parameter of a transistor element. Other examples of equivalent circuit model parameters include the transconductance of bipolar transistors and MOS transistors. 【0061】 Next, regarding the stress compensation current Icomput[A] output by the stress compensation current Icomput[A] configured as described above, the effect of the voltage drop Vcomput[V] caused by the stress compensation current Icomput[A] at the resistive element R1a on the voltage drop Vcomput[V] due to the stress applied to the semiconductor substrate will be explained below. 【0062】The NPN bipolar transistor Qsense inside the stress-compensated current generation circuit 20, like the NPN bipolar transistors Q1 and Q2 inside the transistor characteristic voltage generation circuit 10, experiences a change in collector current due to stress. This change in collector current causes a change in the current gain of the NPN bipolar transistor Qsense. Referring to Fig. 3 of Non-Patent Literature 1, in an NPN bipolar transistor, the rate of change of current gain with respect to stress is approximately equal to the rate of change of collector current. In other words, with respect to stress, there is almost no physical change that determines the base current, and the change in current gain is caused only by the physical change that determines the collector current. This can be explained by the fact that stress only affects the behavior of electrons, which are negatively charged carriers, and has little effect on the behavior of holes, which are positively charged carriers. Since an NPN bipolar transistor generates collector current using electrons as carriers, it can be generally derived that the rate of change of current gain is approximately equal to the rate of change of collector current. Consequently, when the same stress is applied to NPN bipolar transistors Q1, Q2, and Qsense, if the rate of change of the reverse saturation current of NPN bipolar transistors Q1 and Q2 is Δ, then the rate of change of the current gain of NPN bipolar transistor Qsense will also be approximately equal to Δ. Therefore, the voltage drop Vcomput when a stress σ [N] is applied can be expressed as shown in equation 10 below. 【0063】 【0064】 Here, β0 in equation 10 is the current gain of the NPN bipolar transistor Qsense when the stress σ [N] is 0. 【0065】 The principle by which the stress compensation current generation circuit 20 configured as described above cancels out the effect of the stress applied to the semiconductor substrate in the reference voltage generation circuit 4 will be explained below. 【0066】As described above, the reference voltage Vref [V] output from the reference voltage generation circuit 4 is the sum of the bandgap reference voltage Vbgr [V] generated as a result of the operation of the transistor characteristic voltage generation circuit 10 and the voltage drop Vcomput [V] due to the stress compensation current Icomput in the resistive element R1a. Taking equations 7 and 10 above into consideration, the reference voltage Vref [V] at this time can be calculated and expressed as shown in equation 11 below. 【0067】 【0068】Focusing on the final equation of Equation 11, the first term is the bandgap reference voltage Vbgr [V] generated as a result of the operation of the transistor characteristic voltage generation circuit 10 when the stress σ [N] is 0, the second term is the voltage drop Vcomput [V] due to the stress compensation current Icomput of the resistive element R1a when the stress σ [N] is 0, and the third term is the sum of the effects of the stress σ [N] on the reference voltage Vref [V] when it is applied to the NPN bipolar transistors Q1, Q2, and Qsense. At this time, the temperature characteristics of the input current Icompin [A] of the stress compensation current generation circuit 20 are selected and the variable real number k is adjusted so that the coefficient part multiplied by Δ in the third term becomes 0, that is, so that the effect is eliminated even when an unspecified stress σ [N] is applied. Furthermore, using the input current Icompin [A] of the selected stress compensation current generation circuit 20 and the real number k, the third term of the final equation of Equation 11 is set to 0 regardless of temperature, and the resistance value R1 (i.e., the resistance values ​​of the resistive elements R1a and R1b (and R1c which is paired with R1b)) or the resistance value R2 is made adjustable so that the sum of the voltages of the first and second terms of the final equation of Equation 11 has a stable value with respect to temperature. As a result, the reference voltage Vref [V] output from the reference voltage generation circuit 4 has a stable value regardless of the stress applied to the semiconductor substrate and the temperature. Referring to the final equation of Equation 11, the input current Icompin [A] is a factor that determines the value of the reference voltage Vref [V] by multiplying it by the resistance value R1a [Ω] of the resistor R1a. However, considering the manufacturing variations of the resistor R1a for each individual IC chip during mass production, the input current Icompin may be selected so that these variations do not affect the generation of the reference voltage Vref [V]. In other words, the input current Icompin [A] may be selected as a current inversely proportional to the resistance value R1a [Ω] of the resistor R1a. 【0069】In the above example, the voltage drop Vcomput [V] due to the stress compensation current Icomput in the resistor R1a was added to the transistor characteristic voltage. However, the stress compensation current Icomput [A] is a value whose direction and magnitude are changed based on at least one of the direction and magnitude of the stress applied to the semiconductor substrate. Depending on the direction of the stress applied to the semiconductor substrate, the resistor R1a and the stress compensation current generation circuit 20 may be connected such that the voltage drop Vcomput [V] due to the stress compensation current Icomput in the resistor R1a is subtracted from the transistor characteristic voltage. In other words, the real number k shown in Equation 9 may be a negative value. 【0070】 As described above, the reference voltage generation circuit 4 according to the embodiment is a circuit formed on a semiconductor substrate that generates a reference voltage Vref and comprises a group of transistor elements (NPN bipolar transistors Q1 and Q2) composed of two types of transistor elements with different conduction current densities and a group of resistor elements (resistor elements R1a, R1b, R1c, and R2), and a transistor characteristic voltage generation circuit 10 that generates a transistor characteristic voltage (bandgap reference voltage Vbgr) based on the difference in conduction current densities of the two types of transistor elements (NPN bipolar transistors Q1 and Q2) with different conduction current densities, and transistor elements (NPN bipolar transistors Q1 and Q2) that constitute the group of transistor elements The transistor characteristic voltage generation circuit 10 includes a stress-sensing transistor element (NPN bipolar transistor Qsense) having the same structure and material as the transistor characteristic voltage generation circuit 10, and a stress compensation current generation circuit 20 that generates a stress compensation current Icomput whose direction and magnitude are changed based on at least one of the direction and magnitude of the stress applied to the semiconductor substrate. The transistor characteristic voltage generation circuit 10 generates a voltage corresponding to the stress compensation current Icomput by the voltage drop of at least a portion of the constituent elements of the transistor characteristic voltage generation circuit 10 (voltage drop due to the stress compensation current Icomput of the resistor element R1a), and generates a reference voltage Vref by adding or subtracting the voltage drop to the transistor characteristic voltage. 【0071】As a result, in the transistor characteristic voltage generation circuit 10, a voltage corresponding to the stress compensation current Icomput is generated by the voltage drop due to the stress compensation current Icomput across the resistor element R1a, and the reference voltage Vref is generated by adding or subtracting this voltage drop to the transistor characteristic voltage. Consequently, the reference voltage Vref output from the reference voltage generation circuit 4 is a stable value regardless of the stress and temperature applied to the semiconductor substrate. In the reference voltage generation circuit 4, a stable value refers to a voltage value that is constant with respect to absolute temperature. 【0072】 Here, the stress compensation current generation circuit 20 generates the stress compensation current Icomput by multiplying the input current Icompin to the stress compensation current generation circuit 20, or the internal current multiplied by k (where k is a real number), by the equivalent circuit model parameter of the stress sensing transistor element (for example, k * current gain multiplier). As a result, the magnitude of the stress compensation current Icomput can be adjusted by the current gain of the stress sensing transistor element and the multiplier k of the stress compensation current generation circuit 20. 【0073】 Furthermore, the transistor elements constituting the transistor element group (NPN bipolar transistors Q1 and Q2), and the stress sensing transistor element (NPN bipolar transistor Qsense) are all NPN bipolar transistors, the conduction current is the collector current, and the equivalent circuit model parameter is the current gain of the NPN bipolar transistor. This realizes a reference voltage generation circuit 4 that utilizes the similarity between the rate of change of the current gain of the NPN bipolar transistor with respect to stress and the rate of change of the collector current. 【0074】 Furthermore, the reference voltage generation circuit 4 is equipped with a non-volatile memory, and the value of k is variable and may be determined by an m-bit (where m is a positive integer) digital signal (for example, D_in<m-1:0>) connected to the non-volatile memory. This allows the multiplier k of the stress compensation current generation circuit 20 to be adjusted by the value stored in the non-volatile memory, enabling trimming adjustment for each individual IC (i.e., the reference voltage generation circuit 4) during mass production. 【0075】 Next, a reference voltage generation method according to an embodiment will be described. 【0076】 Figure 4 is a flowchart showing the procedure for the reference voltage generation method according to the embodiment. 【0077】 Figure 4 shows the procedure for the reference voltage generation method according to the embodiment, that is, the operation procedure of the reference voltage generation circuit 4 shown in Figure 2. 【0078】 The reference voltage generation circuit 4 generates a reference voltage Vref using a circuit formed on a semiconductor substrate. This involves a transistor characteristic voltage generation step S10, which generates a transistor characteristic voltage (bandgap reference voltage Vbgr) based on the difference in conduction current density between two types of transistor elements with different conduction current densities, and a stress compensation current generation step S11, which generates a stress compensation current Icomput using a stress-sensing transistor element (NPN bipolar transistor Qsense) manufactured in the same process as the two types of transistor elements, in which at least one of the direction and magnitude of the stress applied to the semiconductor substrate is changed. In the transistor characteristic voltage generation step S10, a voltage corresponding to the stress compensation current Icomput is generated by the voltage drop of at least a portion of the constituent elements of the circuit that generates the transistor characteristic voltage (voltage drop due to the stress compensation current Icomput of the resistor element R1a) (S10a), and the reference voltage Vref is generated by adding or subtracting the voltage drop to the transistor characteristic voltage (S10b) (S10c). 【0079】 This enables a reference voltage generation method that outputs a more stable reference voltage regardless of the stress and temperature experienced by the semiconductor substrate than conventional methods. Steps S10 to S10c shown in Figure 4 may be performed simultaneously. In the reference voltage generation circuit 4 shown in Figure 2, steps S10 to S10c are performed simultaneously. 【0080】The reference voltage generation circuit and reference voltage generation method of this disclosure have been described above based on the reference examples and embodiments, but this disclosure is not limited to these reference examples and embodiments. Within the scope of this disclosure, various modifications to the reference examples and embodiments that a person skilled in the art could conceive, as long as they do not depart from the spirit of this disclosure, and other forms constructed by combining some of the components of the reference examples and embodiments, are also included. 【0081】 For example, the various MOS transistors used in the reference examples and embodiments may be replaced with bipolar transistors. 【0082】 The reference voltage generation circuit described herein can be used as a reference voltage generation circuit with suppressed characteristic variations, for example, as a reference voltage generation circuit used in an AD converter or voltage measuring instrument that requires high precision and high stability and is built into an IC chip product for measuring physical quantities. 【0083】 2,4 Reference voltage generation circuit 10 Transistor characteristic voltage generation circuit 20 Stress compensation current generation circuit 22 Current DAC circuit 22a First output section 22b Second output section Q1, Q2, Qsense NPN bipolar transistor Amp Error amplifier R1a, R1b, R1c, R2 Resistor element Q3, Q23a to Q23d, Q24a to Q24c pMOS transistor Q21a, Q21b nMOS transistor Vbgr Bandgap reference voltage Vref, Vref0 Reference voltage Icompin Input current Icompout Stress compensation current Vampout Bias voltage Ibias Bias current value

Claims

1. A reference voltage generation circuit formed on a semiconductor substrate and generating a reference voltage, comprising: a group of transistor elements composed of two types of transistor elements with different conduction current densities and a group of resistor elements, and a transistor characteristic voltage generation circuit that generates a transistor characteristic voltage based on the difference in conduction current densities of the two types of transistor elements with different conduction current densities; and a stress compensation current generation circuit comprising a stress sensing transistor element having the same structure and material as the transistor elements constituting the group of transistor elements, and generating a stress compensation current whose direction and magnitude are changed based on at least one of the direction and magnitude of the stress applied to the semiconductor substrate, wherein the transistor characteristic voltage generation circuit generates a voltage corresponding to the stress compensation current by a voltage drop of at least a portion of the constituent elements of the transistor characteristic voltage generation circuit, and generates a reference voltage by adding or subtracting the voltage drop to the transistor characteristic voltage.

2. The reference voltage generation circuit according to claim 1, wherein the stress compensation current generation circuit generates the stress compensation current by multiplying the input current to the stress compensation current generation circuit or an internal current multiplied by k by the equivalent circuit model parameters of the stress sensing transistor element.

3. The reference voltage generation circuit according to claim 2, wherein the transistor elements constituting the group of transistor elements and the stress sensing transistor elements are all NPN bipolar transistors, the conduction current is the collector current, and the equivalent circuit model parameter is the current gain of the NPN bipolar transistor.

4. The reference voltage generation circuit according to claim 2 or claim 3, further comprising a non-volatile memory, wherein the value of k is variable and its value is determined by an m-bit (where m is a positive integer) digital signal connected to the non-volatile memory.

5. A method for generating a reference voltage using a circuit formed on a semiconductor substrate, comprising: a transistor characteristic voltage generation step of generating a transistor characteristic voltage based on the difference in conduction current densities of two types of transistor elements having different conduction current densities; and a stress compensation current generation step of generating a stress compensation current using a stress-sensing transistor element manufactured in the same process as the two types of transistor elements, wherein the direction and magnitude of the stress applied to the semiconductor substrate are changed based on at least one of the direction and magnitude of the stress, wherein in the transistor characteristic voltage generation step, a voltage corresponding to the stress compensation current is generated by a voltage drop of at least a portion of the constituent elements of the circuit that generates the transistor characteristic voltage, and the reference voltage is generated by adding or subtracting the voltage drop to the transistor characteristic voltage.

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