Semiconductor module

Abstract

This semiconductor module includes a memory cube in which a plurality of memory chips are stacked and which has a via having a first diameter. Each of the plurality of memory chips includes internal wiring including an opening with a second diameter. Each of the plurality of memory chips is stacked while being offset from a reference position by a different shift amount in a cross-sectional view. The via is in contact with a part of the opening of each of the plurality of memory chips in the cross-sectional view.

Description

Semiconductor module

[0001] One embodiment of the present invention relates to a semiconductor module.

[0002] In recent years, electronic computers such as data centers include semiconductor modules including a stacked memory chip in which a plurality of memory chips are stacked, and a plurality of IC (Integrated Circuit) chips including an arithmetic processing circuit. The electronic computer can increase the capacity of the memory by using the semiconductor module and can process a large amount of data in data communication executed between each IC chip and each memory chip.

[0003] For example, Patent Documents 1 to 3, Non-Patent Documents 1 and 2 disclose semiconductor modules including a plurality of IC chips stacked using a plurality of through electrodes, a plurality of bumps, and the like.

[0004] U.S. Patent No. 9,851,401, U.S. Patent No. 9,960,080, U.S. Patent Application Publication No. 2024 / 0006381

[0005] M. Kawan et al., “New Cost-effective Via-last Approach by “One-step TSV” after Wafer Stacking for 3D Memory Applications,” 2019 IEEE 69th Electronic Components Technology Conference (ECTC), (USA) 2019, p. 1996-2002. M. Kawan et al., “One-step TSV process development for 4-layer wafer stacked DRAM,” 2021 IEEE 71st Electronic Components Technology Conference (ECTC), (USA) 2021, p. 673-679.

[0006] On the other hand, the semiconductor module manufacturing methods disclosed in Patent Document 1, Patent Document 2, Patent Document 3, Non-Patent Document 1, or Non-Patent Document 2 involve connecting adjacent IC chips using multiple through-electrodes and multiple microbumps and stacking them, or having different diameters (design values) of the through-electrodes of adjacent IC chips (i.e., different designs for adjacent IC chips). As a result, the manufacturing cost of the semiconductor module manufacturing method may increase, the semiconductor module may have connection defects due to misalignment of adjacent IC chips, and miniaturization of the semiconductor module may become difficult due to differences in the diameter of the through-electrodes.

[0007] In view of these problems, one embodiment of the present invention aims to provide a semiconductor module that can reduce manufacturing costs. Another embodiment of the present invention aims to provide a semiconductor module that can be reliably used over the long term.

[0008] A semiconductor module according to one embodiment of the present invention is a semiconductor module including a memory cube in which a plurality of memory chips are stacked, each of which has vias having a first diameter, each of which includes internal wiring including an opening of a second diameter, each of which is stacked offset from a reference position by different shift amounts in a cross-sectional view, and the via is in contact with a portion of the opening of each of the plurality of memory chips in a cross-sectional view.

[0009] The internal wiring pattern shapes of each of the aforementioned memory chips may be identical.

[0010] The plurality of memory chips are stacked along a third direction perpendicular to the second direction, parallel to the planes formed by the first direction and the second direction perpendicular to the first direction, and at least a portion of the openings of each of the plurality of memory chips may overlap in a top view.

[0011] The shift amount may increase along the third direction from the uppermost memory chip to the lowermost memory chip.

[0012] The semiconductor module according to claim 3, wherein, in a cross-sectional view, the length of the via along the first direction decreases along the third direction from the uppermost memory chip to the lowermost memory chip.

[0013] The aforementioned reference position may be the center of the via.

[0014] Each of the plurality of memory chips may be stacked offset from the reference position in the first or second direction.

[0015] Each of the plurality of memory chips may be stacked with an offset, where the shift amount is the rotation angle around the reference position.

[0016] The system further includes a semiconductor chip for driving the plurality of memory chips, and a redistribution layer including a wiring layer configured to connect the plurality of memory chips along the first and second directions, wherein the plurality of memory chips are arranged between the semiconductor chip and the redistribution layer, and may be electrically connected to the semiconductor chip and the redistribution layer.

[0017] The memory cube comprises a plurality of memory cubes, each having vias having the first diameter, and the plurality of memory chips are stacked on top of each other. The vias of adjacent memory cubes may be electrically connected and superimposed.

[0018] Of the second diameters of the openings in each of the plurality of memory chips, the second diameter of at least one opening may be larger than the first diameter.

[0019] The first diameter may be larger than the second diameter of at least one of the second diameters of the openings in each of the plurality of memory chips.

[0020] The first diameter may be the same as the second diameter.

[0021] These are perspective views and plan views showing the configuration of a semiconductor module according to the first embodiment of the present invention. This is an end view showing the cross-sectional structure of the end of a semiconductor module along the line A1-A2 shown in Figure 1. This is a plan view showing the configuration of internal wiring, openings, and vias of each IC chip according to the first embodiment of the present invention. This is an enlarged end view of a part of the cross-sectional structure of the end of an IC chip according to the first embodiment of the present invention. This is a block diagram showing the configuration of a semiconductor module according to the first embodiment of the present invention. This is a plan view showing the manufacturing method of a semiconductor module according to the first embodiment of the present invention. This is an end a perspective view showing the configuration of a semiconductor module according to the second embodiment of the present invention. This is an end view showing the cross-sectional structure of the end of a semiconductor module along the line B1-B2 shown in Figure 10. This is a plan view showing the configuration of internal wiring, openings, and vias of each IC chip according to the second embodiment of the present invention. This is a perspective view showing the configuration of a semiconductor module according to the third embodiment of the present invention. This is an end view showing the cross-sectional structure of the end of a semiconductor module along the line C1-C2 shown in Figure 10. This is a plan view showing the configuration of internal wiring, openings, and vias of each IC chip according to the fourth embodiment of the present invention. This is a plan view showing the internal wiring, openings, and via configuration of each IC chip according to the fifth embodiment of the present invention. This is an enlarged end view showing a part of the end cross-sectional structure of the IC chip according to the fifth embodiment of the present invention.

[0022] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described below. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals (or numerals followed by a, b, etc.), and detailed explanations may be omitted as appropriate. Furthermore, the letters "First," "Second," etc., attached to each element are convenient indicators used to distinguish each element and have no further meaning unless specifically explained.

[0023] In one embodiment of the present invention, when a member or region is said to be "above (or below)" another member or region, unless otherwise specified, this includes not only the case where it is directly above (or directly below) the other member or region, but also the case where it is above (or below) the other member or region, that is, it includes the case where another component is included between them above (or below) the other member or region.

[0024] In one embodiment of the present invention, the first direction D1 intersects the second direction D2, and the third direction D3 intersects the first direction D1 and the second direction D2 (the D1D2 plane).

[0025] In one embodiment of the present invention, when the terms "identical" and "identical" are used, the terms "identical" and "identical" may include design tolerances. Furthermore, in one embodiment of the present invention, when design tolerances are included, the terms "approximately identical" and "approximately identical" may be used.

[0026] For example, in one embodiment of the present invention, as will be described in detail later, a semiconductor module (for example, semiconductor module 10, see Figure 1) includes a memory cube (for example, memory cube 100, see Figure 1) in which a plurality of IC chips 110 (for example, see Figure 2) are stacked, each having vias (for example, via 162, see Figure 3) having a diameter W1 (for example, see Figure 3). Each of the plurality of IC chips 110 includes internal wiring (for example, internal wiring 151, see Figure 3) that includes an opening (for example, opening 152, see Figure 3) with a diameter W2 larger than the diameter W1. Furthermore, each of the plurality of IC chips 110 is stacked offset from a reference position (for example, center line 163, see Figure 2) by different shift amounts (for example, shift amount OFA, shift amount OFB, see Figure 7) in a cross-sectional view. Furthermore, the vias are in contact with a portion of the openings of each of the plurality of IC chips 110 in a cross-sectional view. In this case, the diameter W2 of at least one of the diameters W2 of the openings in each of the multiple IC chips 110 may be larger than the diameter W1. Also, the diameter W1 may be larger than the diameter W2 of at least one of the diameters W2 of the openings in each of the multiple IC chips 110. Also, the diameter W1 may be the same as the diameter W2.

[0027] [First Embodiment] A semiconductor module 10 according to the first embodiment will be described with reference to Figures 1 to 9. The semiconductor module 10 includes a configuration in which the diameter W2 of at least one opening 152A of each of the openings 152 of a plurality of IC chips 110 is larger than the diameter W1 of the via 162 (opening 161). As an example, the semiconductor module 10 includes a configuration in which the diameter W2 of each of the openings 152 of a plurality of IC chips 110 is larger than the diameter W1 of the via 162 (opening 161). The semiconductor module 10 may also include a configuration in which the diameter W1 is the same as the diameter W2.

[0028] [1-1. Overview of Semiconductor Module 10] First, an overview of the semiconductor module 10 will be described with reference to Figures 1 to 3. Figure 1 is a perspective view showing the configuration of the semiconductor module 10, and a plan view showing multiple vias 162 superimposed on the planes parallel to the first direction D1 and the second direction D2 of the semiconductor chip 200. Figure 2 is an end view showing the cross-sectional structure of the end of the semiconductor module 10 along A1-A2 shown in Figure 1. Figure 3 is a plan view showing the configuration of the internal wiring 151, openings 152 and vias 162 of the IC chip 110 included in the semiconductor module 10. The IC chips 110A, 110B, 110C, and 110S shown in Figure 3, which include a portion of via 162 and internal wiring 151A, a portion of via 162 and internal wiring 151B, a portion of via 162 and internal wiring 151C, and a portion of via 162 and internal wiring 151S, would normally overlap in a plan view. However, for the sake of clarity in the drawing and to make it easier to understand that the IC chips 110A, 110B, and 110C are offset from each other (stacked, joined), they are shown offset from each other for convenience.

[0029] As shown in Figure 1, Figure 2, or Figure 3, the semiconductor module 10 includes at least a via 162 having a diameter W1 and positioned in contact with an opening 161, a memory cube 100 in which a plurality of IC chips 110 are stacked along a third direction D3, and a semiconductor chip 200. Each of the plurality of IC chips 110 also includes internal wiring 151 including an opening 152 with a diameter W2 larger than the diameter W1. The semiconductor module 10 may also include a redistribution layer 300. The diameter W1 may be referred to as the first diameter, and the diameter W2 may be referred to as the second diameter.

[0030] For example, as shown in Figure 1, the length of the semiconductor module 10 along the first direction D1 is length L1, and the length of the semiconductor module 10 along the second direction D2 is length L2. Similarly to the lengths L1 and L2 of the semiconductor module 10, the length of each IC chip 110 along the first direction D1 is length L1, and the length of each IC chip 110 along the second direction D2 is length L2.

[0031] The memory cube 100 is provided between the semiconductor chip 200 and the redistribution layer 300, and is electrically connected to the semiconductor chip 200 and the redistribution layer 300.

[0032] As shown in Figure 2, each of the multiple IC chips 110 is stacked with a virtual center line 163 as the reference point, offset by different amounts from the center line 163 in an end-face view (cross-sectional view). For example, the virtual center line 163 is a line extended parallel to the virtual line along the third direction D3, from the center of the opening 161 on the first surface 102A of the uppermost IC chip 110A along the third direction D3 among the multiple stacked IC chips 110. Also, the center of the opening 161 coincides with the center of the via 162. As an example, the opening 161 in the semiconductor module 10 is circular, and the center line 163 is a virtual line extended from the center of the circle along the third direction D3, but the opening 161 is not limited to a circular shape. For example, the opening 161 may be a polygon such as a triangle, square, or hexagon. For example, if the opening 161 is polygonal, the center line 163 is a virtual line extending from the center of the polygon along the third direction D3.

[0033] For example, as shown in Figure 3, IC chip 110A is positioned with a shift amount OFA along the first direction D1 from the reference position, center line 163; IC chip 110B is positioned with a shift amount OFB on the opposite side of the shift amount OFA along the first direction D1 from the reference position, center line 163; and IC chip 110C is positioned with a shift amount OFC on the opposite side of the shift amount OFB along the first direction D1 from the reference position, center line 163. Furthermore, IC chips 110C, 110B, and 110A are stacked in this order on the second surface 104S of semiconductor chip 200 (IC chip 110S) along the third direction D3.

[0034] For example, the shift amount OFC is greater than the shift amount OFB, and the shift amount OFB is greater than the shift amount OFA. In other words, the shift amount increases as you move along the third direction D3 from the top IC chip 110A to the bottom IC chip 110C.

[0035] Furthermore, each of the multiple IC chips 110 is formed using a photomask with the same layout design. That is, the openings 152, internal wiring 151, etc., have the same pattern shape. Therefore, in an end view (cross-sectional view), the openings 152 and internal wiring 151 contained in each of the multiple IC chips 110 overlap each other.

[0036] The opening 161 is formed in a single drilling step so as to penetrate through the multiple IC chips 110. The via 162 is formed to be in contact with the opening 161. Therefore, in an end view (cross-sectional view), the via 162 is in contact with a portion of each of the openings 152 of the multiple IC chips 110.

[0037] Furthermore, as shown in Figure 2 or Figure 3, via 162 includes vias 167A, 167B, and 167C. Via 167A overlaps with and contacts internal wiring 151A, via 167B overlaps with and contacts internal wiring 151B, and via 167C overlaps with and contacts internal wiring 151C. A portion of via 162 overlaps with and contacts internal wiring 151S without overlapping with internal wirings 151A, 151B, and 151C.

[0038] In other words, the semiconductor module 10 includes a configuration in which openings 152 and internal wiring 151 having the same pattern shape overlap each other between multiple IC chips 110, and a configuration in which multiple IC chips 110 are offset from each other. Therefore, the multiple IC chips 110 (each with internal wiring 151) are electrically connected to each other using vias 162 that are in contact with openings 161 formed in a single opening process.

[0039] As a result, the productivity of the memory cube 100 is improved. Therefore, the manufacturing cost of the semiconductor module 10 can be reduced.

[0040] In addition, since the semiconductor module 10 includes a configuration in which a plurality of IC chips 110 are laminated in advance with an offset from each other, it is possible to suppress making the opening 161 larger than necessary, and the plurality of IC chips 110 can be electrically connected to each other using the via 162 that contacts the opening 161. Further, even when the positions of the lamination of the plurality of IC chips 110 are displaced, a displacement at a position less than the diameter W1 of the opening 161 hardly affects the connection between the via 162 and the internal wiring 151 of each of the plurality of IC chips 110. Therefore, the closer the IC chip 110 is to the semiconductor chip 200 along the third direction D3, the larger the shift amount may be.

[0041] As a result, the semiconductor module 10 can suppress non-connection and disconnection between the plurality of IC chips 110. That is, the semiconductor module 10 can maintain reliability without impairing the long-term reliability of the semiconductor module 10.

[0042] Hereinafter, each component will be described.

[0043] [1-1-1. Outline of Memory Cube 100] The outline of the memory cube 100 will be described with reference to FIGS. 1 to 3. Configurations that are the same as or similar to those in FIGS. 1 to 3 described in "1-1. Outline of Semiconductor Module 10" will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 3 described in "1-1. Outline of Semiconductor Module 10" may be omitted.

[0044] As described in "1-1. Outline of Semiconductor Module 10", the memory cube 100 includes a configuration in which three IC chips 110, namely, IC chips 110A, 110B, and 110C, are laminated in order from the side closer to the second surface 104S of the semiconductor chip 200 (IC chip 110S) along the third direction D3. For example, the memory cube 100 includes a function of storing received data and a function of transmitting stored data.

[0045] If multiple IC chips 110 are not distinguishable from each other, the IC chip is referred to as IC chip 110. If multiple IC chips 110 are distinguishable from each other, the IC chips 110 are referred to as IC chip 110A, IC chip 110B, IC chip 110C, etc. Similarly to multiple IC chips 110, if multiple internal wirings 151 and multiple openings 152 are not distinguishable from each other, the multiple internal wirings and multiple openings 152 are referred to as multiple internal wirings 151 and multiple openings 152. If multiple internal wirings 151 and multiple openings 152 are distinguishable from each other, the multiple internal wirings 151 are referred to as internal wirings 151A, 151B, 151C, and the multiple openings 152 are referred to as openings 152A, 152B, 152C. Note that the IC chip 110 included in the memory cube 100 may be referred to as a memory chip, while the IC chip 110 included in devices other than the memory cube 100 may simply be referred to as an IC chip.

[0046] As will be described in detail later, each of the multiple IC chips 110 includes a transistor layer 130 and a wiring layer 150. The transistor layer 130 includes a semiconductor substrate 170, but for the sake of explanation, the transistor layer 130 and the semiconductor substrate 170 are shown separately in Figure 2. Also, as will be described in detail later, the wiring layer 150 includes a multilayer wiring structure in which through electrodes, wiring and insulating layers are alternately stacked. For example, the wiring layer 150 includes internal wiring 151 including openings 152. The number of layers of multilayer wiring in the wiring layer 150 can be appropriately changed depending on the specifications and application of the semiconductor module 10. In this specification and drawings, the semiconductor substrate 170 (170A, 170B, 170C, 170D, 170E and 170S) is shown as a uniform layer for clarity and to facilitate understanding of the present invention, but it may also include insulating layers for element isolation and electrical insulation from vias, embedded wiring within the substrate, decoupling capacitance elements, etc.

[0047] For example, the IC chip 110A includes a first surface 102A parallel to the first direction D1 and the second direction D2, a second surface 104A opposite to the first surface 102A with respect to the third direction D3, a semiconductor substrate 170A, a transistor layer 130A, and a wiring layer 150A. The IC chip 110B includes a first surface 102B parallel to the first direction D1 and the second direction D2, a second surface 104B opposite to the first surface 102B with respect to the third direction D3, a semiconductor substrate 170B, a transistor layer 130B, and a wiring layer 150B. As shown in FIG. 2, the IC chip 110C includes a first surface 102C, a second surface 104C, a semiconductor substrate 170C, a transistor layer 130C, and a wiring layer 150C corresponding to the IC chips 110A and 110B, respectively.

[0048] For example, techniques such as welding (Fusion Bonding) and silicon direct bonding (Silicon Direct Bonding (SDB)) can be used for laminating (bonding) the IC chips 110 to each other. Welding and silicon direct bonding are techniques used in the relevant technical field, and detailed descriptions are omitted here. For example, the joining of the IC chips 110 such that their wiring layers 150 face each other is denoted as Face to Face Fusion (F2F). For example, the joining of the IC chips 110 such that the semiconductor substrates 170 included in their transistor layers 130 face each other is denoted as Back to Back Fusion (B2B). For example, the joining of the IC chips 110 such that the wiring layer 150 and the semiconductor substrate 170 included in the transistor layer 130 face each other is denoted as Face to Back Fusion (F2B).

[0049] Also, for example, a mounting structure in which the semiconductor substrate side of the IC chip 110 is electrically connected to the semiconductor chip 200 and the stacking direction is upward along the third direction D3 is denoted as face-up mounting. On the other hand, for example, a mounting structure in which the wiring layer side of the IC chip 110 is electrically connected to the semiconductor chip 200 and the stacking direction is downward along the third direction D3 is denoted as face-down mounting.

[0050] The second face 104A of IC chip 110A is bonded to the first face 102B of IC chip 110B, the second face 104B of IC chip 110B is bonded to the first face 102C of IC chip 110C, and the second face 104C of IC chip 110C is bonded to the second face 104S of IC chip 110S. In other words, the memory cube 100 includes F2B bonded IC chips 110A, 110B, and 110C, IC chip 110C is F2F bonded to semiconductor chip 200, and the memory cube 100 is face-down mounted on semiconductor chip 200.

[0051] The number of stacked IC chips 110 in the memory cube 100, the bonding and mounting structure are examples only, and the number of stacked IC chips 110 in the memory cube 100, the bonding and mounting structure are not limited to the bonding and mounting structure shown in Figure 2. The number of stacked IC chips 110, the bonding and mounting structure can be appropriately selected based on the specifications and application of the semiconductor module 10, within the limits that do not deviate from the configuration and manufacturing method of the semiconductor module 10.

[0052] [1-1-2. Overview of Semiconductor Chip 200 and Redistribution Layer 300] An overview of the semiconductor chip 200 and redistribution layer 300 will be described with reference to Figures 1 to 3. Configurations identical or similar to those described in Figures 1 to 3 in "1-1. Overview of Semiconductor Module 10" will be described as necessary, and descriptions of configurations identical or similar to those described in Figures 1 to 3 in "1-1. Overview of Semiconductor Module 10" may be omitted.

[0053] As described in "1-1. Overview of Semiconductor Module 10," the semiconductor chip 200 includes an IC chip 110S. The IC chip 110S includes a first surface 102S parallel to the first direction D1 and the second direction D2, a second surface 104S opposite to the first surface 102S with respect to the third direction D3, a semiconductor substrate 170S, a transistor layer 130S, and a wiring layer 150S. The semiconductor chip 200 includes a plurality of logic modules 211. The semiconductor chip 200 also has the function of driving memory modules 111 (see Figure 5) within a plurality of IC chips 110 using the plurality of logic modules 211. The semiconductor chip 200 may sometimes be referred to as a logic chip.

[0054] Although not shown in the diagram, for example, the semiconductor chip 200 may include multiple magnetic field coupled inter-chip interfaces (Through Chip Interface-IO, TCI-IO) capable of inductor communication. The multiple TCI-IOs are electrically connected to multiple memory modules 111 (see Figure 5) in the memory cube 100 using multiple vias 162.

[0055] For example, TCI-IO includes an inductor-communication-enabled configuration such as multiple inductors, a transmitting / receiving circuit, and a parallel / series conversion circuit. In this configuration, the inductors are electrically connected to the transmitting / receiving circuit, the transmitting / receiving circuit is electrically connected to the parallel / series conversion circuit, and the parallel / series conversion circuit is electrically connected to the memory module 111.

[0056] When the semiconductor chip 200 includes a configuration that enables inductor communication, the semiconductor module 10 may include a second semiconductor chip (not shown) stacked on the lower layer of the semiconductor chip 200 via an adhesive layer (not shown) along a third direction D3. For example, the second semiconductor chip includes a configuration that enables inductor communication similar to the semiconductor chip 200. For example, the second semiconductor chip includes a plurality of inductors (not shown) that can communicate with each other non-contactually with a plurality of inductors in the semiconductor chip 200.

[0057] The redistribution layer 300 includes a first surface 302 parallel to the first direction D1 and the second direction D2, and a second surface 304 opposite to the first surface 302 with respect to the third direction D3. The redistribution layer 300 also includes wiring 301, insulating layer 303, wiring 305, openings 308, and insulating layer 307. Depending on the application and specifications of the semiconductor module 10, the redistribution layer 300 has the function of electrically connecting a plurality of vias 162 exposed on the first surface 102A, and also reconnecting the electrical connections of the internal wiring 151 of each IC chip 110. The degree of freedom of electrical connection of each wiring (not shown) and internal wiring 151 within the semiconductor module 10 is increased by the redistribution layer 300.

[0058] Wiring 301 is in contact with and embedded in an opening 308 formed in the insulating layer 303. Wiring 301 is electrically connected to via 162. Wiring 305 is in contact with the insulating layer 303, covers the exposed wiring 301 in the insulating layer 303, and is electrically connected to wiring 301. Insulating layer 307 covers and is in contact with the insulating layer 303 where wiring 305 is not provided, and with wiring 305.

[0059] Via 162, wiring 301, and wiring 305 are supplied with control signals, data, power supply voltage, ground voltage, etc., and function as conductive paths.

[0060] [1-1-3. Overview of IC Chip 110] An overview of the IC chip 110 will be described with reference to Figure 4. Figure 4 is an enlarged end view of a part of the end cross-sectional structure of the IC chip 110. Components identical or similar to those in Figures 1 to 3 will be described as necessary, and descriptions of components identical or similar to those in Figures 1 to 3 may be omitted.

[0061] As explained in "1-1. Overview of Semiconductor Module 10" and as shown in Figure 4, the IC chip 110 includes a first surface 102 parallel to the first direction D1 and the second direction D2, a second surface 104 opposite to the first surface 102 with respect to the third direction D3, a transistor layer 130, and a wiring layer 150. The first surface 102 is the surface opposite to the surface on which the wiring layer 150 is arranged relative to the transistor layer 130, and the second surface 104 is the surface opposite to the surface on which the transistor layer 130 is arranged relative to the wiring layer 150.

[0062] For example, the transistor layer 130 includes a semiconductor substrate 170, an element isolation region 134, an activation region 135, a transistor 136, an insulating layer 137, part of the wiring 154, and a through electrode 131. For example, the semiconductor substrate 170 is a Si substrate or Si-wafer, and is referred to as a semiconductor substrate.

[0063] For example, the through electrode 131 is formed to penetrate the transistor layer 130 and is electrically connected to the wiring 154.

[0064] As described in "1-1-1. Overview of Memory Cube 100", the wiring layer 150 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the wiring layer 150 includes a portion of the wiring 154, an insulating layer 155, internal wiring 151, an insulating layer 157, an insulating layer 159, and wiring 156. The wiring 156 may be a through electrode.

[0065] For example, wiring 154 is provided through the insulating layer 137 and is electrically connected to the source or drain of transistor 136. For example, internal wiring 151 is provided through the insulating layer 155 and is electrically connected to wiring 154. For example, wiring 156 is provided through the insulating layer 159 and is electrically connected to internal wiring 151.

[0066] The wiring connections shown in Figure 4 are just examples, and the wiring connections are not limited to the configuration shown in Figure 4. The wiring connections can be changed as appropriate based on the application or specifications of the semiconductor module 10.

[0067] [1-2. Configuration of Semiconductor Module 10] The functional block configuration of the semiconductor module 10 will be described with reference to Figure 5. Figure 5 is a block diagram showing the configuration of the semiconductor module 10. Configurations identical or similar to those in Figures 1 to 4 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 4 may be omitted.

[0068] As explained in "1-1. Overview of Semiconductor Module 10" and as shown in Figure 5, the semiconductor module 10 includes a memory cube 100, a redistribution layer 300, and a semiconductor chip 200. The memory cube 100 is electrically connected to the redistribution layer 300 (memory cube 100 with redistribution layer 300).

[0069] The memory cube 100 includes a plurality of memory modules 111. Each of the plurality of memory modules 111 includes a memory cell array 115.

[0070] For example, each of the multiple memory modules 111 includes the function of storing data contained in a received signal into a memory cell array 115, and the function of reading data from the memory cell array 115 and transmitting a signal containing said data. The multiple memory modules 111 are electrically connected to multiple power supply lines 164, multiple grounding lines 165, and multiple signal transmission lines 166.

[0071] As described in "1-1-2. Overview of Semiconductor Chip 200 and Redistribution Layer 300," the semiconductor chip 200 includes a plurality of logic modules 211. The semiconductor chip 200 (the plurality of logic modules 211) is electrically connected to a plurality of power lines 164, a plurality of ground lines 165, and a plurality of signal transmission lines 166, similar to the plurality of memory modules 111.

[0072] Multiple power supply lines 164, multiple grounding lines 165, and multiple signal transmission lines 166 correspond to the conductive paths of multiple internal lines 151 and multiple vias 162 within the memory cube 100, as well as multiple lines 301 and multiple lines 305 within the redistribution layer 300.

[0073] For example, multiple power supply wires 164 and multiple grounding wires 165 may be electrically connected to multiple bumps (not shown) via wiring 156 that penetrates the semiconductor chip 200 (IC chip 110S), and power supply voltage VDD and voltage VSS may be supplied from an external circuit.

[0074] Furthermore, for example, multiple signal transmission lines 166 receive signals from the semiconductor chip 200 (IC chip 110S) including control signals such as address signals and enable signals for controlling the IC chip 110, as well as data.

[0075] The memory cell array 115 includes a plurality of memory cells (not shown in the figure). Each of the plurality of memory cell arrays 115 is, for example, an SRAM (Static Random Access Memory), and each of the plurality of memory cells is an SRAM cell. The SRAM, SRAM cell, and memory module 111 for the SRAM can employ technologies used in the field of SRAM. Therefore, a detailed explanation is omitted here. The plurality of memory cell arrays 115 and the plurality of memory cells may be memory cell arrays and memory cells other than SRAM, for example, an MRAM (Magnetoresistive Random Access Memory) and an MRAM cell.

[0076] [1-3. Method for Manufacturing the Semiconductor Module 10] The method for manufacturing the semiconductor module 10 will be described with reference to Figures 1, 2, 6 to 15. Figure 6 is a plan view showing the substrate 20 in the method for manufacturing the semiconductor module 10. Figure 7 is an end view showing the end cross-sectional structure in step 10 (S10, STEP 10) of the method for manufacturing the semiconductor module 10, and an end view showing an enlarged end cross-sectional structure of region 160. Figure 8 is an end view showing the end cross-sectional structure in step 12 (S12, STEP 12) of the method for manufacturing the semiconductor module 10, and an end view showing an enlarged end cross-sectional structure of region 160. Figure 9 is an end view showing the end cross-sectional structure of region 160 in steps 14 (S14, STEP 14) and 16 (S16, STEP 16) of the method for manufacturing the semiconductor module 10. Configurations identical or similar to those in Figures 1 to 5 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 5 may be omitted.

[0077] For example, the method for manufacturing the semiconductor module 10 can be broadly classified to include S10, S12, S14, and S16. Furthermore, as an example, the method for manufacturing the semiconductor module 10 includes bonding and stacking four IC chips 110 (four chips, four layers).

[0078] When the manufacturing method for the semiconductor module 10 is started, the substrate 20 is prepared. For example, as shown in Figure 6, the substrate 20 includes a first surface 22 and a second surface 24 opposite to the first surface 22 along the third direction D3. The first surface 22 and the second surface 24 overlap with the peripheral region 26 and the IC chip region 28. The first surface 22 is the surface of the IC chip 110 facing the semiconductor substrate 170 and is the same surface as the first surface 102. The second surface 24 is the surface of the IC chip 110 facing the wiring layer 150 and is the same surface as the second surface 104. The IC chip region 28 overlaps with and includes multiple IC chips 110. The peripheral region 26 is the region surrounding the IC chip region 28.

[0079] If the multiple base materials 20 are not distinguishable, the first base material is referred to as base material 20. If the multiple base materials 20 are distinguishable, the base materials 20 are referred to as base material 20A, base material 20B, base material 20C, and so on.

[0080] Step S10 is the step of arranging multiple substrates 20 offset from each other by different shift amounts. For example, as shown in Figure 7, S10 includes arranging multiple substrates 20 offset from a virtual center line 163 by different shift amounts in an end-face view (cross-sectional view), with respect to the center line 163. The range indicated by the arrow with length L1 in Figure 7 is the range in which the bonded substrate is divided into individual pieces, and corresponds to the semiconductor module 10. Note that in order to divide the bonded substrate, a division margin is required between each substrate 20 and the adjacent IC chip 110, but the division margin is omitted in the drawing in order to make the semiconductor module 10 easier to understand.

[0081] For example, the base material 20A includes an IC chip 110A, the IC chip 110A includes a plurality of internal wirings 151A, and each of the plurality of internal wirings 151A includes an opening 152A with a diameter W2. The base material 20A is positioned with a shift amount OFA from a reference position, which is a center line 163, along a first direction D1. More specifically, the center 153A of the opening 152A is positioned with a shift amount OFA from the center line 163, along the first direction D1.

[0082] Similar to the base material 20A, the base material 20B includes an IC chip 110B, the IC chip 110B includes a plurality of internal wirings 151B, each of which includes an opening 152B with a diameter W2. The base material 20B is positioned with a shift amount OFB offset from the center line 163, which is a reference position, to the opposite side of the first direction D1 by a shift amount OFA. More specifically, the center 153B of the opening 152B is positioned with a shift amount OFB offset from the center line 163 to the opposite side of the first direction D1 by a shift amount OFA.

[0083] Similar to substrates 20A and 20B, substrate 20C includes an IC chip 110C, the IC chip 110C includes a plurality of internal wirings 151C, each of which includes an opening 152C with a diameter W2. Substrate 20C is positioned with a shift amount OFC from a reference position, the center line 163, along a first direction D1. More specifically, the center 153C of the opening 152C is positioned with a shift amount OFC on the opposite side of the shift amount OFB along the first direction D1 from the center line 163.

[0084] For example, the base material 20S includes an IC chip 110S, and the IC chip 110S includes a plurality of internal wirings 151S. The base material 20S is positioned with a shift amount of 0 along the first direction D1 from a reference position, which is a center line 163. That is, the base material 20S is positioned without offset from the reference position, which is a center line 163.

[0085] As explained in "1-1. Overview of Semiconductor Module 10", the IC chips 110C, 110B, and 110A are stacked in this order on the second surface 104S of the semiconductor chip 200 (IC chip 110S) along the third direction D3.

[0086] Step S12 is a step in which the multiple base materials 20 arranged in S10 are joined together. As shown in STEP 12 (S12) of Figure 8, base materials 20A, 20B, 20C and 20S are joined together in an offset state. Specifically, the second surface 24A of base material 20A is joined to the first surface 22B of base material 20B, the second surface 24B of base material 20B is joined to the first surface 22C of base material 20C, and the second surface 24C of base material 20C is joined to the second surface 24S of base material 20S. The area indicated by the arrow with diameter W1 shown in Figure 8 is the area in which the opening 161 is formed.

[0087] Step S14 is the step of forming the opening 161. As shown in STEP 14 (S14) of Figure 9, an opening 161 with a diameter W1 is formed in the bonded substrate around the center line 163, along the third direction D3 from the substrate 20A toward the substrate 20S. The opening 161 overlaps with the internal wiring 151A, 151B, 151C and 151S, as well as the openings 152A, 152B and 152C. For example, the opening 161 is formed by photolithography.

[0088] In a cross-sectional view of the end face, the base material 20A is offset by a shift amount OSA, so the internal wiring 151A protrudes inward (towards the center line 163) of the opening 161 along the first direction D1. For example, when the opening 161 is formed by etching, the protruding internal wiring 151A acts as an etching stopper, suppressing etching from the internal wiring 151A toward the base material 20S along the third direction D3. As a result, the length of the opening 161 toward the base material 20S from the internal wiring 151A along the first direction D1 becomes a length W12 that is shorter than the diameter W2.

[0089] In an end-face (cross-sectional) view, the base material 20B is offset by a shift amount OSB, so the internal wiring 151B protrudes inward from the opening 161 (towards the center line 163 and the offset internal wiring 151A) along the first direction D1. For example, similar to the base material 20A, when the opening 161 is formed by etching, the protruding internal wiring 151B acts as an etching stopper, suppressing etching from the internal wiring 151B toward the base material 20S along the third direction D3. As a result, the length of the opening 161 toward the base material 20S from the internal wiring 151B becomes a length W13 that is shorter than the diameter W12.

[0090] In an end-face (cross-sectional) view, the base material 20C is offset by a shift amount OSC, so the internal wiring 151C protrudes inward from the opening 161 (towards the center line 163 and the offset internal wiring 151B) along the first direction D1. For example, similar to base materials 20A and 20B, when the opening 161 is formed by etching, the protruding internal wiring 151C acts as an etching stopper, suppressing etching from the internal wiring 151C toward the base material 20S along the third direction D3. As a result, the length of the opening 161 toward the base material 20S from the internal wiring 151C becomes a length W14 that is shorter than the diameter W13.

[0091] In the end face (cross-sectional) view, the shift amount of the base material 20S is 0, so the opening 161 maintains its length W14 and exposes the internal wiring 151S. The base material 20S may be positioned offset by an arbitrary amount along the first direction D1 from the center line 163, which is the reference position. Here, the arbitrary shift amount is the amount by which the length W14 becomes longer than 0.

[0092] Step S16 is the step of forming vias 162 so as to be in contact with the opening 161. As shown in STEP 16 (S16) of Figure 9, vias 162 are formed so as to be in contact with the opening 161 (inside). As explained in "1-1. Overview of Semiconductor Module 10" with reference to Figure 2, vias 162 include vias 167A, 167B, and 167C, and vias 167A, 167B, and 167C are in contact with and superimposed on the corresponding internal wiring 151. Vias 162 are also formed so as to be in contact with the exposed internal wiring 151S. As a result, vias 162 are in contact with the internal wirings 151A, 151B, 151C, and 151S, and are electrically connected to the internal wirings 151A, 151B, 151C, and 151S. That is, each IC chip 110 is electrically connected by multiple vias 162.

[0093] As shown in the end face (cross-sectional) structure of STEP 16 (S16) in Figure 9, since the via 162 is formed to be in contact with the opening 161 (inside), the length of the via 162 along the first direction becomes shorter along the third direction D3 from the uppermost IC chip 110A to the lowermost IC chip 110S, such as length W1, length W12, length W13, and length W14.

[0094] Although not shown in the diagram, the method for manufacturing the semiconductor module 10 includes forming a redistribution layer 300 on the multiple bonded substrates 20 after step S16. The method for manufacturing the semiconductor module 10 also includes dividing the multiple bonded substrates 20 into multiple chips after forming the redistribution layer 300. Furthermore, the method for manufacturing the semiconductor module 10 may also include dividing the multiple bonded substrates 20 into multiple chips after step S16, and forming a redistribution layer 300 on each of the chips after they have been divided into multiple chips.

[0095] The semiconductor module 10 is formed in the manner described above.

[0096] [Second Embodiment] A semiconductor module 10A according to the second embodiment will be described with reference to Figures 10 to 12. Figure 10 is a perspective view showing the configuration of the semiconductor module 10A. Figure 11 is an end view showing the cross-sectional structure of the end of the semiconductor module 10A along B1-B2 shown in Figure 1. Figure 12 is a plan view showing the configuration of the internal wiring 151, openings 152 and vias 162A of the IC chip 110 included in the semiconductor module 10A. The IC chips 110A, 110C, 110D, and 110E shown in Figure 12, which include a portion of via 162A and internal wiring 151A, IC chip 110C, 110D, 110E, and 110S, which include a portion of via 162A and internal wiring 151S, would normally overlap in a plan view. However, for the sake of clarity in the drawing and to make it easier to understand that IC chips 110A, 110C, 110D, and 110E are offset from each other (stacked, joined), they are shown offset from each other for convenience. Configurations identical or similar to those in Figures 1 to 9 will be explained as necessary, and explanations of identical or similar configurations may be omitted.

[0097] The semiconductor module 10A differs from the semiconductor module 10 in the following configurations 1 to 3. (Configuration 1) The configuration includes a configuration in which the memory cube 100 in the semiconductor module 10 according to the first embodiment is replaced by a memory cube 120A, and a configuration in which via 162 is replaced by via 162A. (Configuration 2) The memory cube 120A includes IC chips 110A, 110B, 110C, 110D, 110E and 110S. IC chips 110A, 110B and 110C are the same as those in the memory cube 100 according to the first embodiment, and the memory cube 120A includes a configuration in which IC chips 110D and 110E are added to the memory cube 100. (Configuration 3) The IC chips 110D and 110E are arranged in the same way as IC chip 110C, shifted by an amount OFC on the opposite side of a shift amount OFB from the center line 163A, which is the reference position, along the first direction D1. Furthermore, IC chip 110D is positioned with a shift amount OFD along the second direction D2 from the reference position, center line 163A, and IC chip 110E is positioned with a shift amount OFE along the second direction D2 from the reference position, center line 163A, in the opposite direction to the offset of IC chip 110D.

[0098] The configurations of semiconductor module 10A other than configurations 1 to 3 are the same as those of semiconductor module 10. Therefore, the following explanation will mainly focus on the differences from semiconductor module 10. Note that, as with semiconductor module 10, the number of stacked IC chips 110, bonding, and mounting structure can be appropriately changed according to the specifications and application of semiconductor module 10A.

[0099] Furthermore, the semiconductor module 10A, like the semiconductor module 10, includes a configuration in which the diameter W2 of at least one of the openings 152A of the multiple IC chips 110 is larger than the diameter W1 of the via 162A (opening 161A). For example, the semiconductor module 10A, like the semiconductor module 10, includes a configuration in which the diameter W2 of each of the openings 152 of the multiple IC chips 110 is larger than the diameter W1 of the via 162A (opening 161A). Furthermore, the semiconductor module 10A, like the semiconductor module 10, may also include a configuration in which the diameter W1 is the same as the diameter W2.

[0100] As shown in Figure 11 or Figure 12, the semiconductor module 10A includes at least a via 162A provided in contact with an opening 161A of diameter W1, a memory cube 120A in which a plurality of IC chips 110 are stacked along a third direction D3, and a semiconductor chip 200. Each of the plurality of IC chips 110 (110A to 110E) includes internal wiring 151 including an opening 152 with a diameter W2 larger than the diameter W1. The semiconductor module 10 may also include a redistribution layer 300. The configuration of the semiconductor chip 200 and the redistribution layer 300 is the same as the configuration of the semiconductor chip 200 and the redistribution layer 300 in the first embodiment.

[0101] For example, as shown in Figure 10, the lengths of the semiconductor module 10A and each IC chip 110 along the first direction D1 and the lengths along the second direction D2 are lengths L1 and L2, respectively, just like the semiconductor module 10.

[0102] As shown in Figures 10 and 11, the memory cube 120A includes a configuration in which five IC chips 110E, 110D, 110C, 110B, and 110A are stacked in this order on the second surface 104S of the semiconductor chip 200 (IC chip 110S) along the third direction D3. For example, the memory cube 120A includes the function of storing received data and the function of transmitting stored data, similar to the memory cube 100.

[0103] The configuration and functions of IC chips 110D and 110E are the same as those of IC chips 110A, 110B, and 110C.

[0104] The first face 101D of IC chip 110D is bonded to the second face 104C of IC chip 110C, the first face 102E of IC chip 110E is bonded to the second face 104D of IC chip 110D, and the first face 102E of IC chip 110E is bonded to the second face 104S of IC chip 110S. In other words, the memory cube 120A includes five F2B bonded IC chips 110A, 110B, 110C, 110D, and 100E, IC chip 110E is F2F bonded to semiconductor chip 200, and the memory cube 120A is face-down mounted on semiconductor chip 200.

[0105] In the semiconductor module 10A, wiring 301 is electrically connected to via 162A, and via 162A, wiring 301, and wiring 305 are supplied with control signals, data, power supply voltage, ground voltage, etc., and function as conductive paths.

[0106] As shown in Figure 11, each of the multiple IC chips 110 is stacked with a virtual center line 163A as the reference point, offset by different amounts from the center line 163A in an end-face view (cross-sectional view). For example, the virtual center line 163A, like the virtual center line 163, is a line extended parallel to the virtual line along the third direction D3, from the center of the opening 161A on the first surface 102A of the uppermost IC chip 110A along the third direction D3 among the multiple stacked IC chips 110. Also, the center of the opening 161A coincides with the center of the via 162A. As an example, the opening 161A in the semiconductor module 10 is circular in shape, similar to the opening 161, and the center line 163A is a virtual line extended from the center of the circle along the third direction D3, however, the opening 161A is not limited to a circular shape. For example, the opening 161A may be a polygon, such as a triangle, quadrilateral, or hexagon, similar to the opening 161. For example, if the opening 161A is a polygon, the center line 163A is a virtual line extending from the center of the polygon along the third direction D3.

[0107] Furthermore, as shown in Figure 11, the opening 161A overlaps with the internal wiring 151A, 151B, 151C, 151D, 151E, and 151S, as well as the openings 152A, 152B, 152C, 152D, and 152E. In addition, via 162A includes vias 167A, 167B, and 167C, similar to via 162, and via 162A further includes vias 167D and 167E.

[0108] As shown in Figure 11 or Figure 12, the IC chip 110D includes a plurality of internal wirings 151D, each of which includes an opening 152D with a diameter W2. The IC chip 110D is positioned with a shift amount OFC from the reference position, the center line 163A, along a first direction D1. The IC chip 110D is also positioned with a shift amount OFD from the reference position, the center line 163A, along a second direction D1. More specifically, the center 153C of the opening 152C is positioned with a shift amount OFC from the center line 163A along the first direction D1 on the opposite side of the shift amount OFB of the IC chip 110B, and with a shift amount OFD from the center line 163A along the second direction D1. As a result, as shown in the end face (cross-sectional) view in Figure 11, the internal wiring 151D protrudes inward from the opening 161A (towards the center line 163A and the offset internal wiring 151B) along the first direction D1. Also, as shown in the plan view in Figure 12, the internal wiring 151D protrudes inward from the opening 161A (towards the center line 163A) along the second direction D2. Therefore, via 167D overlaps with and is in contact with the internal wiring 151D.

[0109] As shown in Figure 11 or Figure 12, the IC chip 110E includes a plurality of internal wirings 151E, each of which includes an opening 152E with a diameter W2. The IC chip 110E is positioned with a shift amount OFC from the reference position, the center line 163A, along the first direction D1. The IC chip 110E is also positioned with a shift amount OFE from the reference position, the center line 163A, along the second direction D1, opposite to the direction in which the IC chip 110D is offset. More specifically, the center 153D of the opening 152D is positioned with a shift amount OFC from the center line 163A along the first direction D1, opposite to the shift amount OFB of the IC chip 110B, and is positioned with a shift amount OFE from the center line 163A along the second direction D1, opposite to the direction in which the IC chip 110D is offset. As a result, as shown in the end face (cross-sectional) view in Figure 11, the internal wiring 151E protrudes inward from the opening 161A along the first direction D1 (towards the center line 163A and the offset internal wiring 151B). Also, as shown in the plan view in Figure 12, the internal wiring 151E protrudes inward from the opening 161A along the second direction D2 (towards the center line 163A and the direction opposite to the offset of the IC chip 110D). Therefore, via 167E overlaps with and is in contact with the internal wiring 151E.

[0110] As described in "1-3. Method for Manufacturing Semiconductor Module 10," the IC chip 110S includes a plurality of internal wirings 151S. The IC chip 110S is positioned with a shift amount of 0 along the first direction D1 from the center line 163A, which is the reference position. In other words, the IC chip 110S is positioned without offset from the center line 163A, which is the reference position.

[0111] As described above, via 162A includes vias 167A, 167B, 167C, 167D, and 167E, and vias 167A, 167B, 167C, 167D, and 167E each contact and superimpose on the corresponding internal wiring 151. In addition, via 162A is formed to contact the exposed internal wiring 151S. As a result, via 162A contacts the internal wirings 151A, 151B, 151C, 151D, 151E, and 151S, and is electrically connected to the internal wirings 151A, 151B, 151C, 151D, 151E, and 151S. In other words, each IC chip 110 is electrically connected by multiple vias 162A.

[0112] Furthermore, for example, the shift amount OFE is greater than the shift amount OFD. Also, the vector amount corresponding to the shift amount of IC chip 110D along the first direction D1 and the second direction D2 is greater than the shift amount OFC of IC chip 110C, and the vector amount corresponding to the shift amount of IC chip 110E along the first direction D1 and the second direction D2 is greater than the vector amount of IC chip 110D. Therefore, similar to semiconductor module 10, the shift amount of semiconductor module 10A increases along the third direction D3 from the uppermost IC chip 110A to the lowermost IC chip 110E.

[0113] Furthermore, although not shown in Figure 11 or Figure 12, similar to the end face (cross-sectional) structure of STEP 16 (S16) in Figure 9, via 162A is formed to be in contact with the opening 161A (inside). Therefore, the length of via 162A along the first direction D1 becomes shorter along the third direction D3 from the uppermost IC chip 110A to the lowermost IC chip 110S.

[0114] Furthermore, each of the multiple IC chips 110 is formed using a photomask with the same layout design. The opening 161A is formed in a single drilling step so as to penetrate the multiple IC chips 110. The via 162A is formed to be in contact with the opening 161A.

[0115] Therefore, the semiconductor module 10A, which includes a plurality of IC chips 110 offset in the first direction D1 or the second direction D2, is configured, similar to the semiconductor module 10, to have openings 152 and internal wiring 151 having the same pattern shape superimposed on each other between the plurality of IC chips 110, and to have a configuration in which the plurality of IC chips 110 are offset from each other. As a result, the plurality of IC chips 110 (each internal wiring 151) are electrically connected to each other using vias 162A that are in contact with the openings 161A formed in a single opening process.

[0116] Furthermore, since the semiconductor module 10A, like the semiconductor module 10, includes a configuration in which multiple IC chips 110 are stacked with a pre-existing offset from each other, it suppresses the need to make the opening 161A larger than necessary, and the multiple IC chips 110 can be electrically connected to each other using vias 162A that are in contact with the opening 161A. Also, even if the stacking positions of the multiple IC chips 110 are misaligned, a misalignment of less than the diameter W1 of the opening 161A has virtually no effect on the connection between the vias 162A and the internal wiring 151 of each of the multiple IC chips 110. Therefore, the shift amount may be increased for IC chips 110 that are closer to the semiconductor chip 200 along the third direction D3.

[0117] As a result, the productivity of the memory cube 120A is improved, similar to the memory cube 100, and the manufacturing costs of the semiconductor module 10A can be reduced. Furthermore, like the semiconductor module 10, the semiconductor module 10A can suppress disconnections and disconnections between multiple IC chips 110. In other words, the semiconductor module 10A can maintain long-term reliability, similar to the semiconductor module 10.

[0118] [Third Embodiment] A semiconductor module 10B according to the third embodiment will be described with reference to Figures 13 and 14. Figure 13 is a perspective view showing the configuration of the semiconductor module 10B. Figure 14 is an end view showing the cross-sectional structure of the end of the semiconductor module 10B along C1-C2 shown in Figure 13. Configurations identical or similar to those in Figures 1 to 12 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 12 may be omitted.

[0119] The semiconductor module 10B differs from the semiconductor module 10 in the following configuration 4. (Configuration 4) The configuration and function include a memory cube 100C having the same configuration and function as the memory cube 100 in the semiconductor module 10 according to the first embodiment, provided between the memory cube 100 and the redistribution layer 300. That is, the semiconductor module 10B includes a configuration and function in which the memory cube 100 is stacked (bonded) in two stages along the third direction D3.

[0120] The configurations of semiconductor module 10B, other than configuration 4, are the same as those of semiconductor module 10. Therefore, the differences from semiconductor module 10 will be mainly explained below. As with semiconductor module 10, the number of stacked IC chips 110, bonding, and mounting structure can be appropriately changed according to the specifications and application of semiconductor module 10B. Furthermore, semiconductor module 10B may include a configuration in which the chips are offset in the first direction D1 and the second direction D2 of semiconductor module 10A.

[0121] Furthermore, the semiconductor module 10B, like the semiconductor module 10, includes a configuration in which the diameter W2 of at least one opening 152A of each of the multiple IC chips 110 is larger than the diameter W1 of the via 162C (opening 161C). For example, the semiconductor module 10B, like the semiconductor module 10, includes a configuration in which the diameter W2 of each of the multiple IC chips 110 is larger than the diameter W1 of the via 162C (opening 161C). Furthermore, the semiconductor module 10A, like the semiconductor module 10, may include a configuration in which the diameter W1 is the same as the diameter W2.

[0122] As shown in Figure 13 or Figure 14, the semiconductor module 10B includes at least a memory cube 100 containing IC chips 110A, 110B, and 110C, a memory cube 100C with a configuration similar to that of memory cube 100, and a semiconductor chip 200. That is, the semiconductor module 10B has seven IC chips 110 bonded together: IC chips 110A, 110B, and 110C, IC chips 110A, 110B, and 110C, and semiconductor chip 200 (IC chip 110S). In addition, the IC chip 110C of the memory cube 100 is face-to-face bonded to the semiconductor chip 200, and the memory cube 100 is face-down mounted on the semiconductor chip 200. The semiconductor module 10 may also include a redistribution layer 300. The configuration of the semiconductor chip 200 and the redistribution layer 300 is the same as the configuration of the semiconductor chip 200 and the redistribution layer 300 in the first embodiment.

[0123] The memory cube 100C is provided between the memory cube 100 and the redistribution layer 300, and is electrically connected to the memory cube 100 and the redistribution layer 300. The memory cube 100C also includes an opening 161C, a via 162C provided in contact with the opening 161C, and a virtual centerline 163C. The opening 161C, the via 162C provided in contact with the opening 161C, and the virtual centerline 163C have the same configuration and function as the opening 161, the via 162 provided in contact with the opening 161, and the virtual centerline 163 in the memory cube 100.

[0124] For example, the method for manufacturing the semiconductor module 10B, as an example of a method for manufacturing the memory cube 100C portion, includes, after step S16 as described in "1-3. Method for Manufacturing Semiconductor Module 10", joining a plurality of substrates 20 having the same configuration and function as substrates 20C, 20B, and 20A to the second surface 104A shown in Figure 9, offset along the third direction D3 in the same manner as substrates 20C, 20B, and 20A. The method for manufacturing the semiconductor module 10B also includes, after joining in this order, forming an opening 161C in the same step as S14, forming a via 162C in the same step as S16 after S14, and forming a redistribution layer 300 as described in "1-3. Method for Manufacturing Semiconductor Module 10" after S16.

[0125] As described above, the manufacturing method for semiconductor module 10B includes an IC chip 110 that has more layers than semiconductor modules 10 and 10A. Furthermore, the manufacturing method for semiconductor module 10B includes the same configuration and functions as semiconductor module 10 and provides the same effects and benefits as semiconductor module 10.

[0126] [Fourth Embodiment] A semiconductor module 10 according to the fourth embodiment will be described with reference to Figure 15. The semiconductor module 10 according to the fourth embodiment includes a configuration in which a plurality of substrates 20 (a plurality of IC chips 110) are stacked (bonded) with an offset, where the rotation angle around the center of the opening 161B (center line 163B) is the shift amount. Figure 15 is a plan view showing the configuration of the internal wiring 151, openings 152 and vias 162 of the IC chip 110 included in the semiconductor module 10. The IC chips 110A, 110B, 110C, and 110S shown in Figure 15, which include a portion of via 162B and internal wiring 151A, respectively, are shown offset from each other for ease of viewing and to clearly show that IC chips 110A, 110B, and 110C are offset from each other (stacked, joined).

[0127] The configuration of the semiconductor module 10 according to the fourth embodiment is the same as that of the semiconductor module 10 according to the first embodiment, except for the configuration in which the rotation angle is used as the shift amount and the modules are stacked (bonded) with an offset. Therefore, the following explanation will mainly focus on the differences from the semiconductor module 10 according to the first embodiment. As with the semiconductor module 10 according to the first embodiment, the number of stacked IC chips 110, bonding, and mounting structure of the IC chip 110 according to the fourth embodiment can be appropriately changed according to the specifications and application of the semiconductor module 10 according to the fourth embodiment.

[0128] Furthermore, the semiconductor module 10 according to the fourth embodiment, like the semiconductor module 10 according to the first embodiment, includes a configuration in which the diameter W2 of at least one opening 152A among the diameters W2 of each opening 152 of the plurality of IC chips 110 is larger than the diameter W1 of the via 162B (opening 161B). For example, the semiconductor module 10 according to the fourth embodiment, like the semiconductor module 10 according to the first embodiment, includes a configuration in which the diameter W2 of each opening 152 of the plurality of IC chips 110 is larger than the diameter W1 of the via 162B (opening 161B). Furthermore, the semiconductor module 10 according to the fourth embodiment may also include a configuration in which the diameter W1 is the same as the diameter W2, similar to the semiconductor module 10 according to the first embodiment.

[0129] As shown in Figure 15, multiple IC chips 110 are arranged with an offset, where the rotation angle around the center of the opening 161B (center line 163B) is the shift amount. For example, the virtual center line 163C, like the virtual center line 163, is a line extended parallel to the virtual line along the third direction D3, from the center of the opening 161B on the first surface 102A of the uppermost IC chip 110A along the third direction D3 among the multiple stacked IC chips 110. Also, the center of the opening 161B coincides with the center of the via 162B. As an example, the opening 161B in the semiconductor module 10 is circular in shape, similar to the opening 161, and the center line 163B is a virtual line extended from the center of the circle along the third direction D3, however, the opening 161B is not limited to a circular shape.

[0130] Furthermore, the opening 161B overlaps with the internal wiring 151A, 151B, 151C, and 151S, as well as the openings 152A, 152B, and 152C. In addition, via 162B includes vias 167AB, 167BB, and 167BC.

[0131] The IC chip 110A includes multiple internal wirings 151A, each of which includes an opening 152A with a diameter W2. The IC chip 110A is positioned counterclockwise from its original position, indicated by the dashed line, by a shift amount of rotation angle α1, around the center of the opening 161B (center line 163B), which is the reference position. At this time, the center 153A of the opening 152A is positioned counterclockwise from its original position, by a shift amount of rotation angle α1 from the center line 163C. As a result, as shown in the plan view in Figure 15, the opening 152A is positioned inside the opening 161B, away from the center line 163B in a clockwise direction. Therefore, the via 167AB overlaps with and touches the internal wiring 151A.

[0132] The IC chip 110B includes multiple internal wirings 151B, each of which includes an opening 152B with a diameter W2. The IC chip 110B is positioned clockwise from its original position, indicated by the dashed line, by a shift amount of rotation angle α2, with respect to the center of the opening 161B (center line 163B), which is the reference position. At this time, the center 153B of the opening 152B is positioned clockwise from its original position, by a shift amount of rotation angle α2 from the center line 163C. As a result, as shown in the plan view in Figure 15, the opening 152B is positioned inside the opening 161B, away from the center line 163B in a counterclockwise direction. Therefore, the via 167BB overlaps with and touches the internal wiring 151B.

[0133] The IC chip 110C includes multiple internal wirings 151C, each of which includes an opening 152C with a diameter W2. The IC chip 110C is positioned counterclockwise from its original position, indicated by the dashed line, by a shift amount of rotation angle α3, around the center of the opening 161B (center line 163B), which is the reference position. At this time, the center 153C of the opening 152C is positioned counterclockwise from its original position, by a shift amount of rotation angle α3 from the center line 163C. As a result, as shown in the plan view in Figure 15, the opening 152C is positioned inside the opening 161B, away from the center line 163B in a counterclockwise direction. Therefore, the via 167BC overlaps with and touches the internal wiring 151C.

[0134] As explained in "1-3. Method for Manufacturing the Semiconductor Module 10," the IC chip 110S includes a plurality of internal wirings 151S. The IC chip 110S is positioned counterclockwise from its original position by a shift amount of rotation angle 0 from the center line 163B, which is the reference position. In other words, the IC chip 110S is positioned without being offset from the center line 163C, which is the reference position.

[0135] As described above, via 162B includes vias 167AB, 167BB, and 167CB, each of which contacts and superimposes the corresponding internal wiring 151. Via 162B is also formed to contact the exposed internal wiring 151S. As a result, via 162B contacts the internal wirings 151A, 151B, 151C, and 151S, and is electrically connected to them. In other words, each IC chip 110 is electrically connected by multiple vias 162B.

[0136] Furthermore, for example, rotation angle α3 is greater than rotation angle α2, and rotation angle α2 is greater than rotation angle α1. Therefore, the shift amount of the semiconductor module 10 according to the fourth embodiment, which is offset by the rotation angle as a shift amount, increases along the third direction D3 from the uppermost IC chip 110A to the lowermost IC chip 110C. That is, the closer the IC chip 110 is to the semiconductor chip 200 (IC chip 110S) along the third direction D3, the larger the shift amount.

[0137] Furthermore, as shown in Figure 15, similar to the end face (cross-sectional) structure of STEP 16 (S16) in Figure 9, via 162B is formed to be in contact with the opening 161B (inside). Therefore, the length of via 162B along the first direction D1 decreases along the third direction D3 from the uppermost IC chip 110A to the lowermost IC chip 110S.

[0138] Furthermore, the semiconductor module 10 according to the fourth embodiment includes the configuration described above, and other configurations in the semiconductor module 10 according to the fourth embodiment include the same configurations as those in the semiconductor module 10 according to the first embodiment. Therefore, even if the semiconductor module 10 includes a configuration in which a plurality of IC chips 110 are arranged with an offset using a rotation angle as the shift amount, the opening 161C is formed in a single drilling step so as to penetrate the plurality of IC chips 110, and the via 162C is formed to be in contact with the opening 161C. In addition, the plurality of IC chips 110 (each internal wiring 151) are electrically connected to each other using the via 162C that is in contact with the opening 161C formed in a single drilling step. As a result, it is possible to suppress making the opening 161C larger than necessary and to electrically connect the plurality of IC chips 110 to each other using the via 162C that is in contact with the opening 161C. Furthermore, even if the stacking positions of the multiple IC chips 110 are misaligned, this does not significantly affect the connection between the via 162C and the internal wiring 151 of each of the multiple IC chips 110. Therefore, as described above, the shift amount can be increased for IC chips 110 that are closer to the semiconductor chip 200 along the third direction D3.

[0139] Therefore, the semiconductor module 10 according to the fourth embodiment, like the semiconductor module 10 according to the first embodiment, can improve the productivity of the memory cube 100, reduce manufacturing costs, suppress disconnections and disconnections between multiple IC chips 110, and maintain reliability over the long term.

[0140] [Fifth Embodiment] A semiconductor module 10D according to the fifth embodiment will be described with reference to Figures 16 and 17. The semiconductor module 10D includes a configuration in which the diameter W3 of a via 162D (opening 161D) is larger than the diameter W4 of at least one opening 152A among the diameters W4 of the openings 161D of the plurality of IC chips 110. As an example, the semiconductor module 10D includes a configuration in which the diameter W3 of a via 162D (opening 161D) is larger than the diameter W3 of the opening 152 of the plurality of IC chips 110. Note that, similar to the semiconductor module 10, the semiconductor module 10D may also include a configuration in which the diameter W3 is the same as the diameter W4. Furthermore, the configuration of the memory cube 100 relating to the semiconductor module 10D may be combined with the configuration in which the IC chip 110 is offset in the second direction D2 according to the second embodiment, the configuration of the memory cube 100 relating to the semiconductor module 10D may be combined with the configuration in which the memory cubes according to the third embodiment are stacked, and the configuration of the memory cube 100 relating to the semiconductor module 10D may be combined with the configuration in which the IC chip 110 is offset using the rotation angle according to the fourth embodiment as the shift amount.

[0141] Figure 16 is an end view showing the cross-sectional structure of the end of the semiconductor module 10D along A1-A2 shown in Figure 1. Figure 17 is a plan view showing the configuration of the internal wiring 151, openings 152, and vias 162D of the IC chip 110 included in the semiconductor module 10D. The IC chip 110A, which includes a part of via 162D and internal wiring 151A, the IC chip 110B, which includes a part of via 162D and internal wiring 151B, the IC chip 110C, which includes a part of via 162D and internal wiring 151C, and the IC chip 110S, which includes a part of via 162D and internal wiring 151S, shown in Figure 17, would normally overlap in a plan view, but for the sake of clarity in the drawing and to make it easier to understand that the IC chips 110A, 110B, and 110C are offset from each other (stacked, joined), they are shown offset from each other for convenience. Configurations identical or similar to those in Figures 1 to 15 will be explained as necessary, and explanations of identical or similar configurations to those in Figures 1 to 15 may be omitted.

[0142] Aside from the configuration in which the diameter W3 of the via 162D (opening 161D) in the semiconductor module 10D is larger than the diameter W3 of each opening 152 of the multiple IC chips 110, the configuration is the same as that of the semiconductor module 10 according to the first embodiment. Therefore, the following will mainly describe the differences from the semiconductor module 10 according to the first embodiment. As with the semiconductor module 10 according to the first embodiment, the number of stacks, bonding and mounting structure of the IC chips 110 according to the fifth embodiment can be appropriately changed according to the specifications and applications of the semiconductor module 10D according to the fifth embodiment.

[0143] As shown in Figure 16 or Figure 17, the semiconductor module 10D includes at least a via 162D having a diameter W3 and positioned in contact with an opening 161D, and a memory cube 100 in which a plurality of IC chips 110 are stacked along a third direction D3. Each of the plurality of IC chips 110 also includes internal wiring 151 containing an opening 152 with a diameter W4 smaller than the diameter W3. The diameter W3 may be referred to as the first diameter, and the diameter W4 may be referred to as the second diameter.

[0144] As shown in Figure 16, each of the multiple IC chips 110 is stacked with a virtual center line 163D as the reference point, offset by different amounts from the center line 163D in an end-face view (cross-sectional view). For example, the virtual center line 163D has the same configuration and function as the virtual center line 163.

[0145] For example, as shown in Figure 17, IC chip 110A is positioned with a shift amount OFF along the first direction D1 from the reference position, center line 163D; IC chip 110B is positioned with a shift amount OFG on the opposite side of the shift amount OFF along the first direction D1 from the reference position, center line 163D; and IC chip 110C is positioned with a shift amount OFH on the opposite side of the shift amount OFG along the first direction D1 from the reference position, center line 163D. IC chips 110A, 110B, and 110C are stacked along the third direction D3 in order of proximity to the second surface 104S of the semiconductor chip 200 (IC chip 110S).

[0146] For example, the shift amount OFG is greater than the shift amount OFH, and the shift amount OFH is greater than the shift amount OFF. That is, the semiconductor module 10D, like the semiconductor module 10, includes a configuration in which the shift amount increases as you move along the third direction D3 from the uppermost IC chip 110A to the lowermost IC chip 110C.

[0147] The opening 161D is formed in a single drilling step, similar to the opening 161, so as to penetrate multiple IC chips 110. The via 162D is formed in the same way as the via 162, so as to be in contact with the opening 161D. Therefore, in an end-face view (cross-sectional view), the via 162D is in contact with a portion of each of the openings 152 of the multiple IC chips 110.

[0148] Furthermore, as shown in Figure 16 or Figure 17, via 162D includes vias 167DA, 167DB, and 167DC. Via 167DA overlaps with and contacts internal wiring 151A, via 167DB overlaps with and contacts internal wiring 151B, and via 167DC overlaps with and contacts internal wiring 151C. A portion of via 162D overlaps with and contacts internal wiring 151S without overlapping with internal wirings 151A, 151B, and 151C. Via 162D is also formed to contact exposed internal wiring 151S. As a result, via 162D is in contact with internal wirings 151A, 151B, 151C, and 151S, and is electrically connected to internal wirings 151A, 151B, 151C, and 151S. In other words, each IC chip 110 is electrically connected by multiple vias 162D.

[0149] Furthermore, since the semiconductor module 10D, like the semiconductor module 10, includes a configuration in which multiple IC chips 110 are stacked with a pre-existing offset from each other, it suppresses the need to make the opening 161D unnecessarily large, and the multiple IC chips 110 can be electrically connected to each other using vias 162D that are in contact with the opening 161D. Also, even if the stacking positions of the multiple IC chips 110 are misaligned, a misalignment of less than the diameter W4 of the opening 161D has virtually no effect on the connection between the vias 162D and the internal wiring 151 of each of the multiple IC chips 110. Therefore, the shift amount may be increased for IC chips 110 that are closer to the semiconductor chip 200 along the third direction D3.

[0150] The semiconductor module 10D includes the configuration described above, and other configurations in the semiconductor module 10D include the same configuration as those in the semiconductor module 10. Therefore, even if the semiconductor module 10D includes a configuration in which the diameter W3 of the via 162D (opening 161D) is larger than the diameter W3 of each opening 152 of the multiple IC chips 110, the opening 161D is formed in a single opening process so as to penetrate the multiple IC chips 110, and the via 162D is formed to be in contact with the opening 161D. Furthermore, the multiple IC chips 110 (each internal wiring 151) are electrically connected to each other using the via 162D that is in contact with the opening 161D formed in a single opening process. As a result, it is possible to suppress making the opening 161D unnecessarily large and to electrically connect the multiple IC chips 110 to each other using the via 162D that is in contact with the opening 161D. Furthermore, even if the stacking positions of the multiple IC chips 110 are misaligned, this does not significantly affect the connection between the via 162D and the internal wiring 151 of each of the multiple IC chips 110. Therefore, as described above, the shift amount can be increased for IC chips 110 that are closer to the semiconductor chip 200 along the third direction D3.

[0151] Therefore, the semiconductor module 10D, like the semiconductor module 10 according to the first embodiment, can improve the productivity of the memory cube 100, reduce manufacturing costs, suppress disconnections and disconnections between multiple IC chips 110, and maintain reliability over the long term.

[0152] The various configurations of the semiconductor modules illustrated as embodiments of the present invention can be combined as appropriate, as long as they do not contradict each other, and technical matters common to each embodiment are included in each embodiment even if not explicitly stated. Furthermore, semiconductor modules disclosed in this specification and drawings, on which a person skilled in the art has added, deleted, or modified components, or added, omitted, or modified processes, are also included in the scope of the present invention, as long as they retain the gist of the present invention.

[0153] Any effects or benefits other than those brought about by the embodiments disclosed herein are to be understood to be brought about by the present invention if they are clear from the description herein or can be easily predicted by a person skilled in the art.

[0154] 10: Semiconductor module, 10A: Semiconductor module, 10B: Semiconductor module, 10D: Semiconductor module, 20: Substrate, 20A: Substrate, 20B: Substrate, 20C: Substrate, 20S: Substrate, 22: First surface, 22B: First surface, 22C: First surface, 24: Second surface, 24A: Second surface, 24B: Second surface, 24C: Second surface, 24S: Second surface, 26: Peripheral area, 28: IC chip area, 100: Memory cube, 100C: Memory cube, 102: First surface, 102A: First surface, 102B: First surface, 102C: First surface, 102D: First surface, 102S: First surface, 104: 2nd surface, 104A: 2nd surface, 104B: 2nd surface, 104C: 2nd surface, 104D: 2nd surface, 104E: 2nd surface, 104S: 2nd surface, 110: IC chip, 110A: IC chip, 110B: IC chip, 110C: IC chip, 110D: IC chip, 110E: IC chip, 110S: IC chip, 111: memory module, 115: memory cell array, 120A: memory cube, 130: transistor layer, 130A: transistor layer, 130B: transistor layer, 130C: transistor layer, 130S: transistor layer, 131: through electrode, 134: element Child isolation region, 135: Activation region, 136: Transistor, 137: Insulating layer, 150: Wiring layer, 150A: Wiring layer, 150B: Wiring layer, 150C: Wiring layer, 150S: Wiring layer, 151: Internal wiring, 151A: Internal wiring, 151B: Internal wiring, 151C: Internal wiring, 151D: Internal Wiring, 151E: Internal wiring, 151S: Internal wiring, 152: Opening, 152A: Opening, 152B: Opening, 152C: Opening, 152D: Opening, 152E: Opening, 153A: Center, 153B: Center, 153C: Center, 153D: Center, 154: Wiring, 155: Insulating layer, 156: Wiring, 1 57: Insulating layer, 159: Insulating layer, 160: Region, 161: Opening, 161A: Opening, 161B: Opening, 161C: Opening, 161D: Opening, 162: Via, 162A: Via, 162B: Via, 162C: Via, 162D: Via, 163: Centerline, 163A: Centerline, 163B: Centerline, 163C: Centerline, 163D: Centerline, 164: Power wiring, 165: Grounding wiring, 166: Signal transmission wiring, 167A: Via, 167AB: Via, 167B: Via, 167BB: Via, 167BC: Via, 167C: Via, 167D: Via, 167DA: Via, 167DB: Via,167DC: via, 167E: via, 170: semiconductor substrate, 170A: semiconductor substrate, 170C: semiconductor substrate, 170S: semiconductor substrate, 170B: semiconductor substrate, 170D: semiconductor substrate, 170E: semiconductor substrate, 200: semiconductor chip, 211: logic module, 300: redistribution layer, 301: wiring, 302: first surface, 303: insulating layer, 304: second surface, 305: wiring, 307: insulating layer, 308: opening

Claims

1. A semiconductor module comprising a memory cube having vias having a first diameter and a plurality of memory chips stacked thereon, wherein each of the plurality of memory chips includes internal wiring including an opening of a second diameter, each of the plurality of memory chips is stacked offset from a reference position by different shift amounts in a cross-sectional view, and the vias are in contact with a portion of the opening of each of the plurality of memory chips in a cross-sectional view.

2. The semiconductor module according to claim 1, wherein the internal wiring pattern shapes of each of the plurality of memory chips are identical.

3. The semiconductor module according to claim 2, wherein the plurality of memory chips are stacked along a third direction perpendicular to the second direction, parallel to a plane formed by a first direction and a second direction perpendicular to the first direction, and at least a portion of the openings of each of the plurality of memory chips overlap in a top view.

4. The semiconductor module according to claim 3, wherein the shift amount increases along the third direction from the uppermost memory chip to the lowermost memory chip.

5. The semiconductor module according to claim 3, wherein, in a cross-sectional view, the length of the via along the first direction decreases along the third direction from the uppermost memory chip to the lowermost memory chip.

6. The semiconductor module according to claim 3, wherein the reference position is the center of the via.

7. The semiconductor module according to claim 3, wherein each of the plurality of memory chips is stacked offset from the reference position in the first or second direction.

8. The semiconductor module according to claim 3, wherein each of the plurality of memory chips is stacked with an offset, where the shift amount is the rotation angle around the reference position.

9. The semiconductor module according to claim 3, further comprising a semiconductor chip for driving the plurality of memory chips, and a redistribution layer including a wiring layer configured to connect the plurality of memory chips along the first and second directions, wherein the plurality of memory chips are disposed between the semiconductor chip and the redistribution layer and are electrically connected to the semiconductor chip and the redistribution layer.

10. The semiconductor module according to claim 3, comprising a plurality of memory cubes, each having vias having the first diameter, and wherein the plurality of memory chips are stacked on top of each other, and the vias of adjacent memory cubes are electrically connected and superimposed.

11. The semiconductor module according to claim 3, wherein the second diameter of at least one of the second diameters of the openings of the plurality of memory chips is larger than the first diameter.

12. The semiconductor module according to claim 3, wherein the first diameter is greater than the second diameter of at least one of the second diameters of the openings of the plurality of memory chips.

13. The semiconductor module according to claim 3, wherein the first diameter is the same as the second diameter.

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