Three-dimensional random access memory

Abstract

In order to prevent programming malfunction and ensure memory performance while achieving high integration, a three-dimensional random access memory and a method for operating same are disclosed. The three-dimensional random access memory comprises: gate electrodes extending in a horizontal direction on a substrate and stacked while being vertically spaced apart from each other; and vertical structures penetrating the gate electrodes and extending in a vertical direction, wherein each of the vertical structures includes a data storage pattern and a bit line vertical portion, and wherein the data storage pattern includes at least one insulating pattern and forms memory cells corresponding to the gate electrodes.

Description

3D Random Access Memory

[0001] The following embodiments relate to a three-dimensional random access memory that promotes high integration while preventing program malfunction and ensuring memory performance, and a method of operation or a method of manufacturing the same.

[0002] A semiconductor device such as a DRAM (Dynamic Random Access Memory) has wiring such as a MOS transistor including a source and a drain, a capacitor electrically connected to the source of the MOS transistor, and a bit line electrically connected to the drain of the MOS transistor.

[0003] These DRAMs began to be implemented in a three-dimensional structure, moving away from the two-dimensional structure, in line with the trend of high integration to secure storage space.

[0004] A 3D DRAM is implemented to support and operate random access based on the gate electrodes and vertical electrodes within the memory cell string, while including a semiconductor structure comprising interlayer insulating layers and gate electrodes that are stacked alternately in the vertical direction and a memory cell string that is extended and penetrates the semiconductor structure in the vertical direction.

[0005] However, conventional 3D random access memory has a problem in that unselected memory cells can be partially programmed by being affected by the voltage applied through the vertical electrode.

[0006] Therefore, a technology to solve the described problem needs to be proposed.

[0007] In addition, since the design for the block in which the vertical structures of memory cells are arranged is not proposed in the existing 3D random access memory, there is a disadvantage that memory performance is degraded when an excessive number of vertical structures are included in the block, causing a delay in voltage application through the word line, and a disadvantage that the integration density is reduced when too few vertical structures are included in the block.

[0008] Therefore, in order to resolve the described disadvantages, a design for a block in which vertical structures of memory cells are arranged needs to be proposed.

[0009]

[0010] One embodiment proposes a three-dimensional random access memory having a structure of a data storage pattern including at least one insulation pattern and a method for operating the memory to solve the problem that a non-selected memory cell may be partially programmed by being affected by a voltage applied through a vertical electrode.

[0011] In addition, some embodiments propose a three-dimensional random access memory having a structure that includes at least one string selection line slit for separating at least one gate electrode corresponding to a string selection line by string selection line block and at least one word line slit for separating at least one gate electrode corresponding to a word line by word line block, in order to solve the disadvantages of memory performance degradation caused by a delay in applying voltage through a word line when too many vertical structures are included in a block and the disadvantage of integration density degradation when too few vertical structures are included in a block.

[0012] However, the technical problems that the present invention aims to solve are not limited to the above problems and can be expanded in various ways without departing from the technical concept and scope of the present invention.

[0013] According to one embodiment, a three-dimensional random access memory may include: gate electrodes that are formed extending in a horizontal direction on a substrate and are spaced apart in a vertical direction and stacked; and vertical structures that penetrate the gate electrodes and extend in the vertical direction—each of the vertical structures includes a data storage pattern and a bit line vertical portion, and the data storage pattern includes at least one insulating pattern and constitutes memory cells corresponding to the gate electrodes.

[0014] According to one aspect, the data storage pattern may be characterized by including at least one insulating pattern on an outer wall, an inner wall, or inside.

[0015] According to another aspect, the at least one insulating pattern may be characterized as being used to prevent memory operation for non-selected memory cells among the memory cells, excluding the target memory cell, during memory operation for the target memory cell.

[0016] According to another aspect, the at least one insulation pattern may be characterized by increasing the operating voltage required for the memory operation or increasing the coercive field in the unselected memory cells to prevent polarization from occurring in the unselected memory cells.

[0017] According to another aspect, the thickness of the at least one insulating pattern may be characterized as being determined to a value that satisfies the condition enabling memory operation for the target memory cell and the condition preventing memory operation for the unselected memory cells.

[0018] According to another aspect, the at least one insulating pattern may be characterized by being formed of a material that satisfies conditions enabling memory operation for the target memory cell and conditions preventing memory operation for the unselected memory cells.

[0019] According to one embodiment, a memory operation method of a three-dimensional random access memory comprising: gate electrodes formed extending in a horizontal direction on a substrate and spaced apart in a vertical direction and stacked; and vertical structures formed extending in the vertical direction penetrating the gate electrodes—each of the vertical structures comprising a data storage pattern and a bit line vertical portion, wherein the data storage pattern comprises at least one insulating pattern and constitutes memory cells corresponding to the gate electrodes—may include the steps of: applying a bit line voltage having at least a partial value of an operating voltage to the bit line vertical portion included in a selected vertical structure among the vertical structures that includes a target memory cell to be subject to memory operation; applying a gate voltage having opposite polarity to the bit line voltage and the remaining partial value of the operating voltage to a selected gate electrode among the gate electrodes corresponding to the target memory cell; and grounding at least one unselected gate electrode among the gate electrodes excluding the selected gate electrode.

[0020] According to one side, the step of applying the bit line voltage may be characterized as a step of preventing memory operation for non-selected memory cells among the memory cells, excluding the target memory cell, by using the at least one insulating pattern included in the outer wall, inner wall, or interior of the data storage pattern.

[0021] According to another aspect, the step of preventing memory operation for the non-selected memory cells may be characterized by increasing the operating voltage required for the memory operation or increasing the coercive field in the non-selected memory cells to prevent polarization from occurring in the non-selected memory cells.

[0022] According to another aspect, the step of applying a gate voltage having a remainder of the operating voltage value may be characterized by applying the gate voltage to the selected gate electrode while the selection transistor of at least one non-selected vertical structure that does not include the target memory cell—the at least one non-selected vertical structure including a bit line vertical portion that is connected to a common bit line horizontal portion with the bit line vertical portion included in the selected vertical structure—is turned off, thereby preventing memory operation for the memory cell corresponding to the selected gate electrode among the memory cells of the at least one non-selected vertical structure.

[0023] According to one embodiment, a three-dimensional random access memory may include: gate electrodes formed extending in a horizontal direction on a substrate and stacked while spaced apart in a vertical direction; vertical structures formed extending in the vertical direction through the gate electrodes—each of the vertical structures comprising a data storage pattern and a bit line vertical portion, wherein the data storage pattern comprises memory cells corresponding to the gate electrodes—; at least one string selection line slit separating at least one gate electrode corresponding to a string selection line among the gate electrodes by string selection line block; and at least one word line slit separating at least one gate electrode corresponding to a word line among the gate electrodes by word line block.

[0024] According to one side, the word line block may be characterized by including a plurality of string selection line blocks.

[0025] According to another aspect, the word line block may be characterized by including a greater number of the vertical structures than the string selection line block.

[0026] According to another aspect, the number of vertical structures included in the word line block may be characterized by being determined and controlled based on the speed at which an operating voltage within the word line block is applied to a target memory cell of a selected vertical structure among the vertical structures through the word line.

[0027] According to another aspect, the at least one word line slit may be characterized as being used as a passage to remove a sacrificial layer and fill the gate electrodes during the process of forming the gate electrodes in the manufacturing process of the three-dimensional random access memory.

[0028] One embodiment proposes a three-dimensional random access memory having a structure of a data storage pattern including at least one insulation pattern and a method for operating the memory, thereby solving the problem that a non-selected memory cell may be partially programmed by being affected by a voltage applied through a vertical electrode.

[0029] In addition, some embodiments propose a three-dimensional random access memory having a structure comprising at least one string selection line slit that separates at least one gate electrode corresponding to a string selection line by string selection line block and at least one word line slit that separates at least one gate electrode corresponding to a word line by word line block, thereby solving the disadvantages of memory performance degradation caused by a delay in voltage application through the word line when too many vertical structures are included in the block and the disadvantage of reduced integration density when too few vertical structures are included in the block, thereby achieving the technical effect of promoting high integration while ensuring memory performance.

[0030] However, the effects of the present invention are not limited to the above effects and can be extended in various ways without departing from the technical concept and scope of the present invention.

[0031] FIG. 1 is a simplified circuit diagram illustrating a three-dimensional random access memory according to one embodiment.

[0032] FIG. 2 is a plan view illustrating a three-dimensional random access memory according to one embodiment.

[0033] FIG. 3 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to the cross-section of FIG. 2 cut along the line A-A'.

[0034] FIGS. 4a and 4b are drawings for explaining the effect of at least one insulation pattern of a three-dimensional random access memory according to one embodiment.

[0035] FIGS. 5a and 5b are cross-sectional views illustrating a three-dimensional random access memory to explain the arrangement structure of at least one insulation pattern according to another embodiment.

[0036] FIG. 6 is a flowchart illustrating a memory operation method of a three-dimensional random access memory according to one embodiment.

[0037] FIG. 7 is a diagram illustrating a memory operation method of a three-dimensional random access memory according to one embodiment.

[0038] FIG. 8 is a simplified circuit diagram illustrating a three-dimensional random access memory according to embodiments.

[0039] FIG. 9 is a plan view illustrating a three-dimensional random access memory according to one embodiment.

[0040] FIG. 10 is a plan view illustrating a three-dimensional random access memory according to another embodiment.

[0041] FIG. 11 is a cross-sectional view illustrating a three-dimensional random access memory according to embodiments, corresponding to the cross-section of FIG. 9 to 10 cut along the line A-A'.

[0042] FIG. 12 is a flowchart illustrating a method for manufacturing a three-dimensional random access memory according to one embodiment.

[0043] FIG. 13 is a flowchart illustrating a method for manufacturing a three-dimensional random access memory according to another embodiment.

[0044] FIG. 14 is a flowchart illustrating the operation method of a three-dimensional random access memory according to embodiments.

[0045] FIG. 15 is a schematic perspective view illustrating an electronic system including a three-dimensional random access memory according to one embodiment.

[0046] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or restricted by the embodiments. Also, the same reference numerals in each drawing indicate the same components.

[0047] Furthermore, the terminology used in this specification is used to appropriately describe preferred embodiments of the present invention, and may vary depending on the intent of the viewer or operator, or the conventions of the field to which the present invention belongs. Accordingly, the definitions of these terms should be based on the content throughout this specification. For example, in this specification, the singular form includes the plural form unless specifically stated otherwise in the text. Also, the terms "comprises" and / or "comprising" used in this specification do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements. Additionally, although terms such as "first," "second," etc., are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by such terms. These terms are used merely to distinguish one specific region, direction, or shape from another region, direction, or shape. Accordingly, a part referred to as the first part in one embodiment may be referred to as the second part in another embodiment.

[0048] Furthermore, it should be understood that various embodiments of the present invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the technical spirit and scope of the present invention in relation to one embodiment. Additionally, it should be understood that the location, arrangement, or configuration of individual components within each presented category of embodiments may be changed without departing from the technical spirit and scope of the present invention.

[0049] Hereinafter, with reference to the drawings, a memory operation method of a 3D random access memory having a structure in which each gate electrode is formed in the shape of a plate extending in the horizontal direction, and vertical structures extending in the vertical direction through the gate electrodes form an array composed of a plurality of columns and rows on a horizontal plane is described in detail.

[0050] The 3D random access memory described below is based on a GAA (Gate-All-Around) based 3-terminal selector memory.

[0051]

[0052] FIG. 1 is a simplified circuit diagram illustrating a three-dimensional random access memory according to one embodiment.

[0053] Referring to FIG. 1, a three-dimensional random access memory according to one embodiment comprises a plurality of bit line horizontal parts (BL1_horizontal part, BL2_horizontal part, BL3_horizontal part; BLH) and a plurality of bit line vertical parts (BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part); BLV) and a plurality of word lines (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, WL2 / 2, 쪋, Including WL2 / n), WL3(WL3 / 1, WL3 / 2, 쪋, WL3 / n), 쪋, WLm(WLm / 1, WLm / 2, 쪋, WLm / n)), multiple bit line vertical parts (BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part); BLV) and multiple word lines (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, Multiple memory cells can be configured at the intersection points of WL2 / 2, 쪋, WL2 / n), WL3(WL3 / 1, WL3 / 2, 쪋, WL3 / n), 쪋, WLm(WLm / 1, WLm / 2, 쪋, WLm / n)).Accordingly, a plurality of memory cells may include a plurality of memory cell strings (CSTR; hereinafter, cell strings) along a plurality of bit line vertical parts (BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part); BLV).

[0054] The bit line horizontal portions (BLH) can be arranged two-dimensionally, spaced apart from each other along the first direction (D1), while extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) can each form a rectangular coordinate system defined by the X, Y, and Z axes, which are orthogonal to each other.

[0055] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit line horizontal portions (BLH). Each of the cell strings (CSTR) includes a bit line vertical portion (BLV), and a plurality of bit line vertical portions (BLV) may be connected in parallel to each of the bit line horizontal portions (BLH).

[0056] Cell strings (CSTRs) may be formed extending in a third direction (D3) and arranged spaced apart from each other along a second direction (D2) by bit line. According to an embodiment, each cell string (CSTR) may include memory cell transistors (MCTs) arranged corresponding to word lines (WL1 (WL1 / 1, WL1 / 2, , WL1 / n), WL2 (WL2 / 1, WL2 / 2, , WL2 / n), WL3 (WL3 / 1, WL3 / 2, , WL3 / n), , WLm (WLm / 1, WLm / 2, , WLm / n)), and string select transistors (SST; hereinafter, select transistors) arranged corresponding to string select lines (SSL1, SSL2, SSL3). Each of the memory cell transistors (MCT) may include a data storage element.

[0057] More specifically, a cell string (CSTR) may be composed of a select transistor (SST) located at the top of the string closest to the bit line horizontal portions (BLH) and multiple memory cell transistors (MCTs) at different distances from the bit line horizontal portions (BLH). That is, the memory cell transistors (MCTs) may be connected in series while arranged along a third direction (D3).

[0058] The select transistor (SST) can be controlled by the string select line (SSL), and the memory cell transistors (MCT) can be controlled by the word lines (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n), WL3(WL3 / 1, WL3 / 2, , WL3 / n), , WLm(WLm / 1, WLm / 2, , WLm / n)).

[0059] Here, the gate electrode (EL-SSL) of the select transistor (SST) may be connected to the string select line (SSL) to be in an equipotential state, and the gate electrodes (EL-WL) of the memory cell transistors (MCT) may be connected in common to one of the word lines (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n), WL3(WL3 / 1, WL3 / 2, , WL3 / n), , WLm(WLm / 1, WLm / 2, , WLm / n)) to be in an equipotential state.

[0060]

[0061] FIG. 2 is a plan view illustrating a three-dimensional random access memory according to one embodiment, FIG. 3 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross section cut along the line A-A' of FIG. 2, FIG. 4a and 4b are drawings for explaining the effect of at least one insulation pattern of a three-dimensional random access memory according to one embodiment, and FIG. 5a and 5b are cross-sectional views illustrating a three-dimensional random access memory to explain the arrangement structure of at least one insulation pattern according to another embodiment.

[0062] The substrate may be a semiconductor substrate, such as a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0063] Stacked structures (ST) may be disposed on a substrate (SUB). The stacked structures (ST) may be formed extending in a first direction (D1) and arranged two-dimensionally along a second direction (D2). Additionally, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0064] Each of the stacked structures (ST) may include gate electrodes (EL; EL-SSL, EL-WL) and interlayer insulating layers (ILD) alternately stacked in a vertical direction perpendicular to the upper surface of the substrate (SUB) (e.g., third direction (D3)). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surface of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction refers to the third direction (D3) or the reverse direction of the third direction (D3).

[0065] Referring again to FIG. 1, the gate electrode (EL-SSL) may be a string select line (SSL), and each of the gate electrodes (EL-WL) may be one of word lines (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n), WL3(WL3 / 1, WL3 / 2, , WL3 / n), , WLm(WLm / 1, WLm / 2, , WLm / n)) stacked in order on a substrate (SUB), and may be a component used as a conductor in a three-dimensional random access memory.

[0066] Each gate electrode (EL) may be formed in the shape of a plate extending in a first direction (D1) and also extending in a second direction (D2), and may have substantially the same thickness in a third direction (D3). Hereinafter, thickness refers to the thickness in the third direction (D3). Each gate electrode (EL) may be formed from a conductive material. For example, each gate electrode (EL) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each gate electrode (EL) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0067] Although not illustrated, either of the upper or lower ends of each of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). For example, the gate electrode located at the top of the gate electrodes (EL) may have the shortest length in the first direction (D1) and the greatest distance from the substrate (SUB) in the third direction (D3). Conversely, the gate electrode located at the bottom of the gate electrodes (EL) may have the longest length in the first direction (D1) and the shortest distance from the substrate (SUB) in the third direction (D3).

[0068] Each interlayer insulating layer (ILD) is depicted as having the same thickness, but is not limited thereto and may have different thicknesses. For example, the bottom and top interlayer insulating layers (ILD) may have a smaller thickness than other interlayer insulating layers (ILD). However, this is exemplary and not limited thereto, and the thickness of each interlayer insulating layer (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating layers (ILD) may be formed of an insulating material to provide insulation between the gate electrodes (EL). For example, the interlayer insulating layers (ILD) may be formed of silicon oxide.

[0069] A plurality of holes (H) penetrating parts of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical structures (VS) may be provided within the holes (H). The vertical structures (VS) may be formed as a plurality of cell strings (CSTR) as shown in FIG. 1, extending in a third direction (D3) while connected to the substrate (SUB). The connection of the vertical structures (VS) to the substrate (SUB) may be achieved by the lower surface of each part of the vertical structures (VS) coming into contact with the upper surface of the substrate (SUB), but is not limited to or restricted thereto and may also be achieved by being embedded inside the substrate (SUB). When a part of each of the vertical structures (VS) is embedded inside the substrate (SUB), the lower surface of the vertical structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).

[0070] Columns of vertical structures (VS) penetrating any one of the stacked structures (ST) may be provided in multiple numbers. As previously described, since the gate electrodes (EL) are formed in a plate shape, the vertical structures (VS) may form an array consisting of multiple columns and rows on the horizontal plane formed by the gate electrodes (EL). For example, as shown in FIG. 2, 12 vertical structures (VS) may penetrate one of the stacked structures (ST) by forming 6 columns and 4 rows. However, the number of vertical structures (VS) forming the array is not limited to or restricted therefrom.

[0071] As such, by forming an array consisting of multiple columns and rows on the horizontal plane of the gate electrodes (EL) formed in the shape of a plate, the 3D random access memory can have a structure in which the integration density of the memory cell string is improved.

[0072] At this time, vertical structures (VS) included in an adjacent pair of columns may be shifted to form different rows on a horizontal plane and arranged so as to be offset from each other. For example, vertical structures (VS) included in the first column may be arranged in the first and third rows, and vertical structures (VS) included in the second column may be arranged in the second and fourth rows, and vertical structures (VS) included in the second column may be arranged in a zigzag shape along the first direction (D1). Accordingly, the density of the memory cell string may be further improved compared to the case where vertical structures (VS) included in an adjacent pair of columns are arranged side by side in the same row on a horizontal plane.

[0073] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). Although the drawings show each of the vertical structures (VS) as having a column shape with equal widths at the top and bottom, they are not limited to this and may have a shape in which the width increases in the first direction (D1) and the second direction (D2) as they go toward the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an elliptical shape, a square shape, or a bar shape.

[0074] These vertical structures (VS) may correspond to the cell strings (CSTR) shown in Fig. 1.

[0075] To this end, each of the vertical structures (VS) may include a data storage pattern (DSP), a bit line vertical portion (BLV), and a select transistor (SST). In each of the vertical structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with the top open, the bit line vertical portion (BLV) may have a shape that fills the space from the bottom to a certain height within the inner space of the data storage pattern (DSP) while being wrapped on the outside by the data storage pattern (DSP), and the select transistor (SST) may have a shape that fills the space from the top to a certain depth within the inner space of the data storage pattern (DSP) while being wrapped on the outside by the data storage pattern (DSP). That is, the select transistor (SST) may be positioned above the bit line vertical portion (BLV) by being located at the top of the inner space of the data storage pattern (DSP).

[0076] The data storage pattern (DSP) surrounds the outer wall of the bit line vertical portion (BLV) and can come into contact with the side walls of the gate electrodes (EL) on the outside. Accordingly, the regions of the data storage pattern (DSP) corresponding to the gate electrodes (EL-WL) can be configured to form memory cells in which memory operations (including write operations such as program operations and erase operations, and read operations) are performed by the voltage applied through the gate electrodes (EL-WL) and the voltage applied to the bit line vertical portion (BLV). Hereinafter, the statement that voltage is applied to the bit line vertical portion (BLV) means that voltage is applied to the bit line horizontal portion (BLH) connected to the bit line vertical portion (BLV) and transmitted to the bit line vertical portion (BLV).

[0077] The memory cells correspond to the memory cell transistors (MCTs) shown in FIG. 1. For this purpose, the data storage pattern (DSP) may be a polarization generating dielectric pattern, which is a data storage element that generates a polarization phenomenon by a voltage applied through the gate electrodes (EL-WL) and a voltage applied to the bit line vertical portion (BLV) to represent a data value as a voltage, current, or resistance change corresponding to the polarization state of the charges.

[0078] For example, as a data storage pattern (DSP), at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr, or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx, or InOx may be used.

[0079] As another example, antiferroelectric materials can be used as data storage patterns (DSP), and ZrO₂ is an example of an antiferroelectric material. x , Zr a X b O x (X may include Hf, Si, Al, Ge, or one of the elements of Group 2 of the periodic table) may be used.

[0080] Although the drawing shows the data storage pattern (DSP) extending in a vertical direction (e.g., the third direction (D3)), it is not limited to or restricted thereto and may have a structure that is spaced apart and arranged only in regions corresponding to the gate electrodes (EL-WL) on the outer wall of the bit line vertical portion (BLV).

[0081] The lower surface of the data storage pattern (DSP) can be located at a lower level than the lower surface of the lowest of the gate electrodes (EL-WL) and can be formed to be in contact with the substrate (SUB).

[0082] In conventional 3D random access memory, during memory operation on a target memory cell, the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) containing the target memory cell is grounded, and the operating voltage (V) is applied through the selected gate electrode (Sel EL) corresponding to the target memory cell. OP Apply the entire value of ) and pass voltage (V) through the unselected gate electrode (Unsel EL) corresponding to the unselected memory cell. PASS By applying ) to the target memory cell, the operating voltage (V OP ) can be applied. In this case, the pass voltage (V PASS Problems may arise where the target memory cell is affected by ).

[0083] Accordingly, during memory operation for the target memory cell, the operating voltage (V) is used through the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) containing the target memory cell. OP Bit line voltage (V) having at least some value of ) BL ) is applied, and the bit line voltage (V) is applied through the selected gate electrode (Sel EL) corresponding to the target memory cell. BL It has opposite polarity to ) and the operating voltage (V OP Gate voltage (V) having the remaining partial value of ) G By applying ) to the target memory cell, the operating voltage (V) is applied as shown in Equation 1 below. OP A method for authorizing ) was proposed.

[0084] <Equation 1>

[0085] |V BL -V G |=V OP

[0086] However, through the bit line vertical portion (BLV) of the selected vertical structure (Sel VS), the operating voltage (V OP Bit line voltage (V) having at least some value of ) BL ) is applied, and the bit line voltage (V) is applied through the selected gate electrode (Sel EL) corresponding to the target memory cell. BL It has opposite polarity to ) and the operating voltage (V OP Gate voltage (V) having the remaining partial value of ) G The method of applying ) is the bit line voltage (V) applied through the bit line vertical portion (BLV). BL Because ) affects the unselected memory cells, it has the disadvantage of causing memory malfunctions in which some of the unselected memory cells are programmed, as shown in FIG. 4a.

[0087] Accordingly, to prevent the above disadvantages, the data storage pattern (DSP) of a three-dimensional random access memory according to one embodiment may include at least one isolation pattern (IP). The at least one isolation pattern (IP) may be used to prevent memory operation on unselected memory cells among the memory cells, excluding the target memory cell, during memory operation on the target memory cell.

[0088] More specifically, at least one insulating pattern (IP) increases the operating voltage required for memory operation as shown in FIG. 4b, or the coercive field (E) in unselected memory cells. C By increasing ), polarization phenomena in unselected memory cells are prevented, thereby preventing some unselected memory cells from being programmed.

[0089] In the drawings, at least one insulating pattern (IP) is depicted as being disposed on the outer wall of the data storage pattern (DSP) (hereinafter, the outer wall refers to the interface where the data storage pattern (DSP) comes into contact with the gate electrodes (EL), but is not limited thereto. For example, at least one insulating pattern (IP) may be disposed on the inner wall of the data storage pattern (DSP) as shown in FIG. 5a (hereinafter, the inner wall refers to the interface where the data storage pattern (DSP) comes into contact with the bit line vertical portion (BLV)), or may be embedded inside the data storage pattern (DSP) as shown in FIG. 5b. Although not depicted in a separate drawing, at least one insulating pattern (IP) may be disposed on at least one of the outer wall, inner wall, or inside of the data storage pattern (DSP).

[0090] At least one such insulation pattern (IP) enables memory operation for the target memory cell through the operating voltage (V) via the bit line vertical portion (BLV) of the selected vertical structure (Sel VS). OP Bit line voltage (V) having at least some value of ) BL ) is applied and the bit line voltage (V) is applied through the selected gate electrode (Sel EL) corresponding to the target memory cell. BL It has opposite polarity to ) and the operating voltage (V OP Gate voltage (V) having the remaining partial value of ) G As ) is applied, the operating voltage (V) to the target memory cell OP Conditions that allow ) to be applied) and conditions that prevent memory operation for non-selected memory cells (operating voltage (V) through the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) for non-selected memory cells included in the selected vertical structure (Sel VS) OP Bit line voltage (V) having at least some value of ) BL It can be formed into a substance that satisfies the condition that ) does not have an effect.

[0091] For example, at least one insulating pattern (IP) may be formed from at least one material among a silicon-based material, a high dielectric constant (High K) material, a low dielectric constant (Low K) material, or an oxide semiconductor material (an oxide semiconductor material having a high bandgap greater than or equal to a preset value).

[0092] Likewise, at least one isolation pattern (IP) enables memory operation for the target memory cell through the operating voltage (V) via the bit line vertical portion (BLV) of the selected vertical structure (Sel VS). OP Bit line voltage (V) having at least some value of ) BL ) is applied and the bit line voltage (V) is applied through the selected gate electrode (Sel EL) corresponding to the target memory cell. BL It has opposite polarity to ) and the operating voltage (V OP Gate voltage (V) having the remaining partial value of ) G As ) is applied, the operating voltage (V) to the target memory cell OP Conditions that allow ) to be applied) and conditions that prevent memory operation for non-selected memory cells (operating voltage (V) through the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) for non-selected memory cells included in the selected vertical structure (Sel VS) OP Bit line voltage (V) having at least some value of ) BL It can be formed with a thickness determined by a value that satisfies the condition that ) does not have an effect.

[0093] A bit line vertical portion (BLV) (hereinafter, the bit line vertical portion (BLV) may be referred to as a vertical electrode) is a component used as a conductor rather than a channel in a three-dimensional random access memory, and can be connected to each of the bit line horizontal portions (BLH) located above the vertical structures (VS) through a select transistor (SST) while being included in each of the vertical structures (VS). To this end, the bit line vertical portion (BLV) can be in contact with the bit line horizontal portions (BLH) through the select transistor (SST) above, and the upper surface of the select transistor (SST) can be substantially co-planar with the data storage pattern (DSP).

[0094] The bit line vertical portion (BLV) may be formed of a conductive material comprising at least one selected from doped semiconductors (e.g., doped silicon, etc.), metals (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.).

[0095] The lower surface of the bit line vertical portion (BLV) may be located at a lower level than the lower surface of the lowest of the gate electrodes (EL) and may be spaced apart from the substrate (SUB) by a certain amount. However, it is not limited to or restricted therefrom.

[0096] The select transistor (SST) can be configured to connect the bit line vertical portion (BLV) to the bit line horizontal portion (BLH) while positioned above the bit line vertical portion (BLV).

[0097] More specifically, the select transistor (SST) can serve as a selector that turns on a selected vertical structure (Sel VS; selected memory cell string) containing a target memory cell that is the target of memory operation among the vertical structures (VS) connected to the same bit line horizontal portion (BLH), and turns off at least one unselected vertical structure (Unsel VS; unselected memory cell string) that does not contain a target memory cell.

[0098] For example, the select transistor (SST) can be used to ensure that, during memory operation for a target memory cell, the operating voltage is applied only to the selected vertical structure (Sel VS) among the vertical structures (VS) connected to the same bit line horizontal portion (BLH), and that the operating voltage is not applied to at least one unselected vertical structure (Unsel VS). In this way, the select transistor (SST) can prevent parasitic capacitance from occurring in at least one unselected vertical structure (Unsel VS) by ensuring that the operating voltage is not applied to at least one unselected vertical structure (Unsel VS).

[0099] To this end, the select transistor (SST) may be formed from a semiconductor material (e.g., polycrystalline silicon or oxide semiconductor material, etc.) that selectively forms a channel to be turned on or turned off depending on the applied voltage. For example, the channel of the select transistor (SST) may be formed from a semiconductor material that turns on or turns off depending on the applied voltage, and the drain and source of the transistor (SST) may be formed by doping the semiconductor material with impurities (N-type impurities) to improve contact resistance with the bit line vertical portion (BLV) or the bit line horizontal portion (BLH).

[0100] The described select transistor (SST) can be used not only as a selector but also to pre-charge a vertical structure (VS). Specifically, the select transistor (SST) may be used to fill a pre-charge voltage to pre-charge a selected vertical structure (Sel VS) containing the target memory cell among the vertical structures (VS) during a read operation on the target memory cell.

[0101] Such a select transistor (SST) is turned on or turned off according to the control of the corresponding gate electrode (EL-SSL), and can enable or disable the included vertical structure (VS).

[0102] The select transistor (SST) is not limited to or restricted to the structure described above and may have a structure that further includes a dielectric pattern (not shown). For example, the select transistor (SST) may have a structure that further includes a dielectric pattern placed on top of a data storage pattern (DSP) corresponding to the select transistor (SST).

[0103] In addition, the select transistor (SST) may have a structure including an embedded pattern (not shown) inside. For example, an embedded pattern may be formed inside the select transistor (SST) with a material that helps diffusion of charges or holes (e.g., an intrinsic semiconductor or a polycrystalline semiconductor material with excellent charge-hole mobility) to facilitate the selection transistor (SST) forming a channel.

[0104] Additionally, the select transistor (SST) may further include a barrier metal layer (not shown) disposed on the contact surface with the bit line vertical portion (BLV). The barrier metal layer may be optionally included or omitted depending on what material forms the bit line vertical portion (BLV). For example, the barrier metal layer may be formed of TiN when the material forming the bit line vertical portion (BLV) is tungsten (W).

[0105] At this time, at least two bit line horizontal parts (BLH) are located at the same height above the vertical structures (VS), and the vertical structures (VS) arranged in the same row in the array may further include a bit line plug (BLPG) positioned at a position offset from the center of each of the vertical structures (VS) to be connected to each of the different bit line horizontal parts (BLH). That is, the vertical structures (VS) arranged in the same row in the array may be connected to each of the different bit line horizontal parts (BLH) through the bit line plug (BLPG) positioned at a position offset from the center of each of the vertical structures (VS).

[0106] A separation trench (not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). Insulating spacers (not shown) may be formed in the separation trench to separate the adjacent stacked structures (ST). For example, the insulating spacers may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0107] A capping insulating film (CAP) may be provided on the stacked structures (ST) and vertical structures (VS). The capping insulating film (CAP) may cover the upper surface of the uppermost of the interlayer insulating layers (ILD). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it moves toward the third direction (D3).

[0108] Bit line horizontal portions (BLH) may be provided on the capping insulating film (CAP) and the bit line contact plug (BLPG). The bit line horizontal portions (BLH) may be formed by extending a conductive material along the second direction (D2) while being spaced apart from each other along the first direction (D2). The conductive material constituting the bit line horizontal portions (BLH) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL).

[0109] The three-dimensional random access memory described above is not limited to or restricted to the described structure, and can be implemented in various structures based on a vertical structure (VS) including a select transistor (SST) and a bit line vertical portion (BLV) according to an implementation example.

[0110] As described, the three-dimensional random access memory can perform memory operations in response to a voltage applied between the bit line horizontal portions (BLH) and bit line vertical portions (BLV) and the gate electrodes (EL).

[0111] Here, the three-dimensional random access memory can perform memory operations on the selected target memory cell by using a select transistor (SST) to turn on (activate) only the selected vertical structure (Sel VS) containing the target memory cell among the vertical structures (VS) connected to the same bit line horizontal portion (BLH) and turning off (deactivate) at least one unselected vertical structure (Unsel VS), and in response to a voltage applied between the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) and the selected gate electrode (Sel EL) among the gate electrodes (EL).

[0112] In particular, the 3D random access memory can prevent memory operations on unselected memory cells included in the selected vertical structure (Sel VS) during memory operations on the target memory cell by using at least one isolation pattern (IP) included in the data storage pattern (DSP).

[0113]

[0114] FIG. 6 is a flowchart illustrating a memory operation method of a three-dimensional random access memory according to one embodiment, and FIG. 7 is a diagram for explaining a memory operation method of a three-dimensional random access memory according to one embodiment.

[0115] The memory operation method described below performs a memory operation on a target memory cell, and is based on the premise that it is performed by a three-dimensional random access memory of the structure described above with reference to FIGS. 1 to 5b.

[0116] In step (S610), the 3D random access memory operates via an operating voltage (V) through a selected bit line horizontal portion (Sel BLH) connected to a selected vertical structure (Sel VS) containing a target memory cell among the vertical structures (VS). OPBit line voltage (V) having at least some value of ) BL By applying ), the operating voltage (V) to the bit line vertical portion (Sel BLV) included in the selected vertical structure (Sel VS) OP Bit line voltage (V) having at least some value of ) BL ) can be applied. For example, a 3D random access memory has an operating voltage (V OP Bit line voltage (V) having half the value of ) BL ) can be applied. In this case, the bit line voltage (V BL ) can be expressed as Equation 2 below.

[0117] <Equation 2>

[0118] V BL =±1 / 2V OP

[0119] In particular, at step (S610), the three-dimensional random access memory utilizes at least one insulating pattern (IP) included within the outer wall, inner wall, or interior of the data storage pattern (DSP) to increase the operating voltage required for memory operation or the coercive field (E) in the unselected memory cells. C By increasing ), polarization phenomena in unselected memory cells can be prevented. By preventing polarization phenomena in unselected memory cells by at least one insulation pattern (IP), memory operation for unselected memory cells can be prevented.

[0120] In step (S610), the three-dimensional random access memory can ground at least one unselected bit line horizontal portion (Unsel BLH) excluding the selected bit line horizontal portion (Sel BLH) among the bit line horizontal portions (BLH).

[0121] In step (S620), the 3D random access memory has a bit line voltage (V) on the selected vertical structure (Sel VS). BLThe select transistor (SST) of the selected vertical structure (Sel VS) can be turned on so that ) is applied.

[0122] Turning on the selection transistor (SST) of the selected vertical structure (Sel VS) can be achieved by applying a turn-on voltage to the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of the selected vertical structure (Sel VS).

[0123] In step (S630), the 3D random access memory has a bit line voltage (V) on at least one unselected vertical structure (Unsel VS) connected to a bit line horizontal portion (Sel BLH) selected identically to a selected vertical structure (Sel VS) among the unselected vertical structures (Unsel VS) that do not include a target memory cell. BL To prevent ) from being applied, the select transistor (SST) of at least one unselected vertical structure (Unsel VS) can be turned off.

[0124] Turning off the selection transistor (SST) of at least one unselected vertical structure (Unsel VS) can be achieved by floating or grounding the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of at least one unselected vertical structure (Unsel VS), or by applying a turn-off voltage to the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of at least one unselected vertical structure (Unsel VS).

[0125] Thus, the 3D random access memory has a bit line voltage (V) on at least one unselected vertical structure (Unsel VS) in step (S630). BLBy turning off the select transistor (SST) of at least one unselected vertical structure (Unsel VS) so that ) is not applied, parasitic capacitance can be prevented from occurring in at least one unselected vertical structure (Unsel VS).

[0126] In step (S640), the 3D random access memory applies a bit line voltage (V) to the selected gate electrode (Sel EL) corresponding to the target memory cell among the gate electrodes (EL-WL). BL It has opposite polarity to ) and the operating voltage (V OP Gate voltage (V) having the remaining partial value of ) G ) can be applied. For example, 3D random access memory has a bit line voltage (V BL It has opposite polarity to ) and the operating voltage (V OP Gate voltage (V) having half the value of ) G ) can be applied. In this case, the gate voltage (V G ) can be expressed as Equation 3 below.

[0127] <Equation 3>

[0128] V G =±1 / 2V OP

[0129] For example, +1 / 2V in step (S610) OP This bit line voltage (V BL If authorized as ), -1 / 2V at step (S640) OP This gate voltage (V G It can be applied as ). As another example, -1 / 2V in step (S610) OP This bit line voltage (V BL If authorized as ), +1 / 2V at step (S640) OP This gate voltage (V G It can be applied as ). As another example, +1 / 3V at step (S610) OP This bit line voltage (V BLIf authorized as ), -2 / 3V at step (S640) OP This gate voltage (V G It can be applied as ). As another example, -1 / 3V in step (S610) OP This bit line voltage (V BL If authorized as ), +2 / 3V at step (S640) OP This gate voltage (V G It can be applied as ). As another example, +3 / 4V at step (S610) OP This bit line voltage (V BL If authorized as ), -1 / 4V at step (S640) OP This gate voltage (V G It can be authorized as ). As another example, -3 / 4V in step (S610) OP This bit line voltage (V BL If authorized as ), +1 / 4V at step (S640) OP This gate voltage (V G It can be authorized as ).

[0130] As such, in steps (S610) and (S640), the operating voltage (V) has opposite polarity to each other. OP Bit line voltage (V) having at least some value of ) BL ) and operating voltage (V OP Gate voltage (V) having the remaining partial value of ) G As each is applied, voltages (V) are applied to the target memory cell as shown in Equation 1 above. BL , V G The operating voltage (V), which is the difference value between ) OP ) can be authorized.

[0131] That is, the 3D random access memory applies an operating voltage (V) to the target memory cell through steps (S610 and S640). OP By applying ), memory operations on the target memory cell can be performed.

[0132] The 3D random access memory, in a state where the select transistor (SST) of at least one unselected vertical structure (Unsel VS) is turned off through step (S630), applies a gate voltage (V) to the selected gate electrode (Sel EL) through step (S640). G By applying ), it is possible to prevent memory operation from occurring for the memory cell corresponding to the selected gate electrode (Sel EL) among the memory cells of at least one unselected vertical structure (Unsel VS).

[0133] In step (S650), the 3D random access memory may ground at least one unselected gate electrode (Unsel EL) among the gate electrodes (EL-WL), excluding the selected gate electrode (Sel EL). Accordingly, the pass voltage (V) applied to the unselected gate electrode (Unsel EL) PASS The problem of the target memory cell being affected by ) can be resolved.

[0134] The steps described above (S610 to S650) may be performed sequentially according to the ascending order of the reference numerals, but are not limited thereto.

[0135] The memory operation described above may be a write operation (a programming operation that writes data "1" to the target memory cell or an erase operation that writes data "0" to the target memory cell) or a read operation on the target memory cell.

[0136] Although the gate electrodes (EL-WL) in FIG. 7 are shown as being separated by block, they are not limited to or restricted thereto, and the gate electrodes (EL-WL) may have a structure in which they are substantially connected independently of the blocks. Even in such cases, the gate electrodes (EL-SSL) of the select transistor (SST) may have a structure in which they are separated by block to turn on or turn off the select transistor (SST) by block.

[0137]

[0138] Hereinafter, with reference to the drawings, a memory operation method of a 3D random access memory having a structure in which each gate electrode is formed in the shape of a plate extending in the horizontal direction, and vertical structures extending in the vertical direction through the gate electrodes form an array composed of a plurality of columns and rows on a horizontal plane is described in detail.

[0139] The 3D random access memory described below is based on a GAA (Gate-All-Around) based 3-terminal selector memory.

[0140]

[0141] FIG. 8 is a simplified circuit diagram illustrating a three-dimensional random access memory according to one embodiment.

[0142] Referring to FIG. 8, a three-dimensional random access memory according to one embodiment comprises a plurality of bit line horizontal parts (BL1_horizontal part, BL2_horizontal part, BL3_horizontal part; BLH) and a plurality of bit line vertical parts (BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part), BL4_vertical part(BL4 / 1_Vertical part, BL4 / 2_Vertical part, BL4 / 3_Vertical part); BLV), and a plurality of word lines (WL1(WL1 / 1, Including WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, WL2 / 2, 쪋, WL2 / n)), multiple bit line vertical parts (BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part), BL4_vertical part(BL4 / 1_Vertical part, BL4 / 2_Vertical part, BL4 / 3_Vertical part);Multiple memory cells can be configured at the intersection points of BLV) and multiple word lines (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, WL2 / 2, 쪋, WL2 / n)). Accordingly, a plurality of memory cells can form a plurality of memory cell strings (CSTR; hereinafter, cell strings) along a plurality of bit line vertical parts (BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part), BL4_vertical part(BL4 / 1_Vertical part, BL4 / 2_Vertical part, BL4 / 3_Vertical part); BLV).

[0143] The bit line horizontal portions (BLH) can be arranged two-dimensionally, spaced apart from each other along the first direction (D1), while extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) can each form a rectangular coordinate system defined by the X, Y, and Z axes, which are orthogonal to each other.

[0144] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit line horizontal portions (BLH). Each of the cell strings (CSTR) includes a bit line vertical portion (BLV), and a plurality of bit line vertical portions (BLV) may be connected in parallel to each of the bit line horizontal portions (BLH).

[0145] Cell strings (CSTRs) may be formed extending in a third direction (D3) and arranged spaced apart from each other along a second direction (D2) by bit line. According to an embodiment, each cell string (CSTR) may include memory cell transistors (MCTs) arranged corresponding to word lines (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n)), and string select transistors (SST; hereinafter, select transistors) arranged corresponding to string select lines (SSL1, SSL2, SSL3). Each memory cell transistor (MCT) may include a data storage element.

[0146] More specifically, a cell string (CSTR) may be composed of a select transistor (SST) located at the top of the string closest to the bit line horizontal portions (BLH) and multiple memory cell transistors (MCTs) at different distances from the bit line horizontal portions (BLH). That is, the memory cell transistors (MCTs) may be connected in series while arranged along a third direction (D3).

[0147] The select transistor (SST) can be controlled by the string select line (SSL), and the memory cell transistors (MCT) can be controlled by the word lines (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n)).

[0148] Here, the gate electrode (EL-SSL) of the select transistor (SST) may be connected to the string select line (SSL) to be in an equipotential state, and the gate electrodes (EL-WL) of the memory cell transistors (MCT) may be connected in common to one of the word lines (WL1 (WL1 / 1, WL1 / 2, , WL1 / n), WL2 (WL2 / 1, WL2 / 2, , WL2 / n)) to be in an equipotential state.

[0149] That is, the gate electrode (EL-SSL) of the select transistor (SST) may represent a string select line (SSL), and the gate electrodes (EL-WL) of the memory cell transistors (MCT) may represent word lines (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n)).

[0150] String selection lines (SSL) can be shared by cell strings (CSTR) included in the same string selection line block (SB1, SB2, SB3, SB4; SB) (e.g., cell strings (CSTR) located in the same column as shown in the drawing), and word lines (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, WL2 / 2, 쪋, WL2 / n)) can be shared by cell strings (CSTR) included in the same word line block (WB1, WB2; WB) (e.g., cell strings (CSTR) located in two adjacent columns as shown in the drawing).

[0151]

[0152] FIG. 9 is a plan view illustrating a three-dimensional random access memory according to one embodiment, FIG. 10 is a plan view illustrating a three-dimensional random access memory according to another embodiment, and FIG. 11 is a cross-sectional view illustrating a three-dimensional random access memory according to embodiments, corresponding to a cross-section cut along the line A-A' of FIG. 9 to 10.

[0153] The substrate (SUB) may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0154] Stacked structures (ST) may be disposed on a substrate (SUB). The stacked structures (ST) may be formed extending in a first direction (D1) and arranged two-dimensionally along a second direction (D2). Additionally, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0155] Each of the stacked structures (ST) may include gate electrodes (EL; EL-SSL, EL-WL) and interlayer insulating layers (ILD) alternately stacked in a vertical direction perpendicular to the upper surface of the substrate (SUB) (e.g., third direction (D3)). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surface of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction refers to the third direction (D3) or the reverse direction of the third direction (D3).

[0156] Referring again to FIG. 8, the gate electrode (EL-SSL) may be a string select line (SSL), and each of the gate electrodes (EL-WL) may be one of the word lines (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n)) stacked sequentially on the substrate (SUB), and may be a component used as a conductor in a three-dimensional random access memory.

[0157] Each of the gate electrodes (EL-WL, EL-SSL) may be formed in the shape of a plate extending in a first direction (D1) and also extending in a second direction (D2), and may have substantially the same thickness in a third direction (D3). Hereinafter, thickness refers to the thickness in the third direction (D3). Each of the gate electrodes (EL-WL, EL-SSL) may be formed from a conductive material. For example, each of the gate electrodes (EL-WL, EL-SSL) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL-WL, EL-SSL) may include at least one of all metal materials that can be formed by ALD in addition to the described metal material.

[0158] As illustrated in FIG. 9, the lower end of each of the stacked structures (ST) may have a stepwise structure (SS) along the first direction (D1). More specifically, the stepwise structure of the gate electrodes (EL-WL, EL-SSL) included in the stacked structures (ST) may be implemented such that the length in the first direction (D1) decreases as the gate electrodes (EL-WL, EL-SSL) move further away from the substrate (SUB). For example, the uppermost electrode among the gate electrodes (EL-WL, EL-SSL) may have the shortest length in the first direction (D1) as it is the electrode with the largest distance from the substrate (SUB) in the third direction (D3). On the other hand, the lowermost electrode among the gate electrodes (EL-WL, EL-SSL) may have the longest length in the first direction (D1) as it is the electrode with the shortest distance from the substrate (SUB) in the third direction (D3).

[0159] However, it is not limited to or restricted thereto, and as illustrated in FIG. 10, the upper end of each of the stacked structures (ST) may also have a stepped structure (SS) along the first direction (D1). Although not illustrated in the drawings, a word line plug (not shown) may be formed on the upper surface of each of the stepped structures (SS) of the gate electrodes (EL-WL, EL-SSL).

[0160] Accordingly, the three-dimensional random access memory can perform memory operation in response to a voltage applied in both directions from the word line plugs at both ends formed in the step structure (SS) at each end of the gate electrodes (EL-WL, EL-SSL) toward a selected vertical structure (Sel VS) containing a target memory cell among the vertical structures (VS).

[0161] Each of the interlayer insulating layers (ILD) is depicted as having the same thickness, but is not limited thereto and may have different thicknesses. For example, the bottom and top interlayer insulating layers (ILD) may have a smaller thickness than other interlayer insulating layers (ILD). However, this is exemplary and is not limited thereto, and the thickness of each interlayer insulating layer (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating layers (ILD) may be formed of an insulating material for insulation between the gate electrodes (EL-WL, EL-SSL). For example, the interlayer insulating layers (ILD) may be formed of silicon oxide.

[0162] A plurality of holes (H) penetrating parts of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical structures (VS) may be provided within the holes (H). The vertical structures (VS) may be formed as a plurality of cell strings (CSTR) as shown in FIG. 8, extending in a third direction (D3) while connected to the substrate (SUB). The connection of the vertical structures (VS) to the substrate (SUB) may be achieved by the lower surface of each part of the vertical structures (VS) coming into contact with the upper surface of the substrate (SUB), but is not limited to or restricted thereto and may also be achieved by being embedded inside the substrate (SUB). When a part of each of the vertical structures (VS) is embedded inside the substrate (SUB), the lower surface of the vertical structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).

[0163] Columns of vertical structures (VS) penetrating any one of the stacked structures (ST) may be provided in multiple numbers. As previously described, since the gate electrodes (EL-WL, EL-SSL) are formed in a plate shape, the vertical structures (VS) may form an array consisting of multiple columns and rows on the horizontal plane formed by the gate electrodes (EL-WL, EL-SSL). For example, as shown in FIG. 9, 18 vertical structures (VS) may penetrate one of the stacked structures (ST) by forming 12 columns and 3 rows. However, the number of vertical structures (VS) forming the array is not limited to or restricted therefrom.

[0164] As such, by forming an array consisting of multiple columns and rows on the horizontal plane of gate electrodes (EL-WL, EL-SSL) formed in the shape of plates, the 3D random access memory can have a structure in which the integration density of the memory cell string is improved.

[0165] At this time, vertical structures (VS) included in an adjacent pair of columns may be shifted and arranged so as to be offset from each other, forming different rows on a horizontal plane. For example, vertical structures (VS) included in the first column may be arranged in the first and third rows, and vertical structures (VS) included in the second column may be arranged in the second row, and vertical structures (VS) included in an adjacent pair of columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the density of the memory cell string may be further improved compared to the case where vertical structures (VS) included in an adjacent pair of columns are arranged side by side in the same row on a horizontal plane.

[0166] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). Although the drawings show each of the vertical structures (VS) as having a column shape with equal widths at the top and bottom, they are not limited to this and may have a shape in which the width increases in the first direction (D1) and the second direction (D2) as they go toward the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an elliptical shape, a square shape, or a bar shape.

[0167] These vertical structures (VS) may correspond to the cell strings (CSTR) shown in Fig. 8.

[0168] To this end, each of the vertical structures (VS) may include a data storage pattern (DSP), a bit line vertical portion (BLV), and a select transistor (SST). In each of the vertical structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with the top open, the bit line vertical portion (BLV) may have a shape that fills the space from the bottom to a certain height within the inner space of the data storage pattern (DSP) while being wrapped on the outside by the data storage pattern (DSP), and the select transistor (SST) may have a shape that fills the space from the top to a certain depth within the inner space of the data storage pattern (DSP) while being wrapped on the outside by the data storage pattern (DSP). That is, the select transistor (SST) may be positioned above the bit line vertical portion (BLV) by being located at the top of the inner space of the data storage pattern (DSP).

[0169] The data storage pattern (DSP) surrounds the outer wall of the bit line vertical portion (BLV) and can come into contact with the side walls of the gate electrodes (EL-WL, EL-SSL) on the outside. Accordingly, the regions of the data storage pattern (DSP) corresponding to the gate electrodes (EL-WL) can be configured to form memory cells in which memory operations (including write operations such as program operations and erase operations, and read operations) are performed by the voltage applied through the gate electrodes (EL-WL) and the voltage applied to the bit line vertical portion (BLV). Hereinafter, the statement that voltage is applied to the bit line vertical portion (BLV) means that voltage is applied to the bit line horizontal portion (BLH) connected to the bit line vertical portion (BLV) and transmitted to the bit line vertical portion (BLV).

[0170] The memory cells correspond to the memory cell transistors (MCTs) shown in FIG. 8. For this purpose, the data storage pattern (DSP) may be a polarization generating dielectric pattern, which is a data storage element that generates a polarization phenomenon by a voltage applied through the gate electrodes (EL-WL) and a voltage applied to the bit line vertical portion (BLV) to represent a data value as a voltage, current, or resistance change corresponding to the polarization state of the charges.

[0171] For example, as a data storage pattern (DSP), at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr, or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx, or InOx may be used.

[0172] As another example, antiferroelectric materials can be used as data storage patterns (DSP), and ZrO₂ is an example of an antiferroelectric material. x , Zr a X b O x (X may include Hf, Si, Al, Ge, or one of the elements of Group 2 of the periodic table) may be used.

[0173] Although the drawing shows the data storage pattern (DSP) extending in a vertical direction (e.g., the third direction (D3)), it is not limited to or restricted thereto and may have a structure that is spaced apart and arranged only in regions corresponding to the gate electrodes (EL-WL) on the outer wall of the bit line vertical portion (BLV).

[0174] The lower surface of the data storage pattern (DSP) can be located at a lower level than the lower surface of the lowest of the gate electrodes (EL-WL) and can be formed to be in contact with the substrate (SUB).

[0175] A bit line vertical portion (BLV) (hereinafter, the bit line vertical portion (BLV) may be referred to as a vertical electrode) is a component used as a conductor rather than a channel in a three-dimensional random access memory, and can be connected to each of the bit line horizontal portions (BLH) located above the vertical structures (VS) through a select transistor (SST) while being included in each of the vertical structures (VS). To this end, the bit line vertical portion (BLV) can be in contact with the bit line horizontal portions (BLH) through the select transistor (SST) above, and the upper surface of the select transistor (SST) can be substantially co-planar with the data storage pattern (DSP).

[0176] The bit line vertical portion (BLV) may be formed of a conductive material comprising at least one selected from doped semiconductors (e.g., doped silicon, etc.), metals (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.).

[0177] The lower surface of the bit line vertical portion (BLV) may be located at a lower level than the lower surface of the lowest of the gate electrodes (EL-WL, EL-SSL) and may be spaced apart from the substrate (SUB) by a certain amount. However, it is not limited to or restricted therefrom.

[0178] The select transistor (SST) can be configured to connect the bit line vertical portion (BLV) to the bit line horizontal portion (BLH) while positioned above the bit line vertical portion (BLV).

[0179] More specifically, the select transistor (SST) can serve as a selector that turns on a selected vertical structure (Sel VS; selected memory cell string) containing a target memory cell that is the target of memory operation among the vertical structures (VS) connected to the same bit line horizontal portion (BLH), and turns off at least one unselected vertical structure (Unsel VS; unselected memory cell string) that does not contain a target memory cell.

[0180] For example, the select transistor (SST) can be used to ensure that, during memory operation for a target memory cell, the operating voltage is applied only to the selected vertical structure (Sel VS) among the vertical structures (VS) connected to the same bit line horizontal portion (BLH), and that the operating voltage is not applied to at least one unselected vertical structure (Unsel VS). In this way, the select transistor (SST) can prevent parasitic capacitance from occurring in at least one unselected vertical structure (Unsel VS) by ensuring that the operating voltage is not applied to at least one unselected vertical structure (Unsel VS).

[0181] To this end, the select transistor (SST) may be formed from a semiconductor material (e.g., polycrystalline silicon or oxide semiconductor material, etc.) that selectively forms a channel to be turned on or turned off depending on the applied voltage. For example, the channel of the select transistor (SST) may be formed from a semiconductor material that turns on or turns off depending on the applied voltage, and the drain and source of the transistor (SST) may be formed by doping the semiconductor material with impurities (N-type impurities) to improve contact resistance with the bit line vertical portion (BLV) or the bit line horizontal portion (BLH).

[0182] The described select transistor (SST) can be used not only as a selector but also to pre-charge a vertical structure (VS). Specifically, the select transistor (SST) may be used to fill a pre-charge voltage to pre-charge a selected vertical structure (Sel VS) containing the target memory cell among the vertical structures (VS) during a read operation on the target memory cell.

[0183] Such a select transistor (SST) is turned on or turned off according to the control of the corresponding gate electrode (EL-SSL), and can enable or disable the included vertical structure (VS).

[0184] The select transistor (SST) is not limited to or restricted to the structure described above and may have a structure that further includes a dielectric pattern (not shown). For example, the select transistor (SST) may have a structure that further includes a dielectric pattern placed on top of a data storage pattern (DSP) corresponding to the select transistor (SST).

[0185] In addition, the select transistor (SST) may have a structure including an embedded pattern (not shown) inside. For example, an embedded pattern may be formed inside the select transistor (SST) with a material that helps diffusion of charges or holes (e.g., an intrinsic semiconductor or a polycrystalline semiconductor material with excellent charge-hole mobility) to facilitate the selection transistor (SST) forming a channel.

[0186] Additionally, the select transistor (SST) may further include a barrier metal layer (not shown) disposed on the contact surface with the bit line vertical portion (BLV). The barrier metal layer may be optionally included or omitted depending on what material forms the bit line vertical portion (BLV). For example, the barrier metal layer may be formed of TiN when the material forming the bit line vertical portion (BLV) is tungsten (W).

[0187] Although FIG. 11 illustrates that the bit line horizontal parts (BLH) are located at different heights above the vertical structures (VS), this is a three-dimensional representation to aid in understanding the structure of the three-dimensional random access memory, and in reality, the bit line horizontal parts (BLH) above the vertical structures (VS) may all be located at the same height. As such, at least two bit line horizontal parts (BLH) are located at the same height above the vertical structures (VS), the vertical structures (VS) arranged in the same row in the array may further include bit line plugs (BLPG) positioned at offset from the center of each vertical structure (VS) to be connected to each of the different bit line horizontal parts (BLH). That is, vertical structures (VS) placed in the same row in the array can be connected to different bit line horizontal parts (BLH) through bit line plugs (BLPG) placed at positions offset from the center of each vertical structure (VS).

[0188] Between adjacent stacked structures (ST), at least one word line slit (WS) may be provided, which extends in a first direction (D1) and is formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant. The at least one word line slit (WS) is a component that separates at least one gate electrode (EL-WL) corresponding to a word line (WL1 (WL1 / 1, WL1 / 2, , WL1 / n), WL2 (WL2 / 1, WL2 / 2, , WL2 / n)) among the gate electrodes (EL-SSL, EL-WL) by word line block (WB1, WB2; WB), and may have a depth etched to the upper surface of the substrate (SUB) in a vertical direction (e.g., a third direction (D3)).

[0189] Here, separating at least one gate electrode (EL-WL) by word line block (WB1, WB2; WB) means having a structure in which at least one gate electrode (EL-WL) is physically and electrically separated by word line block (WB1, WB2; WB). For example, word lines (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, WL2 / 2, 쪋, WL2 / n)) can be physically and electrically separated into word lines (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n)) included in the first word line block (WB1) and word lines (WL2(WL2 / 1, WL2 / 2, 쪋, WL2 / n)) included in the second word line block (WB2) by at least one word line slit (WS).

[0190] Each of the word line blocks (WB1, WB2; WB) may include a plurality of string select line blocks (SB1, SB2, SB3, SB4; SB4). Such string select line blocks (SB1, SB2, SB3, SB4) may be separated by at least one string select slit (SS). More specifically, at least one string select slit (SS) is provided that extends in a first direction (D1) and is formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant, thereby allowing at least one gate electrode (EL-SSL) corresponding to a string select line (SSL) among the gate electrodes (EL-SSL, EL-WL) to be separated by string select line blocks (SB1, SB2, SB3, SB4; SB). To this end, at least one string selection slit (SS) may have an etched depth up to the depth of at least one gate electrode (EL-SSL) corresponding to the string selection line (SSL) in the vertical direction (e.g., third direction (D3)).

[0191] Likewise, separating at least one gate electrode (EL-SSL) by string select line blocks (SB1, SB2, SB3, SB4; SB) means having a structure in which at least one gate electrode (EL-SSL) is physically and electrically separated by string select line blocks (SB1, SB2, SB3, SB4; SB). For example, string select lines (SSL1, SSL2, SSL3, SSL4) can be physically and electrically separated by at least one string select slit (SS) into a string select line (SSL1) included in the first string select line block (SB1), a string select line (SSL2) included in the second string select line block (SB2), a string select line (SSL3) included in the third string select line block (SB3), and a string select line (SSL4) included in the fourth string select line block (SB4).

[0192] As such, since each word line block (WB1, WB2; WB) has a structure that includes multiple string selection line blocks (SB1, SB2, SB3, SB4; SB4), each word line block (WB1, WB2; WB) may include a greater number of vertical structures (VS) than each string selection line block. For example, as shown in FIGS. 9 and 10, each string selection line block (SB1, SB2, SB3, SB4; SB4) may include 9 vertical structures (VS), and each word line block (WB1, WB2; WB) may include 18 vertical structures (VS).

[0193] The number of vertical structures (VS) included in each of the above-described and described string selection line blocks (SB1, SB2, SB3, SB4; SB4) and the number of vertical structures (VS) included in each of the word line blocks (WB1, WB2; WB) are merely examples and can be adaptively determined and adjusted.

[0194] For example, the number of vertical structures (VS) included in each of the word line blocks (WB1, WB2; WB) can be determined and adjusted based on the rate at which an operating voltage is applied within the word line block (WB) to a target memory cell of a selected vertical structure (Sel VS) among the vertical structures (VS) through the word line (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, WL2 / 2, 쪋, WL2 / n)). For a more specific example, the number of vertical structures (VS) included in each of the word line blocks (WB1, WB2; WB) can be determined and adjusted so that the speed at which the operating voltage is applied within the word line block (WB) to the target memory cell of a selected vertical structure (Sel VS) among the vertical structures (VS) through the word line (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n)) is greater than or equal to a preset threshold speed value. In terms of practical design, the number of vertical structures (VS) included in each of the word line blocks (WB1, WB2; WB) can be determined and adjusted within the range of 9,000 to 1,000.

[0195] The at least one word line slit (WS) described above can be used as a passage to remove sacrificial layers (not shown) and fill the gate electrodes (EL-SSL, EL-WL) during the process of forming gate electrodes (EL-SSL, EL-WL) in the manufacturing process of a three-dimensional random access memory. For example, the at least one word line slit (WS) can be used as a passage to remove sacrificial layers during the process of forming gate electrodes (EL-SSL, EL-WL), or as a passage to fill the spaces where the sacrificial layers have been removed with the material constituting the gate electrodes (EL-SSL, EL-WL).

[0196] A capping insulating film (not shown) may be provided on the stacked structures (ST) and vertical structures (VS). The capping insulating film may cover the upper surface of the uppermost of the interlayer insulating layers (ILD). The capping insulating film may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film. The bit line contact plug (BLPG) may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it moves toward the third direction (D3).

[0197] Bit line horizontal portions (BLH) may be provided on the capping insulating film and the bit line contact plug (BLPG). The bit line horizontal portions (BLH) may be formed by extending a conductive material along the second direction (D2) while being spaced apart from each other along the first direction (D2). The conductive material constituting the bit line horizontal portions (BLH) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL-WL, EL-SSL).

[0198] The three-dimensional random access memory described above can perform memory operations based on the described structure in response to voltage applied between the bit line horizontal portions (BLH) and bit line vertical portions (BLV) and the gate electrodes (EL-WL, EL-SSL).

[0199] Here, the three-dimensional random access memory can perform memory operations on the selected target memory cell because, using a select transistor (SST), only the selected vertical structure (Sel VS) containing the target memory cell among the vertical structures (VS) connected to the same bit line horizontal portion (BLH) is turned on (activated) and at least one unselected vertical structure (Unsel VS) is turned off (deactivated), and random access to the target memory cell is possible in response to a voltage applied between the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) and the selected gate electrode (Sel EL-WL) among the gate electrodes (EL-WL, EL-SSL).

[0200]

[0201] FIG. 12 is a flowchart illustrating a method for manufacturing a three-dimensional random access memory according to one embodiment. The manufacturing method described below is a manufacturing method based on a gate-first process and includes steps (S1210 to S1230) for manufacturing a three-dimensional random access memory of the structure described above with reference to FIG. 8 to 11, and is based on the premise that it is performed by an automated and mechanized manufacturing system.

[0202] In step (S1210), the manufacturing system can prepare a semiconductor structure (SEMUI-STR).

[0203] More specifically, the manufacturing system can prepare a semiconductor structure (SEMI-STR) comprising stacked gate electrodes (EL-SSL, EL-WL) that are formed extending horizontally on a substrate (SUB) and spaced apart in the vertical direction, and vertical structures (VS) that are formed extending vertically through the gate electrodes (EL-SSL, EL-WL). Each of the vertical structures (VS) includes a data storage pattern (DSP) and a bit line vertical portion (BLV), and the data storage pattern (DSP) can constitute memory cells corresponding to the gate electrodes (EL-WL).

[0204] At this time, the semiconductor structure (SEMI-STR) may include gate electrodes (EL-SSL, EL-WL) each having a step structure (SS) along the horizontal direction at both ends.

[0205] In step (S1220), the manufacturing system can form at least one string select line slit (SS) that separates at least one gate electrode (EL-SSL) corresponding to a string select line (SSL) among the gate electrodes (EL-SSL, EL-WL) into string select line blocks (SB1, SB2, SB3, SB4; SB).

[0206] Specifically, the manufacturing system can form at least one string selection slit (SS) by etching to a depth of at least one gate electrode (EL-SSL) corresponding to the string selection line (SSL) in a vertical direction (e.g., third direction (D3)) and then filling the etched space with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0207] In step (S1230), the manufacturing system can form at least one word line slit (WS) that separates at least one gate electrode (EL-WL) corresponding to a word line (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, WL2 / 2, 쪋, WL2 / n)) among the gate electrodes (EL-SSL, EL-WL) by word line block (WB1, WB2; WB).

[0208] More specifically, the manufacturing system can form at least one word line slit (WS) by etching the upper surface of the substrate (SUB) so as to be exposed in a vertical direction (e.g., a third direction (D3)) and then filling the etched space with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0209] Additionally, in step (S1230), the manufacturing system may form at least one word line slit (WS) such that the word line blocks (WB1, WB2; WB) include a plurality of string selection line blocks (SB1, SB2, SB3, SB4; SB).

[0210] Additionally, in step (S1230), the manufacturing system can form at least one word line slit (WS) such that the word line blocks (WB1, WB2; WB) include a greater number of vertical structures (VS) than the string selection line blocks (SB1, SB2, SB3, SB4; SB).

[0211] The location where at least one string selection slit (SS) is formed in step (S1220) and the location where at least one word line slit (WS) is formed in step (S1230) can be adaptively determined and adjusted according to the number of vertical structures (VS) to be included in each of the string selection line blocks (SB1, SB2, SB3, SB4; SB) and the number of vertical structures (VS) to be included in each of the word line blocks (WB1, WB2; WB).

[0212] In determining and controlling the location where at least one word line slit (WS) is formed in step (S1230), the manufacturing system may first determine and control the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) based on the rate at which an operating voltage is applied to the memory cell through the word line (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, WL2 / 2, 쪋, WL2 / n)) within the word line blocks (SB1, SB2, SB3, SB4; SB). For example, the manufacturing system can determine and adjust the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) so that the speed at which the operating voltage is applied to the memory cell through the word line (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n)) within the word line blocks (SB1, SB2, SB3, SB4; SB) is greater than or equal to a preset threshold speed value.

[0213] That is, the manufacturing system can first determine and adjust the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) based on the speed at which an operating voltage is applied to a memory cell through the word line (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n)), and then determine and adjust the location where at least one word line slit (WS) is formed according to the number of vertical structures (VS) determined and adjusted.

[0214]

[0215] FIG. 13 is a flowchart illustrating a method for manufacturing a three-dimensional random access memory according to another embodiment. The manufacturing method described below is a manufacturing method based on a gate replacement process and includes steps (S1310 to S1340) for manufacturing a three-dimensional random access memory of the structure described above with reference to FIG. 8 to 11, and is based on the premise that it is performed by an automated and mechanized manufacturing system.

[0216] In step (S1310), the manufacturing system can prepare a semiconductor structure (SEMUI-STR).

[0217] More specifically, the manufacturing system can prepare a semiconductor structure (SEMI-STR) comprising sacrificial layers (SAC) stacked and spaced apart in the vertical direction while extending horizontally on a substrate (SUB), and vertical structures (VS) extending vertically through the sacrificial layers (SAC). Each of the vertical structures (VS) includes a data storage pattern (DSP) and a bit line vertical portion (BLV), and the data storage pattern (DSP) can constitute memory cells corresponding to gate electrodes (EL-WL) to be created after the sacrificial layers (SAC) are removed.

[0218] At this time, the semiconductor structure (SEMI-STR) may include each of the sacrificial layers (SAC) having a step structure (SS) along the horizontal direction at both ends.

[0219] In step (S1320), the manufacturing system can form at least one string select line slit (SS) that separates at least one gate electrode (EL-SSL) corresponding to a string select line (SSL) among the gate electrodes (EL-SSL, EL-WL) into string select line blocks (SB1, SB2, SB3, SB4; SB).

[0220] Specifically, the manufacturing system can form at least one string selection slit (SS) by etching to a depth of the sacrificial layer (SAC) where at least one gate electrode (EL-SSL) corresponding to the string selection line (SSL) is formed in the vertical direction (e.g., third direction (D3)), and then filling the etched space with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0221] In step (S1330), the manufacturing system can form at least one word line slit (WS) that separates at least one gate electrode (EL-WL) corresponding to a word line (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, WL2 / 2, 쪋, WL2 / n)) among the gate electrodes (EL-SSL, EL-WL) by word line block (WB1, WB2; WB).

[0222] More specifically, the manufacturing system can form at least one word line slit (WS) by etching the upper surface of the substrate (SUB) so as to be exposed in a vertical direction (e.g., a third direction (D3)) and then filling the etched space with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0223] Additionally, in step (S1330), the manufacturing system may form at least one word line slit (WS) such that the word line blocks (WB1, WB2; WB) include a plurality of string selection line blocks (SB1, SB2, SB3, SB4; SB).

[0224] Additionally, in step (S1330), the manufacturing system can form at least one word line slit (WS) such that the word line block (WB1, WB2; WB) includes a greater number of vertical structures (VS) than the string selection line block (SB1, SB2, SB3, SB4; SB).

[0225] The location where at least one string selection slit (SS) is formed in step (S1320) and the location where at least one word line slit (WS) is formed in step (S1330) can be adaptively determined and adjusted according to the number of vertical structures (VS) to be included in each of the string selection line blocks (SB1, SB2, SB3, SB4; SB) and the number of vertical structures (VS) to be included in each of the word line blocks (WB1, WB2; WB).

[0226] In determining and controlling the location where at least one word line slit (WS) is formed in step (S1330), the manufacturing system may first determine and control the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) based on the rate at which an operating voltage is applied to the memory cell through the word line (WL1(WL1 / 1, WL1 / 2, 쪋, WL1 / n), WL2(WL2 / 1, WL2 / 2, 쪋, WL2 / n)) within the word line blocks (SB1, SB2, SB3, SB4; SB). For example, the manufacturing system can determine and adjust the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) so that the speed at which the operating voltage is applied to the memory cell through the word line (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n)) within the word line blocks (SB1, SB2, SB3, SB4; SB) is greater than or equal to a preset threshold speed value.

[0227] That is, the manufacturing system can first determine and adjust the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) based on the speed at which an operating voltage is applied to a memory cell through the word line (WL1(WL1 / 1, WL1 / 2, , WL1 / n), WL2(WL2 / 1, WL2 / 2, , WL2 / n)), and then determine and adjust the location where at least one word line slit (WS) is formed according to the number of vertical structures (VS) determined and adjusted.

[0228] In step (S1340), the manufacturing system can remove sacrificial layers (SAC) through at least one word line slit (WS) and create gate electrodes (EL-SSL, EL-WL) in the spaces where the sacrificial layers (SAC) have been removed.

[0229] However, without being limited to or restricted to this, removing the sacrificial layers (SAC) and creating gate electrodes (EL-SSL, EL-WL) in the spaces where the sacrificial layers (SAC) have been removed may be done through a trench other than at least one word line slit (WS).

[0230]

[0231] FIG. 14 is a flowchart illustrating a method of operation of a three-dimensional random access memory according to embodiments. The memory operation method described below performs a memory operation on a target memory cell, and is based on the premise that it is performed by a three-dimensional random access memory of the structure described above with reference to FIG. 8 to 11. In addition, the target memory cell below refers to a memory cell that is the target of the memory operation, and the selected vertical structure (Sel VS) refers to a vertical structure among the vertical structures (VS) that includes the target memory cell.

[0232] In step (S1410), the three-dimensional random access memory can apply voltage in both directions toward a selected vertical structure (Sel VS) among the vertical structures (VS) from the word line plugs at both ends formed in the step structure (SS) having each of the two ends of the gate electrodes (EL-SSL, EL-WL).

[0233] For example, a three-dimensional random access memory can apply an operating voltage in both directions toward a target memory cell from word line plugs at both ends of a selected gate electrode (Sel EL-WL) corresponding to a target memory cell among the gate electrodes (EL-WL). At least one unselected gate electrode (Unsel EL-WL) other than the selected gate electrode (Sel EL-WL) among the gate electrodes (EL-WL) may be grounded.

[0234] Accordingly, in step (S1420), the three-dimensional random access memory can perform memory operations in response to voltage applied in both directions toward the selected vertical structure (Sel VS).

[0235] Although it has been described that the ideal memory operation is performed through steps (S1410 to S1420), it may be performed by additionally executing steps performed by a conventional 3D random access memory.

[0236] For example, prior to or immediately after step (S1410), the steps of applying a voltage through a selected bit line horizontal portion (Sel BLH) connected to a selected vertical structure (Sel VS), turning on a select transistor (SST) of a selected vertical structure (Sel VS) so that the voltage applied through the selected bit line horizontal portion (Sel BLH) is transferred to a target memory cell of the selected vertical structure (Sel VS), and turning off a select transistor (SST) of at least one unselected vertical structure (Unsel VS) so that the voltage applied through the selected bit line horizontal portion (Sel BLH) is not transferred to at least one unselected vertical structure (Unsel VS) connected to a bit line horizontal portion (Sel BLH) selected in the same way as the selected vertical structure (Sel VS) among the unselected vertical structures (Unsel VS) that do not include a target memory cell, thereby additionally performing the steps of: Step (S1420) may be performed in response to Step (S1410) and additionally performed steps.

[0237] The memory operation described above may be a write operation to the target memory cell (a programming operation that writes data "1" to the target memory cell or an erase operation that writes data "0" to the target memory cell).

[0238]

[0239] FIG. 15 is a schematic perspective view illustrating an electronic system including a three-dimensional random access memory according to one embodiment.

[0240] Referring to FIG. 15, an electronic system (1500) including a three-dimensional random access memory according to embodiments may include a main board (1501), a controller (1502) mounted on the main board (1501), one or more semiconductor packages (1503) and a DRAM (1504).

[0241] The semiconductor package (1503) and DRAM (1504) can be connected to the controller (1502) by wiring patterns (1505) provided on the main board (1501).

[0242] The main board (1501) may include a connector (1506) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (1506) may vary depending on the communication interface between the electronic system (1500) and the external host.

[0243] The electronic system (1500) can communicate with an external host according to any one of the interfaces, for example, USB (Universal Serial Bus), PCI Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). The electronic system (1500) can operate by power supplied from an external host, for example, through a connector (1506). The electronic system (1500) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to a controller (1502) and a semiconductor package (1503).

[0244] The controller (1502) can write data to the semiconductor package (1503) or read data from the semiconductor package (1503), and can improve the operating speed of the electronic system (1500).

[0245] The DRAM (1504) may be a buffer memory to mitigate the speed difference between the semiconductor package (1503), which is a data storage space, and an external host. The DRAM (1504) included in the electronic system (1500) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (1503). When the electronic system (1500) includes the DRAM (1504), the controller (1502) may further include a DRAM controller for controlling the DRAM (1504) in addition to the NAND controller for controlling the semiconductor package (1503).

[0246] A semiconductor package (1503) may include first and second semiconductor packages (1503a, 1503b) spaced apart from each other. The first and second semiconductor packages (1503a, 1503b) may each be a semiconductor package including a plurality of semiconductor chips (1520). Each of the first and second semiconductor packages (1503a, 1503b) may include a package substrate (1510), semiconductor chips (1520) on the package substrate (1510), adhesive layers (1530) disposed on the lower surface of each of the semiconductor chips (1520), connection structures (1540) electrically connecting the semiconductor chips (1520) and the package substrate (1510), and a molding layer (1550) covering the semiconductor chips (1520) and the connection structures (1540) on the package substrate (1510).

[0247] The package substrate (1510) may be a printed circuit board including package upper pads (1511). Each semiconductor chip (1520) may include input / output pads (1521). Each semiconductor chip (1520) may include the three-dimensional random access memory described above with reference to FIGS. 1 to 3 or FIGS. 8 to 11. More specifically, each semiconductor chip (1520) may include gate stacking structures (1522) and memory structures (1523). The gate stacking structures (1522) may correspond to the stacking structures (ST) described above, and the memory structures (1523) may correspond to the vertical structures (VS) described above.

[0248] The connection structures (1540) may be, for example, bonding wires that electrically connect the input / output pads (1521) and the package upper pads (1511). Accordingly, in each of the first and second semiconductor packages (1503a, 1503b), the semiconductor chips (1520) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (1511) of the package substrate (1510). According to embodiments, in each of the first and second semiconductor packages (1503a, 1503b), the semiconductor chips (1520) may be electrically connected to each other by through-silicon vias instead of the bonding wire connection structures (1540).

[0249] Unlike what is described, the controller (1502) and the semiconductor chips (1520) may be included in a single package. The controller (1502) and the semiconductor chips (1520) may be mounted on a separate interposer substrate different from the main substrate (1501), and the controller (1502) and the semiconductor chips (1520) may be connected to each other by wiring provided on the interposer substrate.

[0250]

[0251] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results can be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0252] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

1. Gate electrodes stacked and spaced vertically while extending horizontally on the substrate; and Vertical structures extending in the vertical direction through the gate electrodes—each of the vertical structures includes a data storage pattern and a bit line vertical portion, and the data storage pattern includes at least one insulation pattern, thereby constituting memory cells corresponding to the gate electrodes. A three-dimensional random access memory including 2. In Paragraph 1, The above data storage pattern is, A three-dimensional random access memory characterized by including at least one insulating pattern on an outer wall, an inner wall, or inside.

3. In Paragraph 1, The above at least one insulation pattern is, A three-dimensional random access memory characterized by being used to prevent memory operations on unselected memory cells, excluding the target memory cell, among the memory cells during a memory operation on a target memory cell.

4. In Paragraph 3, The above at least one insulation pattern is, A three-dimensional random access memory characterized by increasing the operating voltage required for the memory operation or increasing the coercive field in the non-selected memory cells to prevent polarization from occurring in the non-selected memory cells.

5. In Paragraph 3, The thickness of the above at least one insulation pattern is, A three-dimensional random access memory characterized by being determined as a value satisfying a condition that enables memory operation for the above-mentioned target memory cell and a condition that prevents memory operation for the above-mentioned non-selected memory cells.

6. In Paragraph 3, The above at least one insulation pattern is, A three-dimensional random access memory characterized by being formed of a material that satisfies conditions enabling memory operation for the target memory cell and conditions preventing memory operation for the non-selected memory cells.

7. A memory operation method of a three-dimensional random access memory comprising: gate electrodes formed extending in a horizontal direction on a substrate and spaced apart in a vertical direction and stacked; and vertical structures formed extending in the vertical direction penetrating the gate electrodes—each of the vertical structures comprising a data storage pattern and a bit line vertical portion, wherein the data storage pattern comprises at least one insulating pattern and constitutes memory cells corresponding to the gate electrodes. A step of applying a bit line voltage having at least a partial value of an operating voltage to a bit line vertical portion included in a selected vertical structure among the above vertical structures, which includes a target memory cell that is the target of memory operation; A step of applying a gate voltage having a polarity opposite to the bit line voltage and having the remaining partial value of the operating voltage to a selected gate electrode among the gate electrodes corresponding to the target memory cell; and A step of grounding at least one unselected gate electrode among the gate electrodes, excluding the selected gate electrode. A memory operation method of a three-dimensional random access memory including 8. In Paragraph 7, The step of applying the bit line voltage is, A method for memory operation of a three-dimensional random access memory, characterized by the step of preventing memory operation for unselected memory cells, excluding the target memory cell among the memory cells, by using the at least one insulating pattern included in the outer wall, inner wall, or interior of the data storage pattern.

9. In Paragraph 8, The step of preventing memory operation for the above-mentioned unselected memory cells is: A memory operation method of a three-dimensional random access memory characterized by a step of increasing the operating voltage required for the memory operation or increasing the coercive field in the non-selected memory cells to prevent polarization from occurring in the non-selected memory cells.

10. In Paragraph 7, The step of applying a gate voltage having the remaining partial value of the above operating voltage is, A method for memory operation of a three-dimensional random access memory, characterized by the step of preventing memory operation for a memory cell corresponding to the selected gate electrode among the memory cells of the at least one non-selected vertical structure that does not include the target memory cell—the at least one non-selected vertical structure including a bit line vertical portion common to the bit line horizontal portion included in the selected vertical structure—by applying the gate voltage to the selected gate electrode while the selected transistor is turned off.

11. Gate electrodes stacked and spaced apart in the vertical direction while extending horizontally on the substrate; Vertical structures extending in the vertical direction through the gate electrodes—each of the vertical structures includes a data storage pattern and a bit line vertical portion, and the data storage pattern constitutes memory cells corresponding to the gate electrodes—; At least one string selection line slit for separating at least one gate electrode corresponding to a string selection line among the gate electrodes according to string selection line blocks; and At least one word line slit separating at least one gate electrode corresponding to a word line among the gate electrodes above by word line block A three-dimensional random access memory including 12. In Paragraph 11, The above word line block is, A three-dimensional random access memory characterized by including a plurality of the above-mentioned string selection line blocks.

13. In Paragraph 11, The above word line block is, A three-dimensional random access memory characterized by including a greater number of the vertical structures than the string selection line block.

14. In Paragraph 13, The number of vertical structures included in the above word line block is, A three-dimensional random access memory characterized by the operating voltage within the word line block being determined and controlled based on the rate at which it is applied to a target memory cell of a selected vertical structure among the vertical structures through the word line.

15. In Paragraph 11, The above at least one word line slit is, A 3D random access memory characterized by being used as a channel for removing a sacrificial layer and filling the material constituting the gate electrodes during the process of forming the gate electrodes in the manufacturing process of the 3D random access memory.

Images