Substrate and method for calibration

Abstract

A substrate includes a top substrate layer configured to mate with an electrical connector or electrical cable, a first middle substrate layer, and a lower substrate layer including a lower resistor layer. The top substrate layer or the first middle substrate layer can include a middle resistor layer. The substrate can further include a second middle substrate layer located between the first middle substrate layer and the lower substrate layer, and the second middle substrate layer can be an insulating layer.

Description

Attorney Docket No. 80505.304. PCTSUBSTRATE AND METHOD FOR CALIBRATIONCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Patent Application No. 63 / 733,249 filed on December 12, 2024. The entire contents of thisapplication are hereby incorporated by reference.BACKGROUND OF THE INVENTION1. Field of the Invention

[0002] The present invention generally relates to calibration using an electrical substrate including embedded elements. More specifically, the present invention relates to providing a new test standard for calibrating ganged cable connectors.2. Description of the Related Art

[0003] In general, coaxial calibration standards include fixed terminations, open circuits, short circuits, and through adaptors, specified from DC (0 Hz) to multiple GHz.

[0004] Fig. 1 shows examples of known coaxial tips 1101 to 1104 used for testing and calibration, including a fixed or load termination tip 1101, a short tip 1102, an open tip 1103, and a through tip 1104. The coaxial tips 1101 to 1104 shown in Fig. 1 are screw-on-tight.

[0005] The coaxial tips 1101 to 1104 shown in Fig. 1 provide test standards, that is, elements with known responses, to perform calibration. For example, the fixed or load termination tip 1101 can provide a 50-Q resistance or other characteristic impedance, the short tip 1102 can include small resistor(s) (e.g., two 10-Q resistors) and a copper plate or layer, the open tip 1103 can include a dielectric material and optionally a larger resistor (e.g., a 250-Q resistor), and the through tip 1104 can be used to provide a connection between two ports of a testing device, such as a Vector Network Analyzer (VNA).

[0006] However, calibration problems may arise when attempting to perform testing using a ganged cable connector. Fig. 2 is a perspective view of a known electrical assembly 1200. In the known electrical assembly 1200 shown in Fig. 2, a plurality of cables 1201, for example,coaxial cables, are ganged together in a single connector block 1202. That is, the known electrical assembly 1200 shown in Fig. 2 can define a ganged cable connector.

[0007] Figs. 3A and 3B are block diagrams showing a conventional testing and calibration arrangements 1300A and 1300B of a device under test (DUT) 1301 using a ganged cable connector 1304, such as the electrical assembly 1200 shown in Fig. 2. As shown in Fig. 3A, a VNA 1306 is attached to corresponding VNA cable(s) 1307, which mate with corresponding cable(s) of the ganged cable connector 1304. As shown in Fig.3B, the ganged cable connector 1304 is attached to a substrate 1302 of the DUT 1301, which includes a test circuit 1303 (e.g., a microchip mounted to the substrate). Accordingly, a distance between the VNA 1306 and the DUT 1301 can be about a meter.

[0008] Although the VNA 1306 and VNA cable(s) 1307 have test standards, and thus have known responses, losses and imperfections in transmitted signals may occur from a point A shown in Figs. 3A and 3B.

[0009] Accordingly, it is desired to provide as clean a signal as possible to the test circuit 1303 of the DUT 1301, but losses and imperfections in known cable connectors can cause issues with providing a clean signal. Moreover, it is desired to account for cable connector distortions as much as possible.SUMMARY OF THE INVENTION

[0010] Embodiments of the present invention provide new standards for testing and calibration using a ganged electrical connector or the like.

[0011] A substrate according to an embodiment of the present invention includes a top layer configured to receive an electrical connector, a first intermediate layer, and a lower layer. At least one of the top layer and the first intermediate layer includes a first resistive layer, and the lower layer includes a second resistive layer.

[0012] The top layer can include a first pad that is configured to mate with a first tip of the electrical connector, and the first resistive layer can surround the first pad. The first intermediate layer can include a second pad that is electrically connected to the first pad of thetop layer, and the first resistive layer can surround the second pad. The first pad and the second pad can be electrically connected by a first via through the top layer of the substrate.

[0013] The top layer can include a third pad that is configured to mate with a second tip of the electrical connector, and the first resistive layer can surround the third pad. The first intermediate layer can include a fourth pad that is electrically connected to the third pad of the top layer, and the first resistive layer can surround the fourth pad. The third pad and the fourth pad can be electrically connected by a second via through the top layer of the substrate.

[0014] The plurality of layers of the substrate can further include a second intermediate layer located between the first intermediate layer and the lower layer. The second intermediate layer can be an insulating layer. The second intermediate layer can include at least one opening. The at least one opening can be located below the first resistive layer.

[0015] An electrical assembly according to an embodiment of the present invention includes the substrate, the electrical connector mounted to the substrate, and an electrical cable that is received by the electrical connector. The electrical connector can be a coaxial connector. The electrical cable can be a coaxial cable. The electrical connector can be included in a plurality of electrical connectors mounted to the substrate.

[0016] The electrical cable can be included in a plurality of electrical cables that are received by the electrical connector. The plurality of electrical cables can be ganged together.

[0017] The electrical assembly can further include a backer plate, and the substrate can be at least partially located between the electrical connector and the backer plate.

[0018] The electrical connector can include a mounting peg, the backer plate can include a mounting hole, and the mounting hole of the backer plate can be structured to receive the mounting peg of the electrical connector. The mounting peg can be externally threaded. The mounting hole can be internally threaded. The mounting hole can be a through hole.

[0019] The electrical connector can include a first keying structure, the backer plate can include a first keying hole, and the first keying hole of the backer plate can be structured to receive the first keying structure of the electrical connector. The electrical connector can include a second keying structure, the backer plate can include a second keying hole, and the second keying hole of the backer plate can be structured to receive the second keying structureof the electrical connector and to not receive the first keying structure of the electrical connector.

[0020] The backer plate can include at least one recess. The at least one recess can be aligned with a mating point between electrical cable and the substrate. The at least one recess can provide at least one air gap between the backer plate and the substrate. The substrate can be at least partially located within the at least one recess.

[0021] A calibration and testing method according to an embodiment of the present invention includes preparing an electrical cable, providing a substrate including a first resistive layer, providing test circuitry on or in the substrate, and connecting the electrical cable to the substrate.

[0022] The preparing the electrical cable can include cutting the electrical cable to provide a first cable portion and a second cable portion and soldering an electrical connector to the first cable portion. The first cable portion and the second cable portion can have the same or substantially the same length.

[0023] The substrate can include a plurality of layers, and the first resistive layer can be provided on a lowermost layer of the substrate. The substrate can further include a second resistive layer provided on an interior layer of the substrate.

[0024] The calibration and testing method can further include providing a backer plate, placing the substrate on the backer plate, and mounting an electrical connector the backer plate with the substrate at least partially located between the backer plate and the electrical connector. Connecting the electrical cable to the substrate can include inserting the electrical cable into the electrical connector.

[0025] A substrate according to an embodiment of the present invention includes a top substrate layer configured to mate with an electrical connector or electrical cable, a first middle substrate layer, and a lower substrate layer including a lower resistor layer.

[0026] The first middle substrate layer can include a middle resistor layer.

[0027] The substrate can further include a second middle substrate layer located between the first middle substrate layer and the lower substrate layer. The second middle substrate layer can be an insulating layer. The substrate can further include a third substrate layerincluding at least one opening. The at least one opening can be located below the middle resistor layer of the first middle substrate layer.

[0028] A substrate according to an embodiment of the present invention includes first, second, and third substrate layers, a first metal layer on a top surface of the first substrate layer, a second metal layer between the first and the second substrate layers, a third metal layer between the second and the third substrate layers, and a fourth metal layer on a bottom surface of the third substrate layer. The first metal layer includes a first hole that has a first diameter and that includes a first pad within the first hole. The first metal layer also includes a second hole that has a second diameter and that includes a second pad within the second hole. The second metal layer includes a third hole that is aligned with the first hole, that has a third diameter larger than the first diameter, that includes a third pad within the third hole that is connected to the first pad by a first via through the first substrate layer, and that includes a first embedded resistor layer that surrounds the third pad. The second metal layer also includes a fourth hole that is aligned with the second hole, that has a fourth diameter larger than the second diameter, that includes a fourth pad within the fourth hole that is connected to the second pad by a second via through the first substrate layer, and that includes a second embedded resistor layer that surrounds the fourth pad. The third metal layer includes a fifth hole that is aligned with the first hole and that has a fifth diameter larger than the first diameter. The third metal layer also includes a sixth hole that is aligned with the second hole and that has a sixth diameter larger than the second diameter. The fourth metal layer includes a seventh hole that is aligned with the first hole, that has a seventh diameter larger than the third and the fifth diameters, and that includes a third embedded resister layer. The fourth metal layer also includes an eighth hole that is aligned with the second hole, that has an eighth diameter larger than the fourth and the sixth diameters, and that includes a fourth embedded resistor layer. The substrate further includes first ground vias that extend through the first, the second, and the third layers and that surround the first, the third, the fifth, and the seventh holes. The substrate further includes second ground vias that extend through the first, the second, and the third layers and that are located around the second, the fourth, the sixth, and the eight holes.

[0029] The substrate can further include a first metal shorting layer that connects the third pad to the first ground vias and a second metal shorting layer that connects the fourth pad to the second ground vias. The substrate can further include a first line connecting the third and fourth pads through a channel in the second metal layer.

[0030] The first, the third, and the fifth holes, the first ground vias, and the third embedded resistor layer can define a first cavity. The second, the fourth, and the sixth holes, the second ground vias, and the fourth embedded resistor layer can define a second cavity.

[0031] A calibration system can include the substrate, a first cable including a first tip that is connected to the first pad, a second cable including a second tip that is connected to the second pad, and a test circuit connected to the substrate.

[0032] A calibration system can include a backer plate and the substrate, and the substrate can be attached to the backer plate. The substrate can be included in a recess of a calibration interface of the backer plate. The backer plate can include a mating interface that is opposite to the calibration interface. When a connector is attached to the backer plate such that the connector engages a first surface of an additional substrate located between the backer plate and the connector, the mating interface can engage with a second surface of the additional substrate opposite to the first surface.

[0033] A substrate according to an embodiment of the present invention includes first, second, and third substrate layers, a first metal layer on a top surface of the first substrate layer, a second metal layer between the first and the second substrate layers, a third metal layer between the second and the third substrate layers, and a fourth metal layer on a bottom surface of the third substrate layer. The first metal layer includes a first hole that has a first diameter and that includes a first pad within the first hole. The first metal layer further includes a second hole that has a second diameter and that includes a second pad within the second hole. The second metal layer includes a third hole that is aligned with the first hole, that has a third diameter larger than the first diameter and that includes a third pad within the third hole that is connected to the first pad by a first via through the first substrate layer. The second metal layer further includes a fourth hole that is aligned with the second hole, that has a fourth diameter larger than the second diameter and that includes a fourth pad within the fourth holethat is connected to the second pad by a second via through the first substrate layer. The third metal layer includes a fifth hole that is aligned with the first hole and that has a fifth diameter larger than the first diameter. The third metal layer further includes a sixth hole that is aligned with the second hole and that has a sixth diameter larger than the second diameter. The fourth metal layer includes a seventh hole that is aligned with the first hole, that has a seventh diameter larger than the third and the fifth diameters, and that includes a first embedded resister layer. The fourth metal layer further includes an eighth hole that is aligned with the second hole, that has an eighth diameter larger than the fourth and the sixth diameters, and that includes a second embedded resistor layer. The substrate further includes first ground vias that extend through the first, the second, and the third layers and that surround the first, the third, the fifth, and the seventh holes. The substrate further includes second ground vias that extend through the first, the second, and the third layers and that are located around the second, the fourth, the sixth, and the eight holes. The substrate further includes a first metal shorting layer that connects the third pad to the first ground vias. The substrate further includes a second metal shorting layer that connects the fourth pad to the second ground vias.

[0034] The first, the third, and the fifth holes, the first ground vias, and the first embedded resistor layer can define a first cavity. The second, the fourth, and the sixth holes, the second ground vias, and the second embedded resistor layer can define a second cavity.

[0035] A calibration system can include the substrate, a first cable including a first tip that is connected to the first pad, a second cable including a second tip that is connected to the second pad, and a test circuit connected to the substrate.

[0036] A calibration system can include a backer plate and the substrate, and the substrate can be attached to the backer plate. The substrate can be included in a recess of a calibration interface of the backer plate. The backer plate can include a mating interface opposite to the calibration interface. When a connector is attached to the backer plate such that the connector engages a first surface of an additional substrate located between the backer plate and the connector, the mating interface can engage with a second surface of the additional substrate opposite to the first surface.

[0037] The above and other features, elements, characteristics, steps, and advantages of the present invention will become more apparent from the following detailed description of the embodiments of the present invention with reference to the attached drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Fig. 1 shows examples of known coaxial tips used for testing and calibration.

[0039] Fig. 2 is a perspective view of a known electrical assembly.

[0040] Figs. 3A and 3B are block diagrams showing a conventional testing and calibration arrangement.

[0041] Fig. 4 is a plan view of a first layer of a substrate.

[0042] Fig. 5 is a plan view of a second layer of the substrate shown in Fig. 4.

[0043] Fig. 6 is a plan view of a third layer of the substrate shown in Figs. 4 and 5.

[0044] Fig. 7 is a plan view of a fourth layer of the substrate shown in Figs. 4-6.

[0045] Figs. 8A-8C are plan views of modifications to the second layer shown in Fig. 5.

[0046] Fig. 8D is a close-up schematic view of an additional modification to the second layer shown in Fig. 5.

[0047] Figs. 9A and 9B are cross-sectional views of substrates.

[0048] Fig. 9C is a plan view of the substrate shown in Fig. 9B.

[0049] Fig. 10 is a cross-sectional view of a substrate mated to a cable connector.

[0050] Fig. 11 is a perspective cross-sectional view of the substrate and cable connector shown in Fig. 10.

[0051] Fig. 12 is a close-up view of a portion of the substrate shown in Fig. 10.

[0052] Fig. 13 is a field plot showing energy dissipation within the substrate and the cable connector shown in Figs. 10 and 11.

[0053] Figs. 14A-14C show a process of preparing an electrical cable.

[0054] Fig. 15 shows an alternative example of a testing and calibration process.

[0055] Fig. 16 shows an example of an implementation of one of the substrates shown inFigs. 4-12.

[0056] Fig. 17 is a block diagram showing a testing and calibration arrangement.

[0057] Fig. 18 is a graph showing return loss of substrates including load connections with different embedded resistor layers.

[0058] Fig. 19 is a graph showing insertion loss and return loss of a substrate including a through connection.

[0059] Fig. 20 is a graph showing insertion loss and return loss of a substrate that does not include a lower resistor layer.

[0060] Fig. 21 shows a ganged cable connector.

[0061] Fig. 22 shows the ganged cable connector of Fig. 21 mounted to a backer plate.

[0062] Fig. 23 shows an embedded substrate in the backer plate of Fig. 22.

[0063] Fig. 24 shows a partial cut-away view of a connector block mounted to a substrate and a backer plate.

[0064] Fig. 25 shows an example of a connector block mounted to a substrate and a backer plate.

[0065] Fig. 26 shows an example of a backer plate.

[0066] Fig. 27 is a cross-sectional view of the backer plate shown in Fig. 26.

[0067] Fig. 28 is a cross-sectional view showing a modification to the backer plate shown inFig. 26.

[0068] Figs. 29A and 29D show additional modifications to the backer plates shown in Figs. 29A-29D.DETAILED DESCRIPTION

[0069] Figs. 4-7 show plan views of layers of a substrate 100.

[0070] Fig. 4 is a plan view of a first layer 110 of the substrate 100. Fig. 4 can be a top layer of the substrate 100, that is, an uppermost layer. The top layer 110 of the substrate 100 shown in Fig. 4 can be configured to receive an electrical assembly, for example, the known electrical assembly shown in Fig. 2. Fig. 4 shows an example where the top layer 110 of the substrate 100 can be matched to 2x4 channels of an electrical connector.

[0071] A first metal layer 119 can be provided on the first layer 110 of the substrate 100 shown in Fig. 4. The first metal layer 119 can include at least a first hole 111 that has a firstdiameter and that includes a first pad 112 within the first hole 111 and a second hole 113 that has a second diameter and that includes a second pad 114 within the second hole 113. The first pad 112 can be configured to mate with a corresponding first tip of a first electrical connector, and the second pad 114 can be configured to mate with a corresponding second tip of a second electrical connector. The first and second diameters can be the same or substantially the same or can be configured to mate with different types of electrical connectors. The first and second electrical connectors can be, for example, coaxial cable connectors. Although not shown in Fig. 4, resistor layers can be located on the first layer 110 of the substrate in the first hole 111 between the first pad 112 and the first metal layer 119 and in the second hole 113 between the second pad 114 and the first metal layer 119. These resistor layers on the first layer 110 can be used instead of or in addition to first and second embedded resistor layers 125A and 125B in the second layer 120 discussed below with respect to Fig. 5.

[0072] Fig. 5 is a plan view of an example of a second layer 120 of the substrate 100. Fig. 5 can be an interior layer of the substrate 100 located below the first layer 110 of the substrate 100. As shown in Fig. 5, each of the channels can include a corresponding embedded resistor layers 125, and a resistance of each of the embedded resistor layers 125 can be the same. However, different resistances may be provided for the embedded resistor layers 125 according to other embodiments. The embedded resistor layers 125 can be provided, for example, by depositing a copper layer on the second layer 120, etching the copper layer, and then depositing a resistive material. The example of the second layer 120 of the substrate 100 shown in Fig. 5 can be used as a test for a load standard. The embedded resistor layers 125 can be nominally about 50 Q. However, the embedded resistor layers 125 are not limited thereto, and can vary, for example, from about 30 Q to about 100 Q. That is, the embedded resistor layers 125 are not required to have a tight tolerance around the nominal value of about 50 Q.

[0073] A second metal layer 129 can be provided on the second layer 120 of the substrate 100 shown in Fig. 5, such that the second metal layer 129 is located between the first layer 110 and the second layer 120 of the substrate 100. The second metal layer 129 can include at least a third hole 121 that has a third diameter and that includes a third pad 122 within the third hole 121 and a fourth hole 123 that has a fourth diameter and that includes a fourth pad 124 withinthe fourth hole 123. The second metal layer 129 can include a first embedded resistor layer 125A that surrounds the third pad 122 and a second embedded resistor layer 125B that surrounds the fourth pad 124. As explained above, the first and the second embedded resistor layers 125A and 125B can be omitted in some circumstances, including if resistor layers are included in the first layer 110, as explained above. The third hole 121 can be aligned with the first hole 111 of the first metal layer 119 and can have a diameter larger than the first hole 111. The third pad 122 can be electrically connected to the first pad 112 by a first via through the first substrate layer 110. The fourth hole 123 can be aligned with the second hole 113 of the first metal layer 119 and can have a diameter larger than the second hole 113. The fourth pad 124 can be electrically connected to the second pad 114 by a second via through the first substrate layer 110.

[0074] Fig. 6 is a plan view of a third layer 130 of the substratelOO. Fig. 6 can also be an interior layer of the substrate 100 located below the second layer 120 of the substrate 100. As shown in Fig. 6, openings 131 can be provided under each of the channels, that is, under the embedded resistor layers 125 shown Fig. 5. By providing the openings 131 in the third layer 130 of the substrate 100 as shown in Fig. 6, signal integrity can be improved.

[0075] A third metal layer 139 can be provided on the third layer 130 of the substrate 100 shown in Fig. 6, such that the third metal layer 139 is located between the second layer 120 and the third layer 130 of the substrate 100. The openings 131 of the third metal layer 139 can include at least a fifth hole 131A that has a fifth diameter and a sixth hole 131B that has a sixth diameter. The fifth hole 131A can be aligned with the first hole 111 of the first metal layer 119 and can have a diameter larger than the first hole 111. The sixth hole 131B can be aligned with the second hole 113 of the first metal layer 110 and can have a diameter larger than the second hole 113.

[0076] Fig. 7 is a plan view of a fourth layer 140 of the substrate 100. Fig. 7 can be a bottom of the substrate 110, that is, a lowermost layer located below the third layer 130 of the substrate 100. As shown in Fig. 7, each of the channels can include a corresponding further embedded resistor layer 145, similar to the second layer 120 shown in Fig. 5. A resistance of each of the further embedded resistor layers 145 can be the same. However, differentresistances may be provided for the further embedded resistor layers 145 according to other embodiments. The further embedded resistor layers 145 can be provided, for example, by depositing a copper layer, etching the copper layer, and then depositing a resistive material.

[0077] A fourth metal layer 149 can be provided on the fourth layer 140 of the substrate 100 shown in Fig. 7, such that the fourth metal layer 149 is located between the third and fourth layers 130 and 140 of the substrate 100. The fourth metal layer 149 can include at least a seventh hole 141 that is aligned with the first hole 111 of the first metal layer 119 and an eighth hole 143 that is aligned with the second hole 113 of the first metal layer 119. The seventh hole 141 can have a diameter larger than the third hole 121 and the fifth hole 131A. The eighth hole 143 and can have a diameter larger than the fourth hole 123 and the sixth hole 131B. The seventh hole 141 can include a third embedded resistor layer 145A, and the eighth hole 143 can include a fourth embedded resistor layer 145B.

[0078] By providing the further embedded resistor layers 145 in the fourth metal layer 149 of the fourth layer 140 of the substrate 100 as shown in Fig. 7, energy dissipation from each of the channels is able to be significantly reduced, thereby improving signal integrity. In particular, the further embedded resistor layers 145 in the fourth layer 140 of the substrate 100 can absorb energy that passes the embedded resistor layers 125 in the second layer 120 of the substrate 100 to prevent the energy from being reflected back to the source (e.g., the electrical assembly received by the first layer 110 of the substrate 100). Accordingly, electrical performance is able to be significantly improved, particularly at higher signal frequencies. The further embedded resistor layers 145 can, for example, be nominally about 1000 Q for each of the channels (i.e., per square R). However, the further embedded resistor layers 145 can have other resistances or other predetermined characteristic impedances.

[0079] The substrate 100 can be provided with ground vias 108. For example, first ground vias 108A can extend through the first, second, and third layers 110, 120, 130, and 140 of the substrate 100 and can surround the first, third, fifth, and seventh holes 111, 121, 131A, and 141. Similarly, second ground vias 108B can extend through the first, second, and third layers 110, 120, 130, and 140 of the substrate 100 and can surround the second, fourth, sixth, and eighth holes 113, 123, 131B, and 143. The first, third, and fifth holes 111, 121, and 131A, thefirst ground vias 108A, and the third embedded resistor layer 145A can define a first cavity of the substrate 100. The second, fourth, and sixth holes 113, 123, and 131B, the second ground vias 108B, and the fourth embedded resistor layer 145B can define a second cavity of the substrate 100.

[0080] Although Figs. 4-7 show that the substrate 100 includes four layers, the substrate 100 is not limited thereto. For example, additional layers may be provided, such as additional second layer(s) 120 and additional third layer(s) 130 in an alternating manner.

[0081] Figs. 8A-8C are plan views of modifications 120A, 120B, and 120C to the second layer 120 shown in Fig. 5.

[0082] Fig. 8A shows an example of a first modification 120A to the second layer 120 for testing a short connection in which a signal pin is shorted to ground. The first modification 120A to the second layer 120 shown in Fig. 8A can include, for example, two resistors 125-L that have a low resistance (e.g., about 10 Q) and a copper plate 129-C.

[0083] To modify the substrate 100 for testing a short connection, the substrate 100 can include a first metal shorting layer that electrically connects the third pad 122 to the first ground vias 108A and a second metal shorting layer that electrically connects the fourth pad 124 to the second ground vias 108B, similar to the electrical traces 127A and 127C discussed below with respect to Fig. 8C. As an example, Fig. 8D is a close-up schematic view of an additional modification to the second layer shown in Fig. 5 that includes an electrical trace 125-S that electrically connects the third pad 122 to the first ground vias 108A and another electrical trace 125-S that electrically connects the fourth pad 124 to the second ground vias 108B.

[0084] Fig. 8B shows an example of a second modification 120B to the second layer 120 for testing an open connection. The second modification 120B to the second layer 120 shown in Fig. 8B can be provided without any embedded resistor layer. That is, the first and second holes 121 and 123 of the second modification 120B to the second layer 120 shown in Fig. 8B are not provided with the embedded resistors layers 125 shown in Fig. 5. Since no embedded resistor layer is provided in the second modification 120B to the second layer 120 shown in Fig. 8B, no electrical connection is provided and an open connection can be tested.

[0085] Alternatively, the second modification 120B to the second layer 120 shown in Fig. 8B can include an embedded resistor layer, for example, a resistor that has a significantly higher resistance (e.g., about 250 Q) than the resistors 125-L provided with the first modification 120A shown in Fig. 8A. That is, the second layer 120 can include an embedded resistor for testing an open connection to provide a known value with a tight tolerance.

[0086] Fig. 8C shows an example of a third modification 120C to the second layer 120 for testing a through connection. The third modification 120C to the second layer shown in Fig. 8C can be provided with only electrical traces, such as electrical traces 127A to 127D shown in Fig. 8C, and no embedded resistor layer.

[0087] The third modification 120C to the second layer shown in Fig. 8C can include, for example, two 50-Q lines that have different lengths (e.g., electrical traces 127A and 127C) to aid in measurement error checking. Alternatively or in addition, the third modification 120C to the second layer shown in Fig. 8C can include, for example, two 50-Q lines that have the same length (e.g., electrical traces 127C and 127D).

[0088] To modify the substrate 100 for testing a through connection, the substrate 100 can include a first line or a first trace connecting the third and fourth pads 122 and 124 through a channel in the second metal layer 129 of the second layer 120, similar to the arrangement shown in Fig. 8C.

[0089] Figs. 9A and 9B are cross-sectional views of substrates 200A and 200B, and Fig. 9C is a plan view of the substrate 200B shown in Fig. 9B.

[0090] Fig. 9A shows an example of a substrate 200A provided for testing an open connection, and Figs. 9B and 9C show an example of a substrate 200B provided for testing a short connection.

[0091] The substrate 200A shown in Fig. 9A includes a dielectric material 203 and a resistor layer 201 for reflection damping, similar to the further embedded resistor layers 145 in the fourth layer 140 of the substrate 100 as shown in Fig. 7. In the substrate 200a shown in Fig. 9A, a signal conductor 208 and a via 207, which can be connected to a mating electrical connector, are not electrically connected within the substrate 200A. In contrast, in the substrate 200b shown in Fig. 9B, the signal conductor 208 and the via 207, which can be connected to a matingelectrical connector, are electrically connected to electrically conductive components, such as a layer 205, which can be a copper plate, for shorting.

[0092] In the substrate 200B shown in Figs. 9B and 9C, the layer 205 for shorting can be implemented as a patch laid over a second layer 202 of the substrate 200B, for example, similar to the first modification 120A to the second layer 120 shown in Fig. SA. As shown in Fig. 9C, a metal patch 206 can be overlaid on the second layer 202 of the substrate 200B to short the via 207 and the signal conductor 208 to ground.

[0093] The substrates 200A and 200B shown in Figs. 9B and 9C can be provided without any resistor layer. However, an embedded resistor can be implemented in the substrates 200A and 200B shown in Figs. 9B and 9C, for example, in place of or in addition to the metal patch 206 shown in Fig. 9C, to provide a predetermined signal response.

[0094] The substrates 200A and 200B shown in Figs. 9A and 9B can be provided with a tolerance of less than about 10%, for example.

[0095] Figs. 10 and 11 are cross-sectional views of a substrate 310 mated to a cable connector 330.

[0096] As shown in Figs. 10 and 11, the cable connector 370 can be mated to the substrate 300. Similar to the substrate 100 discussed above with respect Figs. 4-7, the substrate 300 shown in Figs. 10 and 11 can include first, second, third, and fourth layers 310, 320, 330, and 340. As shown in Figs. 10 and 11, a via 307 can be located between the first and second layers 310 and 320 of the substrate 300.

[0097] The cable connector 370 shown in Figs. 10 and 11 includes a center conductor 371 that can transport (i.e., transmit and receive) electrical signals, which can be transported by the via 307 of the substrate 300. Furthermore, the cable connector 370 can include a spring-loaded connector 372 to ensure physical and electrical contact with the substrate 300.

[0098] As shown in Fig. 10, the substrate 300 can include a stripline layer 305, and the substrate 300 can be implemented for SOLR (Short, Open, Load, Reciprocal) calibration. In reciprocal calibration, a signal can be tested to ensure uniformity regardless of the direction of transmission. To provide reciprocal calibration, the stripline layer 305 can connect two different channels of the cable connector 370 (e.g., the center conductors 371 of two differentcoaxial cables). That is, the stripline layer 305 can provide a through connection (e.g., the example of the second modification 120B to the second layer 120 of the substrate 100 shown in Fig. 8C).

[0099] Fig. 12 is a close-up view of a portion of the substrate 300 shown in Figs. 10 and 11.

[0100] As shown in Fig. 12, a resistor layer 325 can be provided by the second layer 320 of the substrate 300, and the resistor layer 325 can be defined by a resistor sheet. The resistor layer 325 can be provided, for example, by depositing a copper layer 329, etching the copper layer, and then depositing a resistive material. The further layer 340 of the substrate 300 can also include a further resistor layer, similar to the fourth layer 140 of the substrate 100 as shown in Fig. 7.

[0101] Fig. 13 is a field plot showing energy dissipation within the substrate 300 and the cable connector 370 shown in Figs. 10 and 11 when the second layer 320 of the substrate 300 includes a 50-Q resistor layer 325.

[0102] As shown in Fig. 13, energy from the cable connector 370 enters the substrate 300. In Fig. 13, areas with darker hatching indicate higher energy content within the cable connector and the substrate, and areas with lighter hatching indicate lower energy content. As shown in Fig. 13, signal energy is primarily located at the interface between the cable connector 370 and the substrate 300 at the first layer 310 of the substate 300, and in the resistor layer 325 and traces at the second layer 320 of the substrate 300. Furthermore, signal energy does not leak past or extend through the further resistor layer at the fourth layer 340 of the substrate 300. That is, substantially all of the signal energy is concentrated in a cavity of the substrate 300 defined by the resistor layers of the second layer 320 and the fourth layer 340 and the via 307. By absorbing the signal energy in the further resistor layer on the fourth layer 340 of the substrate 300 and other surfaces of the substrate cavity, the signal energy can be prevented from reflecting and traveling back to the cable connector 370 and subsequently to the source of the signal. Since reflected energy can decrease the quality of calibration, providing the substrate 300 with the further embedded resistor on the fourth layer 340 of the substrate to absorb signal energy can improve the accuracy of calibration.

[0103] The specific structures of the substrates 100, 200A, 200B, and 300 disclosed herein are only provided as examples, and various modifications can be implemented. For example, a layer of one of the substrates 100, 200A, 200B, and 300 that defines an open, short, or load connection can be provided on any layer of the substrate.

[0104] Figs. 14A-14C show a process of preparing an electrical cable 401.

[0105] The electrical cable 401 prepared by the process shown in Figs. 14A-14C can be used with the substrates disclosed herein for testing and calibration, for example.

[0106] As shown in Fig. 14A, a full-length electrical cable 402 is provided in a first step. The full-length electrical cable 402 can be, for example, a coaxial cable. The full-length electrical cable 402 can include connectors 405 provided at one or both ends thereof, for example, BNC (Bayonet Neill-Concelman) connectors. As shown in Fig. 14B, in a second step, the full-length electrical cable 402 is cut in half to provide two half-length cables 403 of the same or substantially the same length. As shown in Fig. 14C, at least one of the two half-length cables 403 provided by the second step has a tip 406 attached thereto to provide the electrical cable 401.

[0107] The tip 406 attached to the electrical cable 401 shown in Fig. 14C can be soldered onto the half-length cables 403, for example. Furthermore, the tip 406 can be used to connect the electrical cable 401 to any of the substrates disclosed herein.

[0108] After assembling the half-length cables 403 to provide the electrical cables 401 as described above, S-parameters (scattering parameters) of the electrical cables 403 can be measured. As an example, the S-parameters of one of the half-length cables 403 can be determined by bisecting measured S-parameters of the full-length cable 402 or a similar full- length cable. For example, a Vector Network Analyzer (VNA) can be used to determine the S- parameters of the full-length cable 402 or the half-length cable 403.

[0109] The electrical cables 401 can then be assembled with a cable connector and one of the substrates disclosed herein to measure standards and determine S-parameters of the tip 406 and the substrate. A VNA can be used to determine the S-parameters of the tip 406 and the substrate.

[0110] The previously determined S-parameters for the half-length cable 403 can be used to measure the S-parameters of the tip 406 and the substrate. More specifically , the S- parameters for the half-length cable 403 de-embed the S-parameters of the tip 406 and the substrate. An example of de-embedding S-parameters is discussed in J. Song, et. aL, "A deembedding technique for interconnects", IEEE topical meeting on Electrical Performance and Electronic Packaging, pages 129-132, 2001.

[0111] By mathematically removing the S-parameters of the half-length cable 403 from an overall measurement of the half-length cable 403, the tip 406, and the substrate, only the S- parameters of the tip 406 and the standard remain. However, the tip 406 can be considered as an air line, and the impedance of an air line can be determined according to its dimensions as explained by N. M. Ridler, "Connectors, Air Lines and RF Impedance", The IEE Measurement, Sensors, Instrumentation and NDT Professional Network, pages 7 and 8, 2005. That is, the tip 406 provides an accurate reference impedance plane. Accordingly, when the tips 406 are respectively connected to multiple half-length cables 403, the tips can provide accurate and consistent reference planes for each corresponding channel of the multiple half-length cables 403.

[0112] By measuring the S-parameters as explained above, any non-idealities in the halflength cable 403, the tip 406, and the substrate can be determined. Accordingly, when performing testing and calibration using any of the half-length cable 403, the tip 406, and the substrate, the non-idealities between testing equipment (e.g., a VNA) and the substrate can be compensated for.

[0113] Fig. 15 shows an alternative example of a testing and calibration process 450.

[0114] In particular, Fig. 15 shows an alternative example of a process of determining the performance of half-length cables. The example shown in Fig. 15 can be implemented, for example, if the process explained above with respect to Figs. 14A-14C results in too high an error magnitude between different half-length cables, or to simply verify the measurements obtained by the process explained above with respect to Figs. 14A-14C.

[0115] As shown in Fig. 15, a first cable 451 and a second cable 452 can be mated with a substrate 455 and measured in series with a short substrate trace 456 located between the firstcable 451 and the second cable 452. The obtained measurement can then be bisected to determine the measurement of one half-length cable assembly. However, this process assumes that any losses or imperfections in the substrate trace 456 are negligibly small, which can result in some errors in the measurement of the one half-length cable assembly.

[0116] Fig. 16 shows an example implementation 500 of one of the substrates shown in Figs. 4-12. As shown in Fig. 16, the example substrate 500 can include a first metal layer 501, a first laminate layer 502, a second metal layer 503, a first pre-preg layer 504, a second laminate layer 505, a second pre-preg layer 506, a third metal layer 507, a third laminate layer 508, and a fourth metal layer 509.

[0117] Each of the first metal layer 501 and the fourth metal layer 509 can be1 / 2oz. copper with a thickness of about 10 mil. However, most of the fourth metal layer 509 may be removed to provide embedded resistor layer(s). Each of the second metal layer 503 and the third metal layer 507 can be1Z oz. copper with a thickness of about 2.5 mil. The second metal layer 503 can include a resistor layer, for example, a 250-Q resistor layer.

[0118] Each of the first laminate layer 502, the second laminate layer 505, and the third laminate layer 508 can be a composite laminate, for example, a micro-dispersed ceramic in a PTFE-based, woven glass reinforced composite. Each of the first laminate layer 502 and the third laminate layer 508 can have a thickness of about 20 mil. The second laminate layer 505 can have a thickness of about 10 mil, and the second laminate layer 505 may be etched during manufacturing of the example substrate 500.

[0119] Each of the first pre-preg layer 504 and the second pre-preg layer 506 can be a composite material including fibers, such as glass fibers, in a polymer matrix, such as epoxy or resin. A thickness of each of the first pre-preg layer 504 and the second pre-preg layer 506 can be about 2.5 mil.

[0120] Fig. 17 is a block diagram showing a testing and calibration arrangement 600 of a device under test (DUT) 601 using a ganged cable connector 604, such as the electrical assembly 1200 shown in Fig. 2. A substrate 602 of the DUT 601 includes a test circuit (e.g., a microchip mounted to the substrate). The substrate 602 shown in Fig. 17 can be any of the substrates disclosed herein, in particular, the substrates disclosed herein that define testing andcalibration standards for a fixed or load termination, a short connection, an open connection, and a through connection. Accordingly, as shown in Fig. 17, losses and imperfections in transmitted signals may occur only from a point B, in contrast to the point A shown in Figs. 3A and 3B.

[0121] That is, instead of requiring lengthy VNA cables 1307 in the testing and calibration arrangements 1300A and 1300B shown in Figs. 3A and 3B, in which losses and imperfections can occur over a distance of about a meter, the testing and calibration arrangement 600 shown in Fig. 17 can limit a distance at which losses and imperfections can occur to only a few millimeters. In particular, a test path can begin at the substrate 602 as shown in Fig. 17 (point B) instead of at a location spaced away from the substrate 602, such as the connection between the ganged cable connector 1304 and the VNA cable(s) 1307 as shown in Figs. 3A and 3B (point A).

[0122] Fig. 18 is a graph showing return loss of substrates including load connections with different embedded resistor layers. The graph shown in Fig. 18 is representative of any of the substrates disclosed herein which include a load connection. As shown in Fig. 18, providing a substrate with an embedded resistor layer that is nominally about 50 Q (the solid line shown as "TERM_50" in Fig. 18) limits return loss when compared with a similar substrate including an embedded resistor layer that is nominally about 250 Q (the dashed line shown as "TERM 250" in Fig. 18).

[0123] Fig. 19 is a graph showing insertion loss (the solid line shown as "IL" in Fig. 19) and return loss (the dashed line shown as "RL" in Fig. 19) of a substrate including a through connection. The graph shown in Fig. 19 is representative of any of the substrates disclosed herein which include a through connection. As shown in Fig. 19, a usable bandwidth of at least 60 GHz is able to be provided.

[0124] Fig. 20 is a graph showing insertion loss (the solid line shown as "IL" in Fig. 20) and return loss (the dashed line shown as "RL" in Fig. 20) of a substrate that does not include a lower resistor layer. The graph shown in Fig. 20 is representative of any of the substrates disclosed herein which include a through connection, but can similarly be applied to a short, open, or load connection. The further embedded resistor layers in the fourth layer of thesubstrate, as shown in Fig. 7, function as dampers that can significantly reduce or prevent a significant drop in insertion loss above 60 GHz, as shown in Fig. 19, particularly when compared with the insertion loss of a substrate that does not include a lower resistor layer or damper, as Fig. 20.

[0125] Accordingly, the substrates and processes disclosed herein are able to provide as a clean of a signal as possible to the test circuit of the DUT, by limiting a space at which losses and imperfections can occur.

[0126] Fig. 21 shows a ganged cable connector 700. Fig. 22 shows the ganged cable connector 700 of Fig. 21 mounted to a backer plate 720. Fig. 23 shows an embedded substrate 721 in the backer plate 720 of Fig. 22.

[0127] As shown in Fig. 21, the ganged cable connector 700 includes a plurality of electrical cables 701 ganged together in a single connector block 702. The electrical cables 701 can be, for example, coaxial cables. The ganged cable connector 700 shown in Fig. 21 can be mated with any of the substrates disclosed herein.

[0128] As shown in Figs. 22 and 23, the ganged cable connector of Fig. 21 can be mounted to a backer plate 720 with a substrate embedded 721 in the backer plate 720 to mate with the ganged cable connector 700. The embedded substrate 721 shown in Fig. 23 can be provided by any of the substrates disclosed herein. Electrical connections between the ganged cable connector 700 and the substrate 721 can be provided by, for example, pogo pins in the ganged cable connector 700 that mate with corresponding traces or pads on the substrate.

[0129] The backer plate 720 can be dual use and can include a calibration interface and a mounting interface. The calibration interface and the mounting interface can be on opposing surfaces of the backer plate. The ganged cable connector 700 can be calibrated using the calibration interface and can be mounted to a host substrate using the mounting interface.

[0130] The substrate 721 can be mounted to or in the calibration interface of the backer plate 720. For example, the substrate 721 can be included in a recess of the calibration interface of the backer plate 720. The ganged cable connector 700 can be attached to calibration interface of the backer plate 720 so the ganged cable connector 700 can be calibrated.

[0131] The ganged cable connector 700 can be attached to a host substrate (not shown) using the mating interface of the backer plate 720. The ganged cable connector 700 can be attached to the backer plate 720 with the host substrate located between the backer plate 720 and the ganged cable connector 700. The ganged cable connector 700 engages a first surface of the host substrate, and the mating interface of the backer plate 720 engages with a second surface of the host substrate opposite to the first surface.

[0132] Fig. 21 shows that the ganged cable connector 700 can include mounting pegs 703 or the like, and the mounting pegs 703 can be received by corresponding mounting holes of the backer plate 720 shown in Fig. 22. The mounting pegs 703 can include external threads, for example, and the ganged cable connector 700 can be secured to the backer plate 720 by tightening internally threaded nuts (not shown) onto the external threads of the mounting pegs 703. By providing the substrate 721 between the backer plate 720 and the ganged cable connector 700, the backer plate 720 is able to significantly reduce or prevent warping of the substrate 721. That is, the backer plate 720 is preferably formed to have a rigid structure that functions as a stiffening element to help ensure that the substrate 721 lies flat.

[0133] Fig. 21 further shows that the ganged cable connector can include first and second keying structures 704 and 705 that can be received by corresponding first and second keying holes (not shown) in the backer plate 720. The first and second keying structures 704 and 705 can be structured to have different sizes and / or shapes, with the first and second keying holes in the backer plate 720 having corresponding sizes and / or shapes, such that the first keying structure 704 is configured to be received by only the first keying hole and such that the second keying structure 705 is configured to be received by only the second keying hole. That is, the first and second keying structures 704 and 705 and the first and second keying holes can ensure that the ganged cable connector 700 is mated to the backer plate 720 and the substrate 721 in a correct orientation.

[0134] Fig. 24 shows a partial cut-away view of a connector block 802 mounted to a substrate 830 and a backer plate 820.

[0135] The connector block 802 shown in Fig. 24 can be the connector block 702 of the ganged cable connector 700 shown in Fig. 21. As shown in Fig. 24, the connector block 802 caninclude mounting pegs 803 that are received by corresponding mounting holes 823 of the backer plate 820. The mounting pegs 803 can include external threads, and the mounting holes 823 can include internal threads that receive the external threads of the mounting pegs 803 to secure the connector block 802 to the backer plate 820 . The substrate 830 can also include corresponding through holes 833 that are aligned with the mounting holes 823 of the backer plate 820.

[0136] Fig. 25 shows an example of a connector block 852 mounted to a substrate 880 and a backer plate 870.

[0137] The connector block 852 shown in Fig. 25 can be the connector block 702 of the ganged cable connector 700 shown in Fig. 21. As shown in Fig. 25, the connector block 852 can include mounting pegs 853 that are externally threaded. In contrast to the mounting holes 823 of the backer plate 820 shown in Fig. 24, the backer plate 870 shown in Fig. 25 includes through holes (not shown) that may not be internally threaded. Instead, as shown in Fig. 25, the connector block 852 is secured to the backer plate 870 and the substrate 880 by tightening internally threaded nuts 890 onto the external threads of the mounting pegs 853.

[0138] Fig. 26 shows an example of a backer plate 900, and Fig. 1 is a cross-sectional view of the backer plate 900 shown in Fig. 26.

[0139] As shown in Fig. 26, the backer plate 900 can include mounting holes 903 that are structured to receive corresponding mounting pegs of a mating connector, for example, the mounting pegs of the ganged cable connector 700 shown in Fig. 21. The backer plate 900 shown in Fig. 26 can also include a first keying hole 904 and a second keying hole 905 that are differently sized and / or shaped to receive corresponding first and second keying structures of a mating connector, for example, the first keying structure 704 and the second keying structure 705 of the ganged cable connector 700 shown in Fig. 21.

[0140] Figs. 26 and 27 show that the backer plate 900 can include a first recess 911 and a second recess 912 provided along a longitudinal length on a first surface 910 of the backer plate 900. The first recess 911 and the second recess 912 can be included in the mating interface of the backer plate 900. The first recess 911 and the second recess 912 can be located to be aligned in plan view with mating points between electrical connectors and a substrate. Forexample, the first recess 911 can be aligned in plan view with a first row of electrical connectors of a ganged cable connector, and the second recess 912 can be aligned in plan view with a second row of electrical connectors of the ganged cable connector.

[0141] The first recess 911 and the second recess 912 shown in Figs. 26 and 1 provide an air gap between electrically conductive portions of the substrate and the backer plate 900, thereby reducing capacitances that may be formed between the electrically conductive portions of the substrate and the backer plate 900. The first recess 911 and the second recess 912 can each be modified to include a plurality of recesses, such that an individual recess is provided for each mating point between the electrical connectors and the substrate.Furthermore, instead of the first recess 911 and the second recess 912 providing an air gap, an electrically insulating material can be provided in one or both of the first recess 911 and the second recess 912. As another alternative, the first recess 911 and the second recess 912 can be structured to each receive a separate substrate placed therein.

[0142] Fig. 28 is a cross-sectional view showing a first modification 900A to the backer plate 900 shown in Figs. 26 and 27.

[0143] As shown in Fig. 28, a third recess 921 can be provided in a second surface 920 of the backer plate, opposite to the first surface 910 of the substrate that includes the first recess 911 and the second recess 912. The third recess 921 can be structured to receive any one of the substrates disclosed herein. The third recess 921 can be included in the calibration interface of the backer plate.

[0144] Accordingly, the modified backer plate 900A shown in Fig. 28 can be used in a testing and calibration configuration by placing one of the substrates disclosed herein in the third recess 921 and then mounting a ganged electrical connector at the second surface 920 of the backer plate to perform SOLR (Short, Open, Load, Reciprocal) calibration. The modified backer plate 900A shown in Fig. 28 can also be used in a regular configuration by placing a substrate at the first surface 910 of the backer plate and then mounting a ganged electrical connector at the first surface 910 of the backer plate.

[0145] Figs. 29A-29D show additional modifications 900B, 900C, 900D, and 900E to the backer plates 900 and 900A shown in Figs. 26-28. As shown in Figs. 29A-29D, the keying holes904 and 905 of the backer plate 900 can be replaced by notches 904B, 905B, 904C, 905C, 904D, 905D, and 905E or the like in the modified backer plates 900B, 900C, 900D, and 900E. As shown in Figs. 29B-29D, a length of the backer plate 900 can be adjusted to provide shorter backer plates 900C, 900D, and 900E. As shown in Figs. 29C and 29D, one of the mounting holes 903 of the backer plate 900 can be omitted, such that only a single mounting hole 903D and 903E is provided in the modified backer plates 900D and 900E. As shown in Fig. 29D, only a single keying hole 905E or notch can be provided in the modified backer plate 900E.

[0146] The backer plates 720, 820, 870, 900, and 900A-900E described above can be electrically conductive or electrically insulating. If any of the backer plates 720, 820, 870, 900, and 900A-900E is electrically conductive, it can define a ground plane, for example, and can be electrically conductive with at least one conductive layer of one of the substrates 100, 200A, 200B, 300, 455, 500, 602, 721, 830, and 880 disclosed herein, for example, the further embedded resistor layer 145 provided on the fourth layer 140 of the substrate 100 shown in Fig. 7. An electrically insulating backer plate 720, 820, 870, 900, or 900A-900E can be formed of a ceramic material, for example.

[0147] The example embodiments disclosed herein can be applied to connectors transmitting signals in a range from DC (0 Hz) to about 110 GHz, for example. Some example embodiments of the present invention can be applied to 5G, 6G, and Phased Array Systems, as disclosed in Sankararaman et al., "Testing Interconnect Designs for 5G, 6G, and Phased-Array Systems," Mircrowaves&RF, July 10, 2025, URL: https: / / www.mwrf.com / technologies / test- measurement / article / 55302598 / samtec-testing-interconnect-designs-for-5g-6g-and-phased- array-systems, which is incorporated by reference in its entirety.

[0148] While the disclosure has been described with reference to various embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular system, device, or component thereof to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the disclosure not be limited to the particularembodiments disclosed for carrying out this disclosure, but that the disclosure will include all embodiments falling within the scope of the appended claims.

[0149] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0150] The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the disclosure. The described embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

WHAT IS CLAIMED IS:

1. A substrate comprising: a top layer configured to receive an electrical connector; a first intermediate layer; and a lower layer, wherein at least one of the top layer and the first intermediate layer includes a first resistive layer, and the lower layer includes a second resistive layer.

2. The substrate according to claim 1, wherein the top layer includes a first pad that is configured to mate with a first tip of the electrical connector.

3. The substrate according to claim 2, wherein the top layer includes the first resistive layer and the first resistive layer surrounds the first pad.

4. The substrate according to claim 2 or 3, wherein the first intermediate layer includes a second pad that is electrically connected to the first pad of the top layer.

5. The substrate according to claim 4, wherein the first intermediate layer includes the first resistive layer and the first resistive layer surrounds the second pad.

6. The substrate according to claim 4 or 5, wherein the first pad and the second pad are electrically connected by a first via through the top layer of the substrate.

7. The substrate according to one of claims 2-6, wherein the top layer includes a third pad that is configured to mate with a second tip of the electrical connector.

8. The substrate according to claim 7, wherein the top layer includes the first resistive layer and the first resistive layer surrounds the third pad.

9. The substrate according to claim 7 or 8, wherein the first intermediate layer includes a fourth pad that is electrically connected to the third pad of the top layer.

10. The substrate according to claim 9, wherein the first intermediate layer includes the first resistive layer and the first resistive layer surrounds the fourth pad.

11. The substrate according to claim 9 or 10, wherein the third pad and the fourth pad are electrically connected by a second via through the top layer of the substrate.

12. The substrate according to one of claims 2-11, further comprising a second intermediate layer located between the first intermediate layer and the lower layer.

13. The substrate according to claim 12, wherein the second intermediate layer is an insulating layer.

14. The substrate according to claim 12 or 13, wherein the second intermediate layer includes at least one opening.

15. The substrate according to claim 14, wherein the at least one opening is located below the first resistive layer.

16. The substrate according to one of claims 1-15, wherein the electrical connector is a coaxial connector.

17. An electrical assembly comprising: the substrate according to one of claims 1-16;the electrical connector mounted to the substrate; and an electrical cable that is received by the electrical connector.

18. The electrical assembly according to claim 17, wherein the electrical cable is a coaxial cable.

19. The electrical assembly according to claim 17 or 18, wherein the electrical connector is included in a plurality of electrical connectors mounted to the substrate.

20. The electrical assembly according to claims 17-19, wherein the electrical cable is included in a plurality of electrical cables that are received by the electrical connector.

21. The electrical assembly according to claim 20, wherein the plurality of electrical cables are ganged together.

22. The electrical assembly according to one of claims 17-21, further comprising: a backer plate, wherein the substrate is at least partially located between the electrical connector and the backer plate.

23. The electrical assembly according to claim 22, wherein: the electrical connector includes a mounting peg, the backer plate includes a mounting hole, and the mounting hole of the backer plate is structured to receive the mounting peg of the electrical connector.

24. The electrical assembly according to claim 23, wherein the mounting peg is externally threaded.

25. The electrical assembly according to claim 23 or 24, wherein the mounting hole is internally threaded.

26. The electrical assembly according to one of claims 23-25, wherein the mounting hole is a through hole.

27. The electrical assembly according to one of claims 22-26, wherein: the electrical connector includes a first keying structure, the backer plate includes a first keying hole, and the first keying hole of the backer plate is structured to receive the first keying structure of the electrical connector.

28. The electrical assembly according to claim 27, wherein: the electrical connector includes a second keying structure, the backer plate includes a second keying hole, and the second keying hole of the backer plate is structured to receive the second keying structure of the electrical connector and to not receive the first keying structure of the electrical connector.

29. The electrical assembly according to one of claims 22-28, wherein the backer plate includes at least one recess.

30. The electrical assembly according to claim 29, wherein the at least one recess is aligned with a mating point between electrical cable and the substrate.

31. The electrical assembly according to claim 29 or 30, wherein the at least one recess provides at least one air gap between the backer plate and the substrate.

32. The electrical assembly according to one of claims 29-31, wherein the substrate is at least partially located within the at least one recess.

33. A calibration and testing method comprising: preparing an electrical cable; providing a substrate including a first resistive layer; providing test circuitry on or in the substrate; and connecting the electrical cable to the substrate.

34. The calibration and testing method according to claim 33, wherein the preparing the electrical cable includes: cutting the electrical cable to provide a first cable portion and a second cable portion; and soldering an electrical connector to the first cable portion.

35. The calibration and testing method according to claim 34, wherein the first cable portion and the second cable portion have the same or substantially the same length.

36. The calibration and testing method according to one of claims 33-35, wherein: the substrate includes a plurality of layers; and the first resistive layer is provided on a lowermost layer of the substrate.

37. The calibration and testing method according to claim 36, wherein the substrate further includes a second resistive layer provided on an interior layer of the substrate.

38. The calibration and testing method according to one of claims 33-37, further comprising: providing a backer plate; placing the substrate on the backer plate; andmounting an electrical connector the backer plate with the substrate at least partially located between the backer plate and the electrical connector, wherein connecting the electrical cable to the substrate includes inserting the electrical cable into the electrical connector.

39. A substrate comprising: a top substrate layer configured to mate with an electrical connector or electrical cable; a first middle substrate layer; and a lower substrate layer including a lower resistor layer.

40. The substrate according to claim 39, wherein the first middle substrate layer includes a middle resistor layer.

41. The substrate according to claim 39 or 40, further comprising: a second middle substrate layer located between the first middle substrate layer and the lower substrate layer, wherein the second middle substrate layer is an insulating layer.

42. The substrate according to claim 41, further comprising a third substrate layer including at least one opening.

43. The substrate according to claim 42, wherein the at least one opening is located below the middle resistor layer of the first middle substrate layer.

44. A substrate comprising: first, second, and third substrate layers; a first metal layer on a top surface of the first substrate layer and including: a first hole that has a first diameter and that includes a first pad within the first hole; anda second hole that has a second diameter and that includes a second pad within the second hole; a second metal layer between the first and the second substrate layers and including: a third hole that is aligned with the first hole, that has a third diameter larger than the first diameter, that includes a third pad within the third hole that is connected to the first pad by a first via through the first substrate layer, and that includes a first embedded resistor layer that surrounds the third pad; and a fourth hole that is aligned with the second hole, that has a fourth diameter larger than the second diameter, that includes a fourth pad within the fourth hole that is connected to the second pad by a second via through the first substrate layer, and that includes a second embedded resistor layer that surrounds the fourth pad; a third metal layer between the second and the third substrate layers and including: a fifth hole that is aligned with the first hole and that has a fifth diameter larger than the first diameter; and a sixth hole that is aligned with the second hole and that has a sixth diameter larger than the second diameter; a fourth metal layer on a bottom surface of the third substrate layer and including: a seventh hole that is aligned with the first hole, that has a seventh diameter larger than the third and the fifth diameters, and that includes a third embedded resister layer; and an eighth hole that is aligned with the second hole, that has an eighth diameter larger than the fourth and the sixth diameters, and that includes a fourth embedded resistor layer; first ground vias that extend through the first, the second, and the third layers and that surround the first, the third, the fifth, and the seventh holes; and second ground vias that extend through the first, the second, and the third layers and that are located around the second, the fourth, the sixth, and the eight holes.

45. The substrate of claim 44, further comprising:a first metal shorting layer that connects the third pad to the first ground vias; and a second metal shorting layer that connects the fourth pad to the second ground vias.

46. The substrate of claim 44, further comprising a first line connecting the third and fourth pads through a channel in the second metal layer.

47. The substrate of one of claims 44-46, wherein the first, the third, and the fifth holes, the first ground vias, and the third embedded resistor layer define a first cavity; and the second, the fourth, and the sixth holes, the second ground vias, and the fourth embedded resistor layer define a second cavity.

48. A calibration system comprising: the substrate of one of claims 44-47; a first cable including a first tip that is connected to the first pad; a second cable including a second tip that is connected to the second pad; and a test circuit connected to the substrate.

49. A calibration system comprising: a backer plate; and the substrate of one of claims 44-47 attached to the backer plate.

50. The calibration system of claim 49, wherein the substrate is included in a recess of a calibration interface of the backer plate.

51. The calibration system of claim 49 or 50, wherein the backer plate includes a mating interface opposite to the calibration interface; and when a connector is attached to the backer plate such that the connector engages a first surface of an additional substrate located between the backer plate and the connector, themating interface engages with a second surface of the additional substrate opposite to the first surface.

52. A substrate comprising: first, second, and third substrate layers; a first metal layer on a top surface of the first substrate layer and including: a first hole that has a first diameter and that includes a first pad within the first hole; and a second hole that has a second diameter and that includes a second pad within the second hole; a second metal layer between the first and the second substrate layers and including: a third hole that is aligned with the first hole, that has a third diameter larger than the first diameter and that includes a third pad within the third hole that is connected to the first pad by a first via through the first substrate layer; and a fourth hole that is aligned with the second hole, that has a fourth diameter larger than the second diameter and that includes a fourth pad within the fourth hole that is connected to the second pad by a second via through the first substrate layer; a third metal layer between the second and the third substrate layers and including: a fifth hole that is aligned with the first hole and that has a fifth diameter larger than the first diameter; and a sixth hole that is aligned with the second hole and that has a sixth diameter larger than the second diameter; a fourth metal layer on a bottom surface of the third substrate layer and including: a seventh hole that is aligned with the first hole, that has a seventh diameter larger than the third and the fifth diameters, and that includes a first embedded resister layer; and an eighth hole that is aligned with the second hole, that has an eighth diameter larger than the fourth and the sixth diameters, and that includes a second embedded resistor layer;first ground vias that extend through the first, the second, and the third layers and that surround the first, the third, the fifth, and the seventh holes; second ground vias that extend through the first, the second, and the third layers and that are located around the second, the fourth, the sixth, and the eight holes; a first metal shorting layer that connects the third pad to the first ground vias; and a second metal shorting layer that connects the fourth pad to the second ground vias.

53. The substrate of claim 52, wherein the first, the third, and the fifth holes, the first ground vias, and the first embedded resistor layer define a first cavity; and the second, the fourth, and the sixth holes, the second ground vias, and the second embedded resistor layer define a second cavity.

54. A calibration system comprising: the substrate of one of claims 52 or 53; a first cable including a first tip that is connected to the first pad; a second cable including a second tip that is connected to the second pad; and a test circuit connected to the substrate.

55. A calibration system comprising: a backer plate; and the substrate of one of claims 52-54 attached to the backer plate.

56. The calibration system of claim 55, wherein the substrate is included in a recess of a calibration interface of the backer plate.

57. The calibration system of claim 55 or 56, wherein the backer plate includes a mating interface opposite to the calibration interface; andwhen a connector is attached to the backer plate such that the connector engages a first surface of an additional substrate located between the backer plate and the connector, the mating interface engages with a second surface of the additional substrate opposite to the first surface.

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