Bus decoding circuit, method, and two-wire bus communication system

Abstract

The present application provides a bus decoding circuit, a method, and a two-wire bus communication system. The bus decoding circuit comprises a bus decoding module and a threshold output module. The bus decoding module comprises a comparator; a first input end of the comparator receives a bus voltage signal transmitted on a bus, and a second input end of the comparator receives a threshold voltage; the comparator is used for comparing the bus voltage signal with the threshold voltage to obtain a comparison result; the bus decoding module is used for decoding the bus voltage signal on the basis of the comparison result; the threshold output module is used for dynamically adjusting, on the basis of the comparison result, the threshold voltage outputted to the second input end of the comparator. The present application can effectively solve the problem of glitch signal interference and improve the accuracy of bus decoding.

Description

Bus decoding circuit, method and two-bus communication system Cross-reference to related applications

[0001] This patent application claims priority to Chinese Patent Application No. 202411904596.8, filed on December 20, 2024, entitled "Bus Decoding Circuit, Method and Two-Bus Communication System", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a bus decoding circuit, method, and two-bus communication system. Background Technology

[0003] In a two-bus communication system, power and signal share two lines, meaning these two lines provide both power and transmit signals. This type of communication system has advantages such as simple power supply, wide power supply voltage range, fewer connecting wires, and ease of design and construction. However, because traditional two-bus communication systems share two lines for power and signal, the signal may be affected by power fluctuations, resulting in relatively weak anti-interference capabilities and a higher likelihood of misinterpretation. Summary of the Invention

[0004] The purpose of this application is to provide a bus decoding circuit, method, and two-bus communication system that can solve at least one of the technical problems mentioned in the prior art.

[0005] One aspect of this application provides a bus decoding circuit. The bus decoding circuit includes a bus decoding module and a threshold output module. The bus decoding module includes a comparator, a first input terminal of which is connected to a bus voltage signal transmitted on the bus, and a second input terminal of which is connected to a threshold voltage. The comparator is used to compare the bus voltage signal with the threshold voltage to obtain a comparison result. The bus decoding module is used to decode the bus voltage signal based on the comparison result. The threshold output module is used to dynamically adjust the threshold voltage output to the second input terminal of the comparator based on the comparison result.

[0006] Further, the threshold voltage includes a first threshold voltage and a second threshold voltage, and the threshold output module includes a selector, wherein the two selection input terminals of the selector are respectively connected to the first threshold voltage and the second threshold voltage, the control terminal of the selector is connected to the output terminal of the comparator, and the output terminal of the selector is connected to the second input terminal of the comparator. The selector is used to control the selector to select the first threshold voltage or the second threshold voltage output according to the signal output by the output terminal of the comparator.

[0007] Furthermore, the first input terminal of the comparator is the non-inverting input terminal of the comparator, and the second input terminal of the comparator is the inverting input terminal of the comparator.

[0008] Furthermore, the second threshold voltage is greater than the first threshold voltage, wherein when the output of the comparator is high, the selector selects the first threshold voltage to be output to the inverting input of the comparator;

[0009] When the output of the comparator is low, the selector selects the second threshold voltage and outputs it to the inverting input of the comparator.

[0010] Furthermore, the bus decoding circuit also includes a comparator threshold setting module, wherein the comparator threshold setting module is used to set the first threshold voltage and the second threshold voltage of the comparator flipping.

[0011] Furthermore, the comparator threshold setting module includes a resistor voltage divider circuit, which includes multiple voltage divider resistors connected in series, forming multiple voltage divider taps with different voltage division values ​​from the multiple voltage divider resistors. The comparator threshold setting module is used to select the voltages output by two corresponding voltage divider taps as the first threshold voltage and the second threshold voltage, respectively, according to the voltage range of the bus voltage signal.

[0012] Furthermore, the comparator threshold setting module is used to dynamically adjust the magnitudes of the first threshold voltage and the second threshold voltage according to the voltage range of the bus voltage signal transmitted on the bus.

[0013] Furthermore, the comparator threshold setting module includes a memory for storing the voltages of bus voltage signals corresponding to multiple decoding processes. The comparator threshold setting module is used to set the second threshold voltage based on the voltage of the highest bus voltage signal in the multiple decoding processes, and to set the first threshold voltage based on the voltage of the lowest bus voltage signal in the multiple decoding processes.

[0014] Furthermore, the comparator threshold setting module includes a memory that stores the voltage of the bus voltage signal corresponding to the previous decoding process. The comparator threshold setting module is used to set the second threshold voltage according to the voltage of the highest bus voltage signal in the previous decoding process, and to set the first threshold voltage according to the voltage of the lowest bus voltage signal in the previous decoding process.

[0015] Another aspect of this application provides a two-bus communication system. The two-bus communication system includes a master unit, a slave unit, and two buses. The master unit communicates with the slave unit via the two buses. The slave unit includes a bus decoding circuit as described above, which is used to decode the bus voltage signals transmitted on the buses.

[0016] Another aspect of this application provides a bus decoding method. The bus decoding method includes: acquiring a bus voltage signal transmitted on the bus; comparing the bus voltage signal with a threshold voltage to obtain a comparison result; decoding the bus voltage signal based on the comparison result; and dynamically adjusting the threshold voltage based on the comparison result.

[0017] Further, the threshold voltage includes a first threshold voltage and a second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage, and the step of dynamically adjusting the threshold voltage according to the comparison result includes: when the comparison result is high, adjusting the threshold voltage to the first threshold voltage; when the comparison result is low, adjusting the threshold voltage to the second threshold voltage.

[0018] Furthermore, the bus decoding method further includes: dynamically adjusting the magnitudes of the first threshold voltage and the second threshold voltage according to the voltage range of the bus voltage signal.

[0019] Furthermore, the step of dynamically adjusting the magnitude of the first threshold voltage and the second threshold voltage according to the voltage range of the bus voltage signal includes: setting the second threshold voltage according to the voltage of the highest bus voltage signal in multiple decoding processes, and setting the first threshold voltage according to the voltage of the lowest bus voltage signal in multiple decoding processes.

[0020] Furthermore, the step of dynamically adjusting the magnitude of the first threshold voltage and the second threshold voltage according to the voltage range of the bus voltage signal includes: setting the second threshold voltage according to the voltage of the highest bus voltage signal in the previous decoding process, and setting the first threshold voltage according to the voltage of the lowest bus voltage signal in the previous decoding process.

[0021] The bus decoding circuit, method, and two-bus communication system of one or more embodiments of this application can dynamically adjust the threshold voltage based on the comparison result of the bus voltage signal and the threshold voltage, thereby reducing glitches and improving the accuracy of bus decoding.

[0022] The bus decoding circuit, method, and two-bus communication system of one or more embodiments of this application implement bus decoding by using bus dual threshold voltage comparison logic, which can effectively eliminate the influence of glitches and interference signals generated by power fluctuations on decoding and improve anti-interference capability.

[0023] Furthermore, the bus decoding circuit, method, and two-bus communication system of one or more embodiments of this application, through the existence of dual thresholds, allow for more flexible setting of threshold voltages. The first threshold voltage and the second threshold voltage can be dynamically adjusted according to the voltage range of the bus voltage signal, which can accommodate more bus voltage waveforms, making the bus peripheral design simpler and reducing the cost of use. Attached Figure Description

[0024] Figure 1 is a schematic diagram of the working principle of a two-bus communication system in related technologies.

[0025] Figure 2 is a schematic diagram of the decoding of the two-bus communication system shown in Figure 1 when interference signals occur.

[0026] Figure 3 is a schematic diagram of the structure of a bus decoding circuit according to an embodiment of this application.

[0027] Figure 4 is a schematic diagram of bus decoding principle of dual threshold voltage according to an embodiment of this application.

[0028] Figure 5 is a simplified schematic diagram of a two-bus communication system according to an embodiment of this application.

[0029] Figure 6 is a flowchart of a bus decoding method according to an embodiment of this application. Detailed Implementation

[0030] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0031] Figure 1 illustrates the working principle of a two-bus communication system in related technologies. As shown in Figure 1, during communication, a series of high and low bus voltages are generated on the bus. The bus voltage is processed and compared with a pre-set comparator threshold voltage. When the bus voltage is higher than the comparator threshold voltage, the comparator outputs 1; when the bus voltage is lower than the comparator threshold voltage, the comparator outputs 0, thus realizing the conversion of the bus voltage into a 0 or 1 signal to achieve data transmission.

[0032] However, the power supply voltage is not ideally high or low, and there will be many interference signals. Figure 2 shows a decoding diagram of the two-bus communication system shown in Figure 1 when interference signals occur. As shown in Figure 2, the low bus voltage is not very low, and the difference from the comparator's topping threshold voltage is not large. During the decoding process, if the bus power supply fluctuates, such as during code return current extraction, glitches will appear within the dashed box. Although the interference signal is not very high, according to the working principle of the two-bus communication system in Figure 1, as long as it exceeds the comparator's topping threshold voltage, it will affect the comparator's output. The normally transmitted 101 signal will be incorrectly decoded as a 10101 signal, which will inevitably lead to decoding communication failure.

[0033] Related technologies eliminate this type of decoding error in the following ways: For example, by pulling the low bus voltage even lower, but this requires the power supply to provide greater drive capability, which inevitably increases the cost. Alternatively, filters can be added to remove glitches, but the diversity of glitches makes the filters ineffective and adds more logic, making the entire decoding circuit very complex. Another approach is to adjust the threshold voltage of the comparator to prevent glitches from exceeding it; however, this reduces the general applicability of the solution.

[0034] In view of this, this application provides an improved bus decoding circuit that can solve at least one of the technical problems mentioned in the above-mentioned related technologies.

[0035] The bus decoding circuit, method, and two-bus communication system of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0036] Figure 3 illustrates a schematic diagram of a bus decoding circuit 200 according to an embodiment of this application. As shown in Figure 3, the bus decoding circuit 200 according to an embodiment of this application may include a bus decoding module and a threshold output module.

[0037] The bus decoding module includes a comparator 230. The first input of the comparator 230 is connected to the bus voltage signal transmitted on the bus, and the second input is connected to a threshold voltage. The comparator 230 compares the bus voltage signal with the threshold voltage to obtain a comparison result. The bus decoding module can decode the bus voltage signal based on the comparison result of the comparator 230.

[0038] The threshold output module can dynamically adjust the threshold voltage output to the second input terminal of comparator 230 based on the comparison result of comparator 230.

[0039] The bus decoding circuit 200 of this application can reduce glitches and improve the accuracy of bus decoding by setting a threshold output module. The threshold output module can dynamically adjust the threshold voltage of the comparator 230 according to the comparison result of the comparator 230.

[0040] In some embodiments, the threshold voltage may include a first threshold voltage and a second threshold voltage.

[0041] The threshold output module of this application includes a selector 220.

[0042] The two selection inputs of selector 220 are respectively connected to a first threshold voltage and a second threshold voltage; the output of comparator 230 is connected to the control terminal of selector 220 for controlling the output of selector 220; the output of selector 220 is connected to the second input of comparator 230. Selector 220 can control itself to select either the first threshold voltage or the second threshold voltage output based on the signal output from the output of comparator 230, which serves as the threshold voltage for comparator 230 toggles.

[0043] In the embodiments of this application, the first input terminal of comparator 230 is the non-inverting input terminal of comparator 230, and the second input terminal of comparator 230 is the inverting input terminal of comparator 230. That is, the non-inverting input terminal of comparator 230 is connected to the bus voltage signal, and the inverting input terminal of comparator 230 is connected to the output terminal of selector 220.

[0044] The second threshold voltage is greater than the first threshold voltage. For example, selector 220 has a low-level ("0") select input and a high-level ("1") select input. The high-level ("1") select input of selector 220 receives the first threshold voltage, and the low-level ("0") select input of selector 220 receives the second threshold voltage.

[0045] When the output of comparator 230 is a low level "0", selector 220 selects the signal input to the low level ("0") selection input terminal. That is, the output of selector 220 selects the second threshold voltage output and outputs the second threshold voltage to the inverting input terminal of comparator 230 as the threshold voltage for comparator 230 toggles.

[0046] When the output of comparator 230 outputs a high level "1", selector 220 selects the signal input to the high level ("1") selection input terminal. That is, the output of selector 220 selects the first threshold voltage output and outputs the first threshold voltage to the inverting input terminal of comparator 230 as the threshold voltage for comparator 230 to flip.

[0047] In some embodiments, the bus decoding circuit 200 of this application may further include a comparator threshold setting module 210.

[0048] The comparator threshold setting module 210 can be used to set the first threshold voltage and the second threshold voltage for the comparator 230 to flip.

[0049] Optionally, the comparator threshold setting module 210 can dynamically adjust the magnitude of the first threshold voltage and the second threshold voltage according to the voltage range of the bus voltage signal transmitted on the bus. The bus voltage signal is transmitted in the form of high and low voltages, and the first threshold voltage and the second threshold voltage can be reasonably selected between the high voltage and low voltage of the bus voltage signal.

[0050] The comparator threshold setting module 210 of this application can flexibly set the first threshold voltage and the second threshold voltage toggled by the comparator 230. In some embodiments, the comparator threshold setting module 210 may include a resistor voltage divider circuit. The resistor voltage divider circuit includes a plurality of voltage divider resistors connected in series. A plurality of voltage divider taps with different voltage division values ​​are formed from the plurality of voltage divider resistors. The comparator threshold setting module 210 can select the voltages output by the two corresponding voltage divider taps as the first threshold voltage and the second threshold voltage, respectively, according to the voltage range of the bus voltage signal. Thus, the first threshold voltage and the second threshold voltage can be flexibly set.

[0051] Optionally, the comparator threshold setting module 210 may further include a memory, which can be used to store the voltage of the bus voltage signal. For example, the memory stores bus voltage signals corresponding to multiple decoding processes, and a second threshold voltage can be set based on the highest bus voltage signal in the multiple decoding processes, while a first threshold voltage is set based on the lowest bus voltage signal in the multiple decoding processes. Alternatively, the memory stores the bus voltage signal corresponding to the previous decoding process, and a second threshold voltage can be set based on the highest bus voltage signal in the previous decoding process, while a first threshold voltage is set based on the lowest bus voltage signal in the previous decoding process.

[0052] Figure 4 illustrates a bus decoding principle diagram of a dual-threshold voltage according to an embodiment of this application. As shown in Figure 4, when the bus voltage is high (when the comparator 230 outputs 1), the flip-threshold voltage of the comparator 230 is selected as the first threshold voltage; when the bus voltage is low (when the comparator 230 outputs 0), the flip-threshold voltage of the comparator 230 is selected as the second threshold voltage. Thus, even if glitches or interference signals appear within the dashed box during communication, because the comparator 230's flip-threshold voltage has already been adjusted to the second threshold voltage when the comparator 230 outputs 0, and the second threshold voltage can be set relatively high, the glitches or interference signals will not trigger the comparator 230 to flip, effectively eliminating the impact of the glitches or interference on decoding. Therefore, by setting reasonable first and second threshold voltages, interference signals on the bus can be effectively filtered out.

[0053] The bus decoding circuit 200 of this application sets a dual threshold switching voltage for the comparator 230, namely a first threshold voltage and a second threshold voltage. The first threshold voltage or the second threshold voltage can be triggered according to the signal output by the comparator 230 as the threshold voltage for the comparator 230 to switch. Thus, the problem of glitch signal interference can be effectively solved with almost no increase in cost, thereby improving the accuracy of bus decoding.

[0054] This application also provides a two-bus communication system 100. Figure 5 shows a simplified schematic diagram of a two-bus communication system 100 according to an embodiment of this application. As shown in Figure 5, the two-bus communication system 100 according to an embodiment of this application includes a master 110, a slave 120, and two buses 130. The master 110 communicates with the slave 120 through the two buses 130. The slave 120 includes the bus decoding circuit 200 as described above, which can be used to decode the bus voltage signals transmitted on the buses 130.

[0055] This application also provides a bus decoding method. This bus decoding method can be implemented by the bus decoding circuit described in the above embodiments or applied to the two-bus communication system described in the above embodiments. Figure 6 illustrates a flowchart of a bus decoding method according to an embodiment of this application. As shown in Figure 6, the bus decoding method of an embodiment of this application may include steps S1 to S4.

[0056] In step S1, the bus voltage signal transmitted on the bus is acquired.

[0057] In step S2, the bus voltage signal is compared with the threshold voltage to obtain the comparison result.

[0058] In some embodiments, the threshold voltage includes a first threshold voltage and a second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage. In this case, the step S2 of comparing the bus voltage signal with the threshold voltage to obtain the comparison result may further include steps S21 and S22.

[0059] In step S21, when the comparison result is high, the threshold voltage is adjusted to the first threshold voltage.

[0060] In step S22, when the comparison result is low, the threshold voltage is adjusted to the second threshold voltage.

[0061] In step S3, the bus voltage signal is decoded based on the comparison result, and the threshold voltage is dynamically adjusted based on the comparison result.

[0062] It should be noted that in the two-bus communication system 100, both power and signals are transmitted on the bus. Since power is transmitted on the bus, the bus voltage signal transmitted on the bus must initially be a high voltage. At this point, regardless of whether the initial threshold voltage is the first threshold voltage or the second threshold voltage, the initial comparison result will always be high. After obtaining the initial comparison result, the threshold voltage can be adjusted to the first threshold voltage based on the high comparison result. Subsequently, the threshold voltage can be dynamically adjusted to the first threshold voltage or the second threshold voltage based on whether the comparison result is high or low.

[0063] In some embodiments, the bus decoding method of this application may further include step S4.

[0064] In step S4, the magnitudes of the first threshold voltage and the second threshold voltage can be dynamically adjusted according to the voltage range of the bus voltage signal.

[0065] For example, the voltage output of the two corresponding voltage divider taps of the resistor voltage divider circuit can be selected as the first threshold voltage and the second threshold voltage according to the voltage range of the bus voltage signal. The resistor voltage divider circuit includes multiple voltage divider resistors connected in series, and multiple voltage divider taps with different voltage divider values ​​can be formed from the multiple voltage divider resistors.

[0066] The bus decoding circuit 200, method, and two-bus communication system 100 of one or more embodiments of this application can dynamically adjust the threshold voltage based on the comparison result of the bus voltage signal and the threshold voltage, thereby reducing glitches and improving the accuracy of bus decoding.

[0067] The bus decoding circuit 200, method, and two-bus communication system 100 of one or more embodiments of this application implement bus decoding by using bus dual threshold voltage comparison logic, which can effectively eliminate the influence of glitches and interference signals generated by power fluctuations on decoding and improve anti-interference capability.

[0068] In addition, the bus decoding circuit 200, method and two-bus communication system 100 of one or more embodiments of this application have more flexible threshold voltage settings due to the existence of dual thresholds. The first threshold voltage and the second threshold voltage can be dynamically adjusted according to the voltage range of the bus voltage signal, which can adapt to more bus voltage waveforms, making the bus peripheral design simpler and reducing the cost of use.

[0069] The bus decoding circuit, method, and two-bus communication system provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the bus decoding circuit, method, and two-bus communication system of the embodiments of this application. The descriptions of the embodiments above are only for helping to understand the core ideas of this application and are not intended to limit this application. It should be noted that for those skilled in the art, several improvements and modifications can be made to this application without departing from the spirit and principles of this application, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A bus decode circuit, characterized by, It includes a bus decoding module and a threshold output module, wherein, The bus decoding module includes a comparator. The first input terminal of the comparator is connected to the bus voltage signal transmitted on the bus, and the second input terminal of the comparator is connected to a threshold voltage. The comparator is used to compare the bus voltage signal with the threshold voltage to obtain a comparison result. The bus decoding module is used to decode the bus voltage signal according to the comparison result. The threshold output module is used to dynamically adjust the threshold voltage output to the second input terminal of the comparator based on the comparison result.

2. The bus decode circuit of claim 1, wherein, The threshold voltage includes a first threshold voltage and a second threshold voltage, and the threshold output module includes a selector, wherein... The two selection input terminals of the selector are respectively connected to the first threshold voltage and the second threshold voltage. The control terminal of the selector is connected to the output terminal of the comparator, and the output terminal of the selector is connected to the second input terminal of the comparator. The selector is used to control the selector to select the first threshold voltage or the second threshold voltage output according to the signal output by the output terminal of the comparator.

3. The bus decode circuit of claim 2, wherein, The first input terminal of the comparator is the non-inverting input terminal of the comparator, and the second input terminal of the comparator is the inverting input terminal of the comparator.

4. The bus decode circuit of claim 3, wherein, The second threshold voltage is greater than the first threshold voltage, wherein, When the comparator outputs a high level, the selector selects the first threshold voltage and outputs it to the inverting input of the comparator. When the output of the comparator is low, the selector selects the second threshold voltage and outputs it to the inverting input of the comparator.

5. The bus decode circuit of any one of claims 2 to 4, wherein, It also includes a comparator threshold setting module, wherein, The comparator threshold setting module is used to set the first threshold voltage and the second threshold voltage for the comparator to flip.

6. The bus decode circuit of claim 5, wherein, The comparator threshold setting module includes a resistor voltage divider circuit, which includes multiple voltage divider resistors connected in series. Multiple voltage divider taps with different voltage divider values ​​are formed from the multiple voltage divider resistors. The comparator threshold setting module is used to select the voltage output of two corresponding voltage divider taps as the first threshold voltage and the second threshold voltage, respectively, according to the voltage range of the bus voltage signal.

7. The bus decoding circuit according to claim 5 or 6, characterized by The comparator threshold setting module is used to dynamically adjust the magnitudes of the first threshold voltage and the second threshold voltage according to the voltage range of the bus voltage signal transmitted on the bus.

8. The bus decode circuit of claim 7, wherein, The comparator threshold setting module includes a memory for storing the voltages of the bus voltage signals corresponding to multiple decoding processes. The comparator threshold setting module is used to set the second threshold voltage according to the voltage of the highest bus voltage signal in the multiple decoding process, and to set the first threshold voltage according to the voltage of the lowest bus voltage signal in the multiple decoding process.

9. The bus decoding circuit of claim 7, wherein, The comparator threshold setting module includes a memory that stores the voltage of the bus voltage signal corresponding to the previous decoding process. The comparator threshold setting module is used to set the second threshold voltage according to the voltage of the highest bus voltage signal in the previous decoding process, and to set the first threshold voltage according to the voltage of the lowest bus voltage signal in the previous decoding process.

10. A two-bus communication system, characterized by It includes a master unit, a slave unit, and two buses. The master unit communicates with the slave unit through the two buses. The slave unit includes a bus decoding circuit as described in any one of claims 1 to 9. The bus decoding circuit is used to decode the bus voltage signal transmitted on the bus.

11. A bus decoding method, characterized by, include: Acquire the bus voltage signal transmitted on the bus; The bus voltage signal is compared with the threshold voltage to obtain the comparison result; The bus voltage signal is decoded based on the comparison result, and the threshold voltage is dynamically adjusted based on the comparison result.

12. The bus decoding method of claim 11, wherein, The threshold voltage includes a first threshold voltage and a second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage, and the step of dynamically adjusting the threshold voltage based on the comparison result includes: When the comparison result is high, the threshold voltage is adjusted to the first threshold voltage; When the comparison result is low, the threshold voltage is adjusted to the second threshold voltage.

13. The bus decoding method of claim 12, wherein, Also includes: The magnitudes of the first threshold voltage and the second threshold voltage are dynamically adjusted based on the voltage range of the bus voltage signal.

14. The bus decoding method of claim 13, wherein, The step of dynamically adjusting the magnitudes of the first threshold voltage and the second threshold voltage based on the voltage range of the bus voltage signal includes: The second threshold voltage is set based on the voltage of the highest bus voltage signal in the multiple decoding processes, and the first threshold voltage is set based on the voltage of the lowest bus voltage signal in the multiple decoding processes.

15. The bus decoding method of claim 13, wherein, The step of dynamically adjusting the magnitudes of the first threshold voltage and the second threshold voltage based on the voltage range of the bus voltage signal includes: The second threshold voltage is set based on the highest bus voltage signal in the previous decoding process, and the first threshold voltage is set based on the lowest bus voltage signal in the previous decoding process.

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