Coding method, decoding method, and communication apparatus

Abstract

A coding method, a decoding method, and a communication apparatus. The coding method comprises: performing lifting and cyclic shift on a first base matrix on the basis of a first lifting size and a first offset value set corresponding to the first lifting size, so as to obtain a check matrix; and coding first information on the basis of the check matrix, so as to obtain second information, and outputting the second information, wherein offset values in the first offset value set that correspond to a first sub-region and a second sub-region of the first base matrix satisfy a preset relationship. The first sub-region comprises the third row and the fourth row of the first column and / or the third row and the fourth row of the second column in a first region of the first base matrix. The second sub-region comprises the third row and the fourth row of the last column in a second region of the first base matrix. The first region spans from the first column to the Nth column and from the first row to the Mth row of the first base matrix. The second region spans from the (N+1)th column to the (N+P)th column and from the first row to the Mth row of the first base matrix. By means of the method, a high code rate is achieved, and the degradation of the decoding performance is also reduced.

Description

An encoding method, a decoding method, and a communication device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411888336.6, filed on December 19, 2024, with the State Intellectual Property Office of the People's Republic of China, entitled "An Encoding Method, Decoding Method and Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, and a communication device. Background Technology

[0004] Low-density parity check (LDPC) codes are a channel coding scheme that is very close to Shannon lines. They have the characteristics of good performance and low complexity, and have been selected by the 3rd generation partnership project (3GPP) as the coding and decoding scheme for the data channels of 5th generation (5G) communication.

[0005] LDPC encoding supports puncturing; to improve the code rate, punctures can be added to the basis matrix of the LDPC code. However, at higher code rates (or with more punctured columns), decoding performance degrades. How to minimize the performance loss when there are many punctured columns remains to be addressed. Summary of the Invention

[0006] This application provides an encoding method, a decoding method, and a communication device, which can improve decoding performance when there are many punched columns in the base matrix.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] Firstly, an encoding method is provided, which can be applied to a transmitting device (hereinafter referred to as the transmitting device). Unless otherwise specified in this application, the transmitting device can be the transmitting device itself, or a module or unit used to implement some or all of the functions of the transmitting device. For example, the transmitting device can be a circuit or a chip / chip system in the transmitting device, or the transmitting device can be a logic node, logic module, or software that implements all or part of the functions of the transmitting device. In one example, the transmitting device is a terminal device, which can be a terminal device or a circuit or chip / chip system in the terminal device (e.g., a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip or system-in-package (SIP) chip containing a modem core). In another example, the transmitting device is a network device, which may be the network device itself, a component in the network device (e.g., a circuit, a chip, or a chip system), or a module or unit (e.g., a central unit (CU), a distributed unit (DU), or a radio unit (RU)) used to implement some or all of the functions of the network device.

[0009] The method includes: lifting and cyclically shifting a first base matrix according to a first lifting size and a first offset value set corresponding to the first lifting size to obtain a parity check matrix; encoding first information according to the parity check matrix to obtain second information, and outputting the second information. Wherein, the offset values ​​corresponding to the first sub-region of the first base matrix in the first offset value set satisfy a preset relationship with the offset values ​​corresponding to the second sub-region of the first base matrix. The first sub-region includes the third and fourth rows of the first column of the first region of the first base matrix, and / or the third and fourth rows of the second column of the first region of the first base matrix. The second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix. The first region of the first base matrix is ​​the first column to the Nth column and the first row to the Mth row of the first base matrix. The second region of the first base matrix is ​​the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix. M, N, and P are all positive integers.

[0010] In this method, constraints are imposed on the offset values ​​corresponding to the first and second sub-regions of the first basis matrix. For example, the offset values ​​corresponding to the first and second sub-regions of the first basis matrix in the first offset value set satisfy a preset relationship. Compared to offset values ​​that do not satisfy this preset relationship, the parity check matrix obtained based on the first offset value set can minimize the loss of decoding performance while achieving a higher code rate, thereby improving decoding performance.

[0011] In one design, the offset values ​​corresponding to the first sub-region and the second sub-region satisfy a preset relationship, including: r1 and r2 satisfying the constraint of a preset value, which is related to a second lift dimension, and the second lift dimension belongs to the set of first lift dimensions to which the first lift dimension is located. Both r1 and r2 are determined based on the offset values ​​corresponding to the first sub-region, the offset values ​​corresponding to the second sub-region, and the second lift dimension.

[0012] The design constrains r1 and r2 based on a preset value determined by the second lifting dimension, and further constrains the offset values ​​of the first and second sub-regions to minimize the loss of decoding performance at high code rates.

[0013] In one design, the second lift dimension is the maximum value in the set of first lift dimensions.

[0014] The design prioritizes the decoding performance loss corresponding to the maximum lift size. Based on the maximum lift size constraints r1 and r2, it helps to further reduce the decoding performance loss.

[0015] In one design, r1 is determined based on a, b, e, f, and a second lift dimension, and r2 is determined based on c, d, e, f, and a second lift dimension. Where a is the offset value corresponding to the third row of the first column of the first region, b is the offset value corresponding to the fourth row of the first column of the first region, c is the offset value corresponding to the third row of the second column of the first region, d is the offset value corresponding to the fourth row of the second column of the first region, e is the offset value corresponding to the third row of the last column of the second region, and f is the offset value corresponding to the fourth row of the last column of the second region.

[0016] In one design, ab-e+f=s1*Zm+r1;cd-e+f=s2*Zm+r2;where Zm is the second lifting dimension, and s1 and s2 are positive integers.

[0017] In one design, Furthermore, |r1| or |r2| > g*Zm; where r1 and r2 are both positive or negative numbers, and g is a positive number less than or equal to 1 / 2. Alternatively, Furthermore, |r1-r2|>g*Zm; where r1 is a positive number, r2 is a negative number, and g is a positive number less than or equal to 1 / 2; or, r1 is a negative number, r2 is a positive number, and g is a positive number less than or equal to 1 / 2.

[0018] In one design, a first offset value set is determined based on a second offset value set, which corresponds to a first lift dimension. The first offset value set includes a first offset value, the second offset value set includes a second offset value, and the difference between the first offset value and the second offset value is a multiple of a, where a belongs to the first lift dimension set containing the first lift dimension.

[0019] In this design, the first offset value set is obtained by modifying at least one offset value in the second offset value set. The offset values ​​in the second offset value set, except for at least one offset value, do not need to be modified and are compatible with existing offset values.

[0020] In one design, the first translation value is the sum of the second translation value and at least one lift dimension in the first set of lift dimensions.

[0021] In one design, any one of the at least one lift dimension in the first lift dimension set is greater than any other lift dimension in the first lift dimension set other than that at least one lift dimension.

[0022] In this design, at least one boost size is the larger boost size in the first boost size set. Under the same base matrix, it can support longer code lengths and is suitable for high throughput scenarios.

[0023] Secondly, a decoding method is provided, which can be applied to a receiving device (hereinafter referred to as the receiving device). Unless otherwise specified in this application, the receiving device can be the receiving device itself, or a module or unit used to perform some functions of the receiving device, such as a circuit or chip / chip system in the receiving device. Alternatively, the receiving device can be a logic node, logic module, or software module that implements all or part of the functions of the receiving device. In one example, the receiving device is a terminal device or a network device. For details on terminal devices and network devices, please refer to the relevant descriptions of terminal devices and network devices in the first aspect, which will not be repeated here. For ease of description, the following example uses the method applied to a receiving device. When the transmitting device is a terminal device, the receiving device can be a network device; when the receiving device is a network device, the transmitting device can be a terminal device.

[0024] The method includes: obtaining second information; lifting and cyclically shifting a first base matrix according to a first lifting size and a set of first offset values ​​corresponding to the first lifting size to obtain a parity check matrix; and decoding the second information according to the parity check matrix to obtain the first information. Wherein, the offset values ​​corresponding to the first sub-region of the first base matrix in the first offset value set satisfy a preset relationship with the offset values ​​corresponding to the second sub-region of the first base matrix. The first sub-region includes the third and fourth rows of the first column of the first region of the first base matrix, and / or the third and fourth rows of the second column of the first region of the first base matrix. The second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix. The first region of the first base matrix comprises the first column to the Nth column and the first row to the Mth row. The second region of the first base matrix comprises the (N+1)th column to the (N+P)th column and the first row to the Mth row. M, N, and P are all positive integers.

[0025] In one design, the offset values ​​corresponding to the first sub-region and the second sub-region satisfy a preset relationship, including: r1 and r2 satisfying the constraint of a preset value, which is related to a second lift dimension, and the second lift dimension belongs to the set of first lift dimensions to which the first lift dimension is located. Both r1 and r2 are determined based on the offset values ​​corresponding to the first sub-region, the offset values ​​corresponding to the second sub-region, and the second lift dimension.

[0026] In one design, the second lift dimension is the maximum value in the set of first lift dimensions.

[0027] In one design, r1 is determined based on a, b, e, f, and a second lift dimension, and r2 is determined based on c, d, e, f, and a second lift dimension. Where a is the offset value corresponding to the third row of the first column of the first region, b is the offset value corresponding to the fourth row of the first column of the first region, c is the offset value corresponding to the third row of the second column of the first region, d is the offset value corresponding to the fourth row of the second column of the first region, e is the offset value corresponding to the third row of the last column of the second region, and f is the offset value corresponding to the fourth row of the last column of the second region.

[0028] In one design, ab-e+f=s1*Zm+r1;cd-e+f=s2*Zm+r2;where Zm is the second lifting dimension, and s1 and s2 are positive integers.

[0029] In one design, Furthermore, |r1| or |r2| > g*Zm, where r1 and r2 are both positive or negative numbers, and g is a positive number less than or equal to 1 / 2. Alternatively, Furthermore, |r1-r2|>g*Zm, where r1 is a positive number, r2 is a negative number, and g is a positive number less than or equal to 1 / 2; or, r1 is a negative number, r2 is a positive number, and g is a positive number less than or equal to 1 / 2.

[0030] In one design, a first offset value set is determined based on a second offset value set, which corresponds to a first lift dimension. The first offset value set includes a first offset value, the second offset value set includes a second offset value, and the difference between the first offset value and the second offset value is a multiple of a, where a belongs to the first lift dimension set containing the first lift dimension.

[0031] In one design, the first translation value is the sum of the second translation value and at least one lift dimension in the first set of lift dimensions.

[0032] In one design, any one of the at least one lift dimension in the first lift dimension set is greater than any other lift dimension in the first lift dimension set other than that at least one lift dimension.

[0033] For the beneficial effects of the second aspect and its various designs, please refer to the beneficial effects of the first aspect and its various designs; they will not be repeated here.

[0034] Thirdly, embodiments of this application provide a communication device for performing the methods described in the first or second aspect and any of their designs. The beneficial effects can be found in the relevant descriptions of the first or second aspect, which will not be repeated here.

[0035] In one possible design, the communication device includes corresponding means, modules, or units for performing the methods of the first or second aspect. These modules, units, or means can be implemented in software, hardware, or a combination of both. For example, the communication device includes a processing module (sometimes also called a processing unit or processor) and / or input / output interfaces. Input / output interfaces include input interfaces and / or output interfaces, which can be interface circuits, output circuits, input circuits, pins, or related circuits, etc. Optionally, the communication device also includes a transceiver module (sometimes also called a transceiver unit or transceiver). The transceiver module is capable of both transmitting and receiving functions. When the transceiver module performs the transmitting function, it can be called a transmitting module (sometimes also called a transmitting unit), and when it performs the receiving function, it can be called a receiving module (sometimes also called a receiving unit). The transmitting module and the receiving module can be the same functional module, referred to as the transceiver module, which performs both transmitting and receiving functions; or, the transmitting module and the receiving module can be different functional modules, with "transceiver module" being a collective term for these functional modules. These input / output interfaces and modules (units) can perform the corresponding functions in the method examples of the first or second aspect above. For details, please refer to the detailed description in the method examples, which will not be repeated here.

[0036] For example, when the communication device is used to implement the corresponding function in the method example of the first aspect, the processing module is used to lift and cyclically shift the first base matrix according to the first lifting size and the first offset value set corresponding to the first lifting size to obtain a parity check matrix; and to encode the first information according to the parity check matrix to obtain the second information. The transceiver module is used to output the second information. Wherein, the offset value corresponding to the first sub-region of the first base matrix in the first offset value set satisfies a preset relationship with the offset value corresponding to the second sub-region of the first base matrix. The first sub-region includes the third and fourth rows of the first column of the first region of the first base matrix, and / or the third and fourth rows of the second column of the first region of the first base matrix. The second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix. The first region of the first base matrix is ​​the first column to the Nth column and the first row to the Mth row of the first base matrix. The second region of the first base matrix is ​​the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix. M, N, and P are all positive integers.

[0037] For example, when the communication device is used to implement the corresponding function in the method example of the second aspect, the transceiver module is used to acquire the second information. The processing module is used to lift and cyclically shift the first base matrix according to the first lifting size and the first offset value set corresponding to the first lifting size to obtain the parity check matrix; and to decode the second information according to the parity check matrix to obtain the first information. Wherein, the offset value corresponding to the first sub-region of the first base matrix in the first offset value set satisfies a preset relationship with the offset value corresponding to the second sub-region of the first base matrix. The first sub-region includes the third and fourth rows of the first column of the first region of the first base matrix, and / or the third and fourth rows of the second column of the first region of the first base matrix. The second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix. The first region of the first base matrix is ​​the first column to the Nth column and the first row to the Mth row of the first base matrix. The second region of the first base matrix is ​​the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix. M, N, and P are all positive integers.

[0038] Fourthly, embodiments of this application provide a communication device including a processor configured to execute the methods described in the first aspect or the second aspect and any of their designs. This application does not limit the specific type of processor. For example, the processor can be a baseband device, a central processing unit (CPU), or other specific integrated circuits. As another example, the processor can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0039] Optionally, the communication device further includes a communication interface. Optionally, the communication device also includes a memory for storing computer programs (also referred to as code or instructions), data, etc. The processor is coupled to the memory and the communication interface. When the processor reads the computer program, data, etc., from the memory, the methods of the first aspect or the second aspect and any of their designs are executed.

[0040] In one design, the memory is located outside the communication device.

[0041] In one design, the memory is located within the communication device.

[0042] In one design, the processor and memory are integrated together.

[0043] Fifthly, embodiments of this application provide a chip system including a processor and a communication interface for implementing the methods described in the first or second aspect. Optionally, the chip system further includes a memory. The memory stores computer programs (also referred to as code or instructions). The processor retrieves and executes the computer programs from the memory, causing a device equipped with the chip system to perform the methods of the first or second aspect and any of their designs. The chip system may be composed of chips or may include chips and other discrete devices.

[0044] Sixthly, embodiments of this application provide a communication device including an input / output interface and logic circuitry. The input / output interface is used for inputting and / or outputting information. The input / output interface may be an interface circuit, an output circuit, an input circuit, pins, or related circuits, etc. The logic circuitry is used to execute the methods described in the first or second aspect.

[0045] In one implementation of the sixth aspect, when the communication device is a terminal device, the interface circuit can be a radio frequency processing chip in the terminal device, and the processing circuit can be a baseband processing chip in the terminal device. When the communication device is a network device, the interface circuit can be a radio frequency processing chip in the network device, and the processing circuit can be a baseband processing chip in the network device.

[0046] In one implementation of the sixth aspect, when the communication device is a chip or chip system, the input circuit can be an input pin, the output circuit can be an output pin, and the logic circuit can be a transistor, gate circuit, flip-flop, or various other logic circuits. The input signal received by the input circuit can be received and input by, for example, but not limited to, a receiver; the signal output by the output circuit can be, for example, but not limited to, output to a transmitter and transmitted by the transmitter. Furthermore, the input circuit and the output circuit can be the same circuit, which is used as both the input circuit and the output circuit at different times. This application does not limit the specific implementation of the input / output interface and the logic circuit.

[0047] In specific implementation, the aforementioned communication device can be the transmitting device in the first aspect. Alternatively, the communication device can be a device capable of supporting the transmitting end device to implement the functions required by the method provided in the first aspect; for example, the communication device can be a chip or chip system in the transmitting end device. Alternatively, the communication device can be the receiving device in the second aspect. Alternatively, the communication device can be a device capable of supporting the receiving end device to implement the functions required by the method provided in the second aspect; for example, the communication device can be a chip or chip system in the receiving end device. The chip can be a baseband chip and / or a radio frequency chip, and the chip system can be composed of chips or may include chips and other discrete devices.

[0048] In a seventh aspect, embodiments of this application provide a communication system, which includes a terminal device and a network device. The terminal device is used to implement the function of the method described in the first aspect, and the network device is used to implement the function of the method described in the second aspect; or, the terminal device is used to implement the function of the method described in the second aspect, and the network device is used to implement the function of the method described in the first aspect.

[0049] Eighthly, embodiments of this application provide a computer-readable storage medium for storing a computer program or instructions that, when executed, cause the methods described in the first or second aspect and any of their designs to be implemented.

[0050] Ninthly, embodiments of this application also provide a computer program product containing instructions that, when run on a computer, cause the methods described in the first or second aspect and any of their designs to be implemented.

[0051] The beneficial effects of the third to ninth aspects and their implementation methods mentioned above can be referenced to the beneficial effects of the first or second aspects and any one of their designs. Attached Figure Description

[0052] Figure 1 is a schematic diagram of the architecture of a communication system;

[0053] Figures 2A and 2B are schematic diagrams of the basis matrix of LDPC codes;

[0054] Figure 3 shows the matrix structure of the basis matrix of the LDPC code;

[0055] Figure 4 is a schematic diagram of the matrix regions corresponding to different code rates;

[0056] Figure 5 is a schematic diagram of the cyclic shift of the basis matrix of the LDPC code;

[0057] Figure 6 is an example diagram of the basis matrix in a one-sided QC-LDPC code;

[0058] Figure 7 is a schematic diagram of the parity check matrix obtained based on the basis matrix;

[0059] Figure 8 is a schematic diagram of the first two columns of holes in BG1 and BG2;

[0060] Figure 9 is a schematic diagram of the high bit rate region of BG1;

[0061] Figure 10 is another schematic diagram of the high bit rate region of BG1;

[0062] Figure 11 is a flowchart illustrating the method provided in an embodiment of this application;

[0063] Figure 12 is a schematic diagram of the structure of the base matrix of the LDPC code provided in the embodiment of this application;

[0064] Figure 13 is a schematic diagram of the second region provided in an embodiment of this application;

[0065] Figure 14 is a schematic diagram showing that r1 and r2 satisfy the constraints of preset values ​​provided in the embodiments of this application;

[0066] Figure 15A is a schematic diagram of the second offset value set provided in an embodiment of this application;

[0067] Figure 15B is a schematic diagram of the first offset value set provided in an embodiment of this application;

[0068] Figure 16 is a schematic diagram of the performance of the first offset value set and the second offset value set provided in the embodiments of this application;

[0069] Figure 17 is a schematic diagram of a communication device provided in an embodiment of this application;

[0070] Figure 18 is a schematic diagram of another structure of the communication device provided in an embodiment of this application;

[0071] Figure 19 is a schematic diagram of another structure of the communication device provided in the embodiments of this application. Detailed Implementation

[0072] In the embodiments of this application, "transmission" includes "sending" and / or "receiving." "Sending" and "receiving" indicate the direction of signal transmission. For example, "sending information to XX" can be understood as the destination of the information being XX, including direct sending as well as indirect sending through other units, modules, devices, or network elements. "Receiving information from YY" can be understood as the source of the information being YY, including receiving directly from YY via the air interface as well as receiving indirectly from YY via the air interface from other units or modules. "Sending" can also be understood as the "output" of a chip interface, and "receiving" can also be understood as the "input" of a chip interface. In other words, sending and receiving can occur between devices, such as between access network devices and terminal devices, or within a device, such as between components, modules, chips, software modules, or hardware modules within the device via buses, traces, or interfaces.

[0073] In this application embodiment, the number of nouns, unless otherwise specified, refers to "singular nouns or plural nouns," that is, "one or more." "At least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A / B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. For example, A / B means: A or B. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and / or c means the following combinations: a exists alone, b exists alone, c exists alone, a and b exist simultaneously, a and c exist simultaneously, b and c exist simultaneously, or a, b, and c exist simultaneously, where a, b, and c can be single or multiple.

[0074] In the embodiments of this application, "when," "if," and "if" all refer to the device taking corresponding actions under certain objective circumstances, and are not time-limited, nor do they require the device to perform a judgment action, nor do they imply any other limitations. Unless otherwise specified, "if" and "if" can be substituted, and "when" and "in the case of" can be substituted. "When" and "if" / "if" can be substituted.

[0075] In the embodiments of this application, the words "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. In the embodiments of this application, "of," "corresponding, relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0076] In this application's embodiments, ordinal numbers such as "first" and "second" are used to distinguish multiple objects, and are not used to limit the size, content, order, timing, priority, or importance of the multiple objects. For example, "first agent" and "second agent" refer to two different agents, and do not indicate a difference in the priority or importance of these two agents.

[0077] In the embodiments of this application, the solutions in each embodiment can be used in a reasonable combination, and the explanations or descriptions of various terms, similar operations, or steps appearing in the embodiments can be referenced or explained to each other in the embodiments, without limitation.

[0078] The technical solutions provided in the embodiments of this application can be applied to various communication systems, such as long term evolution (LTE) communication systems, 5G mobile communication systems / new radio (NR) communication systems, or future mobile communication systems, or other similar communication systems. Other similar communication systems may include vehicle-to-everything (V2X) systems, internet of things (IoT) systems, local area networks (LANs), or wireless local area networks (WLANs), etc. The WLAN can be a WLAN employing any of the protocols in the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series. The WLAN may include one or more basic service sets (BSSs), and the network nodes in the basic service set include access points (APs) and stations (STAs). The embodiments of this application can also be applied to wireless local area network systems that support the next-generation wireless fidelity (Wi-Fi) protocol of IEEE 802.11ax, such as 802.11be, 802.11bn and other 802.11 series protocols, and can also be applied to wireless personal area network systems based on ultra-wideband (UWB) and sensing systems.

[0079] The method provided in this application embodiment can also be applied to terrestrial networks (TN); or, the method provided in this application embodiment can also be applied to non-terrestrial networks (NTN), such as satellite communication systems, for example, it can be applied to transparent satellite architecture, backhaul satellite architecture or regenerative satellite architecture, etc., without limitation.

[0080] Please refer to Figure 1, which illustrates a communication system applicable to an embodiment of this application. The communication system includes a first device and a second device. The first device and the second device are capable of communication; for example, the first device is a data sender, and the second device is a data receiver. When sending data, the first device can perform operations such as encoding, and after receiving data from the first device, the second device can perform operations such as decoding. For example, the first device can be a network device, and the second device can be a terminal device; or, the first device can be a terminal device, and the second device can be a network device; or, the first device can be a first terminal device, and the second device can be a second terminal device. The network architecture shown in Figure 1 is merely illustrative; the number of the first device and / or the second device can be fewer or more. The communication system described in this application embodiment is for the purpose of more clearly illustrating the technical solutions of the embodiments of this application and does not constitute a limitation on the communication system applicable to the embodiments of this application. For example, the communication system may also include other devices not shown in Figure 1. Those skilled in the art will understand that, with the evolution of network architectures, the technical solutions provided in this application embodiment are also applicable to similar technical problems. When applying the technical solutions of the embodiments of this application to other communication systems, the devices, components, modules, etc. in the embodiments can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0081] In this embodiment, network equipment refers to radio access network (R)AN equipment / RAN node. R)AN and RAN are interchangeable; for ease of description, RAN is used as an example below. RAN can be a 3GPP-related cellular system, such as a 5G / NR mobile communication system, or a future-oriented evolution system. RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), a virtualized RAN (vRAN), NTN, etc. RAN can also be a communication system that integrates two or more of the above systems. RAN equipment can also be called a RAN node, RAN entity, or access node, etc.

[0082] In one possible scenario, a RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), or a base station in a future mobile communication system. RAN nodes can be macro base stations, micro base stations, indoor stations, relay nodes, donor / host nodes, or radio controllers. RAN nodes can also be servers, wearable devices, vehicles, or in-vehicle equipment. For example, in V2X technology, the RAN node can be a roadside unit (RSU). An AP acts as a bridge connecting wired and wireless networks, primarily connecting various wireless network clients and then connecting the wireless network to the Ethernet. This AP can serve as the central hub of the communication system and can be a base station with a Wi-Fi chip, a router, gateway, repeater, communication server, switch, or bridge. The AP can support the 802.11be standard or its next generation, such as Wi-Fi 8 or other WLAN standards. The AP can also support WLAN standards such as 802.11ax, 802.11ac, 802.11n, 802.11g, 802.11b, and 802.11a.

[0083] In another possible scenario, the RAN node can be a module or unit that performs some of the functions of the base station; or multiple RAN nodes can cooperate to assist terminal equipment in achieving wireless access, with different RAN nodes performing some of the functions of the base station. For example, the RAN node can be a CU, DU, or RU. The function of the CU can be implemented by a single entity or by different entities. For example, the function of the CU can be further divided, that is, the control plane and the user plane can be separated and implemented by different entities, namely the control plane CU entity (i.e., CU-control plane (CP) entity) and the user plane CU entity (i.e., CU-user plane (UP) entity). The CU-CP entity and the CU-UP entity can be coupled with the DU to jointly complete the function of the RAN node. The CU and DU can be set up separately or included in the same network element, such as in the baseband unit (BBU). Any of the units among the CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented by software modules, hardware modules, or a combination of software modules and hardware modules.

[0084] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples.

[0085] The CU and DU can be configured according to the protocol layer functions of the wireless network they implement: for example, the CU can be configured to implement the functions of the Packet Data Convergence Protocol (PDCP) layer and above (such as the Radio Resource Control (RRC) layer and / or the Service Data Adaptation Protocol (SDAP) layer); the DU can be configured to implement the functions of protocol layers below the PDCP layer (such as the Radio Link Control (RLC) layer, the Medium Access Control (MAC) layer, and / or the Physical (PHY) layer). For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications or the technical specifications of other applicable communication protocols.

[0086] The above division of CU and DU processing functions according to the protocol layer is merely an example; other division methods are also possible, and this application does not impose any restrictions.

[0087] For example, in one design, the CU or DU can be further divided into partial processing functions with protocol layers. In one design, some functions of the RLC layer and the functions of the protocol layer above the RLC layer are located in the CU, while the remaining functions of the RLC layer and the functions of the protocol layer below the RLC layer are located in the DU.

[0088] For example, in another possible design, the DU and RU cooperate to implement the PHY layer functions, or it can be described as moving a portion of the PHY layer functions of the DU to the RU. A DU can be connected to one or more RUs. The functions of the DU and RU can be configured in various ways depending on the design. For example, the DU is configured to implement baseband functions, and the RU is configured to implement mid-RF functions. Another example is that the DU is configured to implement higher-level functions in the PHY layer, and the RU is configured to implement lower-level functions in the PHY layer, or to implement both lower-level and RF functions. Higher-level functions in the physical layer can include a portion of the physical layer's functions that are closer to the MAC layer, and lower-level functions in the physical layer can include another portion of the physical layer's functions that are closer to the mid-RF side. This application does not limit the specific functions of the DU and RU. The interface between the DU and RU can be called a fronthaul interface. In one design, the CU may not have a PDCP layer; for example, the CU may only include an RRC layer. The CU-CP may not have PDCP-C. The CU-UP may not have PDCP-U, or it may not have a CU-UP. In one design, the DU may not have an RLC layer; for example, the DU may only have a MAC and a higher PHY layer.

[0089] Optionally, when the network device is an O-RAN, it includes a BBU and an RU. The BBU includes at least one CU and at least one DU, and the CU and DU can communicate via at least one midhaul link. The RU can implement lower physical layer (PHY) and radio frequency (RF) functions. In some examples, the RU can be a TRP, a remote radio head (RRH), or other similar entities. In some examples, the Low-PHY can include PHY processing functions such as fast Fourier transform (FFT), inverse fast Fourier transform (IFFT), digital beamforming, and filtering. The BBU can communicate with the CN via a backhaul link, and the RU can communicate with at least one terminal device via an air interface. The BBU can communicate with at least one RU via a fronthaul link. The BBU and RU can be co-located or not.

[0090] Alternatively, the DU and RU may or may not be co-located. The DU and RU can exchange control plane and user plane information via a fronthaul link through a lower-layer split CUS-plane (LLS-CUS) interface. LLS-CUS may include LLS-C and LLS-U interfaces that respectively provide the control plane (C-Plane) and user plane (U-Plane). In some examples, the control plane (C-Plane) refers to real-time control between the DU and RU. The DU and RU exchange management information via an LLS-M interface on the fronthaul link; the management plane (M-Plane) refers to non-real-time management operations between the DU and RU.

[0091] When the RAN is O-RAN, it can also have artificial intelligence (AI) capabilities. For example, O-RAN includes an intelligent controller. The intelligent controller can be a non-real-time RAN intelligent controller (RIC / non-RT RIC / NRT RIC) or a near-real-time RAN intelligent controller (RIC / near-RT RIC / nRT RIC). A non-real-time RIC can be used to implement non-real-time intelligent management of RAN functions, enabling workflows including model training and model updates, and guiding applications / functions in the nRT RIC based on policies. A near-real-time RIC can be used to implement near-real-time intelligent management of the RAN. Through data collection and related operations on the E2 interface, near-real-time control and optimization of O-RAN modules and resources are achieved.

[0092] In the embodiments of this application, the means for implementing the functions of the network device can be the network device itself, or it can be a means that supports the network device in implementing the functions, such as a chip system or a combination of devices or components that can implement the functions of the network device. This means can be installed in the network device. The embodiments of this application do not limit the specific technology or specific device form used in the network device.

[0093] In this application embodiment, anything capable of data communication with a base station can be considered a terminal device. A terminal device is also called a terminal, terminal apparatus, user equipment (UE), mobile station, or mobile terminal, etc. Terminal devices can be widely used in various scenarios. For example, a terminal device can be: a mobile phone, computer, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, station (STA), robotic arm, camera, robot, vehicle, drone, helicopter, airplane, ship, or smart home device (e.g., television, air conditioner, robot vacuum cleaner, speaker, set-top box), relay, customer premises equipment (CPE), etc. Among these, an STA can be a mobile phone supporting Wi-Fi communication, a tablet computer supporting Wi-Fi communication, a set-top box supporting Wi-Fi communication, a smart TV supporting Wi-Fi communication, a smart wearable device supporting Wi-Fi communication, an in-vehicle communication device supporting Wi-Fi communication, and a computer supporting Wi-Fi communication, etc. STA can be a router, switch, or bridge. STA can support the 802.11be standard, as well as various WLAN standards in the 802.11 family, such as 802.11ax, 802.11ac, 802.11n, 802.11g, 802.11b, 802.11a, 802.11be, Wi-Fi 7, Wi-Fi 8, or their next generation.

[0094] The embodiments of this application do not limit the specific technology or device form used in the terminal device. Furthermore, in the embodiments of this application, the terminal device can also be a terminal device in an IoT system, such as a water meter or electricity meter. IoT is an important component of future information technology development. Its main technical characteristic is connecting objects to networks through communication technology, thereby realizing an intelligent network of human-machine interconnection and machine-to-machine interconnection.

[0095] When the terminal device is applied to V2X, it can also be called a V2X device, such as a smart car, an unmanned car, a driverless car, a pilotless car, or an automobile, or an RSU. All the terminal devices described above, if located on a vehicle (e.g., placed / installed inside the vehicle), can be considered in-vehicle terminal devices. In-vehicle terminal devices can be built into a vehicle's in-vehicle module, in-vehicle component, in-vehicle chip, or in-vehicle unit as one or more components or units. The vehicle can implement the methods of this application through the built-in in-vehicle module, in-vehicle component, in-vehicle chip, or in-vehicle unit. In-vehicle terminal devices can be vehicle equipment, in-vehicle modules, vehicles, in-vehicle units (on-board units, OBUs), RSUs, in-vehicle infotainment systems (or in-vehicle transmission units) (telematics boxes, T-boxes), chips, or SoCs, etc., and the aforementioned chips or SoCs can be installed in the vehicle, OBU, RSU, or T-box.

[0096] In the embodiments of this application, the device for implementing the functions of the terminal device can be the terminal device itself, or it can be a device that supports the terminal device in implementing the functions, such as a chip system or a combination of devices or components that can implement the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or device form used in the terminal device.

[0097] The communication system applicable to the embodiments of this application has been described above. To facilitate understanding of the technical solutions provided by the embodiments of this application, the relevant terms and other information involved in the embodiments of this application will be explained below.

[0098] (1) LDPC code

[0099] LDPC codes are error-correcting codes with low-density parity-check matrices. The basic idea is to represent a linear code using a set of sparse parity-check matrices and then use these matrices for error correction at the receiver. The parity-check matrix of an LDPC code is a sparse matrix, meaning the number of non-zero elements in the parity-check matrix is ​​much smaller than the number of zero elements.

[0100] Mainstream LDPC codes have a quasi-cyclic (QC) structure, also known as quasi-cyclic LDPC (QC-LDPC) codes. QC-LDPC codes are a special type of LDPC code with a quasi-periodic structure. Unlike traditional LDPC codes, the parity-check matrix (PCM) of a QC-LDPC code is not completely random, but rather a large matrix constructed by repeating a smaller base matrix. The base matrix can be viewed as a small matrix that constructs the entire LDPC code. The base matrix is ​​typically a small sparse matrix containing elements that define the code structure, such as the position and number of non-zero elements. In QC-LDPC codes, a large-scale PCM can be formed by cyclically shifting or periodically copying the base matrix. This matrix has a low-density structure similar to traditional LDPC codes, but exhibits periodic or quasi-periodic characteristics. For example, if the elements in the base matrix are 0 or 1, expanding the 1s in the base matrix into a cyclic shift matrix and expanding the 0s into a 0 matrix of the corresponding size yields the PCM.

[0101] The basis matrix of an LDPC code can be represented graphically, and this graph is called the base graph (BG).

[0102] The model of BG can be BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the verification equation, and F is the edge relationship (used to represent the relationship between the variables and the verification equation), with an expansion factor of Z. c The QC extension yields a Tanner graph. The Tanner graph model is G = (V, C, E), where V are variable nodes, C are check nodes, and E are edge relationships. The number of columns in the check matrix corresponding to this Tanner graph is N = |V| = Z. c |X|, the number of rows in the parity check matrix M = |C| = Z c The number of non-zero elements in the parity check matrix is ​​|E|=Z|F|.

[0103] A Tanner graph can be viewed as a bipartite graph consisting of variable nodes (variable bits) and check nodes (check equations). Each edge in the Tanner graph represents the relationship between a variable bit and a check equation. Each check equation corresponds to a parity constraint. In other words, the Tanner graph and the parity check matrix are in one-to-one correspondence, composed of two types of nodes: the first type represents the codeword symbol, called variable nodes; the second type represents the check constraint relationship, called check nodes, each check node representing a check constraint relationship. Variable nodes represent the value of each information bit during the encoding process. For a codeword of length N, it has N variable nodes, each corresponding to an information bit or a check bit. Check nodes represent the corresponding parity check equation, checking whether a set of variable nodes (information bits) satisfies the check constraint. Each check equation contains a set of variable bits, constraining the parity of these variable bits (usually their XOR sum is 0). For each row in a parity check matrix H, there is a corresponding check node.

[0104] For example, please refer to Figures 2A and 2B. Figure 2A is an example diagram of the LDPC code basis matrix, and Figure 2B is a Tanner diagram of the LDPC code. In Figures 2A and 2B, {V i} represents the set of variable nodes, {C i} represents the set of verification nodes.

[0105] (2) The basis matrix of LDPC code

[0106] As an example, the basis matrices of the 5G LDPC code include BG1 and BG2. BG1 is a 46x68 matrix, and BG2 is a 42x52 matrix. Both BG1 and BG2 have the matrix structure shown in Figure 3, for example, containing multiple regions as shown in Figure 3. Region A corresponds to the high-rate information column (or the region with the highest code rate), region B corresponds to the core checksum of the high code rate, region C is a zero matrix, region D is the incremental redundancy part of the basis matrix and corresponds to the low code rate, and region E is the incremental redundancy region and is an identity matrix. The values ​​of the basis matrix are 0 or 1; a value of 0 represents an empty element, and a value of 1 represents an edge in the basis graph, or the association between the checksum and the variable.

[0107] BG1 and BG2 are designed for the lowest bitrate. When different bitrates need to be supported, the upper left portion of BG1 or BG2 can be used. Figure 4 shows the matrix regions corresponding to different bitrates. The rows and columns of each dashed box region form a base matrix. As the size of the dashed box region increases, the bitrate of the corresponding base matrix gradually decreases. When rows and columns of the high bitrate region shown in Figure 4 are selected from BG1 or BG2 to form the base matrix, the bitrate of this base matrix is ​​the highest; therefore, this base matrix is ​​also called the highest bitrate matrix. When more rows and columns than the high bitrate region are selected from BG1 or BG2 to form the base matrix, the bitrate of this base matrix is ​​lower than the highest bitrate. Furthermore, as the number of rows and columns increases, the bitrate of the corresponding matrix region gradually decreases.

[0108] Similarly, the base matrix structure applicable to the scheme of this application may also include: region A, region B, region C, region D, and region E. Region A corresponds to the high bitrate information column (or the region of the highest bitrate information column), region B corresponds to the core check for high bitrate, region C is a zero matrix, region D is the incremental redundancy part of the base matrix and corresponds to the low bitrate, and region E is the incremental redundancy region and is an identity matrix. The base matrix takes values ​​of 0 or 1, where a value of 0 represents an empty element, and a value of 1 represents an edge in the base graph, or represents the association between the check and the variable.

[0109] Alternatively, the columns of the base matrix applicable to the scheme of this application consist of information columns and verification columns, and the rows of the base matrix applicable to the scheme of this application consist of the rows corresponding to the core verification, as described below.

[0110] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to area A.

[0111] Check columns: Corresponding to check bits (or check digits, etc.), these are the columns corresponding to regions B and C, and can include core check columns and extended check columns. The core check columns are those corresponding to region B, while the extended check columns are those corresponding to parts of region C. Extended check columns can also be called raptor-like columns. Alternatively, the core check columns are the check columns in region B where the column weight is greater than 1 (region B has 1 element both above and below its diagonal), and the extended check columns are the remaining check columns excluding the core check columns.

[0112] Core rows: The core rows of the base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or regions A, B, or C.

[0113] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate regions, or the columns corresponding to regions A and B.

[0114] The kernel matrix is ​​a matrix region consisting of all the kernel rows and columns of the base matrix. In other words, the kernel matrix is ​​the high-bitrate region of the base matrix, or a portion composed of regions A and B.

[0115] The base matrix (BG) used in this application can be designed with the lowest possible bitrate. When different bitrates need to be supported, the upper left portion of the BG can be used. When rows and columns from a high-bitrate region are selected from the BG to form the base matrix, the bitrate of this base matrix is ​​the highest; therefore, this base matrix is ​​also called the highest bitrate matrix. When more rows and columns than high-bitrate regions are selected from the BG to form the base matrix, the bitrate of this base matrix is ​​lower than the highest bitrate. Furthermore, as the number of rows and columns increases, the bitrate of the corresponding matrix region gradually decreases.

[0116] (3) Constructing the parity check matrix

[0117] Constructing the parity-check matrix is ​​essentially lifting and shifting the basis matrix. The basis matrix has the form H. BG H BG The elements in the matrix are either 0 or 1. The basis matrix H can be increased based on the lifting dimension Zc. BG The matrix is ​​expanded to a complete parity-check matrix H. The expansion process involves expanding the elements of the basis matrix (1) to Zc×Zc cyclic shift matrices and expanding the elements of the basis matrix (0) to Zc×Zc zero matrices. After expansion, the parity-check matrix is ​​obtained. Basis matrix H BG t in i,j (where t) i,j =1) is replaced with a Zc×Zc matrix I(P) i,j ), where I(P i,j ) is a cyclic shift of the identity matrix I of Zc×Zc by P i,j Next (left circular shift or right circular shift) or circular shift P i,j A matrix of degree (mod)Zc, P i,j This is the offset value corresponding to the i-th row and j-th column. Basis matrix H BG The zeros in H are replaced with a Zc×Zc matrix of all zeros. It can be seen that the purpose of lifting the basis matrix is ​​to improve the basis matrix H. BG To transform it into a larger parity check matrix H, the translation aims to shift each H... BG The identity matrix corresponding to the non-zero elements is cyclically shifted into a predefined matrix. Here, Zc can be called the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. "mod" indicates modulo operation.

[0118] When constructing the parity check matrix, first determine the size of Zc, then determine a set of shifting values ​​(SV) corresponding to Zc, and then construct the parity check matrix based on Zc and SV.

[0119] As an example, Table 1 shows various values ​​for the lifting dimension (Zc).

[0120] Table 1

[0121] As shown in Table 1, the values ​​of Zc are... j represents the j-th row in Table 1, where j = 0, 1, 2, 3, 4, 5, 6, 7; a0, a1, a2, a3, a 4, a 5, a6 and a7 are 2, 3, 5, 7, 9, 11, 13, and 15 respectively. k j The value of traverses from 0 to max(k) j ), where max(k0), max(k1), max(k2), max(k3), max(k4), max(k5), max(k6), and max(k7) are 7, 7, 6, 5, 5, 5, 4, 4 respectively. For example, if j = 0, then a0 = 2, and k0 iterates through 0 to 7. Therefore, the value of Zc can be 2*2. 0 ,2*2 1 ,2*2 2 ,2*2 3 ,2*2 4 ,2*2 5 ,2*2 6 ,2*2 7 That is, 2, 4, 8, 16, 32, 64, 128, 256. The cases where j takes values ​​from 1 to 7 are similar and will not be elaborated further.

[0122] Each row of Zc in Table 1 corresponds to a set of SVs (also called SV sets). Table 2 below shows a partial example of a set of SVs defined in the 3GPP 212 protocol. Table 2 shows the basis matrix H. BG The offset SV corresponding to each element with a value of 1 in row 0 i,j It should be noted that Table 2 only shows the offset values ​​corresponding to each element in row 0. In reality, it also includes the offset values ​​corresponding to each element in other rows (such as row 1, row 2, etc.).

[0123] Table 2

[0124] Table 2 shows the basis matrix H. BG The offset SV corresponding to each element with a value of 1 in row 0 i,j The set index i in Table 2LS That is, the set index i in Table 1 LS Furthermore, the basis matrix H BG The cyclic shift values ​​corresponding to the elements with a value of 1 in row 0 can be obtained by taking the modulo of Zc using the offset value corresponding to that element. Table 2 only shows the translation values ​​corresponding to the elements in row 0; in practice, it also includes the translation values ​​corresponding to the elements in other rows (such as row 1, row 2, etc.).

[0125] Referring to Table 2, when Zc takes the values ​​2, 4, 8, 16, 32, 64, 128, or 256, then i LS =0, basis matrix H BG The SV values ​​of the elements with a value of 1 in row 0 are 250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0. Assuming Zc = 4, then the basis matrix H... BG The cyclic shift counts corresponding to the elements with a value of 1 in row 0 are 250 mod 4, 69 mod 4, 226 mod 4, 159 mod 4, 100 mod 4, 10 mod 4, 59 mod 4, 229 mod 4, 110 mod 4, 191 mod 4, 9 mod 4, 195 mod 4, 23 mod 4, 190 mod 4, 35 mod 4, 239 mod 4, 31 mod 4, 1 mod 4, 0 mod 4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. This means that the 4x4 identity matrix is ​​cyclically shifted 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0 times to obtain the basis matrix H. BG The elements in row 0 that have a value of 1 correspond to a 4x4 matrix. For the basis matrix H... BG If the elements in row 0 have a value of 0, then update them to a zero matrix of size 4*4.

[0126] For other values ​​of Zc, there are corresponding offset values ​​and cyclic shift counts, as detailed in Table 2. For the base matrix H... BG The rows other than row 0 are also determined using a similar method to determine the corresponding Zc*Zc matrix.

[0127] When constructing the parity check matrix, for example, if the element in the i-th row and j-th column of the base matrix is ​​1, then it corresponds to a parity check matrix (SV), which can be represented by P. i,jThis represents the offset value corresponding to the i-th row and j-th column. An offset value can be used to calculate the corresponding number of cyclic shifts. Taking Zc=4 as an example, the matrix obtained by cyclically shifting the 4×4 identity matrix to the right by 1, 2, 3, and 0 times respectively is shown in Figure 5, that is, the number of cyclic shifts are 1, 2, 3, and 0 respectively.

[0128] The following example illustrates this. Figure 6 shows an example of the basis matrix in a one-sided QC-LDPC code. This basis matrix is ​​a 3x3 matrix, assuming Zc = 4, and P 0,0 The corresponding right circular shift count is 1, P 0,1 The corresponding right circular shift count is 2, P 1,0 The corresponding number of right circular shifts is 3, P 1,2 The corresponding number of right circular shifts is 3, P 2,2 The corresponding right circular shift count is 1. After expanding the base matrix, we can obtain the parity check matrix as shown in Figure 7.

[0129] The communication system and related terms applicable to the embodiments of this application have been introduced above. The technical problems to be solved by the embodiments of this application are described below.

[0130] During communication, the transmitting end encodes the information to be transmitted according to LDPC codes. Correspondingly, the receiving end demodulates the received information. LDPC encoding supports puncturing, which means that certain bit positions are not transmitted. For example, referring to Figure 8, the first two columns of matrices BG1 and BG2 are punctured columns. At the transmitting end, the bit positions corresponding to the punctured columns are not transmitted; correspondingly, the receiving end does not need to pay attention to the information at the bit positions corresponding to the punctured columns, sets its log-likelihood ratio to 0, and recovers the information through decoding.

[0131] For example, please refer to Figure 9, which is a schematic diagram of the high bitrate region of BG1. The high bitrate region of BG1 is a matrix region composed of region A and region B of BG1. Among them, region A is a 4x22 matrix used to carry data information, and region B is a 4x4 matrix used to carry check information. When the first two columns are punched, the bitrate supported by the high bitrate region is 22 / (22+4-2)=11 / 12≈0.917.

[0132] Currently, BG1 or BG2 has fixed punctured columns, for example, the first two columns of region A. To further improve the code rate, columns in region B are punctured simultaneously with columns in region A. For example, Figure 10 shows another schematic diagram of the high code rate region of BG1, where the first two columns of region A and the last column of region B can be punctured. However, the current design of some available offset values ​​in the base matrix is ​​unreasonable, leading to a decrease in decoding performance when some parity bits are punctured. For example, in high-throughput scenarios, the number of decoding iterations decreases (below 10 iterations), and decoding performance decreases when the code rate is greater than 11 / 12 (e.g., a higher bit error rate at the same signal-to-noise ratio). Therefore, how to reduce the loss of decoding performance when the code rate is greater than 11 / 12 (or when there are many punctured columns) remains to be solved.

[0133] Therefore, the present application provides a solution based on embodiments of this application. By constraining the offset values ​​corresponding to specific positions in the basis matrix, this application can improve decoding performance when the code rate is greater than 11 / 12 (or when there are many punctured columns). For example, it can reduce the bit error rate at the same signal-to-noise ratio.

[0134] The method provided in the embodiments of this application is described below.

[0135] In the following description, taking the method provided in the embodiments of this application applied to the network architecture shown in Figure 1 as an example, the method provided in the embodiments of this application can be executed by a first device and a second device. The steps executed by the first device can be implemented by the first device itself, or by components within the first device (such as a baseband chip, or other processing units or processor modules), or by logic modules or software that complete some or all of the functions of the first device. For example, if the first device is a network device, the steps executed by the first device can be implemented by the network device, or by a CU, DU, or RU that completes some of the functions of the network device. The steps executed by the second device can be implemented by the second device itself, or by components within the second device (such as a baseband chip, or other processing units or processor modules), or by logic modules or software that complete some or all of the functions of the second device. For example, if the second device is a network device, the steps executed by the second device can be implemented by a terminal device, or by a baseband chip or a SoC chip containing a modem core within the terminal device.

[0136] In this communication, the first device and the second device are the two ends. The first device can be either a sender or a receiver. For example, the first device can be a terminal device, and the second device can be a network device. Alternatively, the first device and the second device can be of the same type. For example, the first device can be a first terminal device, and the second device can be a second terminal device.

[0137] In the embodiments of this application, "mod" in the formula means modulo, and "*" means multiplication.

[0138] Please refer to Figure 11, which is a flowchart illustrating the method provided in an embodiment of this application. Figure 11 describes the method from the perspective of the interaction between a first device and a second device. The first device is the data sender, and the second device is the data receiver. It should be understood that this method can also be implemented by other devices, such as a chip or communication device with communication capabilities. Furthermore, the processing performed by a single execution entity can be divided into multiple execution entities, which can be logically and / or physically separated. For example, the second device is a network device, and the processing performed by the second device can be divided into execution by at least one of CU, DU, RU, etc. As shown in Figure 11, the flow of this method includes the following steps.

[0139] S1101, The first device lifts and cyclically shifts the first base matrix according to the first lifting dimension and the first offset value set corresponding to the first lifting dimension to obtain the parity matrix.

[0140] The first basis matrix can be the basis matrix of an LDPC code or a submatrix of the basis matrix of an LDPC code. In this embodiment, the basis matrix has the structure shown in Figure 12. The basis matrix shown in Figure 12 adopts a "raptor-like" structure, which can be gradually extended to low code rates from a high code rate core matrix. In actual use, as shown in the first region of Figure 12, the first M rows and the first N columns of the basis matrix can be extracted. As the code rate decreases, M and N gradually increase, and the area of ​​the matrix used also gradually expands. In other words, the first region is the first column to the Nth column and the first row to the Mth row of the basis matrix. Correspondingly, the second region is the (N+1)th column to the (N+P)th column and the first row to the Mth row of the basis matrix, where M, N, and P are all positive integers.

[0141] The matrix is ​​divided into five regions: The first region corresponds to the high-bitrate information columns, specifically the information bits (or information digits, system bits, etc.). Columns 1 through N are the information columns. The second region corresponds to the high-bitrate core checksum. This region is a square matrix (P = M) and corresponds to the core checksum bits (or core checksum digits). The core checksum can be the checksum corresponding to the highest bitrate, or a checksum with a degree greater than or equal to 2, or a checksum node corresponding to the row set with the highest row weight (significantly higher than other rows). Columns N+1 through N+P are the core checksum columns. The third region is a zero matrix, meaning that all elements from column N+P+1 to the last column are zero. The fourth region is the incremental redundancy portion of the base matrix and corresponds to the low-bitrate extended checksum bits. The fifth region is the incremental redundancy region and is an identity matrix. Both the second and fifth regions are verification parts. The second region is defined as the core verification region, and its features can be non-lower triangular encoded parts (i.e., values ​​above the diagonal are not all 0) or encoded parts with column weights greater than 1. The fifth region is defined as the extended verification region, and its features can be lower triangular encoded parts (i.e., values ​​above the diagonal are all 0) or diagonal matrices.

[0142] Comparatively, regions one and two can also be considered high-rate regions, region three is an all-zero region, region four is an incremental redundancy region, and region five is a raptor-like region. This application does not specify the specific names for regions one through five. For example, region one may also be called region A, region two may also be called region B, region three may also be called region C, region four may also be called region D, and region five may also be called region E.

[0143] Before obtaining the parity check matrix, the first device needs to determine the first base matrix. For example, the first device can determine the first base matrix based on at least one of the following: information length, code length, and code rate, or an application scenario. The information length is the number of bits in the information to be transmitted (e.g., the first information), which may or may not include cyclic redundancy check (CRC) bits. The code length is the length / number of bits to be transmitted, which can be the number of transmitted bits corresponding to the modulated symbol. The code rate refers to the ratio of the information length to the number of transmitted bits. Application scenarios include, for example, enhanced mobile broadband (eMBB), high-throughput scenarios, peak rate scenarios, ultra-reliable low-latency communications (URLLC), and massive machine-type communications (mMTC). The first device can determine the storage content and encoding process applicable to one or more specific scenarios. The information length, code length, and code rate can all be pre-configured by higher-layer signaling, MAC layer signaling, or downlink physical layer signaling. Alternatively, the information length, code length, or code rate can be calculated by the first device. For example, the code length can be determined based on the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bits. The code rate can be indicated by signaling or given by a modulation and coding scheme (MCS) table.

[0144] For example, when the information length is less than or equal to 292 bits, when the information length is less than or equal to 3824 bits and the code rate is less than or equal to 0.67, or when the code rate is less than or equal to 0.25, the first device can determine that the first base matrix is ​​BG2. Similarly, when the information length is greater than 292 bits, when the information length is greater than 3824 bits and / or the code rate is greater than or equal to 0.67, or when the code rate is greater than 0.25, the first device can determine that the first base matrix is ​​BG1.

[0145] Before obtaining the parity-check matrix, the first device also determines a first boosting size (e.g., Zc in this paper). For example, the first device may determine the first boosting size based on the information length, code length, and code rate, or at least one of the following scenarios. The first boosting size is selected from the set of boosting sizes corresponding to the j-th row in Table 1. As mentioned above, the value of the first boosting size is... j represents the j-th row in Table 1, where j = 0, 1, 2, 3, 4, 5, 6, 7, and a0, a1, a2, a3, a4, a5, a6, a7 are 2, 3, 5, 7, 9, 11, 13, 15 respectively. k j The value of traverses from 0 to max(k) j ), where max(k0), max(k1), max(k2), max(k3), max(k4), max(k5), max(k6), and max(k7) are 7, 7, 6, 5, 5, 5, 4, 4 respectively. For ease of description, the lift set containing the first lift dimension is referred to as the first lift dimension set in this paper.

[0146] The order in which the first device determines the first base matrix and the first lifting dimension is not limited. For example, the first device may determine the first base matrix and the first lifting dimension simultaneously. Alternatively, the first device may determine the first base matrix first, and then determine the first lifting dimension.

[0147] Before obtaining the verification matrix, the first device also determines the first offset value set corresponding to the first lift dimension. In Table 1, each row Zc corresponds to an offset value set. The first device can determine the first offset value set corresponding to the first lift dimension from the multiple offset value sets based on the correspondence between multiple lift dimensions and multiple offset value sets.

[0148] This application considers that due to unreasonable offset design, some parity bits are punched, resulting in a decrease in decoding performance. Therefore, embodiments of this application constrain the offset value at specific positions in the first base matrix, achieving better decoding performance when the code rate is greater than 11 / 12 (or when there are many punched columns). For example, when the code rate is greater than 11 / 12 and the number of decoding iterations is small, the bit error rate is reduced under a lower signal-to-noise ratio.

[0149] The following sections will introduce the constraints on specific positions and their offset values.

[0150] The first basis matrix can be the basis matrix of the LDPC code with the structure shown in Figure 12. Specific positions of the first basis matrix include the first sub-region and the second sub-region of the first basis matrix. Specifically, the first sub-region of the first basis matrix includes: the m-th and n-th rows of the first column of the first region of the first basis matrix, and / or, the m-th and n-th rows of the second column of the first region of the first basis matrix, where m and n are positive integers. The first and second columns of the first region are the columns containing the punched positions in the first region; therefore, the first and second columns of the first region are also called the punched columns of the first region. Alternatively, "punched columns of the first region" can be replaced with / include "the first and second columns of the first region".

[0151] The second subregion comprises the m-th and n-th rows of the last column of the second region of the first base matrix. The m-th and n-th rows contain the non-zero elements in the last column of the second region. For example, following the example in Figure 10, the second region (i.e., region B in Figure 10) is a 4×4 matrix, and the rows containing the non-zero elements in the last column of the second region are the third and fourth rows; therefore, m = 3 and n = 4. In other words, the first subregion comprises the third and fourth rows of the first column of the first region of the first base matrix, and / or the third and fourth rows of the second column of the first region of the first base matrix. The second subregion comprises the third and fourth rows of the last column of the second region of the first base matrix.

[0152] For example, as shown in Figure 13, the second region is a 6×6 matrix. The rows containing the non-zero elements of the last column of the second region are the fifth and sixth rows. Therefore, m = 5 and n = 6. In other words, the first sub-region includes the fifth and sixth rows of the first column of the first region of the first base matrix, and / or the fifth and sixth rows of the second column of the first region of the first base matrix. The second sub-region includes the fifth and sixth rows of the last column of the second region of the first base matrix.

[0153] The above example uses the case where m and n are continuous. In some embodiments, m and n are not continuous. For example, the rows containing the non-zero elements of the last column of the second region are the second and fourth rows, therefore, m = 2 and n = 4.

[0154] As mentioned above, the specific location includes a first sub-region and a second sub-region. Correspondingly, the offset value at the specific location includes the offset value corresponding to the first sub-region of the first basis matrix and the offset value corresponding to the second sub-region of the first basis matrix. In the embodiments of this application, the offset values ​​corresponding to the first sub-region of the first basis matrix and the offset values ​​corresponding to the second sub-region of the first basis matrix in the first offset value set satisfy a preset relationship.

[0155] As a design, the offset values ​​corresponding to the first sub-region and the second sub-region satisfy a preset relationship, including that r1 and r2 satisfy the constraints of preset values. Both r1 and r2 are determined based on the offset values ​​corresponding to the first sub-region, the offset values ​​corresponding to the second sub-region, and a second lifting dimension. For example, r1 can be determined based on a, b, e, f, and the second lifting dimension, where a is the offset value corresponding to the m-th row (e.g., the third row) of the first column of the first region, b is the offset value corresponding to the n-th row (e.g., the fourth row) of the first column of the first region, e is the offset value corresponding to the m-th row (e.g., the third row) of the last column of the second region, and f is the offset value corresponding to the n-th row (e.g., the fourth row) of the last column of the second region. r2 can be determined based on c, d, e, f, and the second lifting dimension, where c is the offset value corresponding to the m-th row (e.g., the third row) of the second column of the first region, and d is the offset value corresponding to the n-th row (e.g., the fourth row) of the second column of the first region.

[0156] The second lift dimension belongs to the set of first lift dimensions that contains the first lift dimension. For example, the first lift dimension is any lift dimension in the set of first lift dimensions. Another example is that the second lift dimension is the second largest lift dimension in the set of first lift dimensions. Yet another example is that the second lift dimension is the largest lift dimension in the set of first lift dimensions.

[0157] The preset value is related to the second boost size, or the preset value is determined based on the second boost size. The boost size affects the code length, and thus the performance. Therefore, constraining r1 and r2 based on the preset value determined by the boost size, and further constraining the offset value at a specific position, can reduce the loss of decoding performance. Generally speaking, when r1 and r2 do not meet the preset value constraints, the larger the boost size, the greater the loss of decoding performance. The selection of the offset value should be able to compensate for the decoding performance loss corresponding to both larger and smaller boost sizes. Thus, priority is given to the decoding performance loss corresponding to the largest boost size. Accordingly, the second boost size is the largest boost size in the first boost size set, in order to improve decoding performance as much as possible.

[0158] The following example illustrates the constraint that r1 and r2 satisfy preset values. In the following description, Zm is the second lifting dimension.

[0159] As an example, when both r1 and r2 are positive or negative, Furthermore, |r1| or |r2| > g*Zm, where g is a positive number less than or equal to 1 / 2. Optionally, g is greater than or equal to 3 / 8. For example, g can be equal to 3 / 8, 7 / 16, or 1 / 2.

[0160] Alternatively, when r1 is positive and r2 is negative... Furthermore, |r1-r2|>g*Zm.

[0161] Alternatively, when r1 is negative and r2 is positive, Furthermore, |r1-r2|>g*Zm.

[0162] As another example, ab-e+f=s1*Zm+r1;cd-e+f=s2*Zm+r2,s1 and s2 are positive integers. Or (ab)-(ef)=s1*Zm+r1;(cd)-(ef)=s2*Zm+r2。

[0163] It can be seen that the constraint that r1 and r2 satisfy the preset value means that there are no consecutive g*Zm values ​​such that the remainders of ab, cd, and ef after (mod) Zm are the same as those of the three numbers among the g*Zm values. In other words, if the values ​​from 0 to Zm-1 are marked evenly on the ring in sequence, and ab, cd, and ef are marked on the ring according to their remainders after (mod) Zm, there is no arc with a circumference of length g*Zm that simultaneously covers the three points marked ab, cd, and ef, as shown in Figure 14.

[0164] In this embodiment, the offset values ​​at specific positions of the first base matrix are constrained, while the offset values ​​at other positions are not limited. For example, existing offset values ​​(e.g., Table 2) can be reused for offset values ​​at other positions. From this perspective, it can be considered that the offset values ​​at specific positions in the existing offset values ​​are modified to obtain the offset values ​​provided in this embodiment. Alternatively, for the same lift size, this embodiment provides a new set of offset values ​​(i.e., a first set of offset values). This first set of offset values ​​can be obtained by modifying some offset values ​​in an existing set of offset values ​​(e.g., a second set of offset values), or the first set of offset values ​​can be determined based on the second set of offset values. The second offset value corresponds to the first lift size. For example, the first set of offset values ​​includes first offset values, and the second set of offset values ​​includes second offset values. The second offset values ​​in the second set of offset values ​​can be modified to first offset values ​​to obtain the first set of offset values.

[0165] For example, the position of the second offset value can be the third row of the first column of the first region, the fourth row of the first column of the first region, the third row of the second column of the first region, the fourth row of the second column of the first region, the third row of the last column of the second region, or the fourth row of the last column of the first region.

[0166] The following explains how to change the second offset value to the first offset value.

[0167] The difference between the first offset value and the second offset value is a multiple of 'a', where 'a' belongs to the first lift dimension set containing the first lift dimension. For example, 'a' is the minimum value in the first lift dimension set. As mentioned in Table 1 above, 'a' is {a, a*2, a*2}. 2 ,…,a*2 k The minimum value in}. In this way, r1 and r2 can satisfy the constraints of the preset value.

[0168] As an example, the first translation value is the sum of the second translation value and at least one lift dimension from the first lift dimension set. Assuming the second offset is p, then the first offset is p and {a, a*2, a*2} 2 ,…,a*2 kThe sum of at least one lift dimension in}. For example, the first offset value could be p + a * 2. k-2 p+a*2 k-1 Or p+a*2 k-1 +a*2 k-2 .

[0169] Optionally, any one of the at least one boost size in the first boost size set is larger than any other boost size in the first boost size set. Since a larger boost size allows for longer code lengths, having at least one larger boost size is suitable for high-throughput scenarios.

[0170] The first offset value set can be obtained by modifying the second offset value in the second offset value set to the first offset value. For example, please refer to Figures 15A and 15B, where Figure 15A shows the second offset value set and Figure 15B shows the first offset value set. As can be seen from Figures 15A and 15B, modifying the second offset value (e.g., 167) corresponding to the third row of the second column of the first region to the first offset value (e.g., 23) is a good starting point. It should be understood that "-1" in Figures 15A and 15B corresponds to the position where the element in the base matrix is ​​"0", and the offset value corresponding to the position of "-1" is not stored in the protocol.

[0171] The first device obtains a parity check matrix by lifting and cyclically shifting the first base matrix according to the first lifting dimension and the first offset value set corresponding to the first lifting dimension. The first base matrix includes a first element, which is a non-zero element in the base matrix. Each zero element in the first base matrix corresponds to a zero matrix in the parity check matrix, and each non-zero element in the first base matrix corresponds to a non-zero matrix in the parity check matrix.

[0172] S1102. The first device encodes the first information according to the check matrix to obtain the second information.

[0173] The first information is the information to be sent. The first device encodes the first information according to the parity check matrix to obtain the second information. The second information is the encoded information; for example, the second information can be a physical data block (codeword) obtained by encoding the first information. The process of the first device encoding the first information according to the parity check matrix can be referenced to the process of encoding based on LDPC codes, and will not be elaborated here.

[0174] S1103, The first device outputs the second information.

[0175] Accordingly, the second device receives the second information.

[0176] S1104. The second device decodes the second information according to the check matrix to obtain the first information.

[0177] The second device can determine the parity check matrix. For example, the second device determines a first base matrix, a first lifting size, and a first offset value set corresponding to the first lifting size. It then lifts and cyclically shifts the first base matrix based on the first lifting size and the first offset value set to obtain the parity check matrix. The process by which the second device determines the first base matrix, the first lifting size, and the first offset value set can be referred to in the aforementioned process by which the first device determines the first base matrix, the first lifting size, and the first offset value set, and will not be repeated here.

[0178] The second information can be considered as the first information encoded and modulated before being sent to the second device. After receiving the second information, the second device can decode it to obtain the first information.

[0179] This application provides a first offset value set corresponding to the first lifting dimension. Compared with the second offset value set, the parity check matrix generated based on the first offset value set can reduce the loss of decoding performance.

[0180] For example, please refer to Figure 16, which shows the performance corresponding to the first offset value set and the second offset value set. Figure 16 takes a first lift size of 288 as an example, and takes the first two columns of the first region and the last 0.5 columns of the second region as examples. The first region is a 4x22 matrix used to carry data information, and the second region is a 4x4 matrix used to carry check information. Assuming that the first two columns of the first region are perforated, and the last 0.5 columns of the second region are perforated, then the code rate is 22 / (22+4-2-0.5) = 22 / 23.5, which is greater than 11 / 12. As can be seen from Figure 16, under the same signal-to-noise ratio, the bit error rate corresponding to the first offset value set can be lower than that corresponding to the second offset value set. Under the same bit error rate, the signal-to-noise ratio corresponding to the first offset value set can be higher than that corresponding to the second offset value set. Therefore, the first offset value set can improve decoding performance compared to the second offset value set.

[0181] In the embodiments provided above, the methods provided by the embodiments of this application are described using the execution of a first device and a second device as examples. In this application, each embodiment can be implemented independently or in combination based on certain inherent connections; in each embodiment, different implementation methods can be implemented in combination or independently. To achieve the functions in the methods provided by the embodiments of this application above, the steps executed by the first device can be implemented by the first device itself, or by a functional entity including the first device, or by different functional entities constituting the first device. The steps executed by the second device can be implemented by the second device itself, or by different functional entities constituting the second device, or by a functional entity including the second device. To achieve the functions in the methods provided by the embodiments of this application above, the first device and the second device can include hardware structures and / or software modules, implementing the above functions in the form of hardware structures, software modules, or hardware structures plus software modules. Whether a particular function is executed in the form of hardware structures, software modules, or hardware structures plus software modules depends on the specific application and design constraints of the technical solution.

[0182] Based on the same inventive concept as the method embodiments, this application provides a communication device. The communication device used to implement the above method in the embodiments of this application is described below with reference to the accompanying drawings. The content above can be used in subsequent embodiments, and repeated content will not be repeated.

[0183] Figure 17 is a schematic block diagram of the communication device 1700 provided in an embodiment of this application. The communication device 1700 can correspondingly implement the functions or steps implemented by the first device or the second device in the various method embodiments described above. For example, the communication device 1700 can be the first device in Figure 1; or, the communication device 1700 can be a chip (system) in the first device; or, the communication device 1700 can be a software module of the first device. Alternatively, the communication device 1700 can be the second device in Figure 1; or, the communication device 1700 can be a chip (system) in the second device; or, the communication device 1700 can be a software module of the second device. The first device or the second device can be a terminal device or a network device.

[0184] The communication device 1700 may include a processing module 1710 and a transceiver module 1720. Optionally, it may also include a storage module for storing instructions (code or programs) and / or data. This storage module may be, for example, a memory. The processing module 1710 and the transceiver module 1720 may be coupled to the storage module. For example, the processing module 1710 may read instructions (code or programs) and / or data from the storage module to implement corresponding methods. When the communication device 1700 is a chip in a terminal device, the storage module may be an internal storage module within the chip, such as a register or cache. For example, the storage module may also be an external storage module within the terminal device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM). The aforementioned units may be configured independently or partially or completely integrated.

[0185] Processing module 1710 may be a processor or controller, such as a general-purpose central processing unit (CPU), a general-purpose processor, a digital signal processing unit (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor may also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc. Transceiver module 1720 is a transceiver, interface circuit, bus, pin, or other possible communication interface for receiving signals from other devices. For example, when the device is implemented as a chip, transceiver module 1720 is an interface circuit for the chip to receive signals from other chips or devices, or an interface circuit for the chip to send signals to other chips or devices.

[0186] In one implementation, the communication device 1700 can correspondingly implement the behavior and functions of the first device in the above method embodiments. The communication device 1700 can be a terminal device / network device, a component (e.g., a chip or circuit) within the terminal device / network device, a part of a chip or chipset in the terminal device / network device used to execute the relevant method functions, or a software module in the terminal device / network device capable of implementing the above methods; there are no limitations. For details, please refer to the relevant content of the foregoing method embodiments, which will not be repeated here.

[0187] For example, processing module 1710 is used to lift and cyclically shift the first base matrix according to the first lifting size and the first offset value set corresponding to the first lifting size to obtain a parity check matrix; and to encode the first information according to the parity check matrix to obtain the second information. Transceiver module 1720 is used to output the second information. Wherein, the offset values ​​corresponding to the first sub-region of the first base matrix in the first offset value set satisfy a preset relationship with the offset values ​​corresponding to the second sub-region of the first base matrix. The first sub-region includes the third and fourth rows of the first column of the first region of the first base matrix, and / or the third and fourth rows of the second column of the first region of the first base matrix. The second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix. The first region of the first base matrix is ​​the first column to the Nth column and the first row to the Mth row of the first base matrix. The second region of the first base matrix is ​​the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix. M, N, and P are all positive integers.

[0188] In one implementation, the communication device 1700 can correspondingly implement the behavior and functions of the second device in the above method embodiments. The communication device 1700 can be a terminal device / network device, a component (e.g., a chip or circuit) within the terminal device / network device, a part of a chip or chipset in the terminal device / network device used to execute the relevant method functions, or a software module in the terminal device / network device capable of implementing the above methods; there are no limitations. Wherein, when the first device is a terminal device, the second device can be a network device; when the first device is a network device, the second device can be a terminal device. For details, please refer to the relevant content of the foregoing method embodiments, which will not be repeated here.

[0189] For example, the transceiver module 1720 is used to acquire the second information. The processing module 1710 performs lifting and cyclic shifting on the first base matrix according to the first lifting size and the first offset value set corresponding to the first lifting size to obtain a parity check matrix; and decodes the second information according to the parity check matrix to obtain the first information. Wherein, the offset values ​​corresponding to the first sub-region of the first base matrix and the offset values ​​corresponding to the second sub-region of the first base matrix satisfy a preset relationship. The first sub-region includes the third and fourth rows of the first column of the first region of the first base matrix, and / or the third and fourth rows of the second column of the first region of the first base matrix. The second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix. The first region of the first base matrix is ​​the first column to the Nth column and the first row to the Mth row of the first base matrix. The second region of the first base matrix is ​​the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix. M, N, and P are all positive integers.

[0190] As an optional implementation, the offset values ​​corresponding to the first sub-region and the second sub-region satisfy a preset relationship, including: r1 and r2 satisfy the constraint of a preset value, which is related to the second lift dimension, and the second lift dimension belongs to the set of first lift dimensions to which the first lift dimension is located. Both r1 and r2 are determined based on the offset values ​​corresponding to the first sub-region, the offset values ​​corresponding to the second sub-region, and the second lift dimension.

[0191] As an optional implementation, the second lift size is the maximum value in the set of first lift sizes.

[0192] As an optional implementation, r1 is determined based on a, b, e, f, and the second lifting dimension, and r2 is determined based on c, d, e, f, and the second lifting dimension. Here, a is the offset value corresponding to the third row of the first column of the first region, b is the offset value corresponding to the fourth row of the first column of the first region, c is the offset value corresponding to the third row of the second column of the first region, d is the offset value corresponding to the fourth row of the second column of the first region, e is the offset value corresponding to the third row of the last column of the second region, and f is the offset value corresponding to the fourth row of the last column of the second region.

[0193] As an optional implementation, ab-e+f=s1*Zm+r1;cd-e+f=s2*Zm+r2;where Zm is the second lifting dimension, and s1 and s2 are positive integers.

[0194] As an optional implementation method, Furthermore, |r1| or |r2| > g*Zm, where r1 and r2 are both positive or negative numbers, and g is a positive number less than or equal to 1 / 2. Alternatively, Furthermore, |r1-r2|>g*Zm, where r1 is a positive number, r2 is a negative number, and g is a positive number less than or equal to 1 / 2; or, r1 is a negative number, r2 is a positive number, and g is a positive number less than or equal to 1 / 2.

[0195] As an optional implementation, the first offset value set is determined based on the second offset value set, which corresponds to the first lift dimension. The first offset value set includes the first offset value, the second offset value set includes the second offset value, and the difference between the first offset value and the second offset value is a multiple of a, where a belongs to the first lift dimension set containing the first lift dimension.

[0196] In one implementation, the first translation value is the sum of the second translation value and at least one lift dimension in the first lift dimension set.

[0197] As an optional implementation, any one of the at least one lift dimension in the first lift dimension set is greater than any other lift dimension in the first lift dimension set other than that at least one lift dimension.

[0198] When the communication device 1700 is a chip-based device or circuit, the transceiver module can be an input / output circuit and / or a communication interface; the processing module is an integrated processor, microprocessor, or integrated circuit.

[0199] Figure 18 is a schematic block diagram of a communication device 1800 provided in an embodiment of this application. The communication device 1800 can be the first device or the second device in the above embodiments. For example, the communication device 1800 can be the first device in Figure 1 or a chip (system) within the first device. As another example, the communication device 1800 can be the second device in Figure 1 or a chip (system) within the second device. In this embodiment, the chip system can be composed of chips or can include chips and other discrete devices. Specific functions can be found in the descriptions in the above method embodiments. The first device or the second device is a terminal device or a network device.

[0200] The communication device 1800 includes one or more processors 1801, used to implement or support the communication device 1800 in implementing the functions of the first or second device in the methods provided in the embodiments of this application. For details, please refer to the detailed description in the method examples, which will not be repeated here. The processor 1801 can also be called a processing unit or processing module, and can implement certain control functions. The processor 1801 can be a general-purpose processor or a dedicated processor, etc. For example, it includes: a baseband processor, a central processing unit, an application processor, a modem processor, a graphics processor, an image signal processor, a digital signal processor, a video codec processor, a controller, a memory, and / or a neural network processor, etc. The baseband processor can be used to process communication protocols and communication data. The central processing unit can be used to control the communication device 1800 (e.g., a terminal device or a network device), execute software programs and / or process data. Different processors can be independent devices or integrated into one or more processors, for example, integrated on one or more application-specific integrated circuits.

[0201] In one design, processor 1801 may include program 1803 (sometimes referred to as code or instructions) that can be executed on processor 1801 to cause communication device 1800 to perform the methods described in the embodiments below. In yet another possible design, communication device 1800 includes circuitry (not shown in FIG18) for implementing the functions of the first or second device in the above embodiments.

[0202] In one design, the communication device 1800 may include one or more memories 1802 storing a program 1804 (sometimes referred to as code or instructions), which can be run on the processor 1801 to cause the communication device 1800 to perform the methods described in the above method embodiments.

[0203] In one possible design, the processor 1801 and / or memory 1802 may also store data. The processor and memory may be configured separately or integrated together.

[0204] In one possible design, the communication device 1800 may further include a transceiver and / or an antenna. The processor 1801, sometimes referred to as a processing unit, controls the communication device 1800. The transceiver, sometimes referred to as a transceiver unit, transceiver, transceiver circuit, or simply a transceiver, is used to implement the transmission and reception functions of the communication device 1800 via the antenna.

[0205] In one possible design, the communication device 1800 may further include one or more of the following components: a wireless communication module, an audio module, an external memory interface, internal memory, a universal serial bus (USB) interface, a power management module, an antenna, a speaker, a microphone, an input / output module, a sensor module, a motor, a camera, or a display screen, etc. It is understood that in some embodiments, the communication device 1800 may include more or fewer components, or some components may be integrated, or some components may be separated. These components may be implemented in hardware, software, or a combination of software and hardware.

[0206] Based on the above embodiments, referring to FIG19, this application embodiment also provides another communication device 1900, including: an input / output interface 1910 and a logic circuit 1920; the input / output interface 1910 is used to receive code instructions and transmit them to the logic circuit 1920; the logic circuit 1920 is used to run the code instructions to execute the method executed by the first device or the second device in any of the above embodiments, and can be referred to the above method embodiments, which will not be repeated here.

[0207] When the communication device 1900 is applied to the first device to execute the method performed by the first device, the logic circuit 1920 is used to lift and cyclically shift the first base matrix according to the first lift dimension and the first offset value set corresponding to the first lift dimension to obtain a parity matrix; and to encode the first information according to the parity matrix to obtain the second information. The input / output interface 1910 is used to output the second information. Wherein, the offset value corresponding to the first sub-region of the first base matrix in the first offset value set satisfies a preset relationship with the offset value corresponding to the second sub-region of the first base matrix. The first sub-region includes the third and fourth rows of the first column of the first region of the first base matrix, and / or the third and fourth rows of the second column of the first region of the first base matrix. The second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix. The first region of the first base matrix is ​​the first column to the Nth column and the first row to the Mth row of the first base matrix. The second region of the first base matrix is ​​the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix. M, N, and P are all positive integers.

[0208] When the communication device 1900 is applied to the second device to execute the method performed by the second device, the input / output interface 1910 is used to acquire the second information. The logic circuit 1920 performs a lift and cyclic shift on the first base matrix according to the first lift dimension and the first offset value set corresponding to the first lift dimension to obtain a parity matrix; and decodes the second information according to the parity matrix to obtain the first information. Wherein, the offset values ​​corresponding to the first sub-region of the first base matrix and the offset values ​​corresponding to the second sub-region of the first base matrix satisfy a preset relationship. The first sub-region includes the third and fourth rows of the first column of the first region of the first base matrix, and / or the third and fourth rows of the second column of the first region of the first base matrix. The second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix. The first region of the first base matrix is ​​the first column to the Nth column and the first row to the Mth row of the first base matrix. The second region of the first base matrix is ​​the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix. M, N, and P are all positive integers.

[0209] The communication device in the above embodiments can be a terminal device or a network device, a circuit, a chip applied in a terminal device or network device, or other combined devices or components having the aforementioned terminal device or network device. When the communication device is a terminal device, the transceiver module can be a transceiver, which may include an antenna and radio frequency circuits, etc., and the processing module can be a processor, such as a CPU. When the communication device is a chip system, the communication device can be an FPGA, a dedicated ASIC, a SoC, a CPU, a network processor (NP), a DSP, a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips. The processing module can be the processor of the chip system. The transceiver module or communication interface can be the input / output interface or interface circuit of the chip system. For example, the interface circuit can be a code / data read / write interface circuit. The interface circuit can be used to receive code instructions (the code instructions are stored in memory and can be read directly from memory or through other devices) and transmit them to the processor; the processor can be used to run the code instructions to execute the methods in the above method embodiments. For example, the interface circuit can also be a signal transmission interface circuit between the communication processor and the transceiver.

[0210] This application also provides a communication system, which includes at least one terminal device and at least one network device. The terminal device is a first device for implementing the functions related to the above-described method, and the network device is a second device for implementing the functions related to the above-described method.

[0211] This application also provides a computer-readable storage medium including instructions that, when run on a computer, cause the method executed by the first device or the second device in the method shown in FIG11 to be executed.

[0212] This application also provides a computer program product, including computer program code, which, when executed, causes the method executed by the first device or the second device in the method shown in FIG11 to be executed.

[0213] This application provides a chip system including a processor and potentially a memory, for implementing the functions of the first or second device in the method shown in FIG11. The chip system can be composed of chips or may include chips and other discrete components.

[0214] To achieve the functions of the communication devices shown in Figures 17-19, this application embodiment also provides a chip, including a processor, for supporting the communication device in implementing the functions involved in the first or second device in the above method embodiments. In one possible design, the chip is connected to a memory or the chip includes a memory for storing necessary computer programs or instructions and data for the communication device.

[0215] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0216] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0217] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0218] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0219] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0220] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the essential contributing part of the technical solution of this application, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, external hard drives, ROM, RAM, magnetic disks, or optical disks.

[0221] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

An encoding method, characterized in that, include: The first base matrix is ​​lifted and cyclically shifted according to the first lifting size and the first offset value set corresponding to the first lifting size to obtain the parity check matrix; wherein... The offset values ​​corresponding to the first sub-region of the first base matrix in the first offset value set satisfy a preset relationship with the offset values ​​corresponding to the second sub-region of the first base matrix; the first sub-region includes: the third and fourth rows of the first column of the first region of the first base matrix, and / or, the third and fourth rows of the second column of the first region of the first base matrix; the second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix; the first region is the first column to the Nth column and the first row to the Mth row of the first base matrix, and the second region is the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix, where N, M, and P are all positive integers; The first information is encoded according to the verification matrix to obtain the second information; Output the second piece of information. The method as described in claim 1, characterized in that, The offset values ​​corresponding to the first sub-region and the offset values ​​corresponding to the second sub-region satisfy a preset relationship, including: r1 and r2 satisfy the constraints of a preset value, which is related to the second lift dimension. The second lift dimension belongs to the first lift dimension set where the first lift dimension is located. Both r1 and r2 are determined based on the offset value corresponding to the first sub-region, the offset value corresponding to the second sub-region, and the second lift dimension. The method as described in claim 2, characterized in that, The second lift size is the maximum value in the first lift size set. The method as described in claim 2 or 3, characterized in that, The value of r1 is determined based on a, b, e, f and the second lifting dimension, and the value of r2 is determined based on c, d, e, f and the second lifting dimension; wherein a is the offset value corresponding to the third row of the first column of the first region, b is the offset value corresponding to the fourth row of the first column of the first region, c is the offset value corresponding to the third row of the second column of the first region, d is the offset value corresponding to the fourth row of the second column of the first region, e is the offset value corresponding to the third row of the last column of the second region, and f is the offset value corresponding to the fourth row of the last column of the second region. The method as described in claim 4, characterized in that, ab-e+f=s1*Zm+r1;cd-e+f=s2*Zm+r2;where Zm is the second lifting dimension, and s1 and s2 are positive integers. The method as described in claim 5, characterized in that, Furthermore, |r1| or |r2| > g*Zm, where r1 and r2 are both positive or negative numbers, and g is a positive number less than or equal to 1 / 2; or, Furthermore, |r1-r2|>g*Zm, where r1 is a positive number, r2 is a negative number, and g is a positive number less than or equal to 1 / 2; or r1 is a negative number, r2 is a positive number, and g is a positive number less than or equal to 1 / 2. The method as described in any one of claims 1-6, characterized in that, The first offset value set is determined based on the second offset value set, which corresponds to the first lift dimension. The first offset value set includes a first offset value, and the second offset value set includes a second offset value. The difference between the first offset value and the second offset value is a multiple of 'a', where 'a' belongs to the first lift dimension set. The method as described in claim 7, characterized in that, The first offset value is the sum of the second offset value and at least one lift dimension in the first lift dimension set. The method as described in claim 8, characterized in that, Any one of the at least one lift dimension is greater than any other lift dimension in the first set of lift dimensions except for the at least one lift dimension. A decoding method, characterized in that, The method includes: Obtain the second information; The first base matrix is ​​lifted and cyclically shifted according to the first lifting size and the first offset value set corresponding to the first lifting size to obtain the parity matrix; wherein, the offset value corresponding to the first sub-region of the first base matrix in the first offset value set satisfies a preset relationship with the offset value corresponding to the second sub-region of the first base matrix; the first sub-region includes: the third and fourth rows of the first column of the first region of the first base matrix, and / or, the third and fourth rows of the second column of the first region of the first base matrix; the second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix; the first region is the first column to the Nth column and the first row to the Mth row of the first base matrix, and the second region is the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix, where N, M, and P are all positive integers; The second information is decoded according to the verification matrix to obtain the first information. The method as described in claim 10, characterized in that, The offset values ​​corresponding to the first sub-region and the offset values ​​corresponding to the second sub-region satisfy a preset relationship, including: r1 and r2 satisfy the constraints of a preset value, which is related to the second lift dimension. The second lift dimension belongs to the first lift dimension set where the first lift dimension is located. Both r1 and r2 are determined based on the offset value corresponding to the first sub-region, the offset value corresponding to the second sub-region, and the second lift dimension. The method as described in claim 11, characterized in that, The second lift size is the maximum value in the first lift size set. The method as described in claim 11 or 12, characterized in that, The value of r1 is determined based on a, b, e, f and the second lifting dimension, and the value of r2 is determined based on c, d, e, f and the second lifting dimension; wherein a is the offset value corresponding to the third row of the first column of the first region, b is the offset value corresponding to the fourth row of the first column of the first region, c is the offset value corresponding to the third row of the second column of the first region, d is the offset value corresponding to the fourth row of the second column of the first region, e is the offset value corresponding to the third row of the last column of the second region, and f is the offset value corresponding to the fourth row of the last column of the second region. The method as described in claim 13, characterized in that, ab-e+f=s1*Zm+r1;cd-e+f=s2*Zm+r2;where Zm is the second lifting dimension, and s1 and s2 are positive integers. The method as described in claim 14, characterized in that, Furthermore, |r1| or |r2| > g*Zm, where r1 and r2 are both positive or negative numbers, and g is a positive number less than or equal to 1 / 2; or, Furthermore, |r1-r2|>g*Zm, where r1 is a positive number, r2 is a negative number, and g is a positive number less than or equal to 1 / 2; or r1 is a negative number, r2 is a positive number, and g is a positive number less than or equal to 1 / 2. The method as described in any one of claims 10-15, characterized in that, The first set of offset values ​​is determined based on the second set of offset values, and the second set of offset values ​​corresponds to the first lifting dimension; Wherein, the first set of offset values ​​includes a first offset value, the second set of offset values ​​includes a second offset value, the difference between the first offset value and the second offset value is a multiple of a, and a belongs to the first set of lift dimensions in which the first lift dimension is located. The method as described in claim 16, characterized in that, The first offset value is the sum of the second offset value and at least one lift dimension in the first lift dimension set. The method as described in claim 17, characterized in that, Any one of the at least one lift dimension is greater than any other lift dimension in the first set of lift dimensions except for the at least one lift dimension. An encoding device, characterized in that, include: The processing unit is configured to perform lifting and cyclic shifting on the first base matrix according to the first lifting size and the first offset value set corresponding to the first lifting size to obtain a parity check matrix, and encode the first information according to the parity check matrix to obtain the second information; wherein, The offset values ​​corresponding to the first sub-region of the first base matrix in the first offset value set satisfy a preset relationship with the offset values ​​corresponding to the second sub-region of the first base matrix; the first sub-region includes: the third and fourth rows of the first column of the first region of the first base matrix, and / or, the third and fourth rows of the second column of the first region of the first base matrix; the second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix; the first region is the first column to the Nth column and the first row to the Mth row of the first base matrix, and the second region is the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix, where N, M, and P are all positive integers; The transceiver unit is used to output the second information. The apparatus as claimed in claim 19, characterized in that, The offset values ​​corresponding to the first sub-region and the offset values ​​corresponding to the second sub-region satisfy a preset relationship, including: r1 and r2 satisfy the constraints of a preset value, which is related to the second lift dimension. The second lift dimension belongs to the first lift dimension set where the first lift dimension is located. Both r1 and r2 are determined based on the offset value corresponding to the first sub-region, the offset value corresponding to the second sub-region, and the second lift dimension. The apparatus as claimed in claim 20, characterized in that, The second lift size is the maximum value in the first lift size set. The apparatus as claimed in claim 20 or 21, characterized in that, The value of r1 is determined based on a, b, e, f and the second lifting dimension, and the value of r2 is determined based on c, d, e, f and the second lifting dimension; wherein a is the offset value corresponding to the third row of the first column of the first region, b is the offset value corresponding to the fourth row of the first column of the first region, c is the offset value corresponding to the third row of the second column of the first region, d is the offset value corresponding to the fourth row of the second column of the first region, e is the offset value corresponding to the third row of the last column of the second region, and f is the offset value corresponding to the fourth row of the last column of the second region. The apparatus as claimed in claim 22, characterized in that, ab-e+f=s1*Zm+r1;cd-e+f=s2*Zm+r2;where Zm is the second lifting dimension, and s1 and s2 are positive integers. The apparatus as claimed in claim 23, characterized in that, Furthermore, |r1| or |r2| > g*Zm, where r1 and r2 are both positive or negative numbers, and g is a positive number less than or equal to 1 / 2; or, Furthermore, |r1-r2|>g*Zm, where r1 is a positive number, r2 is a negative number, and g is a positive number less than or equal to 1 / 2; or r1 is a negative number, r2 is a positive number, and g is a positive number less than or equal to 1 / 2. The apparatus as described in any one of claims 19-24, characterized in that, The first offset value set is determined based on the second offset value set, which corresponds to the first lift dimension. The first offset value set includes a first offset value, and the second offset value set includes a second offset value. The difference between the first offset value and the second offset value is a multiple of 'a', where 'a' belongs to the first lift dimension set. The apparatus as claimed in claim 25, characterized in that, The first offset value is the sum of the second offset value and at least one lift dimension in the first lift dimension set. The apparatus as claimed in claim 26, characterized in that, Any one of the at least one lift dimension is greater than any other lift dimension in the first set of lift dimensions except for the at least one lift dimension. A decoding device, characterized in that, include: The processing unit is configured to acquire second information, lift and cyclically shift a first base matrix according to a first lifting size and a first offset value set corresponding to the first lifting size to obtain a parity check matrix, and decode the second information according to the parity check matrix to obtain first information; Wherein, the offset values ​​corresponding to the first sub-region of the first base matrix in the first offset value set and the offset values ​​corresponding to the second sub-region of the first base matrix satisfy a preset relationship; the first sub-region includes: the third and fourth rows of the first column of the first region of the first base matrix, and / or, the third and fourth rows of the second column of the first region of the first base matrix; the second sub-region includes the third and fourth rows of the last column of the second region of the first base matrix; the first region is the first column to the Nth column and the first row to the Mth row of the first base matrix, and the second region is the (N+1)th column to the (N+P)th column and the first row to the Mth row of the first base matrix, where N, M, and P are all positive integers; A transceiver unit is used to receive the second information. The apparatus as claimed in claim 28, characterized in that, The offset values ​​corresponding to the first sub-region and the offset values ​​corresponding to the second sub-region satisfy a preset relationship, including: r1 and r2 satisfy the constraints of a preset value, which is related to the second lift dimension. The second lift dimension belongs to the first lift dimension set where the first lift dimension is located. Both r1 and r2 are determined based on the offset value corresponding to the first sub-region, the offset value corresponding to the second sub-region, and the second lift dimension. The apparatus as claimed in claim 29, characterized in that, The second lift size is the maximum value in the first lift size set. The apparatus as described in claim 29 or 30, characterized in that, The value of r1 is determined based on a, b, e, f and the second lifting dimension, and the value of r2 is determined based on c, d, e, f and the second lifting dimension; wherein a is the offset value corresponding to the third row of the first column of the first region, b is the offset value corresponding to the fourth row of the first column of the first region, c is the offset value corresponding to the third row of the second column of the first region, d is the offset value corresponding to the fourth row of the second column of the first region, e is the offset value corresponding to the third row of the last column of the second region, and f is the offset value corresponding to the fourth row of the last column of the second region. The apparatus as claimed in claim 31, characterized in that, ab-e+f=s1*Zm+r1;cd-e+f=s2*Zm+r2;where Zm is the second lifting dimension, and s1 and s2 are positive integers. The apparatus as claimed in claim 32, characterized in that, Furthermore, |r1| or |r2| > g*Zm, where r1 and r2 are both positive or negative numbers, and g is a positive number less than or equal to 1 / 2; or, Furthermore, |r1-r2|>g*Zm, where r1 is a positive number, r2 is a negative number, and g is a positive number less than or equal to 1 / 2; or r1 is a negative number, r2 is a positive number, and g is a positive number less than or equal to 1 / 2. The apparatus as described in any one of claims 28-33, characterized in that, The first set of offset values ​​is determined based on the second set of offset values, and the second set of offset values ​​corresponds to the first lifting dimension; Wherein, the first set of offset values ​​includes a first offset value, the second set of offset values ​​includes a second offset value, the difference between the first offset value and the second offset value is a multiple of a, and a belongs to the first set of lift dimensions in which the first lift dimension is located. The apparatus as claimed in claim 34, characterized in that, The first offset value is the sum of the second offset value and at least one lift dimension in the first lift dimension set. The apparatus as claimed in claim 35, characterized in that, Any one of the at least one lift dimension is greater than any other lift dimension in the first set of lift dimensions except for the at least one lift dimension. A communication device, characterized in that, The communication device includes at least one processor, the at least one processor being configured to cause the method of any one of claims 1-9 to be performed by the communication device, or the at least one processor being configured to cause the communication device to perform the method of any one of claims 10-18. A chip or chip system, characterized in that, The chip or chip system includes: At least one processor and an interface, the at least one processor being configured to call and execute instructions from the interface, wherein when the at least one processor executes the instructions, the method as claimed in any one of claims 1-9 is executed, or the method as claimed in any one of claims 10-18 is executed. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program or instructions that, when executed on a computer, cause the method as described in any one of claims 1-9 to be performed, or cause the method as described in any one of claims 10-18 to be performed. A computer program product, characterized in that, The computer program product includes one or more computer programs or instructions that, when read and executed by a computer, cause the computer to perform the method as described in any one of claims 1-9, or cause the computer to perform the method as described in any one of claims 10-18.

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