Conditionally clean ancilla qubits and generalized toggle detection for efficient quantum circuit constructions

Abstract

Methods, systems, and apparatus for conditionally clean ancilla qubits in quantum circuits. In one aspect a quantum computing device performs, conditioned on a control register of qubits being on, a target operation on a target register of qubits. For at least two repetitions a first CNOT operation is performed, where a first dirty ancilla qubit is the target and a first subset of control register qubits acts as a control. A second CNOT operation is performed, where a second dirty ancilla qubit is a target, and the first dirty ancilla qubit and a second subset of control register qubits acts as a control. The target operation is applied, conditioned on the second dirty ancilla qubit being on, and a third CNOT operation is performed, where the second dirty ancilla qubit is a target, and the first dirty ancilla qubit and second subset of control register qubits acts as a control.

Description

[0001] Attorney Docket No. 56113-0740WO1

[0002] CONDITIONALLY CLEAN ANCILLA QUBITS AND GENERALIZED TOGGLE DETECTION FOR EFFICIENT QUANTUM CIRCUIT CONSTRUCTIONS

[0003] BACKGROUND

[0004] This specification relates to quantum computing.

[0005] Classical computers have memories made up of bits, where each bit can represent either a zero or a one. Quantum computers maintain sequences of quantum bits, called qubits, where each quantum bit can represent a zero, one or any quantum superposition of zeros and ones. Quantum computers operate by setting qubits in an initial state and controlling the qubits, e.g., according to a sequence of quantum logic gates.

[0006] Ancilla qubits are additional qubits that are used to facilitate certain operations or calculations in a quantum computation, without being part of the input or output of the quantum computation. A clean ancilla qubit is a qubit that is initialized in a known state. A dirty ancilla qubit is a qubit that is not initialized in a known state. Ancilla qubits are often used as temporary workspace when decomposing an arbitrary' n-bit unitary operation into a sequence of gates from a target gate set that contains smaller 1 -qubit, 2-qubit, or 3-qubit unitary operations.

[0007] SUMMARY

[0008] This specification describes efficient quantum circuit constructions that use conditionally clean ancilla qubits and generalized toggle detection.

[0009] In general, one innovative aspect of the subject matter described in this specification can be implemented in a method performed by a quantum computing device, the method comprising: performing, conditioned on each qubit in a control register of qubits being in an on state, a target operation on a target register of one or more qubits, comprising, repeatedly for at least two repetitions: performing a first CNOT operation, wherein a first dirty ancilla qubit is a target for the first CNOT operation and each qubit in a first subset of qubits included in the control register acts as a control for the first CNOT operation; performing a second CNOT operation, wherein a second dirty ancilla qubit is a target for the second CNOT operation, each qubit in a second subset of qubits included in the control register acts as a control for the second CNOT operation, and the first dirty ancilla qubit acts as a control for the second CNOT operation; applying, conditioned on the second dirty ancilla qubit being in an on state, the target operation to the target register Attorney Docket No. 56113-0740WO1

[0010] of qubits; and performing a third CNOT operation, wherein the second dirty ancilla qubit is a target for the third CNOT operation, each qubit in the second subset of qubits included in the control register acts as a control for the third CNOT operation, and the first dirty ancilla qubit acts as a control for the third CNOT operation.

[0011] Other implementations of these aspects includes corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. A system of one or more classical and / or quantum computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0012] The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations the target operation comprises a self-inverse operator. In some implementations the first subset of qubits is different to the second subset of qubits. In some implementations the control register consists of a union of the first subset of qubits and the second subset of qubits.

[0013] In general, another innovative aspect of the subject matter described in this specification can be implemented in a method performed by a quantum computing device, the method comprising: performing an n-bit Toffoli gate on a target qubit and n control qubits in a control register using n — 2 dirty ancilla qubits in an ancilla register, comprising, repeatedly for at least two repetitions: performing a downward cascade of Toffoli gates, wherein each Toffoli gate in the downward cascade targets a respective first dirty ancilla qubit in the ancilla register and uses i) a respective second dirty ancilla qubit and ii) a respective control qubit in the control register as controls; performing a first Toffoli gate, wherein the target qubit is a target for the first Toffoli gate and i) a lowest dirty ancilla qubit in the ancilla register and ii) a lowest control qubit in the control register act as controls; performing an inverse of the downward cascade of Toffoli gates; and performing a second Toffoli gate, wherein i) a highest dirty ancilla qubit in the ancilla register is a target for the second Toffoli gate and ii) two highest control qubits in the control register act as controls.

[0014] Other implementations of these aspects includes corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, Attorney Docket No. 56113-0740WO1

[0015] each configured to perform the actions of the methods. A system of one or more classical and / or quantum computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0016] The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations the downward cascade of Toffoli gates comprises (n — 3) Toffoli gates. In some implementations qubits in each register are ordered, with increasing indices, from top to bottom such that a highest qubit in the register corresponds to a first qubit and a lowest qubit in the register corresponds to a last qubit in the register. In some implementations the ancilla register is positioned below the control register and the target qubit is positioned below the ancilla register. In some implementations each Toffoli gate in the downward cascade uses a respective control qubit that is (n — 2) qubits above the respective second dirty ancilla qubit. In some implementations a first Toffoli gate in the downward cascade of Toffoli gates targets a second highest dirty ancilla qubit, uses a highest dirty ancilla qubit as a control, and uses a third highest control qubit as a control. In some implementations a last Toffoli gate in the downward cascade of Toffoli gates targets a lowest dirty ancilla qubit, uses a second low est dirty ancilla qubit as a control, and uses a second lowest control qubit as a control. In some implementations each Toffoli gate in the downward cascade uses a respective second dirty ancilla qubit that is directly above the respective first dirty ancilla qubit as a control.

[0017] In general, another innovative aspect of the subject matter described in this specification can be implemented in a method performed by a quantum computing device for accumulating an AND of the state of multiple qubits, the method comprising: assigning, to an array of n+1 elements, a clean ancilla qubit at index i — 0 and n system qubits respective indices i = 1,... n; initializing elements in the array, comprising setting an element that corresponds to index i = 0 as marked and setting remaining elements in the array as unmarked; performing a sequence of operations until the array comprises a minimum number of unmarked elements, comprising, at each step in the sequence of operations: labelling each qubit assigned to an index i in the array that corresponds to a marked element as a conditionally clean ancilla qubit; selecting indices t, x, y in the array such that an element that Attorney Docket No. 56113-0740WO1

[0018] corresponds to index t is marked and elements that correspond to indices x and y are unmarked, wherein the indices satisfy t < x < y; and computing an AND of elements that correspond to indices x and y and saving a result of the AND in an element that corresponds to index t, comprising: determining whether a qubit assigned to the index t is a conditionally clean ancilla qubit; in response to determining that the qubit assigned to the index t is a conditionally clean ancilla qubit, applying a Toffoli gate to qubits assigned to indices x, y, and t, wherein the qubit assigned to index t acts as a target qubit, and applying an X gate to the qubit assigned to index t.

[0019] Other implementations of these aspects includes corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. A system of one or more classical and / or quantum computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0020] The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations the method further comprises in response to determining that the qubit assigned to the index t is not a conditionally clean ancilla qubit, determining whether the qubit assigned to the index t is a clean ancilla qubit; and in response to determining that the qubit assigned to the index t is a clean ancilla qubit, applying an AND gate to qubits assigned to indices x, y, and t.

[0021] In some implementations computing the AND of elements that correspond to indices x and y and saving the result of the AND in the element that corresponds to index t assigns qubits that correspond to indices x and y as conditionally clean qubits and assigns the qubit that corresponds to index t as a system qubit.

[0022] In some implementations at each step in the sequence of operations, a conditionally clean qubit assigned an index t is clean conditioned on a first set of system qubits and is used as temporary workspace to store results of computations for a second set of system qubits, wherein the first and second set are disjoint.

[0023] In general, another innovative aspect of the subject matter described in this specification can be implemented in a method performed by a quantum computing device for performing an n-bit Toffoli gate on a target qubit using a control register of control qubits, Attorney Docket No. 56113-0740WO1

[0024] the method comprising: obtaining an ancilla qubit; performing a first Toffoli gate, wherein the ancilla qubit is the target for the first Toffoli gate and a first and second control qubit are controls for the first Toffoli gate; performing a first ladder of Toffoli gates on control qubits in the control register to accumulate n control values on controls using conditionally clean

[0025]

[0026] ancilla qubits; applying NOT gates to a subset of the control qubits; performing a second ladder of Toffoli gates on control qubits in the control register to accumulate an AND of all controls on the first control qubit, wherein the first control qubit stores the accumulated AND as a conditionally clean ancilla qubit; performing a second Toffoli gate, wherein the target qubit is the target for the second Toffoli gate, the first control qubit acts as a control and the ancilla qubit acts as a control; and un-computing the second ladder of Toffoli gates, the NOT gates, the first ladder of Toffoli gates, and the first Toffoli gate to return intermediate conditionally clean ancilla qubits to their original states.

[0027] Other implementations of these aspects includes corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. A system of one or more classical and / or quantum computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0028] The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations a first Toffoli gate in the first ladder of Toffoli gates is applied between a second, third, and fourth control qubit, wherein the second control qubit is the target. In some implementations subsequent Toffoli gates in the first ladder of Toffoli gates are applied to consecutive control qubits, wherein a last control for a previous Toffoli gate is a target for a next Toffoli gate. In some implementations the first ladder comprises an upwards ladder with consecutive Toffoli gates that are applied to control qubits with increasing indices in the control register.

[0029] In some implementations the second ladder comprises a downwards ladder with consecutive Toffoli gates that are applied to control qubits with decreasing indices in the control register. In some implementations the subset of control qubits comprises control qubits used as targets in the first ladder and second ladder of Toffoli gates. Attorney Docket No. 56113-0740WO1

[0030] In some implementations the second ladder of Toffoli gates comprises n — — 2

[0031]

[0032] Toffoli gates. In some implementations the second Toffoli gate applies an n-qubit CnX gate to the target qubit. In some implementations un-computing the second ladder of Toffoli gates and the first ladder of Toffoli gates comprises: performing an inverse of the second ladder of Toffoli gates; applying the NOT gates to the subset of the control qubits; performing an inverse of the first ladder of Toffoli gates; and performing the first Toffoli gate.

[0033] In some implementations the obtained ancilla qubit is a clean ancilla qubit and performing the n-bit Toffoli gate requires 2n-3 Toffoli gates.

[0034] In some implementations the obtained ancilla qubit is a dirty ancilla qubit, and the method further comprises: performing the first ladder of Toffoli gates on the control qubits in the control register; applying the NOT gates to the subset of the control qubits; performing the second ladder of Toffoli gates on the control qubits in the control register; performing the second Toffoli gate, wherein the target qubit is the target for the second Toffoli gate, the first control qubit acts as a control and the ancilla qubit acts as a control; and un-computing the second ladder of Toffoli gates, the NOT gates, and the first ladder of Toffoli gates.

[0035] In some implementations the first ladder of Toffoli gates and the second ladder of Toffoli gates each comprise n-3 Toffoli gates.

[0036] In general, another innovative aspect of the subject matter described in this specification can be implemented in a method performed by a quantum computing device for performing an n-bit Toffoli gate on a target qubit using a control register of control qubits, the method comprising: obtaining a first ancilla qubit and a second ancilla qubit; performing a first Toffoli gate, wherein the first ancilla qubit is the target for the first Toffoli gate and a first and second control qubit are controls for the first Toffoli gate; performing a ladder of Toffoli gates on control qubits in the control register to accumulate an AND of n — 2 control qubits on log n qubits using conditionally clean ancilla qubits; performing, using the second clean ancilla qubit, a multi-bit Toffoli gate to accumulate an AND of all n bit of the n-bit Toffoli on the target qubit; and un-computing the ladder of Toffoli gates and the first Toffoli gate.

[0037] Other implementations of these aspects includes corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. A system of one or more classical and / or quantum computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system that in Attorney Docket No. 56113-0740WO1

[0038] operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0039] The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations the first ancilla qubit is positioned below the control register of control qubits and the target qubit is positioned above the control register of control qubits. In some implementations the ladder of Toffoli gates comprises n-log n-2 Toffoli gates. In some implementations the multi-bit Toffoli gate comprises a (log n + 1)-bit Toffoli gate. In some implementations the ladder of Toffoli gates comprises multiple instances of a depth-2 circuit primitive that applies NOT gates to each of n conditionally clean ancilla qubits and, after application of the NOT gates, applies n Toffoli gates in parallel.

[0040] In some implementations at an i-th layer of Toffoli gates in the ladder of Toffoli gates, an upmost control qubit of 2lcontrol qubits in a one state is used as a target qubit and a remaining 2i— 1 control qubits of the 2icontrol qubits are conditionally clean ancilla qubits that are used as a temporary workspace to flip a state of a next 21+ 1 control qubits through application of i consecutive Toffoli gates with parameters (2k, 2k + 1, k), where k represents an index in the control register.

[0041] In some implementations performing the n-bit Toffoli gate comprises executing a quantum circuit with depth log n. In some implementations un-computing the ladder of Toffoli gates and the first Toffoli gate comprises: performing an inverse of the ladder of Toffoli gates; and applying the first Toffoli gate.

[0042] In some implementations the first ancilla qubit and the second ancilla qubit comprise clean ancilla qubits, and wherein performing the n-bit Toffoli gate requires 2n-3 Toffoli gates.

[0043] In some implementations the first ancilla qubit and the second ancilla qubit comprise dirty ancilla qubits, wherein the method further comprises performing the ladder of Toffoli gates on the control qubits in the control register; performing, using the second clean ancilla qubit, the multi-bit Toffoli gate; and un-computing the ladder of Toffoli gates.

[0044] In some implementations performing the n-bit Toffoli gate requires 4n-8 Toffoli gates. In some implementations performing the multi-bit Toffoli gate to accumulate an AND of all n bit of the n-bit Toffoli on the target qubit comprises applying generalized toggle Attorney Docket No. 56113-0740WO1

[0045] detection. In some implementations the multi-bit Toffoli comprises a (n-l)-bit Toffoli gate and applying generalized toggle detection decomposes the (n-l)-bit Toffoli gate into 2n-5 Toffoli gates using the second ancilla qubit.

[0046] The subject matter described in this specification can be implemented in particular ways so as to realize one or more of the following advantages.

[0047] Clean (or dirty) ancilla qubits are often used as temporary workspace when decomposing an arbitrary n-bit quantum gate into a sequence of gates from a target gate set that contains smaller quantum gates, e.g., single, two-qubit, or three-qubit quantum gates. When evaluating the efficiency of a gate decomposition, there are three main factors to consider - the number of additional ancilla qubits used as temporary workspace, the number of costly gates in the decomposition, and the depth of the decomposed circuit.

[0048] When optimizing quantum circuits, e.g., for surface code architectures in the fault tolerant regime, the target gate set is typically the Clifford + T / Toffoli gate set. The cost of decomposing an arbitrary' n-bit unitary operation using this target gate set is dominated by the number of T / Toffoli gates, which are significantly more expensive to execute compared to Clifford gates. Typically, there is a tradeoff where the number of T / Toffoli gates in the decomposition can be reduced by using a greater number of ancilla qubits as temporary workspace.

[0049] The present disclosure describes a technique that enables certain system qubits to be temporarily used as clean ancilla qubits when conditioned on a subset of other system qubits, referred to herein as conditionally clean ancilla qubits. This technique is applied to generate new optimized quantum circuit constructions for n-qubit quantum gates such as n-qubit Toffoli gates and n-qubit Incrementer circuits in the low ancilla usage regime. The quantum circuit constructions have lower Toffoli gate counts and circuit depth when compared to previously best known constructions in the regime of sub-linear ancilla usage. Lowering Toffoli gate counts and circuit depth can increase the efficiency of the quantum computer on which the quantum circuit is implemented. Moreover, an optimized and / or efficient quantum circuit construction can help to reduce the degree of decoherence introduced to quantum states during operation of the quantum circuit, thus increasing reliability and accuracy.

[0050] The quantum circuit constructions include optimized decompositions for

[0051] (a) an n-bit Toffoli into 2n - 3 Toffoli and O(n) depth using 1 clean ancilla qubit. (b) an n-bit Toffoli into 2n - 3 Toffoli and O(log n) depth using 2 clean ancilla qubits. (c) an n-bit Toffoli into 4n - 7 Toffoli and O(n) depth using 1 dirty ancilla qubit, and Attorney Docket No. 56113-0740WO1

[0052] (d) an n-bit Incrementer into 3n Toffoli and O(n) depth using log2 n(< 5) clean ancilla qubits.

[0053] The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0054] BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts an example quantum computation system.

[0055] FIG. 2A is a circuit diagram that shows an example conditionally clean ancilla qubit. FIG. 2B and FIG. 2C are circuit diagrams that show example conditionally clean ancilla qubits conditioned over multiple control bits.

[0056] FIG. 3A is a circuit diagram that shows an example application of toggle detection to substitute a single clean ancilla qubit with a dirty7ancilla qubit.

[0057] FIG. 3B is a circuit diagram that shows an example implementation of generalized toggle detection.

[0058] FIG. 3C is a circuit diagram that shows an implementation of generalized toggle detection for decomposing an n-bit Toffoli gate into Toffoli gates using borrowed qubits.

[0059] FIG. 4 A is a circuit diagram of a decomposition of an n-bit Toffoli gate into 2n — 3 Toffoli gates using one clean ancilla qubit.

[0060] FIG. 4B is another circuit diagram of a decomposition of an n-bit Toffoli gate into 2n — 3 Toffoli gates using one clean ancilla qubit.

[0061] FIG. 5A is a circuit diagram of a circuit primitive that toggles n conditionally clean ancilla qubits and applies n Toffoli gates in parallel.

[0062] FIG. 5B is a circuit diagram of a decomposition of an n-bit Toffoli gate into 2n — 3 = 15 Toffoli gates using two clean ancilla qubits, where n = 9.

[0063] FIG. 5C is a circuit diagram of a decomposition of n-qubit Toffoli into 2n - 3 Toffoli and O(log n) depth using 2 clean ancilla qubits, where n = 32.

[0064] FIG. 6 is a circuit diagram of a decomposition of n-qubit Toffoli into 4n - 7 Toffoli and O(n) depth using one dirty7ancilla.

[0065] FIG. 7 is a circuit diagram of an example decomposition of n-qubit Toffoli gate into

[0066]

[0067] Attorney Docket No. 56113-0740WO1

[0068] FIG. 8A shows a naive decomposition of an Incrementer gate into n different MCX gates.

[0069] FIG. 8B is a circuit diagram of an example decomposition of an n-qubit Incrementer into 3n Toffoli and 0(n) depth using log2n clean ancilla qubits.

[0070] FIG. 9A is a circuit diagram that reduces the classical-quantum comparison to consuming a ladder of suffix ANDs.

[0071] FIG. 9B is a circuit diagram of an example decomposition of a n-qubit LessThanConst gate.

[0072] FIG. 10 is a flow diagram of an example process for performing, conditioned on each qubit in a control register of qubits being in an on state, a target operation on a target register of one or more qubits.

[0073] FIG. 11 is a flow diagram of an example process for performing an n-bit Toffoli gate on a target qubit and

[0074] FIG. 12 is a flow diagram of an example process for accumulating an AND of multiple qubits, n control qubits in a control register using n-2 dirty ancilla qubits in an ancilla register.

[0075] FIGS. 13-14 are flow diagrams of example processes for performing an n-bit Toffoli gate on a target qubit using a control register of control qubits.

[0076] FIGS. 15A-E show how a conventional unary iteration circuit can be viewed as a tree traversal of a balanced binary tree.

[0077] FIGS. 16A-D shows optimized unary iteration circuit elements using skew trees. Like reference numbers and designations in the various draw ings indicate like elements.

[0078] DETAILED DESCRIPTION

[0079] This specification describes efficient quantum circuit compilations that use conditionally clean ancilla qubits and generalized toggle detection. In the present disclosure, a clean ancilla qubit is a qubit that is initialized in a known state, typically a O-state, and can be discarded or reused after a computation. A clean ancilla qubit has the following properties: expensive allocation since dedicated qubits need to be allocated as clean ancilla qubits, which adds space overhead, cheap consumption since the initial state is known, so any intermediate result stored on the clean ancilla qubit can be consumed directly via a single controlled unitary, and cheap uncomputations since measurement-based un-computation whereby a clean ancilla that is entangled with other qubits can be disentangled and returned Attorney Docket No. 56113-0740WO1

[0080] to the 0-state by measuring in the X basis and applying classically controlled phase corrections can be used.

[0081] A dirty ancilla qubit is a qubit that is in an unknown, arbitrary state and can be temporarily perturbed but must be restored eventually. A dirty7ancilla qubit has the following properties: cheap allocation since any system qubit that is not part of the computation can be borrowed and used as a dirty ancilla qubit, expensive consumption since the initial state is unknown so toggle detection is used to consume the intermediate result which increases gate count, and expensive uncomputations since the dirty ancilla must be returned to its original unknown states, so measurement based un-computation cannot be used.

[0082] A conditionally clean ancilla qubit is a qubit in an unknown initial state which, when given a specific condition on one or more other qubits, e.g., one or more other qubits being ON, is guaranteed to be in a known state (e.g., a 0- or 1 -state). This enables a conditionally clean ancilla qubit, w hich is strictly speaking a dirty ancilla qubit, to be treated as if it were a clean ancilla in many situations whilst avoiding the overhead associated with fully dirty ancilla qubits. Conditionally clean ancilla qubits have the following properties: cheap allocation since system qubits that satisfy certain criteria can be borrowed and used, cheap consumption since the initial state is conditionally know n to that intermediate results can be consumed without the need of toggle detection, and expensive un-computation since conditionally clean ancilla qubits must be returned to its original unknown state and therefore measurement-based uncomputations cannot be used. Conditionally clean ancilla qubits are formally defined below with reference to FIGS. 2A-C.

[0083] Generalized toggle detection is a technique in which a dirty ancilla qubit is substituted in the place of a clean ancilla qubit in a quantum circuit, without incurring an exponential circuit depth overhead.

[0084] The efficient quantum circuit constructions include circuits for decomposing n-qubit Toffoli gates, n-qubit incrementers, and n-qubit less-than-constant in the low ancilla usage regime. The optimized quantum circuit constructions achieve lower Toffoli gate counts and circuit depth when compared to previously best known constructions in the regime of sublinear ancilla usage. As discussed above, lowering Toffoli gate counts and circuit depth may increase the efficiency of the quantum computer on w hich the quantum circuit is implemented. Moreover, an optimized and / or efficient quantum circuit construction may help to reduce the degree of decoherence introduced to quantum states during operation of the quantum circuit, thus increasing reliability and accuracy. Attorney Docket No. 56113-0740WO1

[0085] FIG. 1 depicts an example quantum computation system 100. The example system 100 is an example of a system implemented as part of a quantum computing device in which the systems, components and techniques described in this specification can be implemented.

[0086] The system 100 includes a control processor 102, control electronics 104, and a quantum data plane 106. Although not shown in FIG. 1, in some implementations the example system can also include a classical computer that is in data communication with the control processor plane and facilitates user interactions and access to networks or storage. In some implementations, some or all of the components of the example system 100 can be directly connected. In other implementations, some or all of the components of the example system 100 can be connected through a network, e.g.. a local area network (LAN), wide area network (WAN), the Internet, or a combination thereof.

[0087] The control processor 102 is a classical processor that can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of. a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits, or a combination of one or more of them.

[0088] The control processor 102 is configured to generate quantum circuit compilations for arbitrary n-qubit operations including, e.g., the n-qubit Toffoli gates, n-qubit incrementers. and other operations described in this specification. The compilations decompose the respective operations into sequences of quantum gates from a target gate set that contains smaller qubit operations, e.g., single qubit gates, two-qubit gates, and three-qubit gates. For example, the target gate set can be a Clifford + T / Toffoli universal gate set that includes the Hadamard gate, Pauli X gate (also referred to as a NOT gate), Pauli Y gate, Pauli Z gate, phase gate, CNOT gate, and the Toffoli gate, which is a three-qubit gate that flips the state of a target qubit based on the states of two control qubits (which can be decomposed into a sequence of simpler gates using a non-Clifford T gate).

[0089] The quantum circuit compilations generated by the control processor 102 are optimized quantum circuit compilations that reduce the number of Toffoli gates (or, equivalently the number of T gates) and additional ancilla qubits required by the quantum circuits, e.g., compared to known quantum circuit constructions.

[0090] To generate the optimized quantum circuit compilations, the control processor 102 is configured to identify instances in an initial quantum circuit compilation, e.g., a known Attorney Docket No. 56113-0740WO1

[0091] quantum circuit compilation, where system qubits, e.g., control qubits, can be temporarily utilized as clean ancilla qubits when conditioned on a subset of other system qubits. Such system qubits are referred to as conditionally clean ancilla qubits. The control processor 102 can then generate a quantum circuit compilation that uses such conditionally clean ancilla qubits, instead of having to introduce additional ancilla qubits to the compilation. Example instances of conditionally clean ancilla qubits are described below with reference to FIGS.

[0092] 2A-C.

[0093] In addition, the control processor 102 is configured to identify instances in an initial quantum circuit compilation where so-called generalized toggle detection can be applied to substitute a dirty ancilla qubit in the place of a clean ancilla qubit. An example quantum circuit construction for applying generalized toggle detection is described below with reference to FIGS. 3A-C.

[0094] The control processor 102 is configured to provide data representing optimized quantum circuits to the control electronics 104. The control electronics 104 is configured to convert data received from the control processor 102, e.g., digital signals representing optimized quantum circuits, to analog driving signals 114 (also referred to herein as control signals) required to perform gates and operations included in the optimized quantum circuits on qubits included in the quantum data plane 106.

[0095] For example, the control electronics 104 can include control devices that operate physical qubits included in the quantum data plane 106. Example control devices include arbitrary waveform generators or control devices that tune frequencies of respective qubits by applying driving signals, e.g., voltage pulses, to the qubits through respective control lines, as well as measurement devices that perform physical measurements on properties of the qubits, either directly or indirectly, from which the state(s) of the qubits can be inferred, e.g., readout resonators. A plurality of control lines may be coupled to a register of qubits within the quantum computing device. This may allow operation on the qubits within the register of qubits (the register of qubits is sometimes also called the system register). Measurement results obtained via measurement devices may be provided to the control process 102 for processing and analyzing. The control electronics may include a plurality of control devices. The control devices may include a plurality of control circuits that are coupled to the plurality of control lines.

[0096] In some implementations the control electronics 104 can include a memory 112 that is configured to store data, e.g., data specifying pre-defined optimized quantum circuits and corresponding control pulses generated by the control processor 102. Attorney Docket No. 56113-0740WO1

[0097] The quantum data plane 106 includes physical qubits for performing quantum computations, e.g.. the various quantum circuits and operations described in this specification. The type of qubits that the quantum data plane 106 utilizes is dependent on the types of computations being performed by the system 100. For example, in some cases the quantum data plane 106 can include one or more resonators attached to one or more superconducting qubits, e.g.. Gmon or Xmon qubits. In other cases the quantum data plane 106 can include ion traps, photonic devices or superconducting cavities, which may serve as qubits. Further examples of realizations of qubits include fluxmon qubits, silicon quantum dots or phosphorus impurity qubits. In some cases the qubits may be a part of a quantum circuit.

[0098] Example operations performed by components of the system 100 are described in more detail below with reference to FIGS. 2-15.

[0099] Conditionally clean ancilla qubits

[0100] FIGS. 2A-C show example instances and utilizations of conditionally clean ancilla qubits. As discussed above, clean ancilla qubit is a qubit that is initially guaranteed to be in a O-state and, after the qubit has been used as an ancilla qubit in an operation, must be uncomputed so that the qubit returns to the O-state when the operation is finished. Clean ancilla qubits are useful as temporary workspaces to store intermediate results and decompose multiqubit operations into smaller operations.

[0101] A conditionally clean ancilla qubit can be defined as follows. Let C be a set of control qubits in a quantum arbitrary state \ V)Cand let |x)cbe a state on a control register that satisfies a predicate P. An ancilla qubit |ccu) is a conditionally clean ancilla with respect to the predicate P if. when P is True, the ancilla qubit |ccu) is in a known classical state | / (x)>. In other words, the combined state of the control register \l)cand ancilla register \cca)Pcan be written as

[0102] |¥0ckca> P = a

[0103]

[0104] x\x}c\f(x)} + ax±|x±)c

[0105] where |x)crepresents the control state that satisfies predicate P,

[0106]

[0107] is the perpendicular control state that does not satisfy the predicate P, | / (x)) is a known classical state and I’ tyA A is an arbitrary quantum state. Attorney Docket No. 56113-0740WO1

[0108] It can be seen that any controlled operation CUP S— Us| x){x | + Is\x1){x1| (meaning U is applied if and only if P is true), the conditionally clean qubit |cca) can be used as a clean qubit to act as a temporary workspace. This is because in the subspace where P is True and U is applied, |cca) has a known classical state | (x)) and thus any intermediate results stored on |cca) can be consumed without toggle detection.

[0109] A key example is based on the quantum implementation of the AND gate using a Toffoli gate. A Toffoli gate has two control qubits (c1;c2) and a target qubit (t). The Toffoli gate flips the target if and only if both controls are in the state |1). Consider two qubits, and c2. in an unknow n superposition of states, and a clean ancilla t initialized to |0).

[0110] Application of a Toffoli gate: Toffed^, c2, t) gives

[0111] Toffoli(c1, c2, t)|^}cily)C2|0)t = Mcliy)c2ix Ay)t

[0112] In the situation that the target qubit t is conditioned on being measured in the 11) state (i.e., (Zt) = — 1), if t = 11 ), then it is known that both c1and c2must be in the 11 ) state. Even though and c2might have been in a superposition, within the subspace where t = 11 ), they behave exactly as if they were clean ancillae initialized to |1). Therefore. and c2are conditionally clean, with the condition being (Zt) = — 1, and any computation that does nothing when Zt) =# —lean be compiled as if c±and c2happened to be 1).

[0113] In general, let f: {0, l}n-> {0, l}mbe any function and let Uf be a unitary operator that computes the below function on a clean ancilla register of qubits of size m:

[0114] uf

[0115] |

[0116]

[0117] x)n|0)m4 |x)" | / (x))m.

[0118] If there exists a pair (%, / (%)) such that x is the only element in the domain of f that maps to / (x), then conditioned on the ancilla register being in the state / (%), it is known that the system register would be in the state x. Therefore, the system register can be used as a conditionally clean register that is allocated in a known state x. It can be used as a temporary workspace to store intermediate computation results, assuming those results will be consumed conditioned on the ancilla being in state / (x), before the intermediate computation is un-computed to restore the state of the system register to be the known state x. The system register in this case acts as a register of so-called “conditionally clean” ancilla qubits. Attorney Docket No. 56113-0740WO1

[0119] With this in mind, there are two conditions required to be able to use system qubits in a computation as conditionally clean ancilla qubits. First, at least one clean ancilla qubit must be consumed to compute a function (%) that has a unique inverse x such that, conditioned on the ancilla register being in the state (%), it is known that the system register is in the state x and thus can be used as conditionally clean ancilla qubits to store intermediate results of subsequent computations. Second, any subsequent computation that uses the system register x as conditionally clean qubits to store intermediate results must consume these results conditioned on the ancilla register being in the state (%). That is, let g(y) be the result of the computation that uses register x as a temporary workspace. Then, f x)&.g(y) must be consumed as the final output.

[0120] An example application of conditionally clean ancilla qubits is the use case w here a ladder of AND gates is computed. In this example, the function f is an AND operation and the pair (x = {l}n, (%) = 1) satisfies the conditions defined above. Note that AND operation also distributes such that f(x, y) = f x)&f(y) and therefore (%) can be computed on a temporary qubit and the register x can be used as a register of conditionally clean ancilla qubits to store the result of computing f(y), which is then consumed conditioned on the ancilla qubit being in the state (%) such that the final consumed output is

[0121]

[0122] FIG. 2A is a circuit diagram 200 that show's an example conditionally clean ancilla qubit. In this example, three qubits cO, cl, and ancilla qubit “anc” are initialized in a zero state 10). A Hadamard gate is applied to qubit cO and qubit cl. A Toffoli gate (also referred to in the art as a CCX gate) is applied to the three qubits, where the target qubit is the ancilla qubit “anc” and qubits cO and cl act as controls. As shown, after application of the Hadamard gates and Toffoli gate and given the zero state initialization, if the ancilla qubit “anc” is set (is in a one state) this indicates that the X operation in the Toffoli gate was applied to the ancilla qubit since its state has flipped from zero to one. This, in turn, indicates that both controls in the Toffoli gate were in a known state -“on”.

[0123] In other words, conditioned on the ancilla qubit “anc” being set, the two qubits cO and cl are conditionally clean. These conditionally clean ancillas can be therefore be consumed from outside the sub-circuit in which the qubit is conditioned from, as shown in FIG. 2B.

[0124] FIG. 2B is a circuit diagram 220 that shows example conditionally clean ancilla qubits conditioned over multiple control bits. In step-1, one of the conditionally clean ancilla qubits from FIG. 2A (qubit cl) is consumed in step-2 to produce two more doubly-conditioned Attorney Docket No. 56113-0740WO1

[0125] clean ancilla qubits (qubits c2 and c3). Step-3 shows how the Toffoli gate 232 (which is applied to qubits “trgt”, “anc”. and cl) is equivalent to applying C4X gate (a four-controlled X gate) 234 (which is applied to qubits cO, cl, c2, c3, '‘trgt”) since the qubit “anc” stores cO A cl and conditioned on the ancilla qubit ‘'anc” being True, i.e. cl = True, cl stores c2 A c3.

[0126] Another property of conditionally clean ancilla qubits is that they cannot be used as temporary workspace for computations that involve the control qubits which the conditionally clean ancilla is conditioned on. FIG. 2C is another circuit diagram 230 that shows example conditionally clean ancilla qubits conditioned over multiple control bits. In this example, the staggered pattern continues such that n controls are accumulated on n / 2 controls using only 1 ancilla by step-3. Step-4 shows how conditionally clean ancilla can only be consumed in computations that do not involve the control qubits which the ancilla is conditioned on. To accumulate the result of open controls c3 A cl, only cO can be used as a conditionally clean ancilla since c2, c4 and c5 are all conditionally clean conditioned on cl and therefore cannot be used as temporary workspace for computations involving cl.

[0127] Generalized toggle detection

[0128] FIGS. 3A-C shows how generalized toggle detection can be used to substitute multiple clean ancilla qubits with dirty ancilla qubits with a single round of toggle detection.

[0129] When implementing a controlled version of a self-inverse operation U (e.g., an operator that satisfies U2= H) the use of a clean ancilla qubit can be replaced with a dirty ancilla qubit by repeating the self-inverse controlled operation twice. If the control is “True” and the dirty ancilla flips, the self-inverse of the controlled unitary C — U is applied on both the branches |0) and 11) of the dirty ancilla. If the control is “False”. C — U gets applied twice on the 11) branch and zero times on the |0) branch, effectively applying an identity operation. This technique of substituting a dirty ancilla in the place of a clean ancilla is referred to as “toggle detection.”

[0130] FIG. 3A is a circuit diagram 300 that shows an example application of toggle detection to substitute a single clean ancilla qubit with a dirty ancilla qubit. To perform controlled unitary operator 302 on m target qubits “target”, where n control qubits “ctrl” act as controls, a clean ancilla qubit (prepared in a zero state) can be used. The circuit then includes a CNOT gate applied to the clean ancilla qubit, where the control qubits act as controls, an application of the unitary operator to the target qubit, where the clean ancilla Attorney Docket No. 56113-0740WO1

[0131] qubit acts as a control, and another instance of the CNOT gate so that the state of the clean ancilla qubit returns to its original state. This circuit construction is shown in (i) of FIG. 3 A.

[0132] Alternatively, dirty ancilla qubits (prepared in some unknown state ip) can be used, as shown in circuits (ii) and (iii). In these implementations, an additional application of the unitary operator to the target qubit, where the dirty ancilla qubit acts as a control, is required (either after the second CNOT gate in circuit (i) or before the first CNOT gate in circuit (i)).

[0133] If the implementation of the controlled unitary C — U further borrows a clean ancilla qubit that is to be replaced with a di rty ancilla qubit, a naive strategy w ould be to recursively repeat toggle detection as described above. However, every time toggle detection is applied, a 2x overhead is incurred since C- U is applied twice. Therefore, to replace n clean ancillas with n dirty ancillas, an overhead that scales exponentially as 2” can be incurred.

[0134] However, if the subsequent borrowed dirty ancillas are different from the control qubits used for toggle detection, the borrowed dirty7ancillas can be used as clean ancillas and therefore the incurred 2x overhead can be avoided for each subsequent clean ancilla replaced by a dirty ancilla. This construction is referred to herein as "generalized toggle detection.’7FIG. 3B is a circuit diagram 310 that shows an example implementation of generalized toggle detection, where subsequent dirty7ancilla qubits can be treated as clean ancilla qubits using toggle detection. As shown, by applying the circuit constructions described above with reference to FIG. 3A, the controlled unitary operation can be applied by treating the control register of qubits as tw o registers of ntand n2control qubits and using two dirty ancilla qubits ip and cp. The circuit includes a first CNOT gate 312 that is applied to the first dirty ancilla qubit, where the first control register of control qubits act as controls. The circuit then includes a Toffoli gate 314 that targets the second dirty ancilla qubit and uses the first ancilla qubit and second control register as controls. The circuit then include an application of the unitary operator to the target qubit, w here the second dirty ancilla qubit acts as a control, and another instance of the Toffoli gate 318. The gates 312-318 are then repeated. It is noted that for this circuit compilation, the decomposition of the controlled unitary C — U should not use the ctrl|O] qubits from the top of the register as dirty ancilla qubits.

[0135] All circuit constructions presented below that use clean ancilla qubits can be updated to use dirty ancilla qubits with a 2x Toffoli overhead using Generalized Toggle Detection.

[0136] FIG. 3C is a circuit diagram 330 that shows an implementation of generalized toggle detection for decomposing an n-bit Toffoli gate into 4n — 8 Toffoli using n — 2 borrowed Attorney Docket No. 56113-0740WO1

[0137] qubits. For clarity, the circuit shown in FIG. 3C implements an n = 4 Toffoli gate.

[0138] However, the same technique can be applied to larger or smaller sized Toffoli gates. The circuit shown in FIG. 3C has the same cost as some other circuits for decomposing an n-bit Toffoli gate into Toffoli gates, but has a different structure (the arrows defined by the Toffoli gates in each repetition point towards the target qubit). In some implementations it can be preferable to implement the circuit shown in FIG. 3C. e g., when the underlying qubit connectivity supports the circuit.

[0139] Conditionally clean ancilla qubits and generalized toggle detection for n-qubit Toffoli

[0140]

[0141] circuits An n-qubit Toffoli gate is a generalization of the standard three-qubit Toffoli gate with n control qubits and one target qubit. Application of an n-qubit Tofofli gate flips the state of the target qubit if and only if all n control qubits are in an on-state (1 state). Similar to the three-qubit Toffoli gate, the n-qubit Toffoli gate can be decomposed into a sequence of simpler gates. Decompositions typically use ancilla qubits to manage intermediate states of the control qubits and target qubit, e.g., to store intermediate results of the controlled operations, and sequences of three-qubit Toffoli gates and other controlled gates to gradually combine the control conditions until the target qubit is finally controlled based on the combined condition of all control qubits.

[0142] The task of constructing quantum circuit decompositions for n-qubit Toffoli gates that are assisted by conditionally clean ancilla qubits can be represented by the following problem. Consider an array A with n + 1 elements such that A = [1, 0, 0,.. 0], that is initially A [0] = l and 4[i] = 0 for 0 < i < n. In each step in a sequence of steps, the following operation is performed:

[0143] • select indices t, x, y such that t < x < y and ri[t] = 1, 4[x] = 4[y] = 0, and • flip the values of A [%], A [y], A [t]; that is set A[t] = 0, A[x] = A[y] = 1.

[0144] Any valid scheme of performing the sequence of steps can be characterized using parameters K, T, and D. where K represents the number of unmarked elements (that is i such that A [i] = 0) at the end of the procedure, T represents the number of operations used, and D represents the depth of operations performed in the sequence of steps, where two operations can be performed in parallel if their (x, y, t) tuples are disjoint. The problem objective is to perform the sequence of steps to minimize the number of unmarked elements (zero entries) in the array, where the sequence of steps minimizes the values of K, T and D. Attorney Docket No. 56113-0740WO1

[0145] Each solution to the above described problem can be mapped to a quantum circuit decomposition for accumulating the AND of n-qubits into K qubits (i.e., performing a logical AND operation on n qubits and storing the intermediate results in K ancilla qubits) using exactly T Toffoli gates, Toffoli depth of D and one clean ancilla qubit. This operation forms a basis for an n-qubit Toffoli gate, since the n-qubit Toffoli gate requires computing the AND of n-1 control qubits to determine whether to flip a target qubit or not.

[0146] A sequence of operations satisfying the constraints of the problem described above can be mapped to a circuit decomposition for accumulating the AND of n-qubits into K qubits using exactly T Toffoli gates, Toffoli depth of D and one clean ancilla qubit as follows:

[0147] • For an n-bit Toffoli gate, each of n system qubits are mapped to indices i = 1,..., n in the array A.

[0148] • The index i — 0, which is initially marked, corresponds to the one clean ancilla qubit required by the decomposition.

[0149] • During the course of the procedure, each index i such that Afi] = 1 corresponds to a conditionally clean ancilla qubit which can be consumed as a resource to accumulate the AND of qubits on the right of it.

[0150] • Each operation on a tuple (%, y, t) is replaced with a gate sequence -[Toffoli(x,y, t), X(t)] if t is a conditionally clean ancilla qubit (i.e. t > 0). If t is a clean ancilla qubit (i.e. t = 0), then the operation on the tuple is replaced with an AND(x,y, t) gate. Therefore, each operation computes x&.y (the AND of x and y) and saves the result on the conditionally clean ancilla qubit t. After the operation is performed, x and y are available as conditionally clean ancilla qubits and t is flipped from a conditionally clean ancilla qubit to a system qubit.

[0151] • The constraint that for each operation t < x < y ensures that at any point in time, a conditionally clean qubit t is clean conditioned on a set of control qubits to the left of it and is used as temporary workspace to store results of computations for qubits on the right of it. This invariant ensures that property for conditional cleanliness is always satisfied.

[0152] Decomposition of n-qubit Toffoli into 2n 3 Toffoli and O(n) depth using one clean ancilla qubit

[0153] One solution to the problem described above is obtained via a greedy strategy where in each step, the rightmost marked index t such that Aft] = 1 is selected. By construction, Attorney Docket No. 56113-0740WO1

[0154] there are at least two indices x and y such that t < x < y and A[x] = A[y] = 0. The leftmost such pair of x and y is selected and the operation is applied to the tuple (%, y, t). This greedy procedure provides a solution with K = 2, T = n — 2, 0 = n - 2. The procedure can be mapped to a circuit for decomposing an n-bit Toffoli into 2n — 3 Toffoli gates and O(n) depth using one clean ancilla, as shown in FIG. 4A.

[0155] FIG. 4A is a circuit diagram 400 of a decomposition of an n-bit Toffoli gate into 2n — 3 Toffoli gates using one clean ancilla qubit. In the example shown in FIG. 4A, the n-bit Toffoli gate operates on n = 9 control qubits labelled ctrl[0]-ctrl[8] and one target qubit labelled “‘target." However, the decomposition can also be applied to a smaller or larger number of control qubits. The clean ancilla qubit is labelled “clean ancilla.”

[0156] In step 1, a first Toffoli gate 402 is applied, where control qubits ctrl[O] and Ctrl [1] are the controls and the clean ancilla qubit is the target qubit. The circuit then includes a first ladder of Toffoli gates (an “up” ladder, where “up” refers to the increasing indices) that are applied to a subset of the control qubits. The first ladder of Toffoli gates includes [n / 2] Toffoli gates that accumulate the n control values of the n-bit Toffoli gate on [n / 2] control qubits using conditionally clean ancilla qubits. In this example, after the first Toffoli gate 402 has been performed, the control qubit ctrlfl] can be used as a conditionally clean ancilla qubit to perform Toffoli gate 404, where control qubit ctrlfl] is the target and control qubits ctrl[2] and Ctrl [3] are the controls. After the Toffoli gate 404 has been performed, the control qubit ctrl[3] can be used as a conditionally clean ancilla qubit to perform Toffoli gate 406 where control qubit Ctrl [3] is the target and control qubits ctrl[4] and ctrl[5] are the controls. This ladder of Toffoli gates is repeated down the register of qubits until the [n / 2] -th Toffoli gate has been performed (in this example until a 4-th Toffoli gate has been performed). Step 1 further includes a column of NOT gates, e.g., NOT gate 406. The column ofNOT gates are applied to control qubits Ctrl [0] -Ctrl [5] (or, generally, to each control qubit from control qubit Ctrl 101 to the control qubit that was the target for the most recent Toffoli gate).

[0157] In step 2. the circuit includes a second ladder of Toffoli gates (a “down” ladder, where “down” refers to the decreasing indices) that are applied to a subset of the control qubits. The second ladder of Toffoli gates includes n — \n / 2 J — 2 Toffoli gates that accumulate the AND of all of the controls on the conditionally clean ancilla qubit ctrlO. For example, in the example shown in FIG. 4A, the second ladder of Toffoli gates includes Toffoli gate 408. where control qubits Ctrl [5] and Ctrl [8] are the controls and control qubit Ctrl [4] is the target qubit. After the Toffoli gate 408 has been performed, Toffoli gate 410 is performed, where Attorney Docket No. 56113-0740WO1

[0158] the previous target qubit (control qubit Ctrl [4]) is now a control qubit, the next control qubit (ctrl [3] ) is a second control and a next-next control qubit (ctrl [2] ) is the target. This ladder of Toffoli gates is repeated up the register of qubits until the n — |n / 2J — 2 -th Toffoli gate has been performed (in this example until a 3-th Toffoli gate has been performed).

[0159] In step 3, one Toffoli gate is performed to apply the n-qubit Toffoli (CnX) gate on the target qubit. Control qubit ctrl[0] and the clean ancilla qubit are the controls for the Toffoli gate performed during step 3.

[0160] In step 4, the first ladder of Toffoli gates and the second ladder of Toffoli gates are uncomputed (the operations are performed in reverse order) to return the clean ancilla qubit and the intermediate conditional ancilla qubits to their original states. Note that the uncomputation performed in step 4 requires one less Toffoli gate since the Toffoli gate on the clean ancilla (AND gate) can be un-computed using measurement based un-computation and only Clifford gates.

[0161] As shown, the quantum circuit 400 implements an 9-bit Toffoli gate using 15 Toffoli gates and only one clean ancilla qubit. This is an improvement on known approaches, e.g., those that implement n-bit Toffoli gates using 3n Toffoli gates and one clean ancilla qubit.

[0162] FIG. 4B is another circuit diagram 450 of a decomposition of an n-bit Toffoli gate into 2n — 3 Toffoli gates using one clean ancilla qubit. In the example shown in FIG. 4B, the n-bit Toffoli gate operates on n = 19 control qubits labelled ctrl[O]-ctrl

[0018] and one target qubit labelled "target." The circuit 450 includes the same steps 1-4 described above with reference to FIG. 4A. In step 1, the circuit includes a first ladder of Toffoli gates that are applied to a subset of the control qubits. The first ladder of Toffoli gates includes |jj = 9

[0163]

[0164] Toffoli gates that accumulate the n = 19 control values of the 19-bit Toffoli gate on 9 control qubits using conditionally clean ancilla qubits. Step 1 also includes a column of NOT gates that are applied to each control qubit from ctrl[0] to Ctrl

[0015] . In step 2, a second ladder of Toffoli gates are applied to a subset of the control qubits. The second ladder of Toffoli gates includes n — — 2 = 8 Toffoli gates that accumulate the AND of all of the controls on the

[0165]

[0166] conditionally clean ancilla qubit ctrlO. In step 3 one Toffoli gate is performed to apply the 19-qubit C19X gate on the target qubit. Control qubit Ctrl [0] and the clean ancilla qubit are the controls for the Toffoli gate performed during step 3. In step 4, the first ladder of Toffoli gates and the second ladder of Toffoli gates are un-computed (the operations are performed in reverse order) to return the clean ancilla qubit and the intermediate conditional ancilla qubits to their original states. Attorney Docket No. 56113-0740WO1

[0167] Decomposition of n-qubit Toffoli into 2n — 3 Toffoli and O(log n) depth using two clean ancilla qubits

[0168] Another solution to the problem described above minimizes circuit depth and is described as follows. At an i-th step in the sequence of steps, maintain the invariant that the array A has leftmost I elements in the O-state, the next 2lelements in the 1 -state and all the remaining elements in the O-state. Therefore, the procedure ends in log n such steps and K = log n unmarked elements remain in the array at the end of the procedure. For example, over the course of the algorithm, the array A for n — 36 could look like:

[0169] -At i = 0, A = 1000000000000000000000000000000000000

[0170] - At i = 1, A = 0110000000000000000000000000000000000

[0171] - At i = 2, A = 0011110000000000000000000000000000000

[0172] - At i = 3, A = 0001111111100000000000000000000000000

[0173] - At i = 4, A = 0000111111111111111100000000000000000

[0174] - At i = 5, A = 0000011111111111111111111111111111111

[0175] • In the i-th step, the leftmost 1 of the 2‘ marked elements is utilized as the target and the remaining 2l— 1 marked elements are utilized as a temporary workspace to flip the next 2l+ 1 elements by i consequetive sequence of operations of the form (2k, 2k + 1, k) such that they are all parallelizable and can be performed in depth 1. Therefore, the result is (21— 1) + (2l+ 1) = 21+1marked elements using 2l— 1 operations.

[0176] This procedure produces a solution with K = log n, T = n — log n, and D = log n. In order to map the procedure to a circuit for decomposing an n-bit Toffoli gate into 2n — 3 Toffoli gates and O(log ri) depth, the linear depth procedure described above can be recursively invoked to obtain an O(log r) depth decomposition using 2 clean ancilla qubits.

[0177] FIGS. 5A-C show circuit diagrams for decomposing an n-qubit Toffoli gate into 2n — 3 Toffoli and O(log n) depth using two clean ancilla qubits. FIG. 5A is a circuit diagram 500 of a circuit primitive that first toggles (applies NOT gates to flip the state of) n conditionally clean ancilla qubits and then applies n Toffoli gates in parallel. The depth of this primitive is 2.

[0178] FIG. 5B is a circuit diagram 510 of a decomposition of an n-bit Toffoli gate into 2n — 3 = 15 Toffoli gates using two clean ancilla qubits, where n = 9. However, the decomposition can also be applied to a smaller or larger number of control qubits. Step-1 uses the one clean ancilla to generate two conditionally clean ancillas. Step-2 uses a log- Attorney Docket No. 56113-0740WO1

[0179] depth ladder of (n - log n - 2) Toffoli gates to accumulate the AND of the remaining (n - 2) controls on log n qubits. Step-3 uses a (log n + l)-qubit Toffoli gate to accumulate the AND of all n bits on the target qubit. Step-4 and step-5 un-compute step-2 and step-1 respectively. Step-3 can be implemented by recursively invoking a linear depth construction using one additional clean ancilla from the technique described with reference to FIG. 4A.

[0180] FIG. 5C is a circuit diagram 520 of a decomposition of n-qubit Toffoli into 2n - 3 Toffoli and O(log n) depth using 2 clean ancilla qubits, where n = 32. In this example circuit diagram, operations required to perform the multi-qubit Toffoli gate from step 3 described above with reference to FIG. 5B are shown in the circuit diagram. Note that the 2 Toffoli’s acting on clean ancilla qubits can be replaced with 2 AND / AND'1' pairs.

[0181] Decomposition of n-qubit Toffoli into 4n — 8 Toffoli and O(n) depth using 1 dirty ancilla In the decomposition of an n-qubit Toffoli gate into 2n-3 Toffoli gates using one clean ancilla qubit described above with reference to FIGS. 4A-B, the clean ancilla qubit only becomes the target of a single Toffoli gate and stores cOAcl for the first two control qubits. Therefore, toggle detection can be used to repeat the “up” and “down” ladders of Toffoli gates twice to obtain a construction where the clean ancilla qubit can be a di rty ancilla qubit. This circuit construction is shown in FIG. 6.

[0182] FIG. 6 is a circuit diagram 600 of a decomposition of n-qubit Toffoli into 4n - 7 Toffoli and O(n) depth using one dirty ancilla. In the example shown in FIG. 6, the n-bit Toffoli gate operates on n = 9 control qubits labelled ctrl[0] -ctrl[8] and one target qubit labelled “target.” However, the decomposition can also be applied to a smaller or larger number of control qubits.

[0183] Step I and 5 in the circuit diagram correspond to applications of a Toffoli gate to the dirty ancilla qubit “anc 0, where the first and second control qubits act as the controls. The “up” and "down" ladders of Toffoli gates at steps 2, 4, 6, 8 compute / uncompute the AND of all remaining controls on the conditionally clean qubit ctrl[O]. These steps correspond to the “up” and “down” ladders of Toffoli gates described in FIGS. 4A-B, and for brevity details are not repeated. Step-3 and 7 correspond to step 3 of FIG. 4A and flip the state of the target qubit when all accumulated control bits are ON. When all controls are ON, the state of the target qubit is flipped once in step-3 if the state of the dirty ancilla qubit anc 0 is initially OFF and once in step-7 if the state of the dirty ancilla qubit anc 0 is initially ON. Each of steps 2. Attorney Docket No. 56113-0740WO1

[0184] 4, 6 and 8 require n — 3 Toffoli gates. The construction therefore requires a total of 4n — 8 Toffoli.

[0185] Decomposition of n-qubit Toffoli into 4n — 8 Toffoli and O(n) depth using two dirty ancilla qubits

[0186] In the decomposition of an n-qubit Toffoli gate into 2n-3 Toffoli gates using two clean ancilla qubits described above with reference to FIGS. 5A-C. standard toggle detection can be used in the first round of the decomposition in FIG. 5B to replace the clean ancilla qubit with a dirty ancilla qubit. The recursive decomposition using the linear depth procedure and a second clean ancilla qubit can treat a borrowed dirty ancilla qubit as a clean ancilla qubit, using generalized toggle detection, and therefore the recursive decomposition remains identical to the clean ancilla case. This is shown in FIG. 7.

[0187] FIG. 7 is a circuit diagram of an example decomposition of n-qubit Toffoli gate into 4n - 8 Toffoli gates with O(n) depth using two dirty ancilla qubits. In the example shown in FIG. 7, the n-bit Toffoli gate operates on n = 9 control qubits labelled Ctrl [0] -Ctrl [8] and one target qubit labelled ‘'target.” However, the decomposition can also be applied to a smaller or larger number of control qubits.

[0188] Steps- 1 and 3 implement toggle detection using the first borrowed ancilla qubit. Steps-2 and 4 are similar to steps 2 and 4 of FIG. 5B. For brevity, details are not repeated. Steps-2 and 4 also use generalized toggle detection to decompose an (n - 1 )-bit Toffoli into 2n - 5 Toffoli using one dirty ancilla qubit, by treating the dirty ancilla qubit as clean and using the decomposition from FIG. 5B.

[0189] Conditionally clean ancilla qubits and generalized toggle detection for n-bit incrementer circuit

[0190] An n-bit incrementer circuit is a quantum circuit for adding one to an n-bit binary number, e.g., increment the value stored in a quantum register by one. FIG. 8 A shows a naive decomposition of an Incrementer gate into n different MCX (multi-controlled X) gates. A key observation is that the prefix AND of all of the first i qubits needs to be computed and consumed one by one. With access to n clean ancilla qubits, a ladder of n AND / AND† gates could be constructed such that the i-th ancilla qubit stores the prefix AND of first i qubits. Then, while un-computing the ladder of ANDs each prefix AND can be consumed using a CNOT gate. This gives a decomposition using 2n Toffoli (or n pairs of AND / AND†) gates. Attorney Docket No. 56113-0740WO1

[0191] Conditionally clean ancilla qubits as described in this specification can be used to achieve the same objective - that is compute and un-compute the prefix AND of all of the first n qubits on n different conditionally clean qubits using 2n Toffoli gates and, while, uncomputing the prefix ANDs, consume each prefix AND using a Toffoli gate. This gives an overall Toffoli complexity of 3n instead of 2n, like the clean ancilla qubit case described above, because consuming a prefix AND stored on a conditionally clean ancilla requires a Toffoli gate instead of a CNOT gate.

[0192] Decomposition of n-qubit Incrementer into 3n Toffoli and Ofn) depth using log* 2 n clean

[0193]

[0194] ancilla qubits FIG. 8B is a circuit diagram 850 of an example decomposition of an n-qubit Incrementer into 3n Toffoli and O(n) depth using log2n clean ancilla qubits. The circuit shown in FIG. 8B is similar to the construction described above with reference to FIGS. 5A-C, where instead of processing the i-th batch of size 2‘ in log-depth, it is processed in linear depth and the prefix AND is computed using 2l— 1 conditionally clean ancilla qubits as temporary w orkspace. Also, the same decomposition that computes the prefix AND is recursively applied over the K = log n unmarked items obtained after the first decomposition because the prefix ANDs are to be consumed sequentially and therefore the structure is built recursively. FIG. 8B only shows a first level of decomposition where consuming the prefix ANDs requires application of a log n-controlled MCX instead of a Toffoli gate. This should be decomposed recursively further using the same strategy until log2n < 1. The total number of ancilla qubits required (i.e. number of recursive decompositions required) therefore scales as log2n which is typically < 5 for all practical values of n < 265536.

[0195] In more detail, with access to n clean ancilla qubits, a ladder of n AND / ANDf gates could be constructed such that the i-th ancilla qubit stores the prefix / suffix AND of first / last i qubits. Then, each prefix / suffix AND could be consumed using a CNOT gate controlled on the i-th ancilla. This gives a decomposition which uses 2n Toffoli (or n pairs of AND / ANDf) gates to compute / uncompute every' prefix / suffix AND and they can be consumed using a single CNOT gate.

[0196] With the help of conditionally clean ancilla qubits, the same objective is achieved -i.e. the computation and un-computation of the prefix / suffix AND of all of the n qubits on n different conditionally clean qubits using 2n Toffoli gates and consume each prefix / suffix Attorney Docket No. 56113-0740WO1

[0197] AND using a Toffoli gate. This gives an overall Toffoli complexity of 3n instead of 2n, as in the clean ancilla case described above, because consuming a prefix AND stored on a conditionally clean ancilla requires a Toffoli gate instead of a CNOT gate.

[0198] The construction to compute prefix / suffix AND of all n qubits on n conditionally clean ancilla can be described recursively as follows:

[0199] Let D(n, n - 1) be a circuit primitive that consumes n system qubits and n - 1 (clean or conditionally clean) ancilla qubits and computes the prefix AND of all n system qubits on the n - 1 ancilla qubits. This primitive can be implemented using a sequence of n - 1 Toffoli gates as follows:

[0200] - Toffoli(q[0], q[l], anc[0]), Toffoli(q[2], anc[0], anc[l]), Toffoli(q[3], anc[l], anc[2])... Toffoli(q[n - 1], anc[n - 3], anc[n - 2]).

[0201] Let C(n) be a circuit construction that consumes 1 clean ancilla qubit and computes the prefix AND of n system qubits on n conditionally clean qubits, but the conditionally clean qubits are controlled by log(n) controls (ideally the conditionally clean qubits should be controlled by just 1 control). This primitive can be implemented by:

[0202] - Step-1: Consume a clean qubit and apply D(2. 1) with the 1 clean ancilla as target.

[0203] This produces 2 new conditionally clean qubits.

[0204] Step-2: Consume the two conditionally clean qubits from Step-1 and apply D(3, 2) on the next 3 system qubits. This step consumes 1 conditionally clean qubit as a control for subsequent steps and produces 3 new conditionally clean qubits. So. the total available conditionally clean qubits are now 3 + 2 - 1 = 4.

[0205] Step-3: Consume the 4 conditionally clean qubits from Step-2 and apply D(5, 4) on the next 5 system qubits. This step consumes 1 conditionally clean qubit as a control for subsequent steps and produces 5 new conditionally clean qubits. So. the total available conditionally clean qubits are now 5 + 4 -1 = 8.

[0206] .... (continue for log(n) steps)

[0207] Step-i+1: In the i+l'th step, 2**i available conditionally clean qubits from the i'th step are consumed and D(2**i + 1. 2 ** i) is applied on the next 2 ** i + 1 system qubits. This step consumes 1 conditionally clean qubit as a control for subsequent steps and produces 2 ** i + 1 new conditionally clean qubits. So, the total available conditionally qubits for the next step is 2 ** i + 1 + 2 ** i - 1 = 2 ** (i + 1). Attorney Docket No. 56113-0740WO1

[0208] Since each step consumes 1 conditionally clean qubit as a control for subsequent steps and there are log(n) steps in total, the total number of controls at the end of the procedure are log(n).

[0209] Thus, C(n) consumes 1 clean ancilla qubit and produces a prefix AND of all n system qubits on n conditionally clean ancilla qubits, where the conditionally clean qubits are controlled on log(n) controls.

[0210] C(n) is then applied recursively such that

[0211] Step-1: Consume 1 clean ancilla and apply C(n) on n system qubits to produce prefix / suffix AND of n system qubits on n conditionally clean ancilla with log(n) controls.

[0212] - Step-2: Consume 1 clean ancilla and recursively apply C(log(n)) on log(n) controls left from Step-1 to produce prefix / suffix AND of log(n) qubits using log(log(n)) controls.

[0213] Step-3: Consume 1 clean ancilla and recursively apply C(log(log(n))) on log(log(n)) controls left from Step-2 to produce prefix / suffix AND of log(log(n)) qubits using log(log(log(n))) controls.

[0214] This recursion continues until log*(n) <= 1, which will happen within at-most 5 steps of recursion.

[0215] At the end of the above process, there is a prefix / suffix AND for every index stored on 1 conditionally clean qubit, conditioned on at-most 1 control qubit, which can be accessed using a Toffoli gate.

[0216] Decomposition of n-qubit LessThanConst into 3n Toffoli and Ofn) depth using. log* 2 n clean ancilla qubits

[0217] A LessThanConst primitive implements a Quantum-Classical comparison of the form

[0218] LessThanConstc\x) |t) -> |x) |t ® (x < c))

[0219] FIG. 9A is a circuit diagram that reduces the classical-quantum comparison to consuming a ladder of suffix ANDs where the number of suffix ANDs to consume depends upon the bits of a classical constant c. In the worst case, all n suffix ANDs are consumed.

[0220] After this reduction, the techniques described herein are applied decompose the ladder Attorney Docket No. 56113-0740WO1

[0221] of suffix ANDs into 3n Toffoli’s using log2n clean qubits. The complete decomposition for a specific constant c is shown in shown in FIG. 9B.

[0222] Conditionally clean ancilla qubits for unary iteration and QROM

[0223] Conditionally clean ancilla qubits can also be applied to construct improved circuits for unary iteration and QROM.

[0224] Given an n-bit selection register S and a sequence of unitary operations

[0225] |V0, ■ ■ ■> ^2n-iL each acting on an m-bit target register, unary iteration is a technique that allows unitary operation Vtto be applied to the target register when the selection register stores integer |i). In other words, the action of unary iteration can be described by U =

[0226] 1 (l’l ® where N = 2" is the number of unitaries V to apply on different branches of the superposition. This technique forms a fundamental building block for many quantum algorithms, including the Quantum Read-Only Memory (QROM) operation which is a technique for loading classical data into a quantum superposition.

[0227] Conventional controlled unary iteration constructions use n clean ancilla qubits to iterate on A = 2" indices with a Toffoli cost of N — 1. The present disclosure describes two new constructions for the low ancilla regime where either a constant number of clean ancillae are consumed and system qubits are used as conditionally clean qubits, or n dirty qubits are borrowed from the system.

[0228] Unary iteration can be viewed as a tree traversal where each node of the tree corresponds to one or more elements of the range to be iterated upon and the tree is traversed in a DFS order to produce a circuit that corresponds to unary iteration. FIGS. 15A-E show how a conventional unary iteration circuit can be viewed as a tree traversal of a balanced binary tree.

[0229] FIG. 15 A shows a recursive definition of a balanced binary tree of depth K + 1. The number of leaf nodes in BK is 2Kand number of internal nodes is 2K- 1. When BK+I is used for unary iteration, the left subtree corresponds to indices in the range [0, 2K) (i.e. the K + 1 ’th bit is 0) and the right subtree corresponds to indices in the range [2K, 2K+ 1) (i.e. K + 1’th bit is 1). Outputs are associated only with the leaf nodes.

[0230] FIG. 15B shows that, when used for unary iteration on N elements, a balanced binary tree has N / 2 leaf nodes (marked in red) and N / 2 - 1 internal nodes. A DFS traversal of the tree yields N / 2 - 1 DOWN moves, N / 2 - 1 BOUNCE moves and N / 2 - 1 UP moves. For Attorney Docket No. 56113-0740WO1

[0231] controlled unary iteration, the number of UP / DOWN moves is N / 2 (an edge comes in to the root node). Each move corresponds to a circuit element as shown in FIG. 15C and FIG. 15D.

[0232] FIG. 15C shows circuit elements produced during tree traversal of a balanced binary tree with clean ancilla. Every DOWN and BOUNCE traversal as a Toffoli cost of 1. UP traversal has Toffoli cost of 0 since the AND gate can be uncomputed using measurement based uncomputation. LEAF traversal to consume data has a Toffoli cost of 0. Therefore, controlled unary iteration over N = 2nelements using n clean ancilla has a Toffoli cost of N -1.

[0233] FIG. 15D shows circuit elements produced during tree traversal of a balanced binary tree

[0234] with (potentially dirty) ancilla where measurement based uncomputation is not allowed. Every DOWN, BOUNCE and UP traversal now has a Toffoli cost of 1. LEAF traversal to consume data has a Toffoli cost of 0. Controlled unary iteration over N = 2nelements using n ancilla (without measurement based uncomputation) has a Toffoli cost of 1.5N - 1.

[0235] FIG. 15E shows a QROM circuit to load N = 16 data elements using 4 ancilla qubits without measurement based uncomputation) and 1.5N - 3 = 23 Toffoli gates. The circuit uses the circuit elements described in FIG. 15D and forms the basis of (i) unary iteration using only 2 clean ancilla and 2.5N Toffoli AND (ii) unary iteration using n = log2 N dirty ancilla and 1.5N + O(n v / N) Toffoli.

[0236] In situations where it is cheap to apply the inverse of operations being indexed over, a different tree than balanced binary trees can be used. FIGS. 16A-D shows optimized unary iteration circuit elements using skew trees.

[0237] FIG. 16A shows a recursive definition of a Skew tree of depth K +1. The size of Sk is 2k, therefore when doing unary’ iteration a skew tree associates an output with every node. The idea of using skewed trees for unary iteration is to replace circuits of the form ‘‘if-G then do A; if C

[0238] then do B” with circuits of the form ”do A; if C then do A- 1 • BT Instead of doing A conditionally, A can be done unconditionally but undone in addition to doing B when C is true. This optimization is particularly beneficial when A-1• B is efficient to apply, which is the case for QROM reads, where A and B are both a product of Pauli X gates.

[0239] FIG. 16B shows how' tree traversal of a Skew tree can be translated into unary iteration. When used for unary iteration on N elements, a skew tree has N / 4 leaf nodes and N / 4 internal nodes. A DFS traversal of the tree yields N / 4 DOWN moves. N / 4-1 BOUNCE moves and N / 4 UP moves. Each move corresponds to a circuit element as shown Attorney Docket No. 56113-0740WO1

[0240] in FIGS. 16C-D. The skewed tree associates outputs with every node, instead of only associating outputs with leaf nodes. This halves the size of the tree, which reduces the size of the circuit.

[0241] FIG. 16C shows circuit elements produced during tree traversal of a skew tree with clean

[0242] ancilla. DOWN traversal has a Toffoli cost of 2, BOUNCE traversal has a Toffoli cost of 1, UP traversal has a Toffoli cost of 0 since the AND gate can be uncomputed using measurement based uncomputation. LEAF traversal to consume data has a Toffoli cost of 1. Therefore, controlled unary iteration over N = 2nelements using n clean ancilla has a Toffoli cost of

[0243] N - 1.

[0244] FIG. 16D shows circuit elements produced during tree traversal of a skew tree with (potentially di rty) ancilla where measurement based uncomputation is not allowed. DOWN traversal has a Toffoli cost of 2. BOUNCE, UP and LEAF traversals have a Toffoli cost of 1. Therefore, controlled unary iteration over N = 2nelements using n ancilla (without measurement based uncomputation) using Skew trees has a Toffoli cost of 5 / 4N - 1 = 1.25N - 1.

[0245] The incrementer and comparator circuits described herein can be used to consume a constant number of clean qubits and use the generated conditionally clean qubits to produce / consume a prefix AND ladder. This can be combined with the unary iteration constructions given in FIGS. 15D and FIG. 16D to obtain a constant ancilla version of unary iteration using both balanced binary trees and skewed trees. The main overhead with this approach is that consuming a prefix AND stored on a conditionally clean ancilla requires a Toffoli instead of a CNOT. Therefore, an N Toffoli overhead is obtained in both approaches described above.

[0246] Therefore, with a constant number of clean ancillae and conditionally clean qubits, unary

[0247] iteration can be performed over N elements using 2.5N Toffoli gates via balanced binary¬ trees and 2.25 Toffoli gates via skewed trees.

[0248] With access to n dirty qubits instead of clean qubits, the selection register of size n can be divided into a top half of size k and a bottom half of size n-k. To iterate on the top half, K = 2kk-bit Toffoli gates are executed using the constructions described herein for decomposing n-bit Toffolis into Toffoli gates using conditionally clean qubits. For each of the K Attorney Docket No. 56113-0740WO1

[0249] iterations on the top half, a dirty QROM read is performed on the bottom n - k qubits using n - k borrowed dirty ancillae. Each of these QROM reads has the same tree shape and is of size N / K. Since the ancilla qubits this time are borrowed and can be in an unknown state, a round of laddered toggle detection is also performed. Because all the K QROM trees are of identical shape with differing data elements, the toggle detection can be performed viajust 1 more QROM read of the same size but where for each leaf node i, all data elements from the i’th leaf nodes of each of the K QROM trees are loaded.

[0250] Let QROMDirtyCost(M) denote the Toffoli cost of performing a QROM read on M data

[0251] elements using dirty ancillae (this cost will depend on the specific tree structure used -balanced

[0252] binary or skewed - and the details of the implementation). The overall cost of the procedure is (K + 1) X QROMDirtyCost N / K) + (3(K * k). Setting K=A / N gives a cost of 1.5N + 0 (n N) for dirty QROM via balanced binary tree and 1.25N + 0 (n^N) for dirty QROM via the skewed trees case.

[0253] Example processes

[0254] FIG. 10 is a flow diagram of an example process 1000 for performing, conditioned on each qubit in a control register of qubits being in an on state, a target operation on a target register of one or more qubits. The process 1000 is also referred to herein as generalized toggle detection, as described above with reference to FIGS. 3A-C, and corresponds to the quantum circuit show n in FIG. 3B. For convenience, the process 1000 will be described as being performed by a quantum computing system. For example, the system 100 of FIG. 1, appropriately programmed in accordance with this specification, can perform the process 1 00.

[0255] The system performs a first CNOT operation (a multi-control NOT operation), where a first dirty ancilla qubit is a target for the first CNOT operation and each qubit in a first subset of qubits included in the control register acts as a control for the first CNOT operation (step 1002). The system then performs a second CNOT operation (a multi-control NOT operation), where a second dirty ancilla qubit is a target for the second CNOT operation, each qubit in a second subset of qubits included in the control register acts as a control for the second CNOT operation, and the first dirty ancilla qubit acts as a control for the second CNOT operation (step 1004). The first subset of qubits is different to the second subset of qubits and can include a different number of qubits than the second subset of qubits. The Attorney Docket No. 56113-0740WO1

[0256] control register consists of a union of the first subset of qubits and the second subset of qubits. The system applies, conditioned on the second dirty ancilla qubit being in an on state, the target operation to the target register of qubits (step 1004). The system performs the second CNOT operation again (step 1006), i.e., performs a third CNOT operation, where the second dirty ancilla qubit is a target for the third CNOT operation, each qubit in the second subset of qubits included in the control register acts as a control for the third CNOT operation, and the first dirty ancilla qubit acts as a control for the third CNOT operation. The system then repeats steps 1002-1006.

[0257] FIG. 11 is a flow diagram of an example process 1100 for performing an n-bit Toffoli gate on a target qubit and n control qubits in a control register using n-2 dirty ancilla qubits in an ancilla register. The example process 1100 uses generalized toggle detection, as described above with reference to FIGS. 3A-C and FIG. 10, and corresponds to the quantum circuit shown in FIG. 3C. For convenience, the process 1100 will be described as being performed by a quantum computing system. For example, the system 100 of FIG. 1, appropriately programmed in accordance with this specification, can perform the process 1100.

[0258] In the below description, it is understood that the qubits in each register are ordered, with increasing indices, from top to bottom such that a highest qubit in the register corresponds to a first qubit and a low est qubit in the register corresponds to a last qubit in the register. Further, it is understood that the ancilla register is positioned below the control register and the target qubit is positioned below the ancilla register.

[0259] The system performs a downward cascade of Toffoli gates, where each Toffoli gate in the downward cascade targets a respective first dirty ancilla qubit in the ancilla register and uses i) a respective second dirty ancilla qubit and ii) a respective control qubit in the control register as controls (step 1102). In some implementations the downward cascade of Toffoli gates includes (n-3) Toffoli gates. Each Toffoli gate in the downward cascade uses a respective control qubit that is (n — 2) qubits above the respective second dirty ancilla qubit. A first Toffoli gate in the downward cascade of Toffoli gates targets a second highest dirty ancilla qubit, uses a highest dirty ancilla qubit as a control, and uses a third highest control qubit as a control. A last Toffoli gate in the downward cascade of Toffoli gates targets a low est dirty ancilla qubit, uses a second lowest dirty ancilla qubit as a control, and uses a second lowest control qubit as a control. The Toffoli gates in between cascade down through the register, where each Toffoli gate in the downward cascade uses a respective second dirty ancilla qubit that is directly above the respective first dirty ancilla qubit as a control. Attorney Docket No. 56113-0740WO1

[0260] The system performs a first Toffoli gate, where the target qubit is a target for the first Toffoli gate and i) a lowest dirty ancilla qubit in the ancilla register and ii) a lowest control qubit in the control register act as controls (step 1104). The system then performs an inverse of the downward cascade of Toffoli gates (step 1106). The system then performs a second Toffoli gate, where i) a highest dirty ancilla qubit in the ancilla register is a target for the second Toffoli gate and ii) two highest control qubits in the control register act as controls (step 1106). The system then repeats steps 1102-1106.

[0261] FIG. 12 is a flow diagram of an example process 1200 for accumulating an AND of multiple qubits. For convenience, the process 1200 will be described as being performed by a quantum computing system. For example, the system 100 of FIG. 1, appropriately programmed in accordance with this specification, can perform the process 1200.

[0262] The system assigns, from an array that includes n + 1 elements, a clean ancilla qubit an index i — 0 and n system qubits a respective index i = 1,... n (step 1202). The system initializes elements in the array, including setting an element that corresponds to index i — 0 as marked and setting remaining elements in the array as unmarked (step 1204).

[0263] The system performs a sequence of operations until the array includes a minimum number of unmarked elements. At each step in the sequence of operations, a conditionally clean qubit assigned an index t is clean conditioned on a first set of system qubits and is used as temporary workspace to store results of computations for a second set of system qubits, where the first and second set are disjoint.

[0264] Performing the sequence of operations includes performing the following operations at each step in the sequence of operations: the system labels each qubit assigned to an index i in the array that corresponds to a marked element as a conditionally clean ancilla qubit (step 1206). The system selects indices t, x, y in the array such that an element that corresponds to index t is marked and elements that correspond to indices x and y are unmarked, wherein the indices satisfy t < x < y (step 1208).

[0265] The system then computes an AND of elements that correspond to indices x and y and saving a result of the AND in an element that corresponds to index t (step 1210). This assigns qubits that correspond to indices x and y as conditionally clean qubits and assigns the qubit that corresponds to index t as a system qubit.

[0266] To compute the AND of the elements that correspond to indices x and y and saving a result of the AND in an element that corresponds to index t includes: determining whether a qubit assigned to the index t is a conditionally clean ancilla qubit, in response to determining Attorney Docket No. 56113-0740WO1

[0267] that the qubit assigned to the index t is a conditionally clean ancilla qubit, applying a Toffoli gate to qubits assigned to indices x, y, and t. where the qubit assigned to index t acts as a target qubit, and applying an X gate to the qubit assigned to index t. In response to determining that the qubit assigned to the index t is not a conditionally clean ancilla qubit, the system determines whether the qubit assigned to the index t is a clean ancilla qubit and in response to determining that the qubit assigned to the index t is a clean ancilla qubit, the system applies an AND gate to qubits assigned to indices x. y, and t.

[0268] FIG. 13 is a flow diagram of an example process 1300 for performing an n-bit Toffoli gate on a target qubit using a control register of control qubits. For convenience, the process 1300 will be described as being performed by a quantum computing system. For example, the system 100 of FIG. 1, appropriately programmed in accordance with this specification, can perform the process 1300.

[0269] The system obtains an ancilla qubit and performs a first Toffoli gate, where the ancilla qubit is the target for the first Toffoli gate and a first and second control qubit are controls for the first Toffoli gate (step 1302).

[0270] The system performs a first ladder of Toffoli gates on control qubits in the control register to accumulate n control values on | ] controls using conditionally clean ancilla qubits (step 1304). A first Toffoli gate in the first ladder of Toffoli gates is applied between a second, third, and fourth control qubit, wherein the second control qubit is the target.

[0271] Subsequent Toffoli gates in the first ladder of Toffoli gates are applied to consecutive control qubits, where a last control for a previous Toffoli gate is a target for a next Toffoli gate. In this manner, the first ladder is an upwards ladder (with respect to positions in the register) with consecutive Toffoli gates that are applied to control qubits with increasing indices in the control register.

[0272] The system applies NOT gates to a subset of the control qubits (step 1306). The subset of control qubits includes control qubits used as targets in the first ladder and second ladder of Toffoli gates.

[0273] The system performs a second ladder of Toffoli gates on control qubits in the control register to accumulate an AND of all controls on the first control qubit, where the first control qubit stores the accumulated AND as a conditionally clean ancilla qubit (step 1308). The second ladder is a downw ards ladder with consecutive Toffoli gates that are applied to control qubits with decreasing indices in the control register. The second ladder of Toffoli gates includes n — ⌊n / 2⌋ — 2 Toffoli gates.

[0274]

[0275] Attorney Docket No. 56113-0740WO1

[0276] The system performs a second Toffoli gate, where the target qubit is the target for the second Toffoli gate, the first control qubit acts as a control and the ancilla qubit acts as a control (step 1310). The second Toffoli gate applies an n-qubit CnX gate to the target qubit.

[0277] The system un-computes the second ladder of Toffoli gates, the NOT gates, the first ladder of Toffoli gates, and the first Toffoli gate (step 1312). The un-computing includes performing an inverse of the second ladder of Toffoli gates; applying the NOT gates to the subset of the control qubits; performing an inverse of the first ladder of Toffoli gates; and performing the first Toffoli gate.

[0278] In some implementations the ancilla qubit obtained at step 1302 is a clean ancilla qubit. In these implementations step 1312 returns the ancilla qubit and intermediate conditionally clean ancilla qubits to their original states. Further, in these implementations example process 1300 corresponds to the linear depth (O(n)) quantum circuits shown in FIGS. 4A-B and requires 2n-3 Toffoli gates.

[0279] In other implementations the ancilla qubit obtained at step 1302 is a dirty ancilla qubit. In these implementations example process 1300 further includes the following steps: the system repeats steps 1304. 1306. 1308, 1310, and 1312 (where in the repetition of step 1312 the first Toffoli gate is not uncomputed). In these implementations example process 1300 corresponds to the linear depth quantum circuit show n in FIG. 6 and requires 4n-8 Toffoli gates.

[0280] FIG. 14 is a flow diagram of an example process 1400 for performing an n-bit Toffoli gate on a target qubit using a control register of control qubits. For convenience, the process 1400 will be described as being performed by a quantum computing system. For example, the system 100 of FIG. 1, appropriately programmed in accordance with this specification, can perform the process 1400.

[0281] The system obtains a first ancilla qubit and performs a first Toffoli gate, where the first ancilla qubit is the target for the first Toffoli gate and a first and second control qubit are controls for the first Toffoli gate (step 1402). The first ancilla qubit is positioned below the control register of control qubits and the target qubit is positioned above the control register of control qubits.

[0282] The system performs a ladder of Toffoli gates to accumulate an AND of n — 2 control qubits on log n qubits using conditionally clean ancilla qubits (step 1404). The ladder of Toffoli gates includes n-log n-2 Toffoli gates. The ladder of Toffoli gates includes multiple instances of a depth-2 circuit primitive that applies NOT gates to each of n conditionally clean ancilla qubits and, after application of the NOT gates, applies n Toffoli Attorney Docket No. 56113-0740WO1

[0283] gates in parallel. At an i-th layer of Toffoli gates in the ladder of Toffoli gates, an upmost control qubit of 2lcontrol qubits in a one state is used as a target qubit and a remaining 2i— 1 control qubits of the 2icontrol qubits are conditionally clean ancilla qubits that are used as a temporary workspace to flip a state of a next 21+ 1 control qubits through application of i consecutive Toffoli gates with parameters (2 / c, 2k + 1, fc), where k represents an index in the control register.

[0284] The system performs, using a second ancilla qubit, a multi-bit Toffoli gate to accumulate an AND of all n bit of the n-bit Toffoli on the target qubit (step 1406). The multi-bit Toffoli gate is a (logn + l)-bit Toffoli gate. The multi-bit Toffoli gate can be computed, e.g., using example process 1300 of FIG. 13.

[0285] The system un-computes the ladder of Toffoli gates and the first Toffoli gate to return the intermediate conditionally clean ancilla qubits to their original states (step 1408). Uncomputing the ladder of Toffoli gates and the first Toffoli gate includes performing an inverse of the ladder of Toffoli gates; and applying the first Toffoli gate.

[0286] In some implementations the ancilla qubit obtained at step 1402 is a clean ancilla qubit. In these implementations step 1408 returns the clean ancilla qubit and intermediate conditionally clean ancilla qubits to their original states. Further, in these implementations example process 1400 corresponds to the log(n) depth quantum circuit shown in FIG. 5B and requires 2n-3 Toffoli gates.

[0287] In other implementations the ancilla qubit obtained at step 1402 is a dirty ancilla qubit. In these implementations example process 1400 further includes the following steps: the system repeats steps 1404, 1406. and un-computes the ladder of Toffoli gates (repeats part of step 1408). In these implementations example process 1400 corresponds to the log(n) depth quantum circuit shown in FIG. 7 and requires 4n-8 Toffoli gates.

[0288] Implementations of the digital and / or quantum subject matter and the digital functional operations and quantum operations described in this specification can be implemented in digital electronic circuitry, suitable quantum circuitry’ or. more generally, quantum computational systems, in tangibly-embodied digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term “quantum computational systems” may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators. Quantum computation systems in general and quantum Attorney Docket No. 56113-0740WO1

[0289] computers specifically may be realized or based on different quantum computational models and architectures. For example, the quantum computation system may be based on or described by models such as the quantum circuit model, one-way quantum computation, adiabatic quantum computation, holonomic quantum computation, analog quantum computation, digital quantum computation, or topological quantum computation.

[0290] Implementations of the digital and / or quantum subject matter described in this specification can be implemented as one or more digital and / or quantum computer programs, i.e., one or more modules of digital and / or quantum computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, data processing apparatus. The digital and / or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits, or a combination of one or more of them.

[0291] Alternatively or in addition, the program instructions can be encoded on an artificially-generated propagated signal that is capable of encoding digital and / or quantum information, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode digital and / or quantum information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

[0292] The terms quantum information and quantum data refer to information or data that is carried by, held or stored in quantum systems, where the smallest non-trivial system is a qubit, i.e., a system that defines the unit of quantum information. It is understood that the term ’‘qubit” encompasses all quantum systems that may be suitably approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., with tw o or more levels. By w ay of example, such systems can include atoms, electrons, photons, ions or superconducting qubits. In many implementations the computational basis states are identified with the ground and first excited states, however it is understood that other setups where the computational states are identified with higher level excited states are possible.

[0293] The term “data processing apparatus” refers to digital and / or quantum data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing digital and / or quantum data, including by way of example a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, multiple digital and quantum processors or computers, and combinations thereof. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a Attorney Docket No. 56113-0740WO1

[0294] quantum data processing apparatus that is designed to simulate or produce information about a specific quantum system. In particular, a quantum simulator is a special purpose quantum computer that does not have the capability to perform universal quantum computation. The apparatus can optionally include, in addition to hardware, code that creates an execution environment for digital and / or quantum computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0295] A digital computer program, which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program, which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and translated into a suitable quantum programming language, or can be written in a quantum programming language, e.g., QCL or Quipper.

[0296] A digital and / or quantum computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub-programs, or portions of code. A digital and / or quantum computer program can be deployed to be executed on one digital or one quantum computer or on multiple digital and / or quantum computers that are located at one site or distributed across multiple sites and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a netw ork that may transmit quantum data using quantum systems, e.g. qubits. Generally, a digital data communication network cannot transmit quantum data, however a quantum data communication network may transmit both quantum data and digital data.

[0297] The processes and logic flows described in this specification can be performed by one or more programmable digital and / or quantum computers, operating with one or more digital and / or quantum processors, as appropriate, executing one or more digital and / or quantum computer programs to perform functions by operating on input digital and quantum data and Attorney Docket No. 56113-0740WO1

[0298] generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA or an ASIC, or a quantum simulator, or by a combination of special purpose logic circuitry or quantum simulators and one or more programmed digital and / or quantum computers.

[0299] For a system of one or more digital and / or quantum computers to be “configured to” perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more digital and / or quantum computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by digital and / or quantum data processing apparatus, cause the apparatus to perform the operations or actions. A quantum computer may receive instructions from a digital computer that, when executed by the quantum computing apparatus, cause the apparatus to perform the operations or actions.

[0300] Digital and / or quantum computers suitable for the execution of a digital and / or quantum computer program can be based on general or special purpose digital and / or quantum processors or both, or any other kind of central digital and / or quantum processing unit. Generally, a central digital and / or quantum processing unit will receive instructions and digital and / or quantum data from a read-only memory, a random access memory, or quantum systems suitable for transmitting quantum data, e.g. photons, or combinations thereof.

[0301] Elements of a digital and / or quantum computer include a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry or quantum simulators. Generally, a digital and / or quantum computer will also include, or be operatively coupled to receive digital and / or quantum data from or transfer digital and / or quantum data to, or both, one or more mass storage devices for storing digital and / or quantum data, e.g., magnetic, magneto-optical disks, optical disks, or quantum systems suitable for storing quantum information. However, a digital and / or quantum computer need not have such devices.

[0302] Digital and / or quantum computer-readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; CD-ROM and DVD-ROM disks; and quantum systems, e.g., trapped atoms or electrons. It is Attorney Docket No. 56113-0740WO1

[0303] understood that quantum memories are devices that can store quantum data for a long time with high fidelity- and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

[0304] Control of the various systems described in this specification, or portions of them, can be implemented in a digital and / or quantum computer program product that includes instructions that are stored on one or more non-transitory machine-readable storage media, and that are executable on one or more digital and / or quantum processing devices. The systems described in this specification, or portions of them, can each be implemented as an apparatus, method, or system that may include one or more digital and / or quantum processing devices and memory to store executable instructions to perform the operations described in this specification.

[0305] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

[0306] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0307] Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions Attorney Docket No. 56113-0740WO1

[0308] recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

[0309] What is claimed is:

Claims

Attorney Docket No. 56113-0740WO1CLAIMS1. A method performed by a quantum computing device, the method comprising:performing, conditioned on each qubit in a control register of qubits being in an on state, a target operation on a target register of one or more qubits, comprising, repeatedly for at least two repetitions:performing a first CNOT operation, wherein a first dirty ancilla qubit is a target for the first CNOT operation and each qubit in a first subset of qubits included in the control register acts as a control for the first CNOT operation;performing a second CNOT operation, wherein a second dirty ancilla qubit is a target for the second CNOT operation, each qubit in a second subset of qubits included in the control register acts as a control for the second CNOT operation, and the first dirty ancilla qubit acts as a control for the second CNOT operation;applying, conditioned on the second dirty ancilla qubit being in an on state, the target operation to the target register of qubits; andperforming a third CNOT operation, wherein the second dirty ancilla qubit is a target for the third CNOT operation, each qubit in the second subset of qubits included in the control register acts as a control for the third CNOT operation, and the first dirty ancilla qubit acts as a control for the third CNOT operation.

2. The method of claim 1, wherein the target operation comprises a self-inverse operator.

3. The method of claim 1 or claim 2, wherein the first subset of qubits is different to the second subset of qubits.

4. The method of any one of the preceding claims, wherein the control register consists of a union of the first subset of qubits and the second subset of qubits.

5. A method performed by a quantum computing device, the method comprising:performing an n-bit Toffoli gate on a target qubit and n control qubits in a control register using n — 2 dirty ancilla qubits in an ancilla register, comprising, repeatedly for at least two repetitions:performing a downward cascade of Toffoli gates, wherein each Toffoli gate in the downward cascade targets a respective first dirty ancilla qubit in the ancilla register andAttorney Docket No. 56113-0740WO1uses i) a respective second dirty ancilla qubit and ii) a respective control qubit in the control register as controls;performing a first Toffoli gate, wherein the target qubit is a target for the first Toffoli gate and i) a lowest dirty ancilla qubit in the ancilla register and ii) a lowest control qubit in the control register act as controls;performing an inverse of the downward cascade of Toffoli gates; and performing a second Toffoli gate, wherein i) a highest dirty ancilla qubit in the ancilla register is a target for the second Toffoli gate and ii) two highest control qubits in the control register act as controls.

6. The method of claim 5, wherein the downward cascade of Toffoli gates comprises (n — 3) Toffoli gates.

7. The method of claim 5 or claim 6, wherein qubits in each register are ordered, with increasing indices, from top to bottom such that a highest qubit in the register corresponds to a first qubit and a lowest qubit in the register corresponds to a last qubit in the register.

8. The method of claim 7, wherein the ancilla register is positioned below the control register and the target qubit is positioned below the ancilla register.

9. The method of claim 8, wherein each Toffoli gate in the downward cascade uses a respective control qubit that is (n — 2) qubits above the respective second dirty ancilla qubit.

10. The method of any one of claims 7 to 9, wherein a first Toffoli gate in the downward cascade of Toffoli gates targets a second highest dirty ancilla qubit, uses a highest dirty ancilla qubit as a control, and uses a third highest control qubit as a control.

11. The method of any one of claims 7 to 10, wherein a last Toffoli gate in the downward cascade of Toffoli gates targets a lowest dirty ancilla qubit, uses a second lowest dirty ancilla qubit as a control, and uses a second lowest control qubit as a control.

12. The method of any one of claims 7 to 11, wherein each Toffoli gate in the downward cascade uses a respective second dirty ancilla qubit that is directly above the respective first dirty ancilla qubit as a control.Attorney Docket No. 56113-0740WO113. A system comprising:a quantum processor comprising a plurality of qubits;control electronics configured to apply control signals to the plurality of qubits; and a classical processor configured to process and store instructions for execution by the control electronics;wherein the system is configured to perform operations according to the method of any one of claims 1 to 12.

14. A computer-readable storage medium comprising instructions stored thereon that are executable by control electronics and upon such execution cause the control electronics to apply control signals to a plurality of qubits and perform operations according to the method of any one of claims 1 to 12.

15. A method performed by a quantum computing device for accumulating an AND of the state of multiple qubits, the method comprising:assigning, to an array of n+1 elements, a clean ancilla qubit at index i = 0 and n system qubits respective indices i = 1,... n;initializing elements in the array, comprising setting an element that corresponds to index i = 0 as marked and setting remaining elements in the array as unmarked;performing a sequence of operations until the array comprises a minimum number of unmarked elements, comprising, at each step in the sequence of operations:labelling each qubit assigned to an index i in the array that corresponds to a marked element as a conditionally clean ancilla qubit;selecting indices t, x,y in the array such that an element that corresponds to index t is marked and elements that correspond to indices x and y are unmarked, wherein the indices satisfy t < x < y andcomputing an AND of elements that correspond to indices x and y and saving a result of the AND in an element that corresponds to index t. comprising:determining whether a qubit assigned to the index t is a conditionally clean ancilla qubit;in response to determining that the qubit assigned to the index t is a conditionally clean ancilla qubit, applying a Toffoli gate to qubits assigned to indices x, y.Attorney Docket No. 56113-0740WO1and t. wherein the qubit assigned to index t acts as a target qubit, and applying an X gate to the qubit assigned to index t.

16. The method of claim 15, further comprising:in response to determining that the qubit assigned to the index t is not a conditionally clean ancilla qubit, determining whether the qubit assigned to the index t is a clean ancilla qubit; andin response to determining that the qubit assigned to the index t is a clean ancilla qubit, applying an AND gate to qubits assigned to indices x, y, and t.

17. The method of claim 15 or claim 16. wherein computing the AND of elements that correspond to indices x and y and saving the result of the AND in the element that corresponds to index t assigns qubits that correspond to indices x and y as conditionally clean qubits and assigns the qubit that corresponds to index t as a system qubit.

18. The method of any one of claims 15 to 17. wherein at each step in the sequence of operations, a conditionally clean qubit assigned an index t is clean conditioned on a first set of system qubits and is used as temporary workspace to store results of computations for a second set of system qubits, wherein the first and second set are disjoint.

19. An apparatus comprising:a quantum computing system; anda classical computing system in data communication with the quantum computing system,wherein the system is configured to perform operations according to the method of any one of claims 15 to 18.

20. A method performed by a quantum computing device for performing an n-bit Toffoli gate on a target qubit using a control register of control qubits, the method comprising:obtaining an ancilla qubit;performing a first Toffoli gate, wherein the ancilla qubit is the target for the first Toffoli gate and a first and second control qubit are controls for the first Toffoli gate;performing a first ladder of Toffoli gates on control qubits in the control register to accumulate n control values on ⌊n / 2⌋ controls using conditionally clean ancilla qubits;Attorney Docket No. 56113-0740WO1applying NOT gates to a subset of the control qubits;performing a second ladder of Toffoli gates on control qubits in the control register to accumulate an AND of all controls on the first control qubit, wherein the first control qubit stores the accumulated AND as a conditionally clean ancilla qubit;performing a second Toffoli gate, wherein the target qubit is the target for the second Toffoli gate, the first control qubit acts as a control and the ancilla qubit acts as a control; and un-computing the second ladder of Toffoli gates, the NOT gates, the first ladder of Toffoli gates, and the first Toffoli gate to return intermediate conditionally clean ancilla qubits to their original states.

21. The method of claim 20, wherein a first Toffoli gate in the first ladder of Toffoli gates is applied between a second, third, and fourth control qubit, wherein the second control qubit is the target.

22. The method of claim 21, wherein subsequent Toffoli gates in the first ladder of Toffoli gates are applied to consecutive control qubits, wherein a last control for a previous Toffoli gate is a target for a next Toffoli gate.

23. The method of any one of claims 20 to 22, wherein the first ladder comprises an upwards ladder with consecutive Toffoli gates that are applied to control qubits with increasing indices in the control register.

24. The method of any one of claims 20 to 23, wherein the second ladder comprises a downwards ladder with consecutive Toffoli gates that are applied to control qubits with decreasing indices in the control register.

25. The method of any one of claims 20 to 24, wherein the subset of control qubits comprises control qubits used as targets in the first ladder and second ladder of Toffoli gates.

26. The method of any one of claims 20 to 25, wherein the second ladder of Toffoli gates comprises n — ⌊n / 2⌋ — 2 Toffoli gates.

27. The method of any one of claims 20 to 26. wherein the second Toffoli gate applies an n-qubit CnX gate to the target qubit.Attorney Docket No. 56113-0740WO128. The method of any one of claims 20 to 27, wherein un-computing the second ladder of Toffoli gates and the first ladder of Toffoli gates comprises:performing an inverse of the second ladder of Toffoli gates;applying the NOT gates to the subset of the control qubits;performing an inverse of the first ladder of Toffoli gates; andperforming the first Toffoli gate.

29. The method of any one of claims 20 to 28, wherein the obtained ancilla qubit is a clean ancilla qubit and performing the n-bit Toffoli gate requires 2n-3 Toffoli gates.

30. The method of any one of claims 20 to 29, wherein the obtained ancilla qubit is a dirty ancilla qubit, and wherein the method further comprises:performing the first ladder of Toffoli gates on the control qubits in the control register;applying the NOT gates to the subset of the control qubits;performing the second ladder of Toffoli gates on the control qubits in the control register;performing the second Toffoli gate, wherein the target qubit is the target for the second Toffoli gate, the first control qubit acts as a control and the ancilla qubit acts as a control; andun-computing the second ladder of Toffoli gates, the NOT gates, and the first ladder of Toffoli gates.

31. The method of claim 30, wherein the first ladder of Toffoli gates and the second ladder of Toffoli gates each comprise n-3 Toffoli gates.

32. A system comprising:a quantum processor comprising a plurality of qubits;control electronics configured to apply control signals to the plurality of qubits; and a classical processor configured to process and store instructions for execution by the control electronics;Attorney Docket No. 56113-0740WO1wherein the system is configured to perform operations according to the method of any one of claims 20 to 31.

33. A computer-readable storage medium comprising instructions stored thereon that are executable by control electronics and upon such execution cause the control electronics to apply control signals to a plurality of qubits and perform operations according to the method of any one of claims 20 to 31.

34. A method performed by a quantum computing device for performing an n-bit Toffoli gate on a target qubit using a control register of control qubits, the method comprising:obtaining a first ancilla qubit and a second ancilla qubit:performing a first Toffoli gate, wherein the first ancilla qubit is the target for the first Toffoli gate and a first and second control qubit are controls for the first Toffoli gate;performing a ladder of Toffoli gates on control qubits in the control register to accumulate an AND of n — 2 control qubits on log n qubits using conditionally clean ancilla qubits;performing, using the second clean ancilla qubit, a multi-bit Toffoli gate to accumulate an AND of all n bit of the n-bit Toffoli on the target qubit; andun-computing the ladder of Toffoli gates and the first Toffoli gate.

35. The method of claim 34, wherein performing the multi-bit Toffoli gate comprises recursively performing the method of any one of claims 20-31.

36. The method of claim 34 or claim 35. wherein the first ancilla qubit is positioned below the control register of control qubits and the target qubit is positioned above the control register of control qubits.

37. The method of any one of claims 34 to 36. wherein the ladder of Toffoli gates comprises n-log n-2 Toffoli gates.

38. The method of any one of claims 34 to 37, wherein the multi-bit Toffoli gate comprises a (logn + l)-bit Toffoli gate.Attorney Docket No. 56113-0740WO139. The method of any one of claims 34 to 38, wherein the ladder of Toffoli gates comprises multiple instances of a depth-2 circuit primitive that applies NOT gates to each of n conditionally clean ancilla qubits and, after application of the NOT gates, applies n Toffoli gates in parallel.

40. The method of claim 39, wherein at an i-th layer of Toffoli gates in the ladder of Toffoli gates, an upmost control qubit of 2icontrol qubits in a one state is used as a target qubit and a remaining 2i— 1 control qubits of the 2icontrol qubits are conditionally clean ancilla qubits that are used as a temporary workspace to flip a state of a next 2i+ 1 control qubits through application of i consecutive Toffoli gates with parameters (2k, 2k + 1, k), where k represents an index in the control register.

41. The method of any one of claims 34 to 40. wherein performing the n-bit Toffoli gate comprises executing a quantum circuit with depth log n.

42. The method of any one of claims 34 to 41, wherein un-computing the ladder of Toffoli gates and the first Toffoli gate comprises:performing an inverse of the ladder of Toffoli gates; andapplying the first Toffoli gate.

43. The method of any one of claims 34 to 42, wherein the first ancilla qubit and the second ancilla qubit comprise clean ancilla qubits, and wherein performing the n-bit Toffoli gate requires 2n-3 Toffoli gates.

44. The method of any one of claims 34 to 43, wherein the first ancilla qubit and the second ancilla qubit comprise dirty- ancilla qubits, wherein the method further comprises: performing the ladder of Toffoli gates on the control qubits in the control register; performing, using the second clean ancilla qubit, the multi-bit Toffoli gate; and un-computing the ladder of Toffoli gates.

45. The method of claim 44, wherein performing the n-bit Toffoli gate requires 4n-8 Toffoli gates.Attorney Docket No. 56113-0740WO146. The method of claim 44 or claim 45, wherein performing the multi-bit Toffoli gate to accumulate an AND of all n bit of the n-bit Toffoli on the target qubit comprises applying generalized toggle detection.

47. The method of claim 46, wherein the multi-bit Toffoli comprises a (n-l)-bit Toffoli gate and applying generalized toggle detection decomposes the (n-l)-bit Toffoli gate into 2n-5 Toffoli gates using the second ancilla qubit.

48. A system comprising:a quantum processor comprising a plurality of qubits;control electronics configured to apply control signals to the plurality of qubits; and a classical processor configured to process and store instructions for execution by the control electronics;wherein the system is configured to perform operations according to the method of any one of claims 34 to 47.

49. A computer-readable storage medium comprising instructions stored thereon that are executable by control electronics and upon such execution cause the control electronics to apply control signals to a plurality of qubits and perform operations according to the method of any one of claims 34 to 47.

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