Architecture optimized synthesis of quantum algorithms

Abstract

This application concerns a computer-implemented method for compiling an input unitary acting on a set of logical qubits to an output quantum circuit operable on a quantum system comprising a plurality of output qubits (1), wherein the output qubits (1) of the quantum system are arranged in accordance with a connectivity mesh (11), wherein nodes (111) of the connectivity mesh (11) represent possible sites for the output qubits (1) of the quantum system and each edge (112) of the connectivity mesh (11) indicates that quantum interactions between the output qubits (1) of the quantum system connected by one of the edges (112) are possible, comprising the following steps: providing the connectivity mesh (11) of the quantum system; assigning an index to each of the logical qubits; extracting a set of target labels (2) from the input unitary, wherein the target labels (2) correspond to a set comprising at least one of the indices of the logical qubits; compiling circuit building blocks (4) implementing a subset of the target labels (2), wherein the circuit building blocks (4) comprise body path gates (41) and / or leg gates (42) acting on the output qubits (1), wherein compiling the circuit building blocks (4) comprises: defining a tree (3) comprising a subset of edges (112) and a subset of nodes (111) of the connectivity mesh (11), wherein the tree (3) comprises a body (31) with at least one body node (1111) representing a site for an output qubit (1), wherein the body (31) comprises at least two output qubits (1) at two body nodes (1111) and at least one path (6) connecting all body nodes (1111) of the body (31) and / or at least one leg (32) with at least one leg node (1112) representing a site for an output qubit (1), wherein the at least one leg node (1112) is connected by an edge (112) with at least one body node (1111); adding a body path gate (41) to the output quantum circuit for each body node (1111) along the at least one path (6) and / or adding a leg path gate (42) to the output quantum circuit for each leg node (1112); adding a single-qubit gate (43) to the output quantum circuit for at least one of the target labels (2) of the input unitary, wherein the single-qubit gate acts on the output qubit (1) and at the moment on which the target label (2) is implemented due to the gates of the circuit building blocks (4).

Description

[0001] Architecture optimized synthesis of quantum algorithms

[0002] Embodiments described herein relate to a computer-implemented method for compiling an input unitary acting on a set of logical qubits to an output quantum circuit operable on a quantum system comprising a plurality of output qubits and to the output quantum circuit itself. Further embodiments relate to a method of performing a quantum computation on a quantum system.

[0003] BACKGROUND OF THE INVENTION

[0004] Quantum computers promise exponential computational speedup for many classically intractable problems ranging from efficient and accurate simulation of quantum systems over drug development and financial modelling to solving real-world large-scale optimisation problems. In recent years, both quantum hardware and software experienced enormous leaps of improvements putting modern quantum hardware in the range of (or even beyond) state-of-the art classical computing systems for specialized tasks. However, unlike for classical computation, present day quantum resources of near-term intermediate scale quantum (NISQ) hardware systems are sparse. This is why efficient quantum algorithms are required to elevate performance and leverage quantum advantage.

[0005] In order to run the quantum algorithm, it needs to be physically implemented in a physical quantum system, such that a quantum computation according to the quantum algorithm can be physically carried out. A straightforward way for physically implementing a quantum algorithm may be to assign each logical qubit of the quantum algorithm to a respective physical qubit of the quantum system. The instructions of the quantum algorithm may be implemented by (physically) performing the corresponding quantum operations. By this, a quantum computation can be carried out in which the quantum state of the physical quantum system evolves to a final state, which is measured to obtain a read-out, i.e., an output or a solution.

[0006] The efficiency of quantum algorithms can be measured by various means. A prominent metric is the so-called T-count measuring the number of required T gates necessary for the implementation of a specific algorithm. A low T-count is particularly important for quantum error correction where it constitutes one of the main bottlenecks. For NISQ devices, for which quantum error correction is still out of reach, metrics such as the total gate count or the depth of quantum algorithms have more relevance. In fact, even in the era of fault-tolerant quantum computations, efficient gate count and depth optimised algorithms will be of essential importance to fully utilise the advantages of quantum computers.Current quantum hardware rarely fits the algorithmic connectivity requirements so that ab initio implementations of (multi-body) quantum gates are typically not possible. Although there exist ion-based quantum computers that provide intrinsic all-to-all connectivity, these are usually limited to a few tens of qubits. In many cases, quantum devices, particularly those where the position of the information carriers is physically fixed, provide two-dimensional grids of qubits with nearest-neighbour connectivity, like for example square, hexagonal or octagonal lattices. Thus, many physical quantum systems provide only a limited connectivity between the physical qubits. Therefore, arbitrary connectivity is often emulated by costly SWAP networks or shuttling operations, manoeuvring quantum states, physical qubits, respectively.

[0007] The quantum states of the physical qubits may be swapped by performing SWAP gates onto pairs of physical qubits. Swapping the quantum states of at least two physical qubits such that modifies, especially permutes, the mapping of logical qubits to the physical qubits. When an instruction of a quantum algorithm instructs to perform a two-qubit gate on two logical qubits and the modified mapping is such that the two physical qubits, to which the two logical qubits arc assigned, arc connected, physically performing a two-qubit quantum operation on both physical qubits is possible. Typically, for boing "connected" the two physical qubits arc arranged adjacent to or at least in proximity of each other, which allows for performing a two-body quantum operation on the two constituents. Usually, SWAP gates need to be performed several times during performing a quantum computation implementing a quantum algorithm to assign different pairs of logical qubits (on which a two-body quantum operation should be performed according to an instruction of the quantum algorithm) to connected physical qubits.

[0008] A disadvantage of this approach is that SWAP gates are relatively inefficient in many physical quantum systems. For instance, one SWAP gate may be realized by applying three CNOT gates sequentially. The circuit depth, i.e. the total number of non-parallel quantum operations, and the gate count, i.e. the total number of quantum operations, thus strongly increases by the physical implementation of the quantum algorithm. This leads to longer runtimes of the quantum computation and the necessity to implement more complex sequences of potentially faulty quantum operations. Further, the physical qubits are affected by errors which may be increased by a longer runtime or by the application of faulty quantum operations. A reduction of the runtime will decrease the error rate due to errors caused by idle time. A reduction of the physical quantum operations will further decrease the error rate due to errors caused by faulty quantum operations.

[0009] Recently, parity label tracking was introduced as a compelling alternative to SWAP networks enabling the redesign of established algorithms with reduced gate count and depth.In this approach physical qubits carry a logical (parity) label which can be altered throughout a corresponding algorithm by Clifford operations. However, there is no general approach for finding quantum circuits implementing quantum algorithms via minimizing gate-count and circuit depth which are tailored to the connectivity limitations of the physical qubits.

[0010] SHORT DESCRIPTION OF THE INVENTION

[0011] An object of the present invention is to find an output quantum circuit for any given unitary corresponding to a quantum algorithm implemented on any hardware, wherein the output quantum circuit is gate count and depth optimized.

[0012] A solution to the above-mentioned problem is provided by a computer-implemented method for compiling an input unitary acting on a set of logical qubits to an output quantum circuit operable on a quantum system comprising a plurality of output qubits and by an output quantum circuit operable on a quantum system comprising a plurality of output qubits, wherein the output qubits of the quantum system are arranged in accordance with a connectivity mesh, wherein nodes of the connectivity mesh represent possible sites for the output qubits of the quantum system and each edge of the mesh indicates that quantum interactions between the output qubits of the quantum system connected by one of the edges are possible, comprising the following steps:

[0013] ■ providing the connectivity mesh of the quantum system;

[0014] ■ assigning an index to each of the logical qubits;

[0015] ■ extracting a set of target labels from the input unitary, wherein the target labels correspond to a set comprising at least one of the indices of the logical qubits; ■ compiling circuit building blocks implementing a subset of the target labels, wherein the circuit building blocks comprise body path gates and / or leg gates acting on the output qubits, wherein compiling the circuit building blocks comprises: o defining a tree comprising a subset of edges and a subset of nodes of the connectivity mesh, wherein the tree comprises a body with at least one body node representing a site for an output qubit, wherein the body comprises at least two output qubits at two body nodes and at least one path connecting all body nodes of the body, and / or at least one leg with at least one leg node representing a site for an output qubit, wherein the at least one leg node is connected by an edge with at least one body node;

[0016] o adding a body path gate to the output quantum circuit for each body node along the path and / or adding a leg path gate to the output quantum circuit for each leg node;

[0017] ■ for at least one of the target labels of the input unitary, adding a single-qubit gate to the output quantum circuit, wherein the single-qubit gate acts on the output qubitand at the moment (means: moment in the output quantum circuit) on which the target label is implemented due to the gates of the circuit building block.

[0018] The above-described method for compiling an input unitary to an output quantum circuit is generic and easily adaptable for a wide range of contemporary quantum hardware architectures. It further enables a generic construction recipe to implement quantum algorithms, which are given by the input unitary, on specific quantum computational hardware with certain connectivity limitations and at the same time minimize the gate-count and circuit depth. In a highly favourable manner, the inventive output quantum circuit demonstrates a reduction in the average gate count in comparison to prior art quantum circuits. In fact it significantly reduces the average number of quantum gates per interaction required for the implementation of two- and many-qubit interactions compared to previous approaches.

[0019] Any quantum computation is described by an input unitary relating to a set of (in general abstract) logical qubits. An exemplary physical implementation of the input unitary may be to assign a logical qubit to each output qubit of the quantum system. The physical implementation means that the input unitary is executed by the physical quantum system, according to the invention it is executed via the output quantum circuit. Via indexing the logical qubits these indices can be transferred to the output qubits. The indices of the logical qubits tell which operations must be implemented on which logical qubits for the given input unitary. For example, an operation on logical qubits one and two would have the indices one and two. With the help of the circuit building blocks necessary target labels, containing one or more of these indices, can be implemented on the output qubits. In other words, after implementing the target labels, an output qubit then relates to one or more logical qubits and necessary single qubit gates can be implemented on this output qubit. Implementing the single qubit gates is done at the correct moment of the output quantum circuit, meaning after applying certain circuit building blocks onto the output qubits, such that the required target labels are achieved.

[0020] In certain embodiments the eigenstates of the logical qubits are, preferably bijectively and linearly, mapped to the eigenstates of the output qubits in a chosen basis. In other words, by the mapping each logical qubit is assigned to at least one output qubit.

[0021] In another embodiment the tree comprises at least one leg, wherein the leg path gate corresponds to a CNOT gate or a gate corresponding to a CNOT gate transformed by a singlequbit basis transformation. The logical action of a CNOT can be understood as encoding the parity information of the two qubits involved, the target and the control qubit, on one qubit. Thus, via CNOT gates the target labels can be implemented on certain output qubits with thehelp of the circuit building blocks. In certain bases the target labels can correspond to logical parity labels.

[0022] Further, the at least one path connecting two body nodes of the body may correspond to a Hamiltonian path.

[0023] In another embodiment the body path gates are double CNOT gate with alternate control qubits or a gate corresponding to a double CNOT gate and / or CNOT gates or a gate corresponding to a CNOT gate, wherein the body path gates act on two output qubits along the path. The double CNOT gate combines a SWAP gate with a corresponding CNOT gate acting on the same qubits. Logically, the double CNOT gate allows to swap the parity information of the two output qubits involved and a subsequent encoding of the combined parity on one of the two output qubits. In fact, concatenations of double CNOT gates allows to systematically distribute target labels from one output qubit to all other output qubits, thus, leading to an exemplary circuit building block.

[0024] The connectivity mesh may correspond to a graph chosen from the group consisting of a complete graph, modular all-to-all graph, a planar graph, a square graph, a path graph, or a heavy hexagonal graph. For all these examples of a connectivity mesh it can be shown that the average gate count is smaller than for known prior art circuits. Note, however, that the connectivity mesh is not limited to the mentioned examples.

[0025] Further, the body path gates may be CNOT gates or gates corresponding to CNOT gates. Such a circuit building block comprising these body path gates can correspond to a decoding circuit building block depending on the underlying connectivity mesh, which allows to retain a permutation of the initial target labels on the output qubits.

[0026] Another aspect of the invention concerns a method of performing a quantum computation on a quantum system comprising a plurality of output qubits, wherein the output qubits of the quantum system are arranged in accordance with a connectivity mesh, wherein nodes of the connectivity mesh represent possible sites for the output qubits of the quantum system and each edge of the connectivity mesh indicates that quantum interactions between the output qubits of the quantum system connected by one of the edges are possible, wherein the quantum computation corresponds to an input unitary compiled via the inventive computer-implemented method or implemented via the inventive output quantum circuit.

[0027] The input unitary may correspond to a quantum Fourier transform or a subroutine of a variational quantum algorithm, preferably of a quantum approximate optimization algorithm.Further advantages, features, aspects and details that can be combined with embodiments described herein are evident from the dependent claims, the description and the drawings.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] A full and enabling disclosure to one of ordinary skill in the art is set forth more particularly in the remainder of the specification including reference to the accompanying drawings wherein:

[0030] Fig. 1 shows circuit building blocks for three different connectivity meshes with the resulting gate counts schematically indicated as a function of the connectivity.

[0031] Fig. 2a - 2c show schematic representations of a double CNOT gate (Fig. 2a), concatenations of double CNOT gates (Fig. 2b) and a double CNOT generator circuit generating all possible two-body terms (Fig. 2c).

[0032] Fig. 3a - 3c show an initialisation circuit building block preparing the input target label set for a special three-body generating circuit (Fig. 3a), the special generator circuit for the input target label set (Fig. 3b) and a three-body generator circuit composed of these special generating circuits (Fig. 3c).

[0033] Fig. 4a - 4c show a special four-body generator circuit (Fig. 4a), a generator circuit composed of these special four-body generator circuits (Fig. 4b) and an exemplary k-body generator circuit including exemplary k-1 body generator circuits (Fig. 4c).

[0034] Fig. 5a - 5b show a circuit diagram of a two-body generator circuit on a quantum system with output qubits arranged according to a linear nearest neighbour connectivity mesh (Fig. 5a) and the equivalent generator circuit for a quantum system with all-to-all connected hardware, that is output qubits, where each output qubit shares an edge with any other output qubits of the quantum system (Fig. 5b).

[0035] Fig. 6a - 6d show a Hamiltonian path on a square grid of nine output qubits (Fig. 6a), a Hamiltonian grid path on a square grid of nine qubits (Fig. 6b), an implementation of a circuit building block on a square grid of nine output qubits based on this Hamiltonian grid path on the square grid (Fig. 6c) and as circuit diagram (Fig. 6d).

[0036] Fig. 7a - 7d show schematically the first four consecutive circuit building blocks combined with a respective double CNOT sequence to pigeonhole target labels to corresponding locations of the connectivity mesh to simplify the decoding (Fig. 7a), schematically the decoding step given by a CNOT chain along a conventional Hamiltonian path (Fig. 7b), theinitialiser consisting of two CNOT chains on a minimal Hamiltonian grid path (Fig. 7c, Fig.

[0037] 7d), where the temporal ordering of gates is indicated by the alphabetic labelling.

[0038] Fig. 8a- 8b show a two-body circuit building block designed for a square gird device with twelve output qubits (Fig. 8a) and the generator circuit build via these circuit building blocks (Fig. 8b).

[0039] Fig. 9 shows the output quantum circuit for two subsequent quantum approximate optimization algorithm cycles implemented on a quantum system with a connectivity mesh given by the 3 * 4 square grid architecture of Fig. 8.

[0040] Fig. 10a and 10b show the output quantum circuit for a quantum Fourier transform implemented on a quantum system with linear nearest-neighbour connectivity (Fig. 10a) and all-to-all connectivity (Fig. 10b).

[0041] Fig. 11a and 11b show an example of a circuit comprised of CNOT gates (Fig. 11a) and the reversed circuit (Fig. 11b).

[0042] Fig. 12a- 12c show concatenated circuits (Fig. 12a) and shifted concatenated circuits (Fig. 12b and Fig. 12c).

[0043] Fig. 13a and 13b show a circuit building block for a heavy hexagonal graph (Fig. 13a) and a two-body generating circuit using these circuit building blocks (Fig. 13b).

[0044] Fig. 14 shows exemplary circuit building blocks for a ladder graph.

[0045] DETAILED DESCRIPTION OF THE INVENTION

[0046] Reference will now be made in detail to the various exemplary embodiments, one or more examples of which are illustrated in each figure. Each example is provided by way of explanation and is not meant as a limitation. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet further embodiments. It is intended that the present disclosure includes such modifications and variations.

[0047] Within the following description of the drawings, the same reference numbers refer to the same components. Generally, only the differences with respect to the individual embodiments are described. The structures shown in the drawings are not necessarily depicted true to scale and may contain details drawn in an exaggerated way to allow for a better understanding of the embodiments.The aim of the present invention is to find a computer-implemented method for compiling an input unitary acting on a set of logical qubits to an output quantum circuit operable on a quantum system comprising a plurality of output qubits 1, wherein the output qubits 1 of the quantum system are arranged in accordance with a connectivity mesh 11, wherein nodes 111 of the connectivity mesh 11 represent possible sites for the output qubits 1 of the quantum system and each edge 112 connecting nodes 111 of the mesh 11 indicates that quantum interactions between the output qubits 1 of the quantum system connected by one of the edges 112 are possible. In Fig. 1 three examples of connectivity meshes 11 are shown, namely a linear graph, where the connectivity is given by linear nearest-neighbour interactions, a square grid graph with two-dimensional nearest-neighbour connectivity, and a complete graph with all-to-all connectivity.

[0048] The output qubits 1 may correspond to representations of physical qubits and these terms are used equivalently in the following. The physical qubits are the qubits of a quantum system, onto which quantum operations can be applied.

[0049] The connectivity mesh 11 may be a two-dimensional mesh. The mesh 11 may be embeddable in a two-dimensional manifold, such as in a plane. The nodes 111 of the mesh 11 represent possible sites for the output qubits 1 of the quantum system. The connectivity mesh 11 generally indicates, by its edges 112, which output qubits 1 of the quantum system can interact during a quantum computation when arranged on nodes 111 of the mesh 11. The nodes 111 of the mesh 11 need not be associated with one fixed position in space.

[0050] The connectivity mesh 11 provides physical information about the quantum system, in particular about which output qubit 1 can interact with which other output qubit 1 during any quantum computation. Since quantum interactions in many physical implementations are only realizable between output qubits 1 that are close to each other (short-range interactions), the connectivity mesh 11 and particularly its edges 112 can in this case be viewed as reflecting what is close or short-ranged in the quantum system. The computer-implemented method for compiling an input unitary acting on a set of logical qubits to an output quantum circuit operable on a quantum system comprising a plurality of output qubits 1 explicitly or implicitly considers the connectivity mesh 11 and the physical information about the quantum system contained therein. For an explicit consideration, data about the structure and / or size of the connectivity mesh 11 may be passed as input to the method. Alternatively, the method may implicitly assume a specific structure and / or size of the connectivity mesh 11.

[0051] The output qubits 1 of the quantum system may be superconducting qubits, quantum dots, atoms, ions, photons or any other physical system in which a qubit can be encoded.The input unitary relates to logical qubits and the inventive method allows to compile this input unitary to an output quantum circuit implementable on a physical quantum system. During a quantum computation the quantum state of the output qubits 1 is evolved by performing a sequence of quantum operations on the physical qubits. Quantum operations may be quantum gates (i.e., unitary operations), measurements, or initializations of qubits, among others. Single-body quantum operations, specifically single-qubit operations, are performed on a single output qubit 1. Many -body quantum operations, specifically two- or multi-qubit operations, are performed on at least two output qubits 1. Performing many -body quantum operations demands that the at least two physical qubits 1 on which the quantum operation should be performed are "connected". In other words, two or more qubits being "connected" means that many -body quantum operations may be performed on those qubits. Specifically, this may demand that said qubits 1 are arranged in a close physical proximity of each other, that the physical quantum system provides electrical connections between said output qubits 1 or that, in general, physical interactions can be implemented between said output qubits 1. According to the invention the connectivity of the output qubits is described via the connectivity mesh 11. Note, that the connectivity mesh 11 may change during the runtime of a quantum computation, especially, when the output qubits 1 are moveable. In this case, the connectivity mesh 11 may be attained only in different time steps.

[0052] The linear graph in Fig. l is a one-dimensional chain of output qubits 1 which are connected via connections only to their nearest neighbours, (often called "linear nearest neighbor" or LNN connectivity). The output qubits 1 arc connected to at most two further output qubits 1. The connectivity is thus strongly limited. The output qubits 1 may be arranged on a straight line or on a more general curve ("linear" may mean both, straight line or curve, and refers to "one-dimensional"). Many quantum physical systems, such as ions in linear ion traps, may be limited to such a connectivity.

[0053] Any quantum computation may be described by an input unitary. The input unitary acts on a set of logical qubits, which are in general abstract. The input unitary may be implemented via a quantum circuit on a physical quantum system. Depending on the connectivity mesh 11 describing the connectivity of the quantum system, this quantum circuit contains different quantum gates. A straightforward physical implementation of the input unitary may be to assign a logical qubit to each output qubit 1. In order to relate the logical qubits to the necessary quantum gates of the output quantum circuit, the logical qubits are indexed. For instance, a controlled-NOT gate relating to logical qubits one and two may be denoted by CNOT12. The logical qubits may be indexed with an incrementing index from top to bottom. Each output qubit 1 may be referred to by a logical label corresponding to an index of the logical qubits or a set comprising at least one of the indices of the logical qubits. The initialquantum state of the output qubits 1 may correspond to a state where each logical label corresponds to an index of a logical qubit.

[0054] In Fig. 1 also schematic representations as well as circuit diagrams of circuit building blocks 4 implementing a subset of the target labels 2 for the corresponding connectivity meshes 11 are shown. The schematic representations illustrate how circuit building blocks 4 can be compiled via defining trees 3, see also Fig. 6a and 6b for a detailed example of a tree 3.

[0055] Each tree 3 comprises a subset of edges 112 and a subset of nodes 111 of the connectivity mesh 11 and a body 31 with at least one body node 1111 representing a site for an output qubit 1. In certain embodiments the body 31 comprises at least two output qubits 1 at two body nodes 1111 and at least one path 6 connecting all body nodes 1111 of the body 31. In Fig. 1 the body 31 for the linear graph and the body 31 for the square grid comprise a path 6. Further, the tree 3 may comprise at least one leg 32 with at least one leg node 1112 representing a site for an output qubit 1, wherein the at least one leg node 1112 is connected by an edge 112 with at least one body node 1111. The tree 3 for the linear graph in Fig. 1 does not comprise a leg 32, whereas the tree 3 for the square grid in Fig. 1 does comprise nine legs 32 in this example. Further, the tree 3 for the complete graph in Fig. 1 does comprise a single body node 1111, thus, a body 31 without a path 6, but it comprises four legs 32 for the example with five output qubits 1 in Fig. 1.

[0056] As can be seen in the circuit diagrams in Fig. 1 for the circuit building blocks 4 a body path gate 41 is added to the output quantum circuit for each body node 1111 along the at least one path 6 and a leg path gate 42 is added to the output quantum circuit for each leg node 1112. Thus, for the example of the complete graph, no body path gate 41 is added to the output quantum circuit and for the example of the linear graph no leg path gate 42 is added to the output quantum circuit.

[0057] Further, in Fig. 1 the corresponding gate count of the circuit building blocks 4 depending on the connectivity of the output qubits 1 is shown.

[0058] Details regarding the construction of the circuit building blocks 4 and the output quantum circuit are explained in the following.

[0059] Target labels, target label tracking and k-body operators

[0060] Quantum computers inherently rely on entangling gates to systematically distribute information and perform computations. A typical (Clifford) gate utilised for this purpose is the CNOT gate. The logical action of a CNOT can be understood as encoding the parity information of the two qubits involved, the target and the control qubit, on one qubit. In the z-basis, a CNOT encodes the z parity information on the target qubit, while in the x basis a CNOT gate encodes the x parity information on the control qubit. To capture this abstract notion of the action of a CNOT on a set of physical qubits Q = {1,..., n} we attribute to each qubit j ∈ Q a logical label Cj. These logical labels Cj can be interpreted as the logical z parityencoded on the qubit j. In this language, the action of the CNOT gate, CXc,t, on the sequence of labels f = (fl,..., fn) is given by

[0061] (fl,..., fn) CXc,t = (f l,...,ft-l,ftA fc,..., fn),

[0062] where A denotes the symmetric difference operator. Here, the notation that operators act from the right onto sequences of labels is adopted. In the following we denote the symmetric difference of two labels with shorthand notation fcft:= fcA ft as well as we waive the set notation. For example, if the logical label fi contains the indices p and q we denote fi = pq. Moreover, if not explicitly stated differently, an initial physical state with logical labels fj = j for all j ∈ Q is assumed.

[0063] It is emphasised that the logical labels together with the symmetric difference operation as an addition form a vector space V over GF(2) where the empty set is the zero vector. Interpreting the CXc,t gate as an operator on the n-fold direct product Vn, the CXc,t operator is a bijective operator which maps label sequences that form a basis in V to another label sequences that are again a basis in V. Hence, starting with a label sequence which is basis in V, the logical labels form a basis at any moment within a CNOT circuit and in particular, none of the labels will be empty.

[0064] This furthermore implies that physical qubits, i.e. output qubits 1, are not bound to their initial logical labels. Applying a physical single-qubit gate that implement the logical operation on qubit i then translates into a corresponding logical operation on all the qubits whose parity information is encoded in the label of the physical qubit i,, where the single-qubit operators (j are diagonal in the z-basis. More precisely, a logical operation

[0065]

[0066] (j, can be translated into the Clifford-conjugate physical circuit

[0067]

[0068] = c(f, i) o<;i o c(f, i)t

[0069] where C(f, i) represents a Clifford circuit that produces the target label f at physical qubit i (with the use of CNOT gates acting on label sets according to the equation (fl,..., fn) CXc,t = (f l,...,ft-l,ftA fc,..., fn)). In contrast, the z-diagonal single-qubit operators do not change the labels.

[0070] In general, we define a circuit as a sequence of time steps - called moments - enumerated from 1 to d. Each of these moments contains a number of non-overlapping gates where we require for non-empty circuits at least one gate in the first and in the last moment. The depth of the circuit is d and the gate count or size is the number of gates contained in the circuit. Moreover, A O B denotes the concatenation of two circuits A and B, where the concatenated circuit is the circuit which first contains all moments from A and then all moments from B, and C†the adjoint circuit of some circuit C. An example of a concatenation of circuits is also shown in Fig. 12a, where the three circuits Cl, C2 and C3 are concatenated.For exponentials of logical operators (j it straightforwardly holds that exp (— ia Hje^ ^j)= C

[0071]

[0072] (£, i) O exp(-ia^i) O C(£, i)†

[0073] with a ∈ [0, 2π). If we aim to encode a logical k-body operator, we need to generate the corresponding target label £ with exactly k elements using CNOT circuits C(£, i). As an example, consider a logical two-body rotation RZZij(a) = exp(-iaZiZj) where Zi denotes the z Pauli matrix. RZZij(a) can be implemented using a physical single body rotation gate Rz'(a) = exp(-iaZj) at physical qubit j if the target label 2 of qubit j carries the parity information of the physical qubits i and j, i.e., if physical qubit j carries the label £j hi. Given an initial state with the labels hi and £j we deduce RZZij(a) = CXi,j Rz>(a) CXi,j. The identity can readily be verified by application of these operators on a quantum state (in the z basis). Similarly, a series of logical operators can be encoded with

[0074] I

[0075]

[0076] l( / ,k)es exp(-ianje / < / ) = O( / ,k)esC(£, k) O exp(-ia^k) O C(£, k)†,

[0077] where a£ ∈ [0, 2π) and the set S of tuples (£, k) specifying a target label f and an output qubit k. Note that the left hand side of the equation above does have no dependence on the physical qubits specified in S. This reflects the fact that a logical operator is not aware of the device on which eventually it is implemented. From here it is also clear the target labels 2 according to the inventive claims correspond to a label of an output qubit 1 at a certain moment of the output quantum circuit. At a certain time step - moment - of the quantum circuit a required target label £ is achieved at output qubit k and then the single qubit gate acting on qubit k can be applied. In certain bases the target labels 2 correspond to logical parity labels.

[0078] The inverse Clifford sequences C(£, i)†may be used to decode the produced target label 2 to return to the initial state after each application of a physical non-Clifford gate. This is where a target label tracking can yield an advantage: instead of decoding after every logical nonClifford gate, the target labels 2 can be tracked and the next target label 2 can be encoded using potentially shorter Clifford circuits. Eventually, the decoding can be applied once after the last physical non-Clifford gate I

[0079]

[0080] ]( / ,i)es exp(-ioq < / ) = (O«i)Gs,P=i...|S|CP(f i) O exp(-ioqO) ) O Cciean, where Cp(£, i) is a Clifford circuit that generates the target label £ at output qubit i when applied to the label set generated by Cp-1 and C

[0081]

[0082] clean=O(^i)eS,p=|S|...lCp(£, i)†•

[0083] Note that due to potential cancellations, the actual size and depth of the circuit Cciean can be significantly smaller than the above formula seems to imply. Furthermore, as long as the sequence of logical operators to encode forms a pairwise commuting set, their order is irrelevant. However, depending on the order of physical operators, the corresponding recursively defined Clifford circuits Cp can drastically differ in depth and count. Optimising the order of physical operators with respect to the total gate count or depth of the corresponding Clifford circuits Cp is in general a NP-hard problem akin to the traveling salesman problem.Average count and normalized depth

[0084] Diagonal non-Clifford gates leave the logical labels unchanged as shown above. As long as the label tracking is maintained, relevant non-Clifford gates can always be inserted at corresponding moments of the circuit, i.e., just after a circuit Cp(£, i) produced a target label 2 of interest. Thus, in the following we focus solely on the Clifford parts that generate the desired target labels. Furthermore, in the following it is assumed that Clifford circuits constitute CNOT circuits without loss of generality. Note, that all CNOT gates throughout the application are considered to be CNOT gates or a gate obtainable from a CNOT gate transformed by a single-qubit basis transformation, thus, a gate corresponding to a CNOT gate.

[0085] Consider n qubits and a set L(n) of non-trivial labels over these qubits. We say that a CNOT circuit C(n) generates the labels L(n) from a starting configuration £ = (£1,..., £n) if each label in L(n) appears at least in one moment of the circuit C(n). Note that if C(n) generates the labels L(n) from £ it also generates any subset of L(n). For such a generator circuit C(n) of the label set L(n) we define the average CNOT count as pn(C(n), L(n)) = size (C(n)) / |L(n)| with the total CNOT count size (C(n)) of C(n). Furthermore, we define the asymptotic average CNOT count of some generator circuit family C and some label family L, where C contains circuits C(n) and L some label sets L(n) on n qubits, as

[0086] p(C, L) = lim

[0087]

[0088] pn(C(n), L(n)).

[0089] A similar measure can be defined for the CNOT depth of the generator circuit family C. For this we recognize that every moment of C(n) allows at most [n / 2] CNOT gates applied in parallel. Thus, we define v(C, L) = lim infn→∞(depth (C(n))n) / (2|L(n)|), where depth (C(n)) denotes the depth of the CNOT circuit C(n).

[0090] As discussed above, it is evident that every logical many body operator, that is any input unitary, can be associated with one pair of Clifford CNOT circuit combined with a physical single-body (non-Clifford) gate. The encoding of many-body operators thus requires at least one CNOT gate per many-body operator since we demand all many-body operators to be different and generating target labels can only happen via application of CNOT gates. Thus, we conclude that for any generator circuit C(n) of L(n) we expect pn(C(n), L(n)) > 1.

[0091] For efficient generator circuits with low average gate count of large enough label sets, expressed in the property limn→∞|L(n)| / n —> co, we can draw some basic conclusions.

[0092] For that let us assume we find a generator circuit U(n) of L(n)with pn(U(n), L(n)) = 1 + y, i.e., using only (1 + y)|L(n)| many CNOT gates. Then, using generic counting arguments, one can demonstrate that at least (1 - 2y)|L(n)| of all (1 + y)|L(n)| CNOT gates used in U(n) transform labels £ ∈ L(n) into other labels £' ∈ L(n), where £' has not been generated in prior moments of U(n). As y → 0, almost all gates of U(n) have to act in this way. By this property, we call CNOT gates implementing the above mapping typical CNOT gates.With this in mind we can employ further counting arguments for linear graphs describing quantum systems with linear nearest neighbour interaction (LNN) to find lower bounds for possible values of y. In particular, in case the label set L(n) consists of labels which cannot be pairwise combined to form other labels of L(n), i.e. if £i£j ∉ L(n) with {£i,£j} ∈ L(n), then y > 1 / 3. This is notable since label set with this property appear frequently in subsequent sections. As an example, consider the set of all three-body labels for n qubits on a LNN device: combinations of two three-body labels cannot yield another three-body label. Similar considerations hold for all odd-bodied label sets or label sets where all labels share (at least) on constituent. In all these cases an increased theoretical lower bound of pn> 1 + 1 / 3 applies.

[0093] Generator circuits for two- and three-body operators with linear nearest neighbour (LNN) connectivity:

[0094] A scalable quantum circuit for LNN chains that generates all two-body labels with significantly reduced gate count and depth compared to established algorithms combined with corresponding physical non-Clifford single qubit operators can be used to implement all relevant input unitaries corresponding to logical two-body operators diagonal in the z basis. This is very useful for algorithms like quantum approximate optimisation algorithms (QAOA) or the quantum Fourier transform (QFT).

[0095] In certain embodiments the circuit building blocks 4 comprise double-controlled NOT gates, double CNOT gates or DCNOT gates 31, see also Fig. 2a and 2b, DXc,t = CXc,t O SWAP(c,t), which combines a SWAP gate with a corresponding CNOT gate acting on the same qubits. We observe that £DXc,t = £ (CXc,t O (CXc,t O CXt,c O CXc,t)) = £CXc,t(CXc,t O CXt,c O CXc,t) = (£CXc,t(CXc,t)) (CXt,c O CXc,t) = f (CXt,c O CXc,t), for a sequence of labels £, which implies that combined operation can be achieved with only two CNOT gates.

[0096] Logically, the action of a DXc,t circuit can be understood as swapping the parity information of the two qubits involved and a subsequent encoding of the combined parity on qubit c. The DXc,t circuit is depicted in Fig. 2a.

[0097] These two features are essential for an efficient encoding of many -body operators on the LNN chain, where the location of logical parity information on the devices plays a pivotal role. Concatenations of DCNOT gates, which we call a DCNOT chain, allow to systematically distribute logical parity information from one output qubit to all other qubits

[0098] (£1,..., £n) DXC(1,n)= ((£2... £n)£1, £1), where DXO'+ is a chain of DCNOT gates DXC(1’j)= DXM+1O DX1+1,1+2O • • • O DX-1'‘jacting on the physical qubits {i,... j}, as also shown in Fig. 2b. Here and in the following we use the shorthand notation (£2... £n)£l, £1) = (£2£1, £3 £ 1,..., £n£l, £1). Note that a simple CNOT chain is not able to accomplish the same encoding. CNOT chains either encode an increasing number of logical labels or just pair the logical labels of neighboring qubits when applying their adjoint operation. In contrast, DXC(1,n)encodes the logical parity information originally located on physical qubit one withthe logical parity information of all other physical qubits.

[0099] From the label sequence (fl,..., fn), DXC(n)generates all logical two-body labels that include the label fl. Interestingly, we obtain the generator circuit for all two-body labels containing fl and all two-body labels containing f2 from a concatenation of DXC circuits, since ((f2... fn)f

[0100]

[0101] 1, f IjDXC^1) = ((f 3... fn)f2, f2f 1, fl).

[0102] Similarly, we can construct the generator circuit of all two-body labels just from repeated application of the DCNOT chains on a shrinking set of qubits DXN(n)= DXC(n)O DXC(1,n-1)O ' ' ' O DXC(1,2), which we call DCNOT network of type I. Application of DXN(n)on a label set (fl,..., fn) yields (fl,..., fn)DXN(n)= (fnfn-1, fn-lfn-2,..., f2fl, fl).

[0103] Fig. 2c illustrates the generating circuit 5 DXN(n). Now, the CNOT chain CXC^ may be used to restore the original labels (in reversed order)

[0104] (fnfn-1, fn-lfn-2

[0105]

[0106] ,..., f2f l,f 1) CXC™= (fn,..., fl).

[0107] With 0 we denote the reversed circuit which simply maps each CXi,j to CXn-i+l,n-j+l. The reversed circuit of a circuit C may be defined as the circuit with depth d where each moment m contains the reversed CNOT gates of the CNOT gates of the circuit C at the moment m. An Example of a CNOT circuit and its reversed circuit is also shown in Fig. Ila and 1 lb.

[0108] The strategy for a generator circuit that generates all three-body logical parity labels L(n)3 builds on the two-body generator circuit. Here, the central idea is to encode an additional label f s repeatedly on physical qubit 1 just before every application of a DCNOT chain, yielding the modified DCNOT chain DXC'(n)= CXI, 2 O DXC(2,n). The initialisation circuit building block 4 preparing the input label set for the special three-body generator is depicted in Fig. 3a. The logical label f s is a special label in the sense that the corresponding modified DCNOT network of type I, DXN(n), generates all logical three body labels that contain the label fs. For this reason, we also call the modified DCNOT network of type I, which is defined as DXN(n)= DXN(n)3,n-2, where DXN'(n)3,i= DXC'(i+2)O DXN'(n)3,i-1, 2 < 1 < n - 2and DXN'(n)3,2= DXC'(3)O CX1,2, a so-called special three-body generator. Application of DXN(n)on the label sequence (fs, fl,..., fn-1) yields

[0109] (fs, f 1..., fn-l)DXN'(n)= (fs, fn-lfn-2, fn-2fn-3,..., f2f 1, f Ifs) and DXN'(n)is generating the label set {fsfifj | 1 < i < j < n - 1} from the label sequence (fs, f 1..., fn-1). Therefore, DXN(n)generates all special target three-body labels that include f s. However, the output label set has a slightly inconvenient form as the special label f s is encoded on physical qubit 1 and n. For a LNN chain with periodic boundary conditions, f s can be annihilated on qubit n using a single CNOT gate. However, given open boundary conditions, extra SWAP operations would be required to achieve the same. These problems are circumvented recognizing that the circuit DXN(n)constitutes a special three-body generator not only from the label sequence (fs, fl,..., fn-1) but also from the label sequence (fs, (f 1... fn-l)fs). Then, application of DXN(n)yields (fs, (fl... fn-l)fs) DXN(n)= (fs, fn-lfn-2, fn-2fn-3,..., £2£1, £1) and therefore we reached the same output as in the equation before, except for the isolated special label. The label set (£s, (£1... £n-l)£s) can be obtained via two simple CNOT chains. The first CNOT chain prepares the following label set, as also shown in Fig.

[0110] 3a: (£s, £1,..., £n-l)(CXC(n))†= (£s, £s£l, £1£2..., £n-2£n-l)

[0111] and via a second CNOT chain one can transform that into the required input (£s, £s£l, £1£2,..., £n-2£n-l)CXC(2’n)=(£s, £s£l, £1£2..., £n-2£n-l)=(£s, (£l...£n-l)£s). Each of these CNOT chains correspond to circuit building blocks 4.

[0112] The combined building blocks DXN(n)3= (CX2,3O CXC'(3,n)) QI DXN(n)are depicted in Fig. 3b and is called DCNOT network of type II where CXC'(3,n)is again a CNOT chain containing the same CNOT gates as CXC(3,n)but uses different shifts. Note that DXN(n)3 is also a special three-body generator as indicated by the number 3 in DXN(n)3, since it generates all three-body logical labels that include the special label £s. Importantly, DXN(n)3 maps the input label set on an output label set reusable for forthcoming special three-body generators (£s, £s£l, £1£2..., £n-2£n-l) DXN(n)3: (£s, £s£1, £1£2,..., £n-2£n-1) → (£s, £n-1£n-2, £n-2£n-3,..., £2£1, £1).

[0113] The label set on the right-hand side of this equation has the same structure of logical labels encoded on qubits {2,..., n} (in reversed order) as the input label set has on qubits {1,..., n}. Furthermore, the special label £s is isolated on physical qubit 1. Thus, in the next step, we can now use £1 as the special label and apply a reversed DXN3(2,n)circuit, which is a special three-body generator for the label set {£1,..., £n-l } acting on the physical qubits {2,..., n}. Note that the logical label £s is not being considered in the next step since £s is isolated at qubit 1. Proceeding this strategy on a shrinking set of qubits, we form a generator circuit G(n)3 for all possible three-body logical labels. The corresponding circuit is schematically depicted in Fig. 3c. After the application of the last DCNOT network of type II (that is only acting on three qubits) and a final CNOT gate that acts as a clean-up step, the output label sequence of G(n)3is (£1, £3,..., £4, £2). If we demand the input and output label set to coincide with (£1,..., £n), this can be achieved with a sorting network, which has O(n) depth and O(n2) gate count, which is cheap in comparison to the O(n2) depth and O(n3) gate count of G(n)3. This circuit construction has the neat advantage that consecutive special three-body generators can partially be executed in parallel with an O(n) overlap. Eventually, this leads to a reduced total depth of n2+ O(n), whereas the total gate count amounts to 1 / 3 n3+ O(n2). This result can readily be deduced from the involved building blocks: every special three-body generator is mainly based on DCNOT gates (up to O(n) additional CNOT gates), whereby every DCNOT gate (consisting of two CNOT gates) generates one required three-body label.

[0114] In total, there are |L(n)3| = C(n,3) = 1 / 6 n3+ O(n2) three-body labels. Thus, in leading order, we expect a total count of 2 / 6 n3gates. This yields an asymptotic average gate count of p(Gs, L3) = 2 as well as an asymptotic depth of v(Gs, L3) = 3. We note that for large enough n also most of the special three-body generator circuits must obey the same lower bounds since two labels of the corresponding special label set cannot be combined to form another label from the set.This holds equivalently for every special label set (in which all labels share at least one constituent).

[0115] To obtain an average asymptotic gate count smaller than two on the LNN chain, this requires a finite fraction of labels from L(n)3 to be created using (on average) only a single CNOT gate. Constructing such a circuit becomes exceedingly difficult, if not outright impossible, even for moderately large values of n (~ 10).

[0116] Generator circuits for arbitrary many-body operators

[0117] The above described concepts can be used to construct special four-body generators. To do so we recycle the optimised three-body generator circuit, with inserting an extra label on top of the existing ones. Doing so for the special three-body generator circuit, CNSCX just requires one extra CNOT gate to encode an additional label C s' on the physical qubit that holds the special label f s. Then, the circuit CXSN generates all four-body labels that include f sf s'. However, if we want to utilise the full depth-optimised three-body generator circuit G3 via mirroring every second special 3-body generator, we need to encode the label fs' also on the other end of the LNN chain. Let us assume a similar initial label set as used for the three-body generators, (Cs', fs, (€2... fn-l)fs) encoded using the tools of the latter section. We now use a DX chain to encode the label Cs' on physical qubit n (Cs', fs, (€2...fn-l)fs) DXC(1,n)= (fs'fs, (€2,..., fn-l)(fs'fs), Cs'). Next, we can apply SGN l'h acting on the first n - 1 physical qubits which generates all four-body labels with fs'fs and yields the output labels (

[0118]

[0119] fs'fs, (€2,..., £n-l)(£s'£s), Cs') SG(1’^1)3= (fs'fs, fn-lfn-2... £3£2, €2, Cs').

[0120] Importantly, the output label set of this equation encodes the same label structure (in reversed order) as the input state in (Cs', fs, (€2...fn-l)fs) DXC(1,n)= (fs'fs, (€2,..., fn-l)(fsTs), Cs') before applying the CNOT chain. Thus, to generate the next set of four-body terms, the ones that carry Cs' and €2, we can now apply the qubit reversed circuit CX2,3Q CX3,4Q ' ' ' O CXn — 3,n — 20 C

[0121]

[0122] SC^’n~2^QCNS^1,n~^. This pattern can be repeated and eventually yields a special four-body generator SGN l 1generating all four-body labels that include C s'. We conclude the circuit with a trivial unwinding of the latest four-body term and a cleanup step of 0(n) CNOT count and depth.

[0123] A detailed depiction of the special four-body generator circuit is shown in Fig. 4a.

[0124] Similar to the design of the three-body generator G3, we can build a four-body generator G4 by concatenating n-3 special four-body generators each with different special labels. Thereby, later special four-body generators ignore all labels that have been special in previous parts of the circuit, until the last special 4-body generator only acts on 4 qubits. The circuit design is schematically shown in Fig. 4b.

[0125] The circuit construction for four-body generators can now be utilised to constructively design all special k-body generators with k > 4. The strategy here is to recycle the special (k-l)-body generators for the construction of a special k-body generator. To do so, we encode an additional special label- called the super special label f ss into each of the special label Cs ofthe corresponding special (k-l)-body generator. The corresponding circuit then becomes a super special k-body generator, generating all k-body labels with Cssts. After each super special k-body generator, we apply a clean-up step to restore the input labels. Chaining n-k+1 super special k-body generators (with the same super special label Lss) then yields a special k-body generator (i.e. a generator for all labels that contain Lss). The special k-body generators can then be composed into a k-body generator Gk, see also Fig. 4c.

[0126] An interesting feature of this construction of k-body generators Gk is that each Gk inherits the asymptotic average gate count and depth from the corresponding special (k -l)-body generator since for each k we just introduce an asymptotically negligible amount of extra CX gates. Recursively, this yields the asymptotic average gate count for any Gk to be p(Gk, Lk) = 2 and the asymptotic normalized depth v(Gk, Lk) = k.

[0127] All-to-all connectivity

[0128] On all-to-all connected devices logical information of any qubit is accessible from any other qubit. These quantum systems are described via output qubits arranged according to a complete graph, that is, the connectivity mesh corresponds to a complete graph. This is dramatically different to LNN devices where each qubit is (at most) connected to two other qubits. Thus, for the circuit building blocks 4 as also exemplary depicted in Fig. 1 the trees 3 contain a body 31 with a single body node 1111 and several legs 32 with leg nodes 1112.

[0129] On first glance one might assume corresponding generator circuits to reflect these dramatic architectural differences since all-to-all devices render the positioning of labels inconsequential and label transportation via DX chains is unnecessary. On LNN devices, DXi,j= CXi,jO SWAP(i,j)constitutes the basis of the circuit constructions, providing two essential features: (i) it encodes the combined parity information on the control qubit i and (ii) it transports the initial logical parity information of the control qubit i to the target qubit j. Since the positioning of logical labels is irrelevant on all-to-all architectures, this implies that the action of a DX gate can be emulated on an all-to-all device with just a single CX gate. For that, we replace each SWAP gate with a virtual SWAP gate, which virtually swaps the positions of the qubits involved. Virtual SWAP gates are merely a trick to map the output label sequence of a DX gate on the LNN chain to its corresponding counterpart for all-to-all devices. One can use classical software to keep track of all virtual SWAP gates applied and, in the end of the circuit, we obtain the actual qubit layout by reverting all virtual SWAP gates. With this approach, we can now construct DXC and DXN circuits for all-to-all systems. An example DXNaii-to-aii circuit is depicted in Fig. 5b. For comparison, Fig. 5a displays the corresponding LNN circuit. For the label sequence obtained after every moment m of the circuit in Fig. 5b there exists a bijective map to the corresponding label sequence at moment 2m in the circuit of Fig. 5a. In terms of generated labels, the action of DXNaii-to-aii isidentical with that of DXC for LNN systems. However, DXNaii-to-aii only requires half of the gate count and depth as compared to DXN. We can readily extend these ideas to CXSNaii-to-aii and SG3,aii-to-aii circuits, see also Fig. 2c. Their dominant contribution consists of DXCaii-to-aii circuits and, consequently, we achieve (almost) half of the gate count and depth compared to the LNN construction. Likewise, all the generator circuits profit from this inheritance and a detailed count and depth analysis for the generator circuits G(n)k,aii-to-aii of all the k-body labels L(n)k yields an asymptotic average gate count of p(G(n)k,aii-to-aii, L(n)k) = 1 and an asymptotic normalized depth of v(G(n)k,aii-to-aii, L(n)k) = k / 2. Let us emphasize again that p = 1 corresponds to the theoretical lower bound. Thus, all the (special) k-body generators for any k > 1 are asymptotically optimal circuits where on average each CX creates one label of the labels set L(n)k.

[0130] Two-dimensional connectivity meshes

[0131] From the perspective of connectivity, LNN and all-to-all architectures constitute two extreme cases. LNN devices possess the minimal required connectivity so that every qubit can be reached from any other qubit via residual connections. Each qubit has a minimum of one and a maximum of two directly connected neighbour qubits. In the limit of large qubit numbers, the average neighbour count is q = 2. In all-to-all architectures all qubits are directly connected resulting in an average neighbour count of q = n - 1. In between these two extremes, we can allocate other architectures with an average neighbour count 2 < q < n - 1. A prototypical example are square grid devices, however, the results can be directly transferred to any other connectivity mesh 11, as e.g. also shown for heavy hexagon graphs and ladder graphs.

[0132] If we aim to implement generator circuits on square grid devices, from the above described results we can already conjecture an average gate count 1 < p < 2. This follows directly from the connectivity mesh 11 described by square grid devices, where all qubits can easily be connected in a Hamiltonian path, corresponding to a circuit building block 4 defined by a tree 3 with a body 31 without legs 32, see Fig. 6a. A chosen Hamiltonian path can then be used as an effective LNN model to implement the generator circuits outlined above with an average gate count of p(Gk, Lk) = 2.

[0133] Interpreting square grid devices as effective LNN devices might be convenient, however, this neglects a considerable amount of additional connections. To utilise this untapped potential we pursue a different strategy: instead of laying out a Hamiltonian path we define a path 6 so that all qubits of the square grid are either within the path 6 or directly neighbor this path 6. Fig. 6b depicts such a path 6 on a 3 x 3 square grid where the black solid line indicates the path 6 itself, that is the body 31 of the tree 3 with body nodes 1111 and the dashed lines represent the connections to path neighbors, that is the legs 32 of the tree 3 with leg nodes 1112. Subsequently, we denote paths 6 of this kind as Hamiltonian grid path. Qubits are either directly part of a Hamiltonian grid path or they are direct neighbors to a Hamiltonian grid pathin which case we call them Hamiltonian grid path neighbors, that is qubits occupying a leg node 1112. We call a Hamiltonian grid path minimal, if the number of qubits directly contained in it is minimal (and, as consequence, the number of Hamiltonian grid neighbors is maximal), that is, if the number of body nodes 1111 is minimal and the number of leg nodes 1112 is maximal. For example, the path 6 depicted in Fig. 6a represents a Hamiltonian grid path but it is not minimal. In contrast Fig. 6b shows a minimal Hamiltonian grid path on a 3x3 grid. In the following, we demonstrate how minimal Hamiltonian grid paths can be used to efficiently implement the circuit building blocks 4.

[0134] Let us recapitulate the action the DXi,j gate, which encodes the combined parity information, fifj of qubit i and j onto qubit i while transporting the (initial) parity information of qubit i onto qubit j. The latter property allows to use concatenations of DX gates, i.e. DXC circuits, to encode the label fi on all qubits of the concatenation. On square grids, we can use the additional connections to implement this even more efficiently: we use a chain of DX gates, akin to DXC circuit on LNN devices, applied along a defined minimal Hamiltonian grid path (black arrowed lines in Fig. 6b). However, we intertwine it with CX gates that target the direct Hamiltonian grid path neighbors (dashed lines in Fig. 6b). In this way, the corresponding circuit building block 4, subsequently denoted DXCgrid, encodes the label fl onto all qubits of the square grid. Fig. 6c and 6d show a circuit building block 4 DXCgrid following a minimal Hamiltonian grid path for a 3 x 3 square grid. Compared to a corresponding DXC circuit building block (along a conventional Hamiltonian path), DXCgrid saves ~ 1 / 3 of the involved CX gates.

[0135] Following the construction principles outlined above, we repeatedly apply DXC(1,p)grid circuit building blocks 4 on a shrinking set of qubits p for the construction of DXNgrid circuits. To allow this, after each DXC(1,p)grid a final DX sequence is required to pigeonhole labels and allow subsequent circuit building blocks 4 to address all relevant labels. In Fig. 7a we schematically display the first four consecutive DXCgrid circuit building blocks 4 together with the corresponding pigeonhole DX sequence for a 6x4 square grid. As a general rule for the pigeonhole DX sequence, we first transport a label to one of the Hamiltonian grid path neighbors, the next label is transported to the corresponding Hamiltonian grid path node while the third label then occupies the second Hamiltonian grid path neighbor. Concatenation of n DXCgrid circuit building blocks 4 leaves us with target labels 2 depicted in Fig. 7b. Similar to the LNN circuit construction, we can decode the logical labels 2 using a chain of CX gates (Fig. 7b). Depending on the geometry of the device, extra SWAP gates are necessary to breach the boundaries. Note that, as a consequence of the employed Hamiltonian grid path, after decoding we do not retain the initial label order, however, labels can be tracked and appear in deterministic positions dictated by the input unitary.

[0136] As a whole, the outlined steps yield a generator circuit for all two-body labels G2,grid. In comparison to the corresponding LNN circuit derived above, here we save ~ 1 / 3 of the involved CX gates which leaves us with an average CX count of p(G2,grid, L2) = 1 + 1 / 3.Interestingly, in close analogy to LNN, the DXCgrid circuit building blocks 4 can be stacked to form a DXNgrid circuit. Fig. 8a and 8b display the DXNgrid tree 3 with a body 31 and legs 32 corresponding to the circuit building block 4 (Fig. 8a) used in the two-body generating circuit in Fig. 8b together with a decoding CX chain circuit building block 4 for a 3 * 4 square grid. In a similar way as done above, the shifted concatenation then yields a reduced depth of O(6n). Note that a shifted concatenation Cl Os C2 by s > 0 moments is the circuit which contains all moments of Cl as is and in addition all moments of C2 but shifted by s moments to the right. Of course this is only well-defined if the resulting circuit does not contain overlapping gates. Similarly, we set Cl O_s C2 as the circuit which corresponds to the circuit Cl O C2 but with C2 shifted to the left by s moments afterwards. Examples are given in Fig. 12b and 12c.

[0137] Beyond two-body generator circuits, we can repeat the steps derived for LNN architectures using our modified building blocks DXC. The only additional building block required is an initialiser that prepares a label sequence where a special label £ s is encoded in all other labels while keeping the label Is fixed. On a minimal Hamiltonian grid path, this can be done with two CX trees 3, reaching all body nodes 1111 as well as all leg nodes 1112 (see Fig. 7c and 7d) (note that for the square grid, this can equivalently accomplished with a CX chain along a conventional Hamiltonian path with the same count and depth). The alphabetic labelling in Fig. 7c and 7d indicate the temporal ordering of the body path gates 41 and leg path gates 42. With this, special three-body generators are constructed using the initialiser circuit building blocks 4 of Fig. 7c and 7d together with a controlled DXNgrid circuit. Combining this with the second initialiser Fig. 7d and a decoder (Fig. 7b) circuit building block 4 after each controlled DXNgrid circuit this yields the full three-body generator.

[0138] Note that to adapt the LNN circuit to the square grid, we just need to replace the respective circuit building blocks 4 (see Fig. 3) with the ones suitable for square grids. Following this recipe, we obtain a depth overhead originating from the special three-body generators not aligning properly (in contrast to the respective case for LNN devices; compare Fig. 3c). The concatenation of the special three-body generator for square grids SGk, square and its reversed counterpart SGk squarecan be shifted at most by [4 / 3 nJ. This originates from the form of the DXNgrid circuits (compare Fig. 8b) where each constituent DXCgrid circuit is displaced by 6 with a corresponding length of O(4 / 3n).

[0139] We emphasize that this procedure is generic and can be generalized to all connectivity meshes 11 which can be connected in a tree 3 such as e.g. ladders, heavy hexagons or connectivity meshes 11 with non-local connectivity. For a connectivity mesh 11 of interest, we define a minimal Hamiltonian grid path, that is a tree 3 with maximum amount of leg nodes 1112 and minimum amount of body nodes 1111. Based on this, we construct the respective circuit building blocks 4: a DXC circuit, a decoder and an initialiser. Up to implementation details,one can then readily design any k-body generator of interest. Examples of circuit building blocks 4 for a heavy hexagon graph is given in Fig. 13a. In contrast to the square graphs discussed above quantum systems with output qubits 1 arranged according to a heavy hexagon graph do not possess a Hamiltonian graph 6 for the circuit building blocks 4.

[0140] However, as depicted in Fig. 13a all output qubits 1 can be connected according to a tree 3, where (roughly) every 6-th qubit is occupying a leg node 1112. In the bulk of a heavy hexagonal layout every other qubit has three neighbours. Thus, trees 3, based on sub-graphs of heavy hexagons, can have as many as 1 / 4 of the involved qubits 1 occupying leg nodes 1112. Via applying the principles described above along the tree 3 of Fig. 13a, one can immediately conclude the CNOT count of a two-body generator: Since one out of three qubits 1 represents a leg node 1112, for generating three new two-body labels five CNOT gates are required. Thus, the average asymptotic count is p(G2, L2) = 5 / 3.

[0141] Fig. 13b illustrates the construction of the generating circuit for all two-body target labels DXNhex using shifted concatenations of DXNhex circuit building blocks 4. Size and depth of the generating circuit is given by size(DXN(n)hex)=5 / 6 n2+ O(n) and depth(DXN(n)hex)= 5n + 0(1).

[0142] Note that, unlike for square grids, here the lack of a Hamiltonian path complicates the decoding: Instead of a simple CNOT chain, here decoding requires 2n CNOT gates, as can be also seen in Fig. 13b schematically.

[0143] Another example of a circuit building block 4 is shown in Fig. 14 for a connectivity mesh 11 corresponding to a ladder graph. The circuit building blocks 4 in Fig. 14 enable a construction of a size and depth optimised 2-body generator on a ladder graph. Note that,

[0144] while the strategy used for the square grid and heavy hexagon devices is very robust and works for a variety of hardware connectivities, in comparison to the LNN case, it only improves the CX count, but may result in sub-optimal depth scaling. Therefore, here we present an alternative strategy that improves both, count and depth, compared to the LNN case. This, however, comes at the cost of stronger requirements on the hardware connectivity. This approach can be exemplified via the ladder graph. The main idea of the ladder construction is that instead of moving target labels only through a single path, one can also use two paths, corresponding to the two rows of the ladder, see step 1 and step 2 in Fig.

[0145] 14. A further circuit building block 4 is the decoding shown on the right hand side in Fig. 14. With this one can achieve the following size and depth of the generating circuits size(DXN(n))=3 / 4n2+ O(n) and depth(DXN(n))= 3n + O(1).

[0146] Interestingly, these scaling factors are exactly halfway between the constructions for complete graphs and linear graphs, but only require a moderate increase of the hardware connectivity. This strategy could in principle be extended to build k-body generators. However, to keep this depth scaling a higher level of connectivity on the hardware is required, like a checkerboard connectivity. Also, it is possible to extend this strategy to more lanes where labels are moved.The approach of using trees 3 for compiling circuit building blocks 4 can also be applied for LNN and all-to-all architectures, though the respective paths are not recognized as such. In the LNN case, a minimal tree 3 coincides with a conventional Hamiltonian path i.e. there are no legs 32. For all-to-all devices a minimal tree 3 is trivial as its body 31 contains just a single body node 1111 with all other qubits corresponding to leg nodes 1112.

[0147] APPLICATIONS

[0148] Quantum approximate optimization algorithms (QAOA) applied to k-SAT problems QAOA is considered a promising candidate algorithm to solve combinatorial optimisation problems using quantum computers. The algorithm follows a quantum-classical protocol to reach the ground state of an (typically) Ising-like problem Hamiltonian. This requires the repeated application of a parameterised problem unitary Up(P), which encodes the problem Hamiltonian, followed by a parameterised driver unitary Ux(a). The concatenation of a driver together with a problem unitary defines a QAOA cycle. The prepared candidate state after p QAOA cycles |

[0149]

[0150] y(a, P))=I];=i Ux(aj)Up(Pj)|+)®nyields a trial energy expectation value which is then used in a quantum-classical feedback loop to optimise the 2p parameters aj, Pj with j E [1, p]. In prior art the implementation of QAOA for all-to-all connected

[0151] QUBO problems on LNN devices using parity label tracking was discussed. There, the corresponding problem Hamiltonian is described by an all-to-all connected Ising Hamiltonian of the form HQUBO =Sfc=iS7<fc / 7fcZ7Zk+ 2;=i hjZj. The implementation of the problem unitary UQUBO = exp(-ipHquBo) thus requires the encoding of all logical two-body rotation operators exp(-i / 7kZ7Zk), a task that can be accomplished using the two body-generator G2 (intertwined with single-body rotation gates wherever corresponding parity labels are available). Utilizing the circuit building blocks developed above can generalize this to arbitrary higher order binary optimisation (HUBO) problems which we can efficiently implement on a multitude of different architectures. For example, to encode a problem unitary exp(-ipHnuBo) with a problem Hamiltonian of the form

[0152] H

[0153]

[0154] HUBO =££=1lj<klk<iMjklZjZkZt+ SLi lj<kJjkZjZk+ hjZj

[0155] we can use the three-body generator circuit G3 (which is automatically also a generator of all two-body terms). Adapting the required generator circuit G3 readily yields the corresponding on the architecture of interest.

[0156] In prior art it was demonstrated for a QAOA encoding with a depth of O(2n) per QAOA cycle (up to an initialisation encoding circuit). In contrast, a QAOA algorithm for QUBO problems on LNN devices implemented based on the two-body generators G2 would yield a depth of O(4n) per QAOA cycle. To improve on this, we can employ a similar strategy as used for the design of the three-body generators: Instead of concatenating bare G2 generators in subsequent QAOA cycles, we use a shifted concatenation of alternating two-body generators G2 and reversed two-body generators G2. After each two-body generator we apply a decoding CX chain to regain (a permutation) of the original labels. This is followed by shiftedconcatenations of the x rotation gates of the driver unitary. In this way, shifted concatenation of all building blocks achieves a reduction of the total QAOA algorithm depth by a factor ~ 2. Eventually, provided p » 1, this trick yields a depth of O(2n) per QAOA cycle

[0157] on LNN devices. A similar approach can be utilized for all-to-all architectures, reducing the depth per QAOA cycle from O(2n) to O(n).

[0158] For other architectures, a depth efficient implementation of QAOA requires more care. As discussed, the two-body generator tend to become asymmetric so that shifted concatenations of, for instance, G2, grid and G2 griddo not align properly (compare Fig. 8b). Each G2,grid, G2 grid■> respectively, has a depth of O(6n), while their shifted concatenation allows only for an overlap of O( 4 / 3 n). However, if Gk is a generator circuit for all k-body terms from a set of single-bodied labels, then also the adjoint circuit Gk= Gkis a k-body generator from a set of single-bodied labels. Thus, instead of concatenating G2,grid and G2 gridfor subsequent QAOA cycles, we can also concatenate G2,grid and G2 grid~1. This enables a better alignment and a larger overlap of subsequent QAOA blocks using shifted concatenation. In Fig. 9 we schematically illustrate this approach for two subsequent QAOA cycles on the 3x4 square grid architecture shown in Fig. 8a. In between the two Hamiltonian encoding blocks a permutation of the single body labels is available so that we can apply the x rotation of the driver unitary. For p » 1, shifted concatenation of QAOA blocks build from G2,grid and G2 gridreduces the total depth by a factor of ~ 2 so that eventually we obtain a depth of O(3n) per QAOA cycle. This is on par with the best known depth, however saving a factor of 9 / 4 in gate count. Similar approaches can be applied for other two-dimensional architectures. For all the architectures we investigate, we obtain a circuit depth that is at most equal to the best-known result with a simultaneously significant improvement in gate count. In fact in most cases both metrics outperform existing algorithms.

[0159] Quantum Fourier Transform

[0160] The quantum Fourier transform (QFT) constitutes a major cornerstone algorithm in quantum computing and lays the foundation to many seminal algorithms such as the Shor’s factorisation algorithm. In recent years, a multitude of algorithms was developed to implement QFT on various architectures optimising either depth or gate count. Thereby, state-of art approaches typically use architecture optimised SWAP networks. Here we demonstrate how to apply the conclusion drawn in the invention for the design of gate count and depth optimised implementations of QFT adapted to different architectures.

[0161] Recently, in prior art it was shown how parity label tracking can yield reductions in gate count and depth when implementing QFT on LNN devices. Up to single-qubit z rotations, the QFT circuit can (mainly) be understood as a combination of DXC circuits neatly intertwined with single-qubit Hadamard gates. Fig. 10a depicts the corresponding QFT output quantum circuit. In between subsequent DXC we add the necessary single-body z rotations and Hadamard gates, which we decompose into z and x rotation gates. Notably, aside from single-qubit gates, the QFT implemented in this way only uses DXC circuits together with a final CX chain as a cleanup / decoding step. Thus, by replacing the respective building blocks we can easily adapt this approach to other architectures. In essence, this amounts to replacing each DXC circuit with its corresponding counterpart on the architecture of interest and inserting corresponding single-body z rotation gates. For instance, using the mapping established here, we can map the circuit of Fig. 10a to a corresponding output quantum circuit optimised for all-to-all devices shown in Fig. 10b. By virtue of mapping DXC to DXCaii-to-aii, we can directly conclude that the CNOT gate count and depth of the algorithm halves.

[0162] Analogously, once a DXC circuit together with a decoding circuit is available on a given architecture, implementing a corresponding QFT circuit is straightforward. The obtained average count and depth of respective DXN circuits can then directly transferred also to the corresponding QFT implementation (up to single-qubit gates). Notably, the implementations can significantly improve the gate count while the depth of our algorithms is at most equivalent with the best known state-of-the-art implementations.

[0163] Summary

[0164] Efficient quantum algorithms constitute a cornerstone for the development of quantum computing. The invention contributes to this development by establishing generic algorithmic tools for the efficient implementation of logical many-body operators on quantum devices with typical contemporary architectures. This is done via a method for compiling a given input unitary to an output quantum circuit depending on a connectivity mesh 11 describing the underlying quantum system. Resulting output quantum circuits are highly optimised both in gate count and circuit depth and significantly outperform competing output quantum circuits for known algorithms. Using the inventive circuit building blocks 4 we construct generator circuits that are surprisingly close to the provable lower bound or - in the case of all-to-all connected devices - even align with it.

[0165] Further, a generic framework for the construction of generator circuits using the circuit building blocks suitable for a wide range of architectures is derived and the role of connectivity is analysed. Thereby, we find that even moderate increments in connectivity can yield significant efficiency improvements. Five exemplary different devices described by different connectivity meshes 11 are investigated in detail: LNN devices, heavy hexagon devices, square grid devices, ladder devices and all-to-all devices. The average gate count of the derived generator circuits interpolates from LNN with an asymptotic average gate count of p = 2 over heavy hexagon, p = 5 / 3, square grids, p = 4 / 3, and ladder p = 3 / 2, to all-to-all with p = 1, where p = 1 corresponds to the theoretical lower bound. The developed formalism can be understood as a means to map the output quantum circuits between architectures of different connectivity. This lets us conjecture that the class of optimal circuits derived within our formalism extends beyond the all-to-all architecture. As a first step in this direction we prove that p > 1 (in fact we find p > 1 +1 / 13 for generator circuits of odd-bodied label stets onLNN devices). Further, the inventive compilation is investigated for the implementation of two important quantum routines corresponding to certain input unitaries: the QAOA applied to (hyper)-graph binary optimisation problems and the seminal quantum Fourier transform and its approximation on all-to-all architectures.

Claims

Claims:

1. A computer-implemented method for compiling an input unitary acting on a set of logical qubits to an output quantum circuit operable on a quantum system comprising a plurality of output qubits (1), wherein the output qubits (1) of the quantum system are arranged in accordance with a connectivity mesh (11), wherein nodes (111) of the connectivity mesh (11) represent possible sites for the output qubits (1) of the quantum system and each edge (112) of the connectivity mesh (11) indicates that quantum interactions between the output qubits (1) of the quantum system connected by one of the edges (112) are possible, comprising the following steps: o providing the connectivity mesh (11) of the quantum system;o assigning an index to each of the logical qubits;o extracting a set of target labels (2) from the input unitary, wherein the target labels (2) correspond to a set comprising at least one of the indices of the logical qubits;o compiling circuit building blocks (4) implementing a subset of the target labels (2) on the output qubits (1), wherein the circuit building blocks (4) comprise body path gates (41) and / or leg gates (42) acting on the output qubits (1), wherein compiling the circuit building blocks (4) comprises:■ defining a tree (3) comprising a subset of edges (112) and a subset of nodes (111) of the connectivity mesh (11), wherein the tree (3) comprises a body (31) with at least one body node (1111) representing a site for an output qubit (1), wherein the body (31) comprises at least two output qubits (1) at two body nodes (1111) and at least one path (6) connecting all body nodes (1111) of the body (31) and / or at least one leg (32) with at least one leg node (1112) representing a site for an output qubit (1), wherein the at least one leg node (1112) is connected by an edge (112) with at least one body node (1111);■ adding a body path gate (41) to the output quantum circuit for each body node (1111) along the at least one path (6) and / or adding a leg path gate (42) to the output quantum circuit for each leg node (1112); o adding a single-qubit gate (43) to the output quantum circuit for at least one of the target labels (2) of the input unitary, wherein the single-qubit gate acts on the output qubit (1) and at the moment on which the target label (2) is implemented due to the gates of the circuit building blocks (4).

2. The computer-implemented method according to claim 1, wherein the tree (3) comprises at least one leg (32), wherein the leg path gates (42) are CNOT gates or gates corresponding to CNOT gates.

3. The computer-implemented method according to claim 1 or 2, wherein the target labels (2) correspond to logical parity labels.

4. The computer-implemented method according to any of the preceding claims, wherein the body (31) comprises at least two output qubits (1) at two body nodes (1111), wherein the at least one path (6) connecting all body nodes (1111) of the body (31) corresponds to a Hamiltonian path.

5. The computer-implemented method according to any of the preceding claims, wherein the body (31) comprises at least two output qubits (1) at two body nodes (1111), wherein the body path gates (41) are double CNOT gates with alternate control qubits or gates corresponding to double CNOT gates and / or CNOT gates or gates corresponding to CNOT gates, wherein each body path gate (41) acts on two output qubits (1) along the at least one path (6).

6. The computer-implemented method according to any of the preceding claims, wherein the connectivity mesh (11) corresponds to a graph chosen from the group consisting of a complete graph, modular all-to-all graph, a planar graph, a square graph, a path graph, or a hexagonal graph or a heavy hexagonal graph.

7. The computer-implemented method according to any of the preceding claims, wherein the output quantum circuit comprises at least one circuit building block (4) with body path gates (41) corresponding to CNOT gates.

8. The computer-implemented method according to any of the preceding claims, wherein the eigenstates of the logical qubits are, preferably bijectively and linearly, mapped to the eigenstates of the output qubits (1) in a chosen basis.

9. A method of performing a quantum computation on a quantum system comprising a plurality of output qubits (1), wherein the output qubits (1) of the quantum system are arranged in accordance with a connectivity mesh (11), wherein nodes (111) of the connectivity mesh (11) represent possible sites for the output qubits (1) of the quantum system and each edge (112) of the connectivity mesh (11) indicates that quantum interactions between the output qubits (1) of the quantum system connected by one of the edges (112) are possible, wherein the quantum computation corresponds to an input unitary compiled via the computer-implemented method according to any of the claims 1 to 8 or implemented via the output quantum circuit according to any of the claims 12 to 15.

10. The method according to claim 9, wherein the input unitary corresponds to a quantum Fourier transform or a subroutine of a variational quantum algorithm, preferably of a quantum approximate optimization algorithm.

11. The method according to claim 9 or claim 10, wherein the method comprises preparing at least a portion of the output qubits (1) in an initial quantum state.

12. An output quantum circuit operable on a quantum system comprising a plurality of output qubits (1), wherein the output qubits (1) of the quantum system are arranged in accordance with a connectivity mesh (11), wherein nodes (111) of the connectivity mesh (11) represent possible sites for the output qubits (1) of the quantum system and each edge (112) of the connectivity mesh (11) indicates that quantum interactions between the output qubits (1) of the quantum system connected by one of the edges (112) are possible, wherein the output quantum circuit comprises:o circuit building blocks (4) implementing a subset of target labels (2), wherein each circuit building block (4) is configured to act on output qubits (1) arranged according to a tree (3) comprising a subset of edges (112) and a subset of nodes (111) of the connectivity mesh (11), wherein the tree (3) comprises a body (31) with at least one body node (1111) representing a site for an output qubit (1), wherein the body (31) comprises at least two output qubits (1) at two body nodes (1111) and at least one path (6) connecting all body nodes (1111) of the body (31) and / or at least one leg (32) with at least one leg node (1112) representing a site for an output qubit (1), wherein the at least one leg node (1112) is connected by an edge (112) with at least one body node (1111),wherein the circuit building blocks (4) comprise body path gates (41) for each body node (1111) along the at least one path (6) and / or a leg path gate (42) for each leg node (1112),o single-qubit gates for at least one of the target labels (2), wherein each singlequbit gate is configured to act on the output qubit (1) and at the moment on which the target label (2) is implemented due to the gates of the circuit building blocks (4).

13. The output quantum circuit according to claim 12, wherein the body path gates (41) are double CNOT gates with alternate control qubits or gates corresponding to double CNOT gates and / or CNOT gates or gates corresponding to CNOT gates, wherein each body path gate (41) is configured to act on two output qubits (1) along the at least one path (6).

14. The output quantum circuit according to claim 12 or 13, wherein the leg path gates (42) are CNOT gates or gates corresponding to a CNOT gates.

15. The output quantum circuit according to any of the claims 12 to 14 comprising a concatenation of circuit building blocks (4) acting on a decreasing or increasing number of output qubits (1).

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