Pixel circuit and driving method therefor, and display substrate

Abstract

A pixel circuit and a driving method therefor, and a display substrate. The pixel circuit comprises a driving sub-circuit (21), a data writing sub-circuit (22), a power supply control sub-circuit (23), a coupling sub-circuit (24) and a reset control sub-circuit (25), wherein the driving sub-circuit (21) is connected to a first node (N1), a second node (N2) and a third node (N3); the data writing sub-circuit (22) is connected to a first scanning line (GL1), a data line (DL) and a fourth node (N4); the power supply control sub-circuit (23) is connected to a first light-emission control line (EM1), the second node (N2) and a first power supply line (VDD); the coupling sub-circuit is connected to the first node (N1), the second node (N2) and the fourth node (N4); the reset control sub-circuit (25) is connected to a second scanning line (GL2), the first node (N1) and a first reference voltage line (REF1); and during driving, the pixel circuit comprises a data writing phase, a threshold compensation phase and a light-emission phase, which are sequentially performed.

Description

Pixel circuits and their driving methods, display substrates Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a pixel circuit and its driving method, and a display substrate. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess advantages such as ultra-thinness, wide viewing angle, active emission, high brightness, continuously adjustable emission color, low cost, fast response speed, low power consumption, wide operating temperature range, and flexible display capabilities. They have gradually become a promising next-generation display technology and are receiving increasing attention. Based on different driving methods, OLEDs can be divided into two types: passive matrix (PM) and active matrix (AM). AMOLEDs are current-driven devices that use independent thin-film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This embodiment provides a pixel circuit and its driving method, as well as a display substrate.

[0005] On one hand, this embodiment provides a pixel circuit, which includes a driving sub-circuit, a data writing sub-circuit, a power control sub-circuit, a coupling sub-circuit, and a reset control sub-circuit. The driving sub-circuit is connected to a first node, a second node, and a third node. The data writing sub-circuit is connected to a first scan line, a data line, and a fourth node. The power control sub-circuit is connected to a first light emission control line, a second node, and a first power supply line. The coupling sub-circuit is connected to the first node, the second node, and the fourth node. The reset control sub-circuit is connected to a second scan line, the first node, and a first reference voltage line. When driven, the pixel circuit includes a data writing stage, a threshold compensation stage, and a light emission stage performed sequentially. During the data writing stage, the data writing sub-circuit, under the control of the first scan line, writes the data signal of the data line to the fourth node. The reset control sub-circuit... Under the control of the second scan line, the control sub-circuit writes the first reference voltage signal of the first reference voltage line into the first node. Under the control of the first light emission control line, the power control sub-circuit connects the first power line to the second node. In the threshold compensation stage, under the control of the first light emission control line, the power control sub-circuit disconnects the connection between the first power line and the second node, so that the driving sub-circuit compensates for the threshold voltage. In the light emission stage, under the control of the first light emission control line, the power control sub-circuit connects the connection between the first power line and the second node. The coupling sub-circuit couples and boosts the voltage of the first node according to the voltage change of the second node and the voltage of the fourth node, so that the driving sub-circuit provides driving current according to the voltage difference between the first node and the second node.

[0006] On the other hand, this embodiment provides a driving method for a pixel circuit. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a power control sub-circuit, a coupling sub-circuit, and a reset control sub-circuit. The driving cycle of the pixel circuit includes a refresh frame, which includes a data writing stage, a threshold compensation stage, and a light emission stage performed sequentially. In the data writing stage, the data writing sub-circuit, under the control of the first scan line, writes the data signal of the data line to the fourth node. The reset control sub-circuit, under the control of the second scan line, writes the first reference voltage signal of the first reference voltage line to the first node. The power control sub-circuit, under the control of the first light emission control line... Under control, the connection between the first power line and the second node is made on; in the threshold compensation stage, the power control sub-circuit, under the control of the first light emission control line, disconnects the connection between the first power line and the second node, so that the driving sub-circuit compensates for the threshold voltage; in the light emission stage, the power control sub-circuit, under the control of the first light emission control line, makes the connection between the first power line and the second node on. The coupling sub-circuit couples and boosts the voltage of the first node according to the voltage change of the second node and the voltage of the fourth node, so that the driving sub-circuit provides driving current according to the voltage difference between the first node and the second node.

[0007] On the other hand, this embodiment provides a display substrate, including: pixel circuits as described in any embodiment of this disclosure.

[0008] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0009] Overview of the attached figures

[0010] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0011] Figure 1 is an equivalent circuit diagram of a pixel circuit;

[0012] Figure 2 is a schematic diagram of the structure of a pixel circuit according to at least one embodiment of the present disclosure;

[0013] Figure 3 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0014] Figure 4 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0015] Figure 5 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0016] Figure 6 is a timing diagram of one operation of the pixel circuit shown in Figure 5;

[0017] Figure 7 is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0018] Figure 8A is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0019] Figure 8B is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0020] Figure 9A is a timing diagram of the pixel circuit shown in Figure 8A during the frame refresh stage.

[0021] Figure 9B is a timing diagram of the pixel circuit shown in Figure 8B during the frame refresh stage.

[0022] Figures 10A and 11A are two timing diagrams of the pixel circuit shown in Figure 8A during the frame holding stage;

[0023] Figures 10B and 11B are two timing diagrams of the pixel circuit shown in Figure 8B during the frame holding stage.

[0024] Figure 12 is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0025] Figure 13 is a timing diagram of the pixel circuit shown in Figure 12 during the frame refresh stage.

[0026] Figures 14 and 15 show two timing diagrams of the pixel circuit shown in Figure 12 during the frame holding stage.

[0027] Figure 16 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0028] Figure 17 is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0029] Figure 18 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0030] Figure 19 is a flowchart of a pixel circuit driving method according to at least one embodiment of the present disclosure.

[0031] Detailed Explanation

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0033] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0034] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0035] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0036] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "coupling" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or link; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Coupling" can include "electrical connection," which can include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0037] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0038] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0039] In this specification, "approximately" and "about" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" includes values ​​differing by less than 10%, such as values ​​differing by less than 5%.

[0040] In this disclosure, the effective level signal includes the level signal of the conducting transistor. For example, the effective level signal of the conducting P-type transistor is a low level signal, and the effective level signal of the conducting N-type transistor is a high level signal.

[0041] Figure 1 shows an equivalent circuit diagram of a pixel circuit. As shown in Figure 1, the pixel circuit includes seven transistors (i.e., transistors T01 to T07) and a storage capacitor Cst. All seven transistors are of the same type; for example, all seven transistors are P-type transistors. The gates of transistors T02 and T04 are connected to the first gate line GATE1, the gate of transistor T01 is connected to the second gate line GATE2, the gate of transistor T07 is connected to the third gate line GATE3, and the gates of transistors T05 and T06 are connected to the light emission control line EML. In this pixel circuit, the data voltage provided by the data signal line DATA can drive transistor T03 to write the data voltage and compensate for the threshold voltage Vth. During the data writing stage, transistors T02 and T04 use the same scan signal provided by the first gate line GATE1 to achieve data writing and threshold voltage compensation.

[0042] However, as the resolution and frequency of display devices increase, the above-mentioned scheme of using data voltage for threshold voltage compensation will encounter a driving bottleneck. For example, as the display refresh rate increases, the data writing time (1H) of a single row of pixel circuits within a frame will gradually decrease. As the data writing time decreases, insufficient threshold voltage compensation will occur.

[0043] This embodiment provides a pixel circuit and its driving method, as well as a display substrate, which can improve the compensation effect of threshold voltage, thereby improving display performance.

[0044] Figure 2 is a schematic diagram of the structure of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2, the pixel circuit of the present disclosure embodiment may include at least: a driving sub-circuit 21, a data writing sub-circuit 22, a power control sub-circuit 23, a coupling sub-circuit 24, and a reset control sub-circuit 25.

[0045] The driving sub-circuit 21 is connected to the first node N1, the second node N2, and the third node N3, and is configured to provide a driving signal to the third node N3 under the control of the first node N1 and the second node N2. The data writing sub-circuit 22 is connected to the first scan line GL1, the data line DL, and the fourth node N4, and is configured to write the data signal provided by the data line DL to the fourth node N4 under the control of the first scan line GL1. The power control sub-circuit 23 is connected to the first light emission control line EM1, the first power line VDD, and the second node N2, and is configured to connect or disconnect the electrical connection between the first power line VDD and the second node N2 under the control of the first light emission control line EM1. The coupling sub-circuit 24 is connected to the first node N1, the second node N2, and the fourth node N4, and is configured to couple and boost the voltage of the first node N1 according to the voltage change of the second node N2 and the voltage of the fourth node N4. The reset control sub-circuit 25 is connected to the second scan line GL2, the first reference voltage line REF1 and the first node N1 respectively, and is configured to write the first reference voltage signal of the first reference voltage line REF1 into the first node N1 under the control of the second scan line GL2.

[0046] The pixel circuit includes a data writing stage, a threshold compensation stage, and a light emission stage performed sequentially during driving. In the data writing stage, the data writing sub-circuit 22, under the control of the first scan line GL1, writes the data signal of the data line DL into the fourth node N4. The reset control sub-circuit 23, under the control of the second scan line GL2, writes the first reference voltage signal of the first reference voltage line REF1 into the first node N1. The power control sub-circuit 23, under the control of the first light emission control line EM1, connects the first power line VDD to the second node N2.

[0047] During the threshold compensation stage, the power control sub-circuit 23, under the control of the first light-emitting control line EM1, disconnects the connection between the first power line VDD and the second node N2, so that the driving sub-circuit 21 can compensate for the threshold voltage.

[0048] During the light-emitting stage, the power control sub-circuit 23, under the control of the first light-emitting control line EM1, connects the first power line VDD to the second node N2. The coupling sub-circuit 24 couples and raises the voltage of the first node N1 according to the voltage change of the second node N2 and the voltage of the fourth node N4, so that the driving sub-circuit 21 provides driving current according to the voltage difference between the first node N1 and the second node N2.

[0049] In the pixel circuit of this embodiment, during the data writing phase, the data writing sub-circuit 22, under the control of the first scan line GL1, writes the data signal of the data line DL to the fourth node N4; the reset control sub-circuit 23, under the control of the second scan line GL2, writes the first reference voltage signal of the first reference voltage line REF1 to the first node N1; and the power control sub-circuit 23, under the control of the first light emission control line EM1, connects the first power line VDD to the second node N2. During the threshold compensation phase, under the control of the first light emission control line EM1, the power control sub-circuit 23 disconnects the first power line VDD from the second node N2, thereby enabling the driving... Sub-circuit 21 compensates for the threshold voltage. During the light-emitting stage, the power control sub-circuit 23, under the control of the first light-emitting control line EM1, connects the first power line VDD to the second node N2. The coupling sub-circuit 24 couples and raises the voltage of the first node N1 according to the voltage change of the second node N2 and the voltage of the fourth node N4, so that the driving sub-circuit 21 provides driving current according to the voltage difference between the first node N1 and the second node N2. This separates the data writing and threshold compensation processes, ensuring the threshold compensation time during high frame rate driving, thereby achieving a better compensation effect. At the same time, this pixel circuit can compensate for the voltage drop (IR Drop) of the first power line VDD, making the circuit a promising candidate for large-size display panels.

[0050] In some examples, the time for the data writing sub-circuit 22 to write the data signal to the fourth node N4 can be less than the time for the driving sub-circuit 21 to compensate for the threshold voltage. This example can separate the data writing process and the threshold voltage compensation process. By increasing the compensation time for the threshold voltage, the compensation effect of the threshold voltage can be improved, thereby improving the uniformity of the screen display.

[0051] In some examples, the first scan line GL1 can be configured to provide a first scan signal, and the second scan line GL2 can be configured to provide a second scan signal. The first scan signal can be configured to control the data writing sub-circuit 22 to write a data signal to the fourth node N4, and the second scan signal can be configured to control the reset control sub-circuit 25 to write a first reference voltage signal to the first node N1. The first scan signal can be different from the second scan signal. For example, the duration of the effective level signal of the first scan signal can be shorter than the duration of the effective level signal of the second scan signal.

[0052] In some examples, as shown in Figure 2, the pixel circuit may further include a first reset sub-circuit 26, which is connected to the second scan line GL2 or the first reset control line Reset_H, the first initial voltage line INIT1, and the third node N3, respectively. The first reset sub-circuit 26 is configured to write the first initial voltage signal of the first initial voltage line INIT1 to the third node N3 under the control of the second scan line GL2 or the first reset control line Reset_H. For example, the first reset sub-circuit 26 may write the first initial voltage signal of the first initial voltage line INIT1 to the third node N3 during the data writing phase and / or the threshold compensation phase.

[0053] In this embodiment, the third node N3 can be directly connected to the first electrode of the light-emitting element; however, this disclosure does not limit this. In this embodiment, writing a first initial voltage signal to the third node N3 via the first reset circuit 26 can eliminate residual positive charge on the surface of the first electrode of the light-emitting element, thereby improving the lifespan of the light-emitting element.

[0054] Figure 3 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the pixel circuit may further include a light-emitting control sub-circuit 27, which is connected to a second light-emitting control line EM2, a third node N3, and a sixth node N6, respectively, and configured to turn on or off the connection between the third node N3 and the sixth node N6 under the control of the second light-emitting control line EM2. For example, during the data writing stage and the threshold compensation stage, the light-emitting control sub-circuit 27 disconnects the connection between the third node N3 and the sixth node N6; during the light-emitting stage, the light-emitting control sub-circuit 27 turns on the connection between the third node N3 and the sixth node N6, so that the first power line VDD provides a driving current to the first electrode of the light-emitting element, driving the light-emitting element to emit light.

[0055] In this embodiment of the present disclosure, the sixth node N6 can be directly connected to the first electrode of the light-emitting element; however, the present disclosure does not limit this.

[0056] In some examples, as shown in Figure 3, the pixel circuit may further include a second reset sub-circuit 28, which is connected to a reset control line, a second initial voltage line INIT2, and a sixth node N6, respectively. The second reset sub-circuit 28 is configured to write the second initial voltage signal of the second initial voltage line INIT2 into the sixth node N6 under the control of the reset control line. For example, the second reset sub-circuit 28 may write the second initial voltage signal of the second initial voltage line INIT2 into the sixth node N6 during the data writing phase and / or the threshold compensation phase.

[0057] In this embodiment, the first initial voltage signal is written to the third node N3 by the first reset sub-circuit 26, which can reset the third node N3; the second initial voltage signal is written to the sixth node N6 by the second reset sub-circuit 28, which can eliminate the leakage current of the light-emitting control sub-circuit 27, prevent the light-emitting element from emitting light in the dark due to the influence of the leakage current, improve the display quality, and eliminate the residual positive charge on the surface of the first electrode of the light-emitting element, which can improve the life of the light-emitting element.

[0058] In some examples, the reset control line can be any of the following: the first scan line GL1, the second scan line GL2, or the first reset control line Reset_H; however, this disclosure does not limit it.

[0059] In some examples, the first light-emitting control line EM1 can be configured to provide a first light-emitting control signal, and the second light-emitting control line EM2 can be configured to provide a second light-emitting control signal. The first light-emitting control signal can be configured to control the power supply light-emitting control sub-circuit 23 to write a first power supply voltage signal to the second node N2, and the second light-emitting control signal can be configured to control the light-emitting control sub-circuit 27 to turn on the third node N3 and the sixth node N6 to provide a driving signal to the light-emitting element, causing the light-emitting element to emit light. The first light-emitting control signal may be different from the second light-emitting control signal.

[0060] In some examples, the first reset control line Reset_H can be configured to provide a first reset control signal. The first reset control signal can be configured to control the first reset sub-circuit 26 to write a first initial voltage signal to the third node N3, or it can be configured to control the second reset sub-circuit 28 to write a second initial voltage signal to the sixth node N6. The first initial voltage signal can be the same as or different from the second initial voltage signal; this disclosure does not limit this.

[0061] In some examples, the first initial voltage signal may be equal to the second initial voltage signal, the first initial voltage signal may be less than the first power supply voltage signal, the first reference voltage signal may be less than the first power supply voltage signal, and the magnitude relationship between the first reference voltage signal and the first initial voltage signal (or the second initial voltage signal) can be set as needed. For example, the threshold voltage of the driving transistor may be -3V, the first initial voltage may be -2V, the first power supply voltage may be 4.6V, and the first reference voltage may be 2V; however, this disclosure does not impose any limitations on these aspects.

[0062] In some examples, the light-emitting element can be an organic light-emitting diode (OLED). The first electrode of the light-emitting element can be an anode, and the second electrode can be a cathode. However, this embodiment is not limited to this.

[0063] In some examples, the first power line VDD can continuously provide a constant high-level signal; for example, the first power line VDD can provide a first power supply voltage signal. The second power line VSS can continuously provide a constant low-level signal; for example, the second power line VSS can provide a second power supply voltage signal. The first power supply voltage signal can be greater than the second power supply voltage signal.

[0064] Figure 4 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 4, the coupling sub-circuit 24 may include a coupling control sub-circuit 241, a first coupling sub-circuit 242, and a second coupling sub-circuit 243. The coupling control sub-circuit 241 is connected to the coupling control line, the first node N1, and the fourth node N4, respectively. The first coupling sub-circuit 242 is connected to the fourth node N4 and the fifth node N5, respectively. The second coupling sub-circuit 243 is connected to the fifth node N5 and the second node N2, respectively.

[0065] During the light-emitting stage, the coupling control sub-circuit 241 conducts the first node N1 and the fourth node N4 under the control of the coupling control line; the first coupling sub-circuit 242 and the second coupling sub-circuit 243 couple and boost the voltage of the fourth node N4 according to the voltage change of the second node N2.

[0066] In this example, the coupling control line can be the second emission control line EM2 or the second scan line GL2; however, this disclosure does not limit it in this regard.

[0067] In some examples, as shown in Figure 4, the reset control subcircuit 25 may include a first reset control subcircuit 251 and a second reset control subcircuit 252. The first reset control subcircuit 251 is connected to the second scan line GL2, the first reference voltage line REF1, and the fifth node N5, and is configured to write the first reference voltage signal of the first reference voltage line REF1 into the fifth node N5 under the control of the second scan line GL2. The second reset control subcircuit 252 is connected to the second scan line GL2, the first node N1, and the fifth node N5, and is configured to turn on or off the fifth node N5 and the first node N1 under the control of the second scan line GL2. For example, in the data writing stage and / or the threshold compensation stage, the first reset control subcircuit 251 and the second reset control subcircuit 252 may first write the first reference voltage signal of the first reference voltage line REF1 into the fifth node N5, and then turn on the first node N1 and the fifth node N5, so that the voltage of the first node N1 also becomes the first reference voltage.

[0068] In this example, referring to Figures 2 to 4, the third node N3 in the pixel circuit of Figure 4 can be directly electrically connected to the first electrode of the light-emitting element (i.e., similar to the pixel circuit shown in Figure 2), or it can be first electrically connected to the light-emitting control sub-circuit, and then electrically connected to the first electrode of the light-emitting element through the light-emitting control sub-circuit (i.e., similar to the pixel circuit shown in Figure 3). This disclosure does not limit this.

[0069] Figure 5 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 5, the coupling control sub-circuit 241 includes a coupling control transistor T2, the first coupling sub-circuit 242 includes a first capacitor C1, the second coupling sub-circuit 243 includes a second capacitor C2, the control electrode of the coupling control transistor T2 is electrically connected to the second light-emitting control line EM2, the first electrode of the coupling control transistor T2 is electrically connected to the fourth node N4, the second electrode of the coupling control transistor T2 is electrically connected to the first node N1, the first plate of the first capacitor C1 is electrically connected to the fourth node N4, the second plate of the first capacitor C1 is electrically connected to the fifth node N5, the first plate of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate of the second capacitor C2 is electrically connected to the second node N2.

[0070] In some examples, as shown in Figure 5, the first reset control sub-circuit 251 includes a first reset control transistor T3, and the second reset control sub-circuit 252 includes a second reset control transistor T4.

[0071] Specifically, the control electrode of the first reset control transistor T3 is electrically connected to the second scan line GL2, the first electrode of the first reset control transistor T3 is electrically connected to the first reference voltage line REF1, and the second electrode of the first reset control transistor T3 is electrically connected to the fifth node N5; the control electrode of the second reset control transistor T4 is electrically connected to the second scan line GL2, the first electrode of the second reset control transistor T4 is electrically connected to the fifth node N5, and the second electrode of the second reset control transistor T4 is electrically connected to the first node N1.

[0072] In some examples, as shown in Figure 5, the data writing sub-circuit 22 includes a data writing transistor T1, wherein the control electrode of the data writing transistor T1 is electrically connected to the first scan line GL1, the first electrode of the data writing transistor T1 is electrically connected to the data line DL, and the second electrode of the data writing transistor T1 is electrically connected to the fourth node N4.

[0073] In some examples, as shown in Figure 5, the driving sub-circuit 21 includes a driving transistor T5, wherein the control terminal of the driving transistor T5 is electrically connected to the first node N1, the first terminal of the driving transistor T5 is electrically connected to the second node N2, and the second terminal of the driving transistor T5 is electrically connected to the third node N3.

[0074] In some examples, as shown in Figure 5, the power control sub-circuit 23 includes a power control transistor T7, wherein the control electrode of the power control transistor T7 is electrically connected to the first light-emitting control line EM1, the first electrode of the power control transistor T7 is electrically connected to the first power line VDD, and the second electrode of the power control transistor T7 is electrically connected to the second node N2.

[0075] In some examples, as shown in Figure 5, the first reset sub-circuit 26 includes a first reset transistor T6, wherein the control electrode of the first reset transistor T6 is electrically connected to the second scan line GL2, the first electrode of the first reset transistor T6 is electrically connected to the first initial voltage line INIT1, and the second electrode of the first reset transistor T6 is electrically connected to the third node N3.

[0076] In this example, the first node N1 is the connection point of the coupling control transistor T2, the second reset control transistor T4, and the driving transistor T5. The second node N2 is the connection point of the second capacitor C2, the power control transistor T7, and the driving transistor T5. The third node N3 is the connection point of the first reset transistor T6, the driving transistor T5, and the first electrode of the light-emitting element. The fourth node N4 is the connection point of the data writing transistor T1, the coupling control transistor T2, and the first capacitor C1. The fifth node N5 is the connection point of the first capacitor C1, the second capacitor C2, the first reset control transistor T3, and the second reset control transistor T4.

[0077] Figure 5 shows an exemplary structure of the driver sub-circuit 21, data writing sub-circuit 22, power control sub-circuit 23, coupling control sub-circuit 241, first coupling sub-circuit 242, second coupling sub-circuit 243, first reset control sub-circuit 251, second reset control sub-circuit 252, and first reset sub-circuit 26. It is easy for those skilled in the art to understand that the implementation of the above sub-circuits is not limited to this, as long as their functions can be achieved.

[0078] In some examples, as shown in Figure 5, the data writing transistor T1, coupling control transistor T2, first reset control transistor T3, second reset control transistor T4, drive transistor T5, first reset transistor T6, and power control transistor T7 can all be P-type thin-film transistors, such as low-temperature polycrystalline silicon (LTPS) thin-film transistors. The active layer of the LTPS thin-film transistor can be made of low-temperature polycrystalline silicon (LTPS). LTPS thin-film transistors have advantages such as high mobility and fast charging.

[0079] Figure 6 is a timing diagram of the pixel circuit shown in Figure 5. As shown in Figure 5, the pixel circuit of this example includes: 7 transistors (i.e., transistors T1 to T7), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 7 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reference voltage line REF1 and first initial voltage line INIT1), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0080] In some examples, as shown in Figure 6, the operation of the pixel circuit can include a first stage t11 to a third stage t13 within a frame time period. The potentials of each node at different stages are shown in Table 1. In Table 1, V OLED This represents the potential of the first electrode of the light-emitting element.

[0081] Table 1

[0082] Before the current frame is displayed, specifically before the first stage t11 of the current frame display, the output of the second light-emitting control line EM2 is set to a low-level signal. This means the second light-emitting control signal provided by EM2 is a low-level signal. The coupling control transistor T2 is in the ON state under the action of the second light-emitting control signal. Simultaneously, the outputs of the first light-emitting control line EM1 are both set to a high-level signal, and the corresponding controlled transistors are in the OFF state. The light-emitting element EL is in the previous frame's light-emitting display stage.

[0083] The first stage t11 can also be called the reset and data writing stage. In the first stage t11 of the current frame, the first scan signal provided by the first scan line GL1 jumps to a low level signal, the second scan signal provided by the second scan line GL2 jumps to a low level signal, the first light emission control signal provided by the first light emission control line EM1 remains at a low level signal, and the second light emission control signal provided by the second light emission control line EM2 jumps to a high level signal.

[0084] Under the influence of the low-level signal provided by the first scan line GL1, the data writing transistor T1 is turned on, and the data signal provided by the data line DL is written to the fourth node N4 through the turned-on data writing transistor T1, changing the voltage of the fourth node N4 to Vdata. Under the influence of the low-level signal provided by the second scan line GL2, the first reset control transistor T3, the second reset control transistor T4, and the first reset transistor T6 are turned on. The first reference voltage signal provided by the first reference voltage line REF1 is provided to the fifth node N5 through the turned-on first reset control transistor T3, resetting the potential of the fifth node N5 to the first reference voltage Vref1. Simultaneously, the potential of the fifth node N5 is provided to the first node N1 through the turned-on second reset control transistor T4, resetting the potential of the first node N1 to the first reference voltage Vref1. Since the first node N1 is electrically connected to the control electrode of the driving transistor T5, the control electrode of the driving transistor T5 is also reset to the first reference voltage Vref1. The first initial voltage signal provided by the first initial voltage line INIT1 is written to the third node N3 through the conducting first reset transistor T6. The voltage of the third node N3 is reset to the first initial voltage Vinit1. Since the third node N3 is electrically connected to the anode of the light-emitting element EL, the light-emitting element EL is also reset. Under the action of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 remains in the conducting state. The first power supply voltage signal provided by the first power supply line VDD is provided to the second node N2 through the conducting power control transistor T7, that is, the potential of the second terminal of the driving transistor T5 becomes the first power supply voltage Vdd. Since the voltages of the control terminal and the second terminal of the driving transistor T5 are both in a fixed bias state, the driving transistor T5 is turned on, preparing for the threshold compensation in the second stage t12. It should be noted that in the first stage t11, in order for the driving transistor T5 to turn on, the turn-on condition of the driving transistor T5 should be met, that is, Vref1-Vdd should be less than the threshold voltage Vth of the driving transistor T5, that is, Vdd should be greater than Vref1-Vth.

[0085] The second stage t12 can also be called the threshold compensation stage. In the second stage t12 of the current frame, the first scan signal provided by the first scan line GL1 jumps to a high level signal, the second scan signal provided by the second scan line GL2 remains at a low level signal, the first light emission control signal provided by the first light emission control line EM1 jumps to a high level signal, and the second light emission control signal provided by the second light emission control line EM2 remains at a high level signal.

[0086] Since the second scan signal provided by the second scan line GL2 remains at a low level, the first reset control transistor T3, the second reset control transistor T4, and the first reset transistor T6 remain in the on state. The first reference voltage signal provided by the first reference voltage line REF1 is still transmitted to the fifth node N5 and the first node N1. The voltages of the fifth node N5 and the first node N1 remain at the first reference voltage Vref1. The first initial voltage signal provided by the first initial voltage line INIT1 is still written to the third node N3. The voltage of the third node N3 remains at the first initial voltage Vinit1.

[0087] Since both the first light-emitting control line EM1 and the second light-emitting control line EM2 output high-level signals, both the power control transistor T7 and the coupling control transistor T2 are turned off. In this situation, the second node N2 is disconnected from the first power line VDD, and the second terminal of the driving transistor T5 is in a floating state. The driving transistor T5 undergoes a discharge process, changing from being on to being off, thus causing the potential of the second terminal of the driving transistor T5 to change from Vdd to Vref1-Vth, where Vth is the threshold voltage of the driving transistor T5. It should be noted that during this second stage t12, when the driving transistor T5 undergoes a discharge process, the potential of the second terminal of the driving transistor T5 starts to decrease from Vdd until it decreases to Vref1-Vth, at which point the conduction condition of the driving transistor T5 is not met, causing the driving transistor T5 to turn off.

[0088] It should be noted that the range of threshold voltage compensation performed by the driving transistor T5 can be adjusted by adjusting the magnitudes of the first power supply voltage Vdd and the first initial voltage Vinit1.

[0089] The third stage t13 can also be called the emission stage. In the third stage t13 of the current frame, the first emission control signal provided by the first emission control line EM1 jumps to a low level signal, the second emission control signal provided by the second emission control line EM2 jumps to a low level signal, the first scan signal provided by the first scan line GL1 remains at a high level, and the second scan signal provided by the second scan line GL2 jumps to a high level signal.

[0090] Under the influence of a low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is supplied to the second node N2 through the turned-on power control transistor T7. Under the influence of a low-level signal provided by the second light-emitting control line EM2, the coupling control transistor T2 is turned on, and the data writing transistor T1, the first reset control transistor T3, the second reset control transistor T4, and the first reset transistor T6 are all turned off.

[0091] Because the potential of the second terminal of the driving transistor T5 changes from Vref1-Vth to Vdd, under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 changes from Vref1 to Vdata+Vdd-Vref1+Vth, causing the driving transistor T5 to conduct and drive the light-emitting element EL to emit light. Specifically, because the coupling control transistor T2 is turned on, the control terminal of the driving transistor T5 is connected to the first terminal of the first capacitor C1; because the power control transistor T7 is turned on, the potential of the second terminal of the driving transistor T5 (i.e., the second terminal of the second capacitor) changes from Vref1-Vth to Vdd, and the change in potential of the second terminal of the driving transistor T5 is Vdd-Vref1+Vth. According to the law of conservation of charge, the potential of the control terminal of the driving transistor T5 becomes Vdata+Vdd-Vref1+Vth.

[0092] When driving the pixel circuit provided in the above embodiments using the driving method provided in this disclosure, in the first stage t11, the control electrode potential of the driving transistor T5 is changed to the first reference voltage Vref1, and the potential of the second electrode of the driving transistor T5 is changed to Vdd, so that the voltages of the control electrode and the second electrode of the driving transistor T5 are both in a fixed bias state, thereby initializing the driving transistor T5. Therefore, regardless of whether each pixel unit displays a black or white image in the previous frame, the driving transistor T5 starts the display of the next frame from a fixed bias state, thereby effectively improving the problem of short-term image retention caused by hysteresis.

[0093] In the second stage t12, by controlling the second terminal of the driving transistor T5 to be disconnected from the first power line VDD, the driving transistor T5 undergoes a discharge process until the driving transistor T5 is turned off.

[0094] In the third stage t13, the potential of the second terminal of the driving transistor T5 jumps from Vref1-Vth to the power supply voltage Vdd. Under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 jumps to Vdata+Vdd-Vref1+Vth, thereby turning on the driving transistor T5. At this time, the voltage difference Vgs between the control terminal and the second terminal of the driving transistor T5 is Vdata-Vref1+Vth. The driving current I generated when the driving transistor T5 is turned on and operating in saturation is: I = k×(Vdata-Vref1) 2 , where k is a constant.

[0095] It is evident that the driving current I is only related to the data voltage Vdata and the first reference voltage Vref1, and has no relation to the threshold voltage Vth of the driving transistor T5 or the first power supply voltage Vdd. Therefore, when driving the pixel circuit using the driving method provided in this embodiment, the uniformity of the driving current is improved, effectively solving the impact of IR Drop and the threshold voltage of the driving transistor T5 on the uniformity of the display brightness of the display device, and ensuring the uniformity of the display brightness of the display device.

[0096] Furthermore, in the pixel circuit provided in this embodiment, the range of the data voltage Vdata of the pixel circuit can be adjusted by adjusting the magnitude of the first reference voltage Vref1. The higher the voltage signal of the first reference voltage Vref1, the higher the lower limit of the data voltage Vdata.

[0097] The cathode of the light-emitting element EL is electrically connected to the second power supply line VSS. The second power supply voltage provided by the second power supply line VSS is selected according to the characteristics of the light-emitting element EL to ensure that the driving transistor T5 operates in saturation. In this embodiment, the second power supply voltage provided by the second power supply line VSS is lower than the first power supply potential provided by the first power supply line VDD. When the first power supply line VDD is high, the second power supply line VSS can be low, or the second power supply line VSS can be grounded.

[0098] Figure 7 is another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. Compared with the equivalent circuit diagram of the pixel circuit shown in Figure 5, the pixel circuit of Figure 7 adds a light emission control sub-circuit 27 and a second reset sub-circuit 28.

[0099] In some examples, as shown in Figure 7, the data writing subcircuit 22 includes a data writing transistor T1, the coupling control subcircuit 241 includes a coupling control transistor T2, the first coupling subcircuit 242 includes a first capacitor C1, the second coupling subcircuit 243 includes a second capacitor C2, the first reset control subcircuit 251 includes a first reset control transistor T3, the second reset control subcircuit 252 includes a second reset control transistor T4, the driving subcircuit 21 includes a driving transistor T5, the first reset subcircuit 26 includes a first reset transistor T6, the power control subcircuit 23 includes a power control transistor T7, the light emission control subcircuit 27 includes a light emission control transistor T8, and the second reset subcircuit 28 includes a second reset transistor T9.

[0100] Specifically, the control electrode of data writing transistor T1 is electrically connected to the first scan line GL1, the first electrode of data writing transistor T1 is electrically connected to the data line DL, and the second electrode of data writing transistor T1 is electrically connected to the fourth node N4. The control electrode of coupling control transistor T2 is electrically connected to the second light-emitting control line EM2, the first electrode of coupling control transistor T2 is electrically connected to the fourth node N4, and the second electrode of coupling control transistor T2 is electrically connected to the first node N1. The first plate of the first capacitor C1 is electrically connected to the fourth node N4, and the second plate of the first capacitor C1 is electrically connected to the fifth node N5. The first plate of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate of the second capacitor C2 is electrically connected to the second node N2. The control electrode of the first reset control transistor T3 is electrically connected to the second scan line GL2, the first electrode of the first reset control transistor T3 is electrically connected to the first reference voltage line REF1, and the second electrode of the first reset control transistor T3 is electrically connected to the fifth node N5. The control electrode of the second reset control transistor T4 is electrically connected to the second scan line GL2, the first electrode of the second reset control transistor T4 is electrically connected to the fifth node N5, and the second electrode of the second reset control transistor T4 is electrically connected to the first node N1. The control electrode of the driving transistor T5 is electrically connected to the first node N1, the first electrode of the driving transistor T5 is electrically connected to the second node N2, and the second electrode of the driving transistor T5 is electrically connected to the third node N3. The control electrode of the first reset transistor T6 is electrically connected to the second scan line GL2, the first electrode of the first reset transistor T6 is electrically connected to the first initial voltage line INIT1, and the second electrode of the first reset transistor T6 is electrically connected to the third node N3. The control electrode of the power control transistor T7 is electrically connected to the first light-emitting control line EM1, the first electrode of the power control transistor T7 is electrically connected to the first power supply line VDD, and the second electrode of the power control transistor T7 is electrically connected to the second node N2. The control electrode of the light-emitting control transistor T8 is electrically connected to the second light-emitting control line EM2. The first electrode of the light-emitting control transistor T8 is electrically connected to the third node N3, and the second electrode of the light-emitting control transistor T8 is electrically connected to the sixth node N6. The control electrode of the second reset transistor T9 is electrically connected to either the first scan line GL1 or the second scan line GL2. The first electrode of the second reset transistor T9 is electrically connected to the second initial voltage line INIT2, and the second electrode of the second reset transistor T9 is electrically connected to the sixth node N6. The sixth node N6 is electrically connected to the first electrode of the light-emitting element EL, and the second electrode of the light-emitting element EL is electrically connected to the second power supply line VSS.

[0101] In this example, the first node N1 is the connection point of the coupling control transistor T2, the second reset control transistor T4, and the driving transistor T5. The second node N2 is the connection point of the second capacitor C2, the power control transistor T7, and the driving transistor T5. The third node N3 is the connection point of the first reset transistor T6, the driving transistor T5, and the light-emitting control transistor T8. The fourth node N4 is the connection point of the data writing transistor T1, the coupling control transistor T2, and the first capacitor C1. The fifth node N5 is the connection point of the first capacitor C1, the second capacitor C2, the first reset control transistor T3, and the second reset control transistor T4. The sixth node N6 is the connection point of the light-emitting control transistor T8, the second reset transistor T9, and the first electrode of the light-emitting element.

[0102] Figure 7 shows an exemplary structure of the driver sub-circuit 21, data writing sub-circuit 22, power control sub-circuit 23, coupling control sub-circuit 241, first coupling sub-circuit 242, second coupling sub-circuit 243, first reset control sub-circuit 251, second reset control sub-circuit 252, first reset sub-circuit 26, light emission control sub-circuit 27, and second reset sub-circuit 28. It is readily understood by those skilled in the art that the implementation of the above sub-circuits is not limited to this, as long as their functions can be achieved.

[0103] In some examples, as shown in Figure 7, the data writing transistor T1, coupling control transistor T2, first reset control transistor T3, second reset control transistor T4, driving transistor T5, first reset transistor T6, power control transistor T7, light-emitting control transistor T8, and second reset transistor T9 can all be P-type thin-film transistors, for example, low-temperature polycrystalline silicon (LTPS) thin-film transistors. The active layer of the LTPS thin-film transistor can be made of low-temperature polycrystalline silicon (LTPS). LTPS thin-film transistors have advantages such as high mobility and fast charging.

[0104] The pixel circuit shown in Figure 7 can still be driven using the timing diagram shown in Figure 6. As shown in Figure 7, the pixel circuit in this example includes: 9 transistors (i.e., transistors T1 to T9), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 8 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reference voltage line REF1, first initial voltage line INIT1 and second initial voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0105] The following detailed examples, using the timing diagram shown in Figure 6, illustrate the operation of the pixel circuit shown in Figure 7 at different stages (t11 to t13). In the pixel circuit shown in Figure 7, all transistors in each sub-circuit are P-type transistors. It is assumed that the control electrode of the second reset transistor T9 is connected to the first scan line GL1.

[0106] In this example, during the display of an image frame, the operation of the pixel circuit can still include the first stage t11 to the third stage t13. The potentials of each node at different stages are shown in Table 2.

[0107] Table 2

[0108] Before the current frame is displayed, specifically before the first stage t11 of the current frame display, the second light-emitting control signal provided by the second light-emitting control line EM2 is a low-level signal. Coupled control transistor T2 and light-emitting control transistor T8 are in a conducting state under the action of the second light-emitting control signal. The output of the first light-emitting control line EM1 is set to a low-level signal, meaning the first light-emitting control signal provided by the first light-emitting control line EM1 is a low-level signal. The power control transistor T7 is in a conducting state under the action of the first light-emitting control signal. Simultaneously, the outputs of the first scan line GL1 and the second scan line GL2 are both set to high-level signals, and the corresponding controlled transistors are all in a closed state. The light-emitting element EL is in the previous frame's light-emitting display stage.

[0109] The first stage t11 can also be called the reset and data writing stage. In the first stage t11 of the current frame, the first scan signal provided by the first scan line GL1 jumps to a low level signal, the second scan signal provided by the second scan line GL2 jumps to a low level signal, the first light emission control signal provided by the first light emission control line EM1 remains at a low level signal, and the second light emission control signal provided by the second light emission control line EM2 jumps to a high level signal.

[0110] Under the action of the low-level signal provided by the first scan line GL1, the data writing transistor T1 and the second reset transistor T9 are turned on. The data signal provided by the data line DL is written to the fourth node N4 through the turned-on data writing transistor T1, and the voltage of the fourth node N4 becomes Vdata. The second initial voltage signal provided by the second initial voltage line INIT2 is written to the sixth node N6 through the turned-on second reset transistor T9, and the voltage of the sixth node N6 is reset to the second initial voltage Vinit2. Since the sixth node N6 is electrically connected to the anode of the light-emitting element EL, the light-emitting element EL is also reset. Under the influence of the low-level signal provided by the second scan line GL2, the first reset control transistor T3, the second reset control transistor T4, and the first reset transistor T6 are turned on. The first reference voltage signal provided by the first reference voltage line REF1 is provided to the fifth node N5 through the turned-on first reset control transistor T3, so that the potential of the fifth node N5 is reset to the first reference voltage Vref1. At the same time, the potential of the fifth node N5 is provided to the first node N1 through the turned-on second reset control transistor T4, so that the potential of the first node N1 is also reset to the first reference voltage Vref1. Since the first node N1 is electrically connected to the control electrode of the driving transistor T5, the control electrode of the driving transistor T5 is reset to the first reference voltage Vref1. The first initial voltage signal provided by the first initial voltage line INIT1 is written to the third node N3 through the turned-on first reset transistor T6, so that the voltage of the third node N3 is reset to the first initial voltage Vinit1. Under the influence of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 remains in the on state. The first power supply voltage signal provided by the first power supply line VDD is supplied to the second node N2 through the on-state power control transistor T7, that is, the potential of the second terminal of the driving transistor T5 becomes the first power supply voltage Vdd. Since the voltages of the control terminal and the second terminal of the driving transistor T5 are both in a fixed bias state, the driving transistor T5 is turned on, preparing for the threshold compensation in the second stage t12. It should be noted that in the first stage t11, in order for the driving transistor T5 to turn on, the turn-on condition of the driving transistor T5 should be met, that is, Vref1-Vdd should be less than the threshold voltage Vth of the driving transistor T5.

[0111] The second stage t12 can also be called the threshold compensation stage. In the second stage t12 of the current frame, the first scan signal provided by the first scan line GL1 jumps to a high level signal, the second scan signal provided by the second scan line GL2 remains at a low level signal, the first light emission control signal provided by the first light emission control line EM1 jumps to a high level signal, and the second light emission control signal provided by the second light emission control line EM2 remains at a high level signal.

[0112] Since the second scan signal provided by the second scan line GL2 remains at a low level, the first reset control transistor T3, the second reset control transistor T4, and the first reset transistor T6 remain in the on state. The first reference voltage signal provided by the first reference voltage line REF1 is still transmitted to the fifth node N5 and the first node N1. The voltages of the fifth node N5 and the first node N1 remain at the first reference voltage Vref1. The first initial voltage signal provided by the first initial voltage line INIT1 is still written to the third node N3. The voltage of the third node N3 remains at the first initial voltage Vinit1.

[0113] Since both the first light-emitting control line EM1 and the second light-emitting control line EM2 output high-level signals, the power control transistor T7, the light-emitting control transistor T8, and the coupling control transistor T2 are all turned off. In this situation, the second node N2 is disconnected from the first power line VDD, and the second terminal of the driving transistor T5 is in a floating state. The driving transistor T5 undergoes a discharge process, changing from being on to being off, thus causing the potential of the second terminal of the driving transistor T5 to change from Vdd to Vref1-Vth, where Vth is the threshold voltage of the driving transistor T5. It should be noted that during this second stage t12, when the driving transistor T5 undergoes a discharge process, the potential of the second terminal of the driving transistor T5 starts to decrease from Vdd until it decreases to Vref1-Vth, at which point the conduction condition of the driving transistor T5 is not met, causing the driving transistor T5 to turn off.

[0114] In this embodiment of the disclosure, the range of threshold voltage compensation performed by the driving transistor T5 can be adjusted by adjusting the magnitudes of the first power supply voltage Vdd and the first initial voltage Vinit1.

[0115] The third stage t13 can also be called the emission stage. In the third stage t13 of the current frame, the first emission control signal provided by the first emission control line EM1 jumps to a low level signal, the second emission control signal provided by the second emission control line EM2 jumps to a low level signal, the first scan signal provided by the first scan line GL1 remains at a high level, and the second scan signal provided by the second scan line GL2 jumps to a high level signal.

[0116] Under the influence of a low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is supplied to the second node N2 through the turned-on power control transistor T7. Under the influence of a low-level signal provided by the second light-emitting control line EM2, the coupling control transistor T2 and the light-emitting control transistor T8 are turned on, while the data writing transistor T1, the first reset control transistor T3, the second reset control transistor T4, the first reset transistor T6, and the second reset transistor T9 are all turned off.

[0117] Because the potential of the second terminal of the driving transistor T5 changes from Vref1-Vth to Vdd, under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 changes from Vref1 to Vdata+Vdd-Vref1+Vth, causing the driving transistor T5 to conduct and drive the light-emitting element EL to emit light. Specifically, because the coupling control transistor T2 is turned on, the control terminal of the driving transistor T5 is electrically connected to the first terminal of the first capacitor C1; because the power control transistor T7 is turned on, the potential of the second terminal of the driving transistor T5 (i.e., the second terminal of the second capacitor) changes from Vref1-Vth to Vdd, and the change in potential of the second terminal of the driving transistor T5 is Vdd-Vref1+Vth. According to the law of conservation of charge, the potential of the control terminal of the driving transistor T5 becomes Vdata+Vdd-Vref1+Vth.

[0118] When driving the pixel circuit provided in the above embodiments using the driving method provided in this disclosure, in the first stage t11, the control electrode potential of the driving transistor T5 is changed to the first reference voltage Vref1, and the potential of the second electrode of the driving transistor T5 is changed to Vdd, so that the voltages of the control electrode and the second electrode of the driving transistor T5 are both in a fixed bias state, thereby initializing the driving transistor T5. Therefore, regardless of whether each pixel unit displays a black or white image in the previous frame, the driving transistor T5 starts the display of the next frame from a fixed bias state, thereby effectively improving the problem of short-term image retention caused by hysteresis.

[0119] In the second stage t12, by controlling the second terminal of the driving transistor T5 to be disconnected from the first power line VDD, the driving transistor T5 undergoes a discharge process until the driving transistor T5 is turned off.

[0120] In the third stage t13, the potential of the second terminal of the driving transistor T5 jumps from Vref1-Vth to the power supply voltage Vdd. Under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 jumps to Vdata+Vdd-Vref1+Vth, thereby turning on the driving transistor T5. At this time, the voltage difference Vgs between the control terminal and the second terminal of the driving transistor T5 is Vdata-Vref1+Vth. The driving current I generated when the driving transistor T5 is turned on and operating in saturation is: I = k×(Vdata-Vref1) 2 , where k is a constant.

[0121] Figure 8A is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Compared with the equivalent circuit diagram of the pixel circuit shown in Figure 7, in the pixel circuit shown in Figure 8A, the data writing transistor T1, the first reset control transistor T3, and the second reset control transistor T4 are all N-type transistors, and the other transistors are all P-type transistors. Furthermore, the display cycle of this pixel circuit includes both refresh frames and hold frames.

[0122] In some examples, as shown in Figure 8A, the data writing subcircuit 22 includes a data writing transistor T1, the coupling control subcircuit 241 includes a coupling control transistor T2, the first coupling subcircuit 242 includes a first capacitor C1, the second coupling subcircuit 243 includes a second capacitor C2, the first reset control subcircuit 251 includes a first reset control transistor T3, the second reset control subcircuit 252 includes a second reset control transistor T4, the driving subcircuit 21 includes a driving transistor T5, the first reset subcircuit 26 includes a first reset transistor T6, the power control subcircuit 23 includes a power control transistor T7, the light emission control subcircuit 27 includes a light emission control transistor T8, and the second reset subcircuit 28 includes a second reset transistor T9.

[0123] Specifically, the control electrode of data writing transistor T1 is electrically connected to the first scan line GL1, the first electrode of data writing transistor T1 is electrically connected to the data line DL, and the second electrode of data writing transistor T1 is electrically connected to the fourth node N4. The control electrode of coupling control transistor T2 is electrically connected to the second scan line GL2, the first electrode of coupling control transistor T2 is electrically connected to the fourth node N4, and the second electrode of coupling control transistor T2 is electrically connected to the first node N1. The first plate of the first capacitor C1 is electrically connected to the fourth node N4, and the second plate of the first capacitor C1 is electrically connected to the fifth node N5. The first plate of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate of the second capacitor C2 is electrically connected to the second node N2. The control electrode of the first reset control transistor T3 is electrically connected to the second scan line GL2, the first electrode of the first reset control transistor T3 is electrically connected to the first reference voltage line REF1, and the second electrode of the first reset control transistor T3 is electrically connected to the fifth node N5. The control electrode of the second reset control transistor T4 is electrically connected to the second scan line GL2, the first electrode of the second reset control transistor T4 is electrically connected to the fifth node N5, and the second electrode of the second reset control transistor T4 is electrically connected to the first node N1. The control electrode of the driving transistor T5 is electrically connected to the first node N1, the first electrode of the driving transistor T5 is electrically connected to the second node N2, and the second electrode of the driving transistor T5 is electrically connected to the third node N3. The control electrode of the first reset transistor T6 is electrically connected to the first reset control line Reset_H, the first electrode of the first reset transistor T6 is electrically connected to the first initial voltage line INIT1, and the second electrode of the first reset transistor T6 is electrically connected to the third node N3. The control electrode of the power control transistor T7 is electrically connected to the first light emission control line EM1, the first electrode of the power control transistor T7 is electrically connected to the first power supply line VDD, and the second electrode of the power control transistor T7 is electrically connected to the second node N2. The control electrode of the light-emitting control transistor T8 is electrically connected to the second light-emitting control line EM2. The first electrode of the light-emitting control transistor T8 is electrically connected to the third node N3, and the second electrode of the light-emitting control transistor T8 is electrically connected to the sixth node N6. The control electrode of the second reset transistor T9 is electrically connected to the first reset control line Reset_H. The first electrode of the second reset transistor T9 is electrically connected to the second initial voltage line INIT2, and the second electrode of the second reset transistor T9 is electrically connected to the sixth node N6. The sixth node N6 is electrically connected to the first electrode of the light-emitting element EL, and the second electrode of the light-emitting element EL is electrically connected to the second power supply line VSS.

[0124] In this example, the first node N1 is the connection point of the coupling control transistor T2, the second reset control transistor T4, and the driving transistor T5. The second node N2 is the connection point of the second capacitor C2, the power control transistor T7, and the driving transistor T5. The third node N3 is the connection point of the first reset transistor T6, the driving transistor T5, and the light-emitting control transistor T8. The fourth node N4 is the connection point of the data writing transistor T1, the coupling control transistor T2, and the first capacitor C1. The fifth node N5 is the connection point of the first capacitor C1, the second capacitor C2, the first reset control transistor T3, and the second reset control transistor T4. The sixth node N6 is the connection point of the light-emitting control transistor T8, the second reset transistor T9, and the first electrode of the light-emitting element.

[0125] Figure 8A shows an exemplary structure of the driver sub-circuit 21, data writing sub-circuit 22, power control sub-circuit 23, coupling control sub-circuit 241, first coupling sub-circuit 242, second coupling sub-circuit 243, first reset control sub-circuit 251, second reset control sub-circuit 252, first reset sub-circuit 26, light emission control sub-circuit 27, and second reset sub-circuit 28. It will be readily understood by those skilled in the art that the implementation of the above sub-circuits is not limited to this, as long as their functions can be achieved.

[0126] In some examples, as shown in Figure 8A, the data writing transistor T1, the first reset control transistor T3, and the second reset control transistor T4 can all be N-type transistors. The coupling control transistor T2, the driving transistor T5, the first reset transistor T6, the power control transistor T7, the light-emitting control transistor T8, and the second reset transistor T9 can all be P-type thin-film transistors. The pixel circuit in this example can be implemented using Low Temperature Polycrystalline Oxide (LTPO) technology. LTPO technology combines the advantages of Low Temperature Polycrystalline Silicon (LTPS) and Indium Gallium Zinc Oxide (IGZO), and can reduce power consumption while maintaining a high refresh rate.

[0127] Figure 8B is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Compared with the equivalent circuit diagram of the pixel circuit shown in Figure 8A, in the pixel circuit shown in Figure 8B, a connected bias voltage line Bias is set at the fifth node N5. During the low-frequency refresh stage (hold frame stage), the bias voltage line Bias and the second capacitor C2 couple and boost the voltage of the second node N2. The first initial voltage line INIT1 and the first reset transistor T6 reset the third node N3, thereby biasing the first and second terminals of the driving transistor T5, improving the biasing effect of the driving transistor T5.

[0128] Figure 9A is a timing diagram of the pixel circuit shown in Figure 8A during frame refresh, and Figures 10A and 11A are two timing diagrams of the pixel circuit shown in Figure 8A during frame holding. As shown in Figure 8A, the pixel circuit of this example includes: 9 transistors (i.e., transistors T1 to T9), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 9 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, second light emission control line EM2, first reference voltage line REF1, first reset control line Reset_H, first initial voltage line INIT1 and second initial voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0129] Figure 9B is a timing diagram of the pixel circuit shown in Figure 8B during frame refresh, and Figures 10B and 11B are two timing diagrams of the pixel circuit shown in Figure 8B during frame holding. As shown in Figure 8B, the pixel circuit of this example includes: 9 transistors (i.e., transistors T1 to T9), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 10 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, bias voltage line Bias, first light emission control line EM1, second light emission control line EM2, first reference voltage line REF1, first reset control line Reset_H, first initial voltage line INIT1 and second initial voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0130] The following section, using the timing diagram shown in Figure 9A, provides detailed examples of the operation of the pixel circuit shown in Figure 8A during different stages (t11 to t13) of frame refresh.

[0131] In this example, during the frame refresh phase, the operation of the pixel circuit during the display of an image frame can include stages t21 to t23. The potentials of each node at different stages are shown in Table 3.

[0132] Table 3

[0133] Referring to Figures 8A and 9A, the first stage t21 can also be called the reset and data writing stage. In the first stage t21 of the current frame, the first scan signal provided by the first scan line GL1 is a high-level signal, the second scan signal provided by the second scan line GL2 is a high-level signal, the first light emission control signal provided by the first light emission control line EM1 is a low-level signal, the second light emission control signal provided by the second light emission control line EM2 is a high-level signal, and the first reset control signal provided by the first reset control line Reset_H is a low-level signal.

[0134] Under the influence of the high-level signal provided by the first scan line GL1, the data writing transistor T1 is turned on, and the data signal provided by the data line DL is written to the fourth node N4 through the turned-on data writing transistor T1, and the voltage of the fourth node N4 becomes Vdata. Under the influence of the low-level signal provided by the first reset control line Reset_H, the first reset transistor T6 and the second reset transistor T9 are turned on, and the first initial voltage signal provided by the first initial voltage line INIT1 is written to the third node N3 through the turned-on first reset transistor T6, and the voltage of the third node N3 is reset to the first initial voltage Vinit1. The second initial voltage signal provided by the second initial voltage line INIT2 is written to the sixth node N6 through the turned-on second reset transistor T9, and the voltage of the sixth node N6 is reset to the second initial voltage Vinit2. Since the sixth node N6 is electrically connected to the anode of the light-emitting element EL, the light-emitting element EL is also reset. Under the influence of the high-level signal provided by the second scan line GL2, the first reset control transistor T3 and the second reset control transistor T4 are turned on. The first reference voltage signal provided by the first reference voltage line REF1 is provided to the fifth node N5 through the turned-on first reset control transistor T3, so that the potential of the fifth node N5 is reset to the first reference voltage Vref1. At the same time, the potential of the fifth node N5 is provided to the first node N1 through the turned-on second reset control transistor T4, so that the potential of the first node N1 is also reset to the first reference voltage Vref1. Since the first node N1 is electrically connected to the control electrode of the driving transistor T5, the control electrode of the driving transistor T5 is reset to the first reference voltage Vref1. Under the influence of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on. The first power supply voltage signal provided by the first power supply line VDD is provided to the second node N2 through the turned-on power control transistor T7, that is, the potential of the second electrode of the driving transistor T5 becomes the first power supply voltage Vdd. Since the voltages at both the control and second terminals of the driving transistor T5 are in a fixed bias state, the driving transistor T5 is turned on, preparing for the threshold compensation in the second stage t22. It should be noted that in the first stage t21, in order for the driving transistor T5 to turn on, the turn-on condition of the driving transistor T5 should be met, that is, Vref1-Vdd should be less than the threshold voltage Vth of the driving transistor T5.

[0135] The second stage t22 can also be called the threshold compensation stage. In the second stage t22 of the current frame, the first scan signal provided by the first scan line GL1 jumps to a low level signal, the second scan signal provided by the second scan line GL2 remains at a high level signal, the first light emission control signal provided by the first light emission control line EM1 jumps to a high level signal, the second light emission control signal provided by the second light emission control line EM2 remains at a high level signal, and the first reset control signal provided by the first reset control line Reset_H remains at a low level signal.

[0136] Since the second scan signal provided by the second scan line GL2 remains high, the first reset control transistor T3 and the second reset control transistor T4 remain on. The first reference voltage signal provided by the first reference voltage line REF1 is still transmitted to the fifth node N5 and the first node N1, and the voltages of the fifth node N5 and the first node N1 remain the first reference voltage Vref1. Since the first reset control signal provided by the first reset control line Reset_H remains low, the first reset transistor T6 and the second reset transistor T9 remain on. The first initial voltage signal provided by the first initial voltage line INIT1 is still written to the third node N3, and the voltage of the third node N3 remains the first initial voltage Vinit1. The second initial voltage signal provided by the second initial voltage line INIT2 is still written to the sixth node N6, and the voltage of the sixth node N6 remains the second initial voltage Vinit2.

[0137] Since both the first light-emitting control line EM1 and the second light-emitting control line EM2 output high-level signals, both the power control transistor T7 and the light-emitting control transistor T8 are turned off. In this situation, the second node N2 is disconnected from the first power line VDD, and the second terminal of the driving transistor T5 is in a floating state. The driving transistor T5 undergoes a discharge process, changing from being on to being off, thus causing the potential of the second terminal of the driving transistor T5 to change from Vdd to Vref1-Vth, where Vth is the threshold voltage of the driving transistor T5. It should be noted that during this second stage t22, when the driving transistor T5 undergoes a discharge process, the potential of the second terminal of the driving transistor T5 starts to decrease from Vdd until it decreases to Vref1-Vth, at which point the conduction condition of the driving transistor T5 is not met, causing the driving transistor T5 to turn off.

[0138] In this embodiment of the disclosure, the range of threshold voltage compensation performed by the driving transistor T5 can be adjusted by adjusting the magnitudes of the first power supply voltage Vdd and the first initial voltage Vinit1.

[0139] The third stage t23 can also be called the emission stage. In the third stage t23 of the current frame, the first emission control signal provided by the first emission control line EM1 jumps to a low level signal, the second emission control signal provided by the second emission control line EM2 jumps to a low level signal, the first scan signal provided by the first scan line GL1 remains at a low level, the second scan signal provided by the second scan line GL2 jumps to a low level signal, and the first reset control signal provided by the first reset control line Reset_H jumps to a high level signal.

[0140] Under the influence of a low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is supplied to the second node N2 through the turned-on power control transistor T7. Under the influence of a low-level signal provided by the second light-emitting control line EM2, the light-emitting control transistor T8 is turned on, and under the influence of a low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on. The data writing transistor T1, the first reset control transistor T3, the second reset control transistor T4, the first reset transistor T6, and the second reset transistor T9 are all turned off.

[0141] Because the potential of the second terminal of the driving transistor T5 changes from Vref1-Vth to Vdd, under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 changes from Vref1 to Vdata+Vdd-Vref1+Vth, causing the driving transistor T5 to conduct and drive the light-emitting element EL to emit light. Specifically, because the coupling control transistor T2 is turned on, the control terminal of the driving transistor T5 is electrically connected to the first plate of the first capacitor C1; because the power control transistor T7 is turned on, the potential of the second terminal of the driving transistor T5 (i.e., the second plate of the second capacitor) changes from Vref1-Vth to Vdd, and the change in potential of the second terminal of the driving transistor T5 is Vdd-Vref1+Vth. According to the law of conservation of charge, the potential of the control terminal of the driving transistor T5 becomes Vdata+Vdd-Vref1+Vth.

[0142] When driving the pixel circuit provided in the above embodiments using the driving method provided in this disclosure, in the first stage t21, the control electrode potential of the driving transistor T5 is changed to the first reference voltage Vref1, and the potential of the second electrode of the driving transistor T5 is changed to Vdd, so that the voltages of the control electrode and the second electrode of the driving transistor T5 are both in a fixed bias state, thereby initializing the driving transistor T5. Therefore, regardless of whether each pixel unit displays a black or white image in the previous frame, the driving transistor T5 starts the display of the next frame from a fixed bias state, thereby effectively improving the problem of short-term image retention caused by hysteresis.

[0143] In the second stage t22, by controlling the second terminal of the driving transistor T5 to be disconnected from the first power line VDD, the driving transistor T5 undergoes a discharge process until the driving transistor T5 is turned off.

[0144] In the third stage t23, the potential of the second terminal of the driving transistor T5 jumps from Vref1-Vth to the power supply voltage Vdd. Under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 jumps to Vdata+Vdd-Vref1+Vth, thereby turning on the driving transistor T5. At this time, the voltage difference Vgs between the control terminal and the second terminal of the driving transistor T5 is Vdata-Vref1+Vth. The driving current I generated when the driving transistor T5 is turned on and operating in saturation is: I = k×(Vdata-Vref1) 2 , where k is a constant.

[0145] It should be noted that the operating range of the driving transistor T5 is related to the magnitude of the first reference voltage Vref1. The higher the first reference voltage Vref1, the larger the minimum value of the data signal Vdata_min. In addition, the threshold voltage compensation range of the driving transistor T5 can be adjusted by adjusting the magnitude of the first power supply voltage Vdd provided by the first power supply line VDD and the first initial voltage Vinit1 provided by the first initial signal line. The value of the first power supply voltage Vdd is greater than Vref1-Vth. The second power supply voltage provided by the second power supply line VSS is selected according to the characteristics of the light-emitting element EL to ensure that the driving transistor T5 operates in saturation.

[0146] On the other hand, during the frame holding phase, the operation of the pixel circuit can include a fourth stage t24 and a fifth stage t25. The fourth stage t24 can also be called the light holding stage, and the fifth stage t25 can also be called the reset stage. The potentials of each node in different stages are shown in Table 4.

[0147] Table 4

[0148] Referring to Figures 10A and 8A, during the hold frame phase, the first scan signal provided by the first scan line GL1 remains at a low level, and no new data signal is written. That is, the light-emitting element EL displays the image using the grayscale values ​​written in the refresh frame. During the hold frame phase, the second scan signal provided by the second scan line GL2 also remains at a low level. In each fourth phase t24, when both the first light-emitting control signal provided by the first light-emitting control line EM1 and the second light-emitting control signal provided by the second light-emitting control line EM2 are low, the drive current generated by the drive transistor T5 is transmitted to the light-emitting element EL to drive it to emit light.

[0149] In the fourth stage t24, the first light-emitting control signal output from the first light-emitting control line EM1 is a low-level signal, the second light-emitting control signal output from the second light-emitting control line EM2 is a low-level signal, and the first reset control signal output from the first reset control line Reset_H is a high-level signal. Under the action of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is provided to the second node N2 through the turned-on power control transistor T7. Under the action of the low-level signal provided by the second light-emitting control line EM2, the light-emitting control transistor T8 is turned on, and under the action of the low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on. The data writing transistor T1, the first reset control transistor T3, the second reset control transistor T4, the first reset transistor T6, and the second reset transistor T9 are all turned off.

[0150] In the fourth stage t24, the output of the second scan line GL2 remains low, that is, the coupling control transistor T2 remains on. Therefore, the voltage change of the second terminal of the driving transistor T5 is coupled to the first node N1 by the first capacitor C1, the second capacitor C2 and the coupling control transistor T2, so that the voltage of the first node N1 is Vdata+Vdd-Vref1+Vth, thereby driving the current.

[0151] In the fifth stage t25, the first light-emitting control signal output from the first light-emitting control line EM1 is a low-level signal, the second light-emitting control signal output from the second light-emitting control line EM2 is a high-level signal, and the first reset control signal output from the first reset control line Reset_H is a low-level signal. Under the action of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is provided to the second node N2 through the turned-on power control transistor T7. Under the action of the high-level signal provided by the second light-emitting control line EM2, the light-emitting control transistor T8 is turned off, and the light-emitting element EL does not emit light. Under the action of the low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on, and under the action of the low-level signal provided by the first reset control line Reset_H, the first reset transistor T6 and the second reset transistor T9 are turned on, while the data writing transistor T1, the first reset control transistor T3, and the second reset control transistor T4 are all turned off.

[0152] The first initial voltage signal provided by the first initial voltage line INIT1 is written to the third node N3 through the first reset transistor T6, and the voltage of the third node N3 is reset to the first initial voltage Vinit1. The second initial voltage signal provided by the second initial voltage line INIT2 is written to the sixth node N6 through the second reset transistor T9, and the voltage of the sixth node N6 is reset to the second initial voltage Vinit2. Since the sixth node N6 is electrically connected to the anode of the light-emitting element EL, the light-emitting element EL is also reset.

[0153] As shown in Figure 11A, the frequency of setting the reset phase during the hold frame phase does not correspond one-to-one with the hold light phase. That is, as shown in Figure 10A, a reset phase can be set every other hold light phase, or a reset phase can be set every multiple hold light phases. Figure 11A exemplarily shows a reset phase set every two hold light phases; of course, the number of intervals can be set more as needed, which is not limited in this article.

[0154] The operation of the pixel circuit shown in Figure 8B can be referred to the operation of the pixel circuit shown in Figure 8A described above, and will not be repeated here. In Figure 8B, the first plate (fifth node N5) of the second capacitor C2 is pulled up by the bias voltage line Bias during the low-frequency refresh stage (specifically the reset stage t25), and coupled to the second node N2 through the second capacitor C2, thereby improving the bias effect of the driving transistor T5.

[0155] Referring to Figures 8B and 10B (or 11B), in the fifth stage t25, the first light-emitting control signal output from the first light-emitting control line EM1 is a high-level signal, the second light-emitting control signal output from the second light-emitting control line EM2 is a high-level signal, the first reset control signal output from the first reset control line Reset_H is a low-level signal, and the bias voltage signal output from the bias voltage line Bias is a high-level signal. Under the action of the high-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned off, and the bias voltage signal provided by the bias voltage line Bias is coupled to the second node N2 through the second capacitor C2, causing the voltage of the second node N2 to be pulled high. Under the action of the high-level signal provided by the second light-emitting control line EM2, the light-emitting control transistor T8 is turned off, and the light-emitting element EL does not emit light. Under the influence of the low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on. Under the influence of the low-level signal provided by the first reset control line Reset_H, the first reset transistor T6 and the second reset transistor T9 are turned on, while the data writing transistor T1, the first reset control transistor T3 and the second reset control transistor T4 are all turned off.

[0156] It should be noted that, in conjunction with Figures 8B and 9B, the bias voltage line Bias can also pull up the potential of the first plate (fifth node N5) of the second capacitor C2 during the threshold compensation stage (t22), and couple it to the second node N2 through the second capacitor C2, thereby further improving the reset effect of the driving transistor T5.

[0157] Figure 12 is another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. Compared with the equivalent circuit diagram of the pixel circuit shown in Figure 8A, the pixel circuit of Figure 12 does not include the light emission control sub-circuit 27 and the second reset sub-circuit 28, which can reduce the signal traces in the display panel and simplify the timing of driving the pixel circuit. The display cycle of this pixel circuit still includes both refresh frames and hold frames.

[0158] In some examples, as shown in Figure 12, the data writing subcircuit 22 includes a data writing transistor T1, the coupling control subcircuit 241 includes a coupling control transistor T2, the first coupling subcircuit 242 includes a first capacitor C1, the second coupling subcircuit 243 includes a second capacitor C2, the first reset control subcircuit 251 includes a first reset control transistor T3, the second reset control subcircuit 252 includes a second reset control transistor T4, the drive subcircuit 21 includes a drive transistor T5, the first reset subcircuit 26 includes a first reset transistor T6, and the power control subcircuit 23 includes a power control transistor T7.

[0159] Specifically, the control electrode of data writing transistor T1 is electrically connected to the first scan line GL1, the first electrode of data writing transistor T1 is electrically connected to the data line DL, and the second electrode of data writing transistor T1 is electrically connected to the fourth node N4. The control electrode of coupling control transistor T2 is electrically connected to the second scan line GL2, the first electrode of coupling control transistor T2 is electrically connected to the fourth node N4, and the second electrode of coupling control transistor T2 is electrically connected to the first node N1. The first plate of the first capacitor C1 is electrically connected to the fourth node N4, and the second plate of the first capacitor C1 is electrically connected to the fifth node N5. The first plate of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate of the second capacitor C2 is electrically connected to the second node N2. The control electrode of the first reset control transistor T3 is electrically connected to the second scan line GL2, the first electrode of the first reset control transistor T3 is electrically connected to the first reference voltage line REF1, and the second electrode of the first reset control transistor T3 is electrically connected to the fifth node N5. The control electrode of the second reset control transistor T4 is electrically connected to the second scan line GL2, the first electrode of the second reset control transistor T4 is electrically connected to the fifth node N5, and the second electrode of the second reset control transistor T4 is electrically connected to the first node N1. The control electrode of the driving transistor T5 is electrically connected to the first node N1, the first electrode of the driving transistor T5 is electrically connected to the second node N2, and the second electrode of the driving transistor T5 is electrically connected to the third node N3. The control electrode of the first reset transistor T6 is electrically connected to the first reset control line Reset_H, the first electrode of the first reset transistor T6 is electrically connected to the first initial voltage line INIT1, and the second electrode of the first reset transistor T6 is electrically connected to the third node N3. The control electrode of the power control transistor T7 is electrically connected to the first light emission control line EM1, the first electrode of the power control transistor T7 is electrically connected to the first power supply line VDD, and the second electrode of the power control transistor T7 is electrically connected to the second node N2. The third node N3 is electrically connected to the first electrode of the light-emitting element EL, and the second electrode of the light-emitting element EL is electrically connected to the second power line VSS.

[0160] In this example, the first node N1 is the connection point of the coupling control transistor T2, the second reset control transistor T4, and the driving transistor T5. The second node N2 is the connection point of the second capacitor C2, the power control transistor T7, and the driving transistor T5. The third node N3 is the connection point of the first reset transistor T6, the driving transistor T5, and the first electrode of the light-emitting element EL. The fourth node N4 is the connection point of the data writing transistor T1, the coupling control transistor T2, and the first capacitor C1. The fifth node N5 is the connection point of the first capacitor C1, the second capacitor C2, the first reset control transistor T3, and the second reset control transistor T4.

[0161] Figure 12 shows an exemplary structure of the driver sub-circuit 21, data writing sub-circuit 22, power control sub-circuit 23, coupling control sub-circuit 241, first coupling sub-circuit 242, second coupling sub-circuit 243, first reset control sub-circuit 251, second reset control sub-circuit 252, and first reset sub-circuit 26. It is easy for those skilled in the art to understand that the implementation of the above sub-circuits is not limited to this, as long as their functions can be achieved.

[0162] In some examples, as shown in Figure 12, the data write transistor T1, the first reset control transistor T3, and the second reset control transistor T4 can all be N-type transistors. The coupling control transistor T2, the drive transistor T5, the first reset transistor T6, and the power control transistor T7 can all be P-type thin-film transistors, which can be implemented using low-temperature polycrystalline oxide (LTPO) technology. LTPO technology combines the advantages of low-temperature polycrystalline silicon (LTPS) and indium gallium zinc oxide (IGZO), and can reduce power consumption while maintaining a high refresh rate.

[0163] Figure 13 is a timing diagram of the pixel circuit shown in Figure 12 during frame refresh, and Figures 14 and 15 are two timing diagrams of the pixel circuit shown in Figure 12 during frame holding. As shown in Figure 12, the pixel circuit of this example includes: 7 transistors (i.e., transistors T1 to T7), 2 capacitor units (i.e., first capacitor C1 and second capacitor C2), 8 input terminals (i.e., data line DL, first scan line GL1, second scan line GL2, first light emission control line EM1, first reference voltage line REF1, first reset control line Reset_H, first initial voltage line INIT1 and second initial voltage line INIT2), and 2 power supply terminals (i.e., first power supply line VDD and second power supply line VSS).

[0164] The following section, using the timing diagram shown in Figure 13, provides detailed examples illustrating the operation of the pixel circuit shown in Figure 12 during different stages (t31~t33) of frame refresh.

[0165] In this example, during the frame refresh phase, the operation of the pixel circuit during the display of an image frame can include stages t31 to t33. The potentials of each node at different stages are shown in Table 5.

[0166] Table 5

[0167] The following is a detailed introduction.

[0168] Referring to Figures 12 and 13, the first stage t31 can also be called the reset and data writing stage. In the first stage t31 of the current frame, the first scan signal provided by the first scan line GL1 is a high-level signal, the second scan signal provided by the second scan line GL2 is a high-level signal, the first light emission control signal provided by the first light emission control line EM1 is a low-level signal, and the first reset control signal provided by the first reset control line Reset_H is a low-level signal.

[0169] Under the influence of the high-level signal provided by the first scan line GL1, the data writing transistor T1 is turned on, and the data signal provided by the data line DL is written to the fourth node N4 through the turned-on data writing transistor T1, and the voltage of the fourth node N4 becomes Vdata. Under the influence of the low-level signal provided by the first reset control line Reset_H, the first reset transistor T6 is turned on, and the first initial voltage signal provided by the first initial voltage line INIT1 is written to the third node N3 through the turned-on first reset transistor T6, and the voltage of the third node N3 is reset to the first initial voltage Vinit1. Since the third node N3 is electrically connected to the anode of the light-emitting element EL, the light-emitting element EL is also reset. Under the influence of the high-level signal provided by the second scan line GL2, the first reset control transistor T3 and the second reset control transistor T4 are turned on. The first reference voltage signal provided by the first reference voltage line REF1 is provided to the fifth node N5 through the turned-on first reset control transistor T3, so that the potential of the fifth node N5 is reset to the first reference voltage Vref1. At the same time, the potential of the fifth node N5 is provided to the first node N1 through the turned-on second reset control transistor T4, so that the potential of the first node N1 is also reset to the first reference voltage Vref1. Since the first node N1 is electrically connected to the control electrode of the driving transistor T5, the control electrode of the driving transistor T5 is reset to the first reference voltage Vref1. Under the influence of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on. The first power supply voltage signal provided by the first power supply line VDD is provided to the second node N2 through the turned-on power control transistor T7, that is, the potential of the second electrode of the driving transistor T5 becomes the first power supply voltage Vdd. Since the voltages at both the control and second terminals of the driving transistor T5 are in a fixed bias state, the driving transistor T5 is turned on, preparing for the threshold compensation in the second stage t32. It should be noted that in the first stage t31, in order for the driving transistor T5 to turn on, the turn-on condition of the driving transistor T5 should be met, that is, Vref1-Vdd should be less than the threshold voltage Vth of the driving transistor T5.

[0170] The second stage t32 can also be called the threshold compensation stage. In the second stage t32 of the current frame, the first scan signal provided by the first scan line GL1 jumps to a low level signal, the second scan signal provided by the second scan line GL2 remains at a high level signal, the first light emission control signal provided by the first light emission control line EM1 jumps to a high level signal, and the first reset control signal provided by the first reset control line Reset_H remains at a low level signal.

[0171] Since the second scan signal provided by the second scan line GL2 remains high, the first reset control transistor T3 and the second reset control transistor T4 remain on. The first reference voltage signal provided by the first reference voltage line REF1 is still transmitted to the fifth node N5 and the first node N1, and the voltages of the fifth node N5 and the first node N1 remain the first reference voltage Vref1. Since the first reset control signal provided by the first reset control line Reset_H remains low, the first reset transistor T6 remains on, and the first initial voltage signal provided by the first initial voltage line INIT1 is still written to the third node N3, and the voltage of the third node N3 remains the first initial voltage Vinit1.

[0172] Because the first light-emitting control line EM1 outputs a high-level signal, the power control transistor T7 is turned off. In this situation, the second node N2 is disconnected from the first power line VDD, and the second terminal of the driving transistor T5 is in a floating state. The driving transistor T5 undergoes a discharge process, changing from being on to being off, thus causing the potential of the second terminal of the driving transistor T5 to change from Vdd to Vref1-Vth, where Vth is the threshold voltage of the driving transistor T5. It should be noted that during this second stage t32, when the driving transistor T5 undergoes the discharge process, the potential of the second terminal of the driving transistor T5 starts to decrease from Vdd until it decreases to Vref1-Vth, at which point the conduction condition of the driving transistor T5 is not met, causing the driving transistor T5 to turn off.

[0173] In this embodiment of the disclosure, the range of threshold voltage compensation performed by the driving transistor T5 can be adjusted by adjusting the magnitudes of the first power supply voltage Vdd and the first initial voltage Vinit1.

[0174] The third stage t33 can also be called the light emission stage. In the third stage t33 of the current frame, the first light emission control signal provided by the first light emission control line EM1 jumps to a low level signal, the first scan signal provided by the first scan line GL1 remains at a low level, the second scan signal provided by the second scan line GL2 jumps to a low level signal, and the first reset control signal provided by the first reset control line Reset_H jumps to a high level signal.

[0175] Under the influence of a low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is supplied to the second node N2 through the turned-on power control transistor T7. Under the influence of a low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on, and the data writing transistor T1, the first reset control transistor T3, the second reset control transistor T4, and the first reset transistor T6 are all turned off.

[0176] Because the potential of the second terminal of the driving transistor T5 changes from Vref1-Vth to Vdd, under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 changes from Vref1 to Vdata+Vdd-Vref1+Vth, causing the driving transistor T5 to conduct and drive the light-emitting element EL to emit light. Specifically, because the coupling control transistor T2 is turned on, the control terminal of the driving transistor T5 is electrically connected to the first plate of the first capacitor C1; because the power control transistor T7 is turned on, the potential of the second terminal of the driving transistor T5 (i.e., the second plate of the second capacitor) changes from Vref1-Vth to Vdd, and the change in potential of the second terminal of the driving transistor T5 is Vdd-Vref1+Vth. According to the law of conservation of charge, the potential of the control terminal of the driving transistor T5 becomes Vdata+Vdd-Vref1+Vth.

[0177] When driving the pixel circuit provided in the above embodiments using the driving method provided in this disclosure, in the first stage t31, the control electrode potential of the driving transistor T5 is changed to the first reference voltage Vref1, and the potential of the second electrode of the driving transistor T5 is changed to Vdd, so that the voltages of the control electrode and the second electrode of the driving transistor T5 are both in a fixed bias state, thereby initializing the driving transistor T5. Therefore, regardless of whether each pixel unit displays a black or white image in the previous frame, the driving transistor T5 starts the display of the next frame from a fixed bias state, thereby effectively improving the problem of short-term image retention caused by hysteresis.

[0178] In the second stage t32, by controlling the second terminal of the driving transistor T5 to be disconnected from the first power line VDD, the driving transistor T5 undergoes a discharge process until the driving transistor T5 is turned off.

[0179] In the third stage t33, the potential of the second terminal of the driving transistor T5 jumps from Vref1-Vth to the power supply voltage Vdd. Under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 jumps to Vdata+Vdd-Vref1+Vth, thereby turning on the driving transistor T5. At this time, the voltage difference between the control terminal and the second terminal of the driving transistor T5 is Vgs=Vdata-Vref1+Vth. The driving current I generated when the driving transistor T5 is turned on and working in saturation state is: I=k×(Vdata-Vref1)2, where k is a constant.

[0180] It should be noted that the operating range of the driving transistor T5 is related to the magnitude of the first reference voltage Vref1. The higher the first reference voltage Vref1, the larger the minimum value of the data signal Vdata_min. In addition, the threshold voltage compensation range of the driving transistor T5 can be adjusted by adjusting the magnitude of the first power supply voltage Vdd provided by the first power supply line VDD and the first initial voltage Vinit1 provided by the first initial signal line. The value of the first power supply voltage Vdd is greater than Vref1-Vth. The second power supply voltage provided by the second power supply line VSS is selected according to the characteristics of the light-emitting element EL to ensure that the driving transistor T5 operates in saturation.

[0181] On the other hand, during the frame holding phase, the operation of the pixel circuit can include a fourth stage (t34) and a fifth stage (t35). The fourth stage (t34) can also be called the light-holding stage, and the fifth stage (t35) can also be called the reset stage. The potentials of each node at different stages are shown in Table 6.

[0182] Table 6

[0183] Referring to Figures 12 and 14, during the hold frame phase, the first scan signal provided by the first scan line GL1 remains at a low level, and no new data signal is written. That is, the light-emitting element EL displays the image using the grayscale values ​​written in the refresh frame. During the hold frame phase, the second scan signal provided by the second scan line GL2 also remains at a low level. In each fourth phase t34, when the first light-emitting control signal provided by the first light-emitting control line EM1 is low, the drive current generated by the drive transistor T5 is transmitted to the light-emitting element EL to drive it to emit light.

[0184] In the fourth stage t34, the first light-emitting control signal output from the first light-emitting control line EM1 is a low-level signal, and the first reset control signal output from the first reset control line Reset_H is a high-level signal. Under the action of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is provided to the second node N2 through the turned-on power control transistor T7. Under the action of the low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on, and the data writing transistor T1, the first reset control transistor T3, the second reset control transistor T4, and the first reset transistor T6 are all turned off.

[0185] In the fourth stage t34, the output of the second scan line GL2 remains low, meaning that the coupling control transistor T2 remains on. Therefore, the voltage change of the second terminal of the driving transistor T5 is coupled to the first node N1 using the first capacitor C1, the second capacitor C2, and the coupling control transistor T2, so that the voltage of the first node N1 is Vdata+Vdd-Vref1+Vth, thereby driving the current.

[0186] In the fifth stage t35, the first light-emitting control signal output from the first light-emitting control line EM1 is a high-level signal, and the first reset control signal output from the first reset control line Reset_H is a low-level signal. Under the action of the high-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned off, and the light-emitting element EL does not emit light. Under the action of the low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on, and under the action of the low-level signal provided by the first reset control line Reset_H, the first reset transistor T6 is turned on, while the data writing transistor T1, the first reset control transistor T3, and the second reset control transistor T4 are all turned off.

[0187] The first initial voltage signal provided by the first initial voltage line INIT1 is written to the third node N3 through the first reset transistor T6, and the voltage of the third node N3 is reset to the first initial voltage Vinit1. Since the third node N3 is electrically connected to the anode of the light-emitting element EL, the light-emitting element EL is also reset.

[0188] As shown in Figure 15, the frequency of setting the reset phase during the hold frame phase does not correspond one-to-one with the hold light phase. That is, as shown in Figure 14, a reset phase can be set every other hold light phase, or a reset phase can be set every multiple hold light phases. Figure 15 exemplarily shows a reset phase set every two hold light phases, but the number of intervals can be set more as needed, which is not limited in this article.

[0189] Figure 16 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 16, the coupling sub-circuit 24 may include a coupling control sub-circuit 241, a first coupling sub-circuit 242, and a second coupling sub-circuit 243. The coupling control sub-circuit 241 is connected to the coupling control line, the first node N1, and the fourth node N4, respectively. The first coupling sub-circuit 242 is connected to the fourth node N4 and the fifth node N5, respectively. The second coupling sub-circuit 243 is connected to the fifth node N5 and the second node N2, respectively.

[0190] During the light-emitting stage, the coupling control sub-circuit 241 conducts the first node N1 and the fourth node N4 under the control of the coupling control line; the first coupling sub-circuit 242 and the second coupling sub-circuit 243 couple and boost the voltage of the fourth node N4 according to the voltage change of the second node N2.

[0191] In this example, the coupling control line can be the second scan line GL2; however, this disclosure does not limit it to this.

[0192] In some examples, as shown in Figure 16, the reset control subcircuit 25 may include a first reset control subcircuit 251 and a second reset control subcircuit 252. The first reset control subcircuit 251 is connected to the second scan line GL2, the first reference voltage line REF1, and the first node N1, and is configured to write the first reference voltage signal of the first reference voltage line REF1 to the first node N1 under the control of the second scan line GL2. The second reset control subcircuit 252 is connected to the second scan line GL2, the first node N1, and the fifth node N5, and is configured to turn on or off the fifth node N5 and the first node N1 under the control of the second scan line GL2. For example, in the data writing stage and / or the threshold compensation stage, the first reset control subcircuit 251 and the second reset control subcircuit 252 may first write the first reference voltage signal of the first reference voltage line REF1 to the first node N1, and then turn on the first node N1 and the fifth node N5, meaning the voltage of the fifth node N5 also becomes the first reference voltage.

[0193] Figure 17 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 17, the data writing sub-circuit 22 includes a data writing transistor T1, the coupling control sub-circuit 241 includes a coupling control transistor T2, the first coupling sub-circuit 242 includes a first capacitor C1, the second coupling sub-circuit 243 includes a second capacitor C2, the first reset control sub-circuit 251 includes a first reset control transistor T3, the second reset control sub-circuit 252 includes a second reset control transistor T4, the driving sub-circuit 21 includes a driving transistor T5, the first reset sub-circuit 26 includes a first reset transistor T6, the power control sub-circuit 23 includes a power control transistor T7, the light emission control sub-circuit 27 includes a light emission control transistor T8, and the second reset sub-circuit 28 includes a second reset transistor T9.

[0194] Specifically, the control electrode of data writing transistor T1 is electrically connected to the first scan line GL1, the first electrode of data writing transistor T1 is electrically connected to the data line DL, and the second electrode of data writing transistor T1 is electrically connected to the fourth node N4. The control electrode of coupling control transistor T2 is electrically connected to the second scan line GL2, the first electrode of coupling control transistor T2 is electrically connected to the fourth node N4, and the second electrode of coupling control transistor T2 is electrically connected to the first node N1. The first plate of the first capacitor C1 is electrically connected to the fourth node N4, and the second plate of the first capacitor C1 is electrically connected to the fifth node N5. The first plate of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate of the second capacitor C2 is electrically connected to the second node N2. The control electrode of the first reset control transistor T3 is electrically connected to the second scan line GL2, the first electrode of the first reset control transistor T3 is electrically connected to the first reference voltage line REF1, and the second electrode of the first reset control transistor T3 is electrically connected to the first node N1. The control electrode of the second reset control transistor T4 is electrically connected to the second scan line GL2, the first electrode of the second reset control transistor T4 is electrically connected to the first node N1, and the second electrode of the second reset control transistor T4 is electrically connected to the fifth node N5. The control electrode of the driving transistor T5 is electrically connected to the first node N1, the first electrode of the driving transistor T5 is electrically connected to the second node N2, and the second electrode of the driving transistor T5 is electrically connected to the third node N3. The control electrode of the first reset transistor T6 is electrically connected to the first reset control line Reset_H, the first electrode of the first reset transistor T6 is electrically connected to the first initial voltage line INIT1, and the second electrode of the first reset transistor T6 is electrically connected to the third node N3. The control electrode of the power control transistor T7 is electrically connected to the first light emission control line EM1, the first electrode of the power control transistor T7 is electrically connected to the first power supply line VDD, and the second electrode of the power control transistor T7 is electrically connected to the second node N2. The control electrode of the light-emitting control transistor T8 is electrically connected to the second light-emitting control line EM2. The first electrode of the light-emitting control transistor T8 is electrically connected to the third node N3, and the second electrode of the light-emitting control transistor T8 is electrically connected to the sixth node N6. The control electrode of the second reset transistor T9 is electrically connected to the first reset control line Reset_H. The first electrode of the second reset transistor T9 is electrically connected to the second initial voltage line INIT2, and the second electrode of the second reset transistor T9 is electrically connected to the sixth node N6. The sixth node N6 is electrically connected to the first electrode of the light-emitting element EL, and the second electrode of the light-emitting element EL is electrically connected to the second power supply line VSS.

[0195] In this example, the first node N1 is the connection point of coupling control transistor T2, first reset control transistor T3, second reset control transistor T4, and driving transistor T5. The second node N2 is the connection point of second capacitor C2, power control transistor T7, and driving transistor T5. The third node N3 is the connection point of first reset transistor T6, driving transistor T5, and light-emitting control transistor T8. The fourth node N4 is the connection point of data writing transistor T1, coupling control transistor T2, and first capacitor C1. The fifth node N5 is the connection point of first capacitor C1, second capacitor C2, and second reset control transistor T4. The sixth node N6 is the connection point of light-emitting control transistor T8, second reset transistor T9, and the first electrode of the light-emitting element.

[0196] Figure 17 shows an exemplary structure of the driver sub-circuit 21, data writing sub-circuit 22, power control sub-circuit 23, coupling control sub-circuit 241, first coupling sub-circuit 242, second coupling sub-circuit 243, first reset control sub-circuit 251, second reset control sub-circuit 252, first reset sub-circuit 26, light emission control sub-circuit 27, and second reset sub-circuit 28. It is easy for those skilled in the art to understand that the implementation of the above sub-circuits is not limited to this, as long as their functions can be achieved.

[0197] In some examples, as shown in Figure 17, the data writing transistor T1, the first reset control transistor T3, and the second reset control transistor T4 can all be N-type transistors. The coupling control transistor T2, the driving transistor T5, the first reset transistor T6, the power control transistor T7, the light-emitting control transistor T8, and the second reset transistor T9 can all be P-type thin-film transistors, which can be implemented using low-temperature polycrystalline oxide (LTPO) technology. LTPO technology combines the advantages of low-temperature polycrystalline silicon (LTPS) and indium gallium zinc oxide (IGZO), and can reduce power consumption while maintaining a high refresh rate.

[0198] The pixel circuit shown in Figure 17 can be driven using the timing diagrams shown in Figures 9A and 10A (or 11A). The following detailed examples, using the timing diagrams shown in Figures 9A and 10A (or 11A), illustrate the operation of the pixel circuit shown in Figure 17 at different stages (t21~t25).

[0199] The display cycle of the pixel circuit includes refresh frames and hold frames. The refresh frame includes a first stage t21, a second stage t22, and a third stage t23. The potentials of each node in different stages are shown in Table 7.

[0200] Table 7

[0201] Referring to Figures 17 and 9A, the first stage t21 can also be called the reset and data writing stage. In the first stage t21 of the current frame, the first scan signal provided by the first scan line GL1 is a high-level signal, the second scan signal provided by the second scan line GL2 is a high-level signal, the first light emission control signal provided by the first light emission control line EM1 is a low-level signal, the second light emission control signal provided by the second light emission control line EM2 is a high-level signal, and the first reset control signal provided by the first reset control line Reset_H is a low-level signal.

[0202] Under the influence of the high-level signal provided by the first scan line GL1, the data writing transistor T1 is turned on, and the data signal provided by the data line DL is written to the fourth node N4 through the turned-on data writing transistor T1, and the voltage of the fourth node N4 becomes Vdata. Under the influence of the low-level signal provided by the first reset control line Reset_H, the first reset transistor T6 and the second reset transistor T9 are turned on, and the first initial voltage signal provided by the first initial voltage line INIT1 is written to the third node N3 through the turned-on first reset transistor T6, and the voltage of the third node N3 is reset to the first initial voltage Vinit1. The second initial voltage signal provided by the second initial voltage line INIT2 is written to the sixth node N6 through the turned-on second reset transistor T9, and the voltage of the sixth node N6 is reset to the second initial voltage Vinit2. Since the sixth node N6 is electrically connected to the anode of the light-emitting element EL, the light-emitting element EL is also reset. Under the influence of the high-level signal provided by the second scan line GL2, the first reset control transistor T3 and the second reset control transistor T4 are turned on. The first reference voltage signal provided by the first reference voltage line REF1 is provided to the first node N1 through the turned-on first reset control transistor T3, so that the potential of the first node N1 is reset to the first reference voltage Vref1. At the same time, the potential of the first node N1 is provided to the fifth node N5 through the turned-on second reset control transistor T4, so that the potential of the fifth node N5 is also reset to the first reference voltage Vref1. Since the first node N1 is electrically connected to the control electrode of the driving transistor T5, the control electrode of the driving transistor T5 is reset to the first reference voltage Vref1. Under the influence of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on. The first power supply voltage signal provided by the first power supply line VDD is provided to the second node N2 through the turned-on power control transistor T7, that is, the potential of the second electrode of the driving transistor T5 becomes the first power supply voltage Vdd. Since the voltages at both the control and second terminals of the driving transistor T5 are in a fixed bias state, the driving transistor T5 is turned on, preparing for the threshold compensation in the second stage t22. It should be noted that in the first stage t21, in order for the driving transistor T5 to turn on, the turn-on condition of the driving transistor T5 should be met, that is, Vref1-Vdd should be less than the threshold voltage Vth of the driving transistor T5.

[0203] The second stage t22 can also be called the threshold compensation stage. In the second stage t22 of the current frame, the first scan signal provided by the first scan line GL1 jumps to a low level signal, the second scan signal provided by the second scan line GL2 remains at a high level signal, the first light emission control signal provided by the first light emission control line EM1 jumps to a high level signal, the second light emission control signal provided by the second light emission control line EM2 remains at a high level signal, and the first reset control signal provided by the first reset control line Reset_H remains at a low level signal.

[0204] Since the second scan signal provided by the second scan line GL2 remains high, the first reset control transistor T3 and the second reset control transistor T4 remain on. The first reference voltage signal provided by the first reference voltage line REF1 is still transmitted to the first node N1 and the fifth node N5, and the voltages of the first node N1 and the fifth node N5 remain the first reference voltage Vref1. Since the first reset control signal provided by the first reset control line Reset_H remains low, the first reset transistor T6 and the second reset transistor T9 remain on. The first initial voltage signal provided by the first initial voltage line INIT1 is still written to the third node N3, and the voltage of the third node N3 remains the first initial voltage Vinit1. The second initial voltage signal provided by the second initial voltage line INIT2 is still written to the sixth node N6, and the voltage of the sixth node N6 remains the second initial voltage Vinit2.

[0205] Since both the first light-emitting control line EM1 and the second light-emitting control line EM2 output high-level signals, both the power control transistor T7 and the light-emitting control transistor T8 are turned off. In this situation, the second node N2 is disconnected from the first power line VDD, and the second terminal of the driving transistor T5 is in a floating state. The driving transistor T5 undergoes a discharge process, changing from being on to being off, thus causing the potential of the second terminal of the driving transistor T5 to change from Vdd to Vref1-Vth, where Vth is the threshold voltage of the driving transistor T5. It should be noted that during this second stage t22, when the driving transistor T5 undergoes a discharge process, the potential of the second terminal of the driving transistor T5 starts to decrease from Vdd until it decreases to Vref1-Vth, at which point the conduction condition of the driving transistor T5 is not met, causing the driving transistor T5 to turn off.

[0206] In this embodiment of the disclosure, the range of threshold voltage compensation performed by the driving transistor T5 can be adjusted by adjusting the magnitudes of the first power supply voltage Vdd and the first initial voltage Vinit1.

[0207] The third stage t23 can also be called the emission stage. In the third stage t23 of the current frame, the first emission control signal provided by the first emission control line EM1 jumps to a low level signal, the second emission control signal provided by the second emission control line EM2 jumps to a low level signal, the first scan signal provided by the first scan line GL1 remains at a low level, the second scan signal provided by the second scan line GL2 jumps to a low level signal, and the first reset control signal provided by the first reset control line Reset_H jumps to a high level signal.

[0208] Under the influence of a low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is supplied to the second node N2 through the turned-on power control transistor T7. Under the influence of a low-level signal provided by the second light-emitting control line EM2, the light-emitting control transistor T8 is turned on, and under the influence of a low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on. The data writing transistor T1, the first reset control transistor T3, the second reset control transistor T4, the first reset transistor T6, and the second reset transistor T9 are all turned off.

[0209] Because the potential of the second terminal of the driving transistor T5 changes from Vref1-Vth to Vdd, under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 changes from Vref1 to Vdata+Vdd-Vref1+Vth, causing the driving transistor T5 to conduct and drive the light-emitting element EL to emit light. Specifically, because the coupling control transistor T2 is turned on, the control terminal of the driving transistor T5 is electrically connected to the first plate of the first capacitor C1; because the power control transistor T7 is turned on, the potential of the second terminal of the driving transistor T5 (i.e., the second terminal of the second capacitor) changes from Vref1-Vth to Vdd, and the change in potential of the second terminal of the driving transistor T5 is Vdd-Vref1+Vth. According to the law of conservation of charge, the potential of the control terminal of the driving transistor T5 becomes Vdata+Vdd-Vref1+Vth.

[0210] When driving the pixel circuit provided in the above embodiments using the driving method provided in this disclosure, in the first stage t21, the control electrode potential of the driving transistor T5 is changed to the first reference voltage Vref1, and the potential of the second electrode of the driving transistor T5 is changed to Vdd, so that the voltages of the control electrode and the second electrode of the driving transistor T5 are both in a fixed bias state, thereby initializing the driving transistor T5. Therefore, regardless of whether each pixel unit displays a black or white image in the previous frame, the driving transistor T5 starts the display of the next frame from a fixed bias state, thereby effectively improving the problem of short-term image retention caused by hysteresis.

[0211] In the second stage t22, by controlling the second terminal of the driving transistor T5 to be disconnected from the first power line VDD, the driving transistor T5 undergoes a discharge process until the driving transistor T5 is turned off.

[0212] In the third stage t23, the potential of the second terminal of the driving transistor T5 jumps from Vref1-Vth to the power supply voltage Vdd. Under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 jumps to Vdata+Vdd-Vref1+Vth, thereby turning on the driving transistor T5. At this time, the voltage difference between the control terminal and the second terminal of the driving transistor T5 is Vgs=Vdata-Vref1+Vth. The driving current I generated when the driving transistor T5 is turned on and working in saturation state is: I=k×(Vdata-Vref1)2, where k is a constant.

[0213] It should be noted that the operating range of the driving transistor T5 is related to the magnitude of the first reference voltage Vref1. The higher the first reference voltage Vref1, the larger the minimum value of the data signal Vdata_min. In addition, the threshold voltage compensation range of the driving transistor T5 can be adjusted by adjusting the magnitude of the first power supply voltage Vdd provided by the first power supply line VDD and the first initial voltage Vinit1 provided by the first initial signal line. The value of the first power supply voltage Vdd is greater than Vref1-Vth. The second power supply voltage provided by the second power supply line VSS is selected according to the characteristics of the light-emitting element EL to ensure that the driving transistor T5 operates in saturation.

[0214] On the other hand, the holding frame includes a fourth stage t24 and a fifth stage t25. The fourth stage t24 can also be called the holding emission stage, and the fifth stage t25 can also be called the reset stage. The potentials of each node in different stages are shown in Table 8.

[0215] Table 8

[0216] Referring to Figures 17 and 10A, during the hold frame phase, the first scan signal provided by the first scan line GL1 remains at a low level, and no new data signal is written. That is, the light-emitting element EL displays the image using the grayscale values ​​written in the refresh frame. The second scan signal provided by the second scan line GL2 also remains at a low level. In each fourth phase t24, when both the first light-emitting control signal provided by the first light-emitting control line EM1 and the second light-emitting control signal provided by the second light-emitting control line EM2 are low, the drive current generated by the drive transistor T5 is transmitted to the light-emitting element EL to drive it to emit light.

[0217] In the fourth stage t24, the first light-emitting control signal output from the first light-emitting control line EM1 is a low-level signal, the second light-emitting control signal output from the second light-emitting control line EM2 is a low-level signal, and the first reset control signal output from the first reset control line Reset_H is a high-level signal. Under the action of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is provided to the second node N2 through the turned-on power control transistor T7. Under the action of the low-level signal provided by the second light-emitting control line EM2, the light-emitting control transistor T8 is turned on, and under the action of the low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on. The data writing transistor T1, the first reset control transistor T3, the second reset control transistor T4, the first reset transistor T6, and the second reset transistor T9 are all turned off.

[0218] In the fourth stage t24, the output of the second scan line GL2 remains low, that is, the coupling control transistor T2 remains on. Therefore, the voltage change of the second terminal of the driving transistor T5 is coupled to the first node N1 by the first capacitor C1, the second capacitor C2 and the coupling control transistor T2, so that the voltage of the first node N1 is Vdata+Vdd-Vref1+Vth, thereby driving the current.

[0219] In the fifth stage t25, the first light emission control signal output provided by the first light emission control line EM1 is a low-level signal, the second light emission control signal output provided by the second light emission control line EM2 is a high-level signal, and the first reset control signal output provided by the first reset control line Reset_H is a low-level signal.

[0220] Under the influence of a low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is supplied to the second node N2 through the turned-on power control transistor T7. Under the influence of a high-level signal provided by the second light-emitting control line EM2, the light-emitting control transistor T8 is turned off, and the light-emitting element EL does not emit light. Under the influence of a low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on. Under the influence of a low-level signal provided by the first reset control line Reset_H, the first reset transistor T6 and the second reset transistor T9 are turned on, while the data writing transistor T1, the first reset control transistor T3, and the second reset control transistor T4 are all turned off.

[0221] The first initial voltage signal provided by the first initial voltage line INIT1 is written to the third node N3 through the first reset transistor T6, and the voltage of the third node N3 is reset to the first initial voltage Vinit1. The second initial voltage signal provided by the second initial voltage line INIT2 is written to the sixth node N6 through the second reset transistor T9, and the voltage of the sixth node N6 is reset to the second initial voltage Vinit2. Since the sixth node N6 is electrically connected to the anode of the light-emitting element EL, the light-emitting element EL is also reset.

[0222] As shown in Figure 11A, the frequency of setting the reset phase during the hold frame phase does not correspond one-to-one with the hold light phase. That is, as shown in Figure 10A, a reset phase can be set every other hold light phase, or a reset phase can be set every multiple hold light phases. Figure 11A exemplarily shows a reset phase set every two hold light phases; of course, the number of intervals can be set more as needed, which is not limited in this article.

[0223] Figure 18 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 18, the data writing sub-circuit 22 includes a data writing transistor T1, the coupling control sub-circuit 241 includes a coupling control transistor T2, the first coupling sub-circuit 242 includes a first capacitor C1, the second coupling sub-circuit 243 includes a second capacitor C2, the first reset control sub-circuit 251 includes a first reset control transistor T3, the second reset control sub-circuit 252 includes a second reset control transistor T4, the driving sub-circuit 21 includes a driving transistor T5, the first reset sub-circuit 26 includes a first reset transistor T6, and the power control sub-circuit 23 includes a power control transistor T7.

[0224] Specifically, the control electrode of data writing transistor T1 is electrically connected to the first scan line GL1, the first electrode of data writing transistor T1 is electrically connected to the data line DL, and the second electrode of data writing transistor T1 is electrically connected to the fourth node N4. The control electrode of coupling control transistor T2 is electrically connected to the second scan line GL2, the first electrode of coupling control transistor T2 is electrically connected to the fourth node N4, and the second electrode of coupling control transistor T2 is electrically connected to the first node N1. The first plate of the first capacitor C1 is electrically connected to the fourth node N4, and the second plate of the first capacitor C1 is electrically connected to the fifth node N5. The first plate of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate of the second capacitor C2 is electrically connected to the second node N2. The control electrode of the first reset control transistor T3 is electrically connected to the second scan line GL2, the first electrode of the first reset control transistor T3 is electrically connected to the first reference voltage line REF1, and the second electrode of the first reset control transistor T3 is electrically connected to the first node N1. The control electrode of the second reset control transistor T4 is electrically connected to the second scan line GL2, the first electrode of the second reset control transistor T4 is electrically connected to the first node N1, and the second electrode of the second reset control transistor T4 is electrically connected to the fifth node N5. The control electrode of the driving transistor T5 is electrically connected to the first node N1, the first electrode of the driving transistor T5 is electrically connected to the second node N2, and the second electrode of the driving transistor T5 is electrically connected to the third node N3. The control electrode of the first reset transistor T6 is electrically connected to the first reset control line Reset_H, the first electrode of the first reset transistor T6 is electrically connected to the first initial voltage line INIT1, and the second electrode of the first reset transistor T6 is electrically connected to the third node N3. The control electrode of the power control transistor T7 is electrically connected to the first light emission control line EM1, the first electrode of the power control transistor T7 is electrically connected to the first power supply line VDD, and the second electrode of the power control transistor T7 is electrically connected to the second node N2. The third node N3 is electrically connected to the first electrode of the light-emitting element EL, and the second electrode of the light-emitting element EL is electrically connected to the second power line VSS.

[0225] In this example, the first node N1 is the connection point of coupling control transistor T2, first reset control transistor T3, second reset control transistor T4, and driving transistor T5. The second node N2 is the connection point of second capacitor C2, power control transistor T7, and driving transistor T5. The third node N3 is the connection point of first reset transistor T6, driving transistor T5, and the first electrode of the light-emitting element. The fourth node N4 is the connection point of data writing transistor T1, coupling control transistor T2, and first capacitor C1. The fifth node N5 is the connection point of first capacitor C1, second capacitor C2, and second reset control transistor T4.

[0226] Figure 18 shows an exemplary structure of the driver sub-circuit 21, data writing sub-circuit 22, power control sub-circuit 23, coupling control sub-circuit 241, first coupling sub-circuit 242, second coupling sub-circuit 243, first reset control sub-circuit 251, second reset control sub-circuit 252, and first reset sub-circuit 26. It is readily understood by those skilled in the art that the implementation of the above sub-circuits is not limited to this, as long as their functions can be achieved.

[0227] In some examples, as shown in Figure 18, the data write transistor T1, the first reset control transistor T3, and the second reset control transistor T4 can all be N-type transistors. The coupling control transistor T2, the drive transistor T5, the first reset transistor T6, and the power control transistor T7 can all be P-type thin-film transistors, which can be implemented using low-temperature polycrystalline oxide (LTPO) technology. LTPO technology combines the advantages of low-temperature polycrystalline silicon (LTPS) and indium gallium zinc oxide (IGZO), and can reduce power consumption while maintaining a high refresh rate.

[0228] The pixel circuit shown in Figure 18 can be driven using the timing diagrams shown in Figures 13 to 15. The following detailed examples, using the timing diagrams shown in Figures 13 to 15, illustrate the operation of the pixel circuit shown in Figure 18 at different stages (t31 to t35).

[0229] The display cycle of the pixel circuit includes refresh frames and hold frames. The refresh frame includes a first stage t31, a second stage t32, and a third stage t33. The potentials of each node at different stages are shown in Table 9.

[0230] Table 9

[0231] Referring to Figures 18 and 13, the first stage t31 can also be called the reset and data writing stage. In the first stage t31 of the current frame, the first scan signal provided by the first scan line GL1 is a high-level signal, the second scan signal provided by the second scan line GL2 is a high-level signal, the first light emission control signal provided by the first light emission control line EM1 is a low-level signal, and the first reset control signal provided by the first reset control line Reset_H is a low-level signal.

[0232] Under the influence of the high-level signal provided by the first scan line GL1, the data writing transistor T1 is turned on, and the data signal provided by the data line DL is written to the fourth node N4 through the turned-on data writing transistor T1, and the voltage of the fourth node N4 becomes Vdata. Under the influence of the low-level signal provided by the first reset control line Reset_H, the first reset transistor T6 is turned on, and the first initial voltage signal provided by the first initial voltage line INIT1 is written to the third node N3 through the turned-on first reset transistor T6, and the voltage of the third node N3 is reset to the first initial voltage Vinit1. Since the third node N3 is electrically connected to the anode of the light-emitting element EL, the light-emitting element EL is also reset. Under the influence of the high-level signal provided by the second scan line GL2, the first reset control transistor T3 and the second reset control transistor T4 are turned on. The first reference voltage signal provided by the first reference voltage line REF1 is provided to the first node N1 through the turned-on first reset control transistor T3, so that the potential of the first node N1 is reset to the first reference voltage Vref1. At the same time, the potential of the first node N1 is provided to the fifth node N5 through the turned-on second reset control transistor T4, so that the potential of the fifth node N5 is also reset to the first reference voltage Vref1. Since the first node N1 is electrically connected to the control electrode of the driving transistor T5, the control electrode of the driving transistor T5 is reset to the first reference voltage Vref1. Under the influence of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on. The first power supply voltage signal provided by the first power supply line VDD is provided to the second node N2 through the turned-on power control transistor T7, that is, the potential of the second electrode of the driving transistor T5 becomes the first power supply voltage Vdd. Since the voltages at both the control and second terminals of the driving transistor T5 are in a fixed bias state, the driving transistor T5 is turned on, preparing for the threshold compensation in the second stage t32. It should be noted that in the first stage t31, in order for the driving transistor T5 to turn on, the turn-on condition of the driving transistor T5 should be met, that is, Vref1-Vdd should be less than the threshold voltage Vth of the driving transistor T5.

[0233] The second stage t32 can also be called the threshold compensation stage. In the second stage t32 of the current frame, the first scan signal provided by the first scan line GL1 jumps to a low level signal, the second scan signal provided by the second scan line GL2 remains at a high level signal, the first light emission control signal provided by the first light emission control line EM1 jumps to a high level signal, and the first reset control signal provided by the first reset control line Reset_H remains at a low level signal.

[0234] Since the second scan signal provided by the second scan line GL2 remains high, the first reset control transistor T3 and the second reset control transistor T4 remain on. The first reference voltage signal provided by the first reference voltage line REF1 is still transmitted to the first node N1 and the fifth node N5, and the voltages of the first node N1 and the fifth node N5 remain at the first reference voltage Vref1. Since the first reset control signal provided by the first reset control line Reset_H remains low, the first reset transistor T6 remains on, and the first initial voltage signal provided by the first initial voltage line INIT1 is still written to the third node N3, and the voltage of the third node N3 remains at the first initial voltage Vinit1.

[0235] Because the first light-emitting control line EM1 outputs a high-level signal, the power control transistor T7 is turned off. In this situation, the second node N2 is disconnected from the first power line VDD, and the second terminal of the driving transistor T5 is in a floating state. The driving transistor T5 undergoes a discharge process, changing from being on to being off, thus causing the potential of the second terminal of the driving transistor T5 to change from Vdd to Vref1-Vth, where Vth is the threshold voltage of the driving transistor T5. It should be noted that during this second stage t32, when the driving transistor T5 undergoes the discharge process, the potential of the second terminal of the driving transistor T5 starts to decrease from Vdd until it decreases to Vref1-Vth, at which point the conduction condition of the driving transistor T5 is not met, causing the driving transistor T5 to turn off.

[0236] In this embodiment of the disclosure, the range of threshold voltage compensation performed by the driving transistor T5 can be adjusted by adjusting the magnitudes of the first power supply voltage Vdd and the first initial voltage Vinit1.

[0237] The third stage t33 can also be called the light emission stage. In the third stage t33 of the current frame, the first light emission control signal provided by the first light emission control line EM1 jumps to a low level signal, the first scan signal provided by the first scan line GL1 remains at a low level, the second scan signal provided by the second scan line GL2 jumps to a low level signal, and the first reset control signal provided by the first reset control line Reset_H jumps to a high level signal.

[0238] Under the influence of a low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is supplied to the second node N2 through the turned-on power control transistor T7. Under the influence of a low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on, and the data writing transistor T1, the first reset control transistor T3, the second reset control transistor T4, and the first reset transistor T6 are all turned off.

[0239] Because the potential of the second terminal of the driving transistor T5 changes from Vref1-Vth to Vdd, under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 changes from Vref1 to Vdata+Vdd-Vref1+Vth, causing the driving transistor T5 to conduct and drive the light-emitting element EL to emit light. Specifically, because the coupling control transistor T2 is turned on, the control terminal of the driving transistor T5 is electrically connected to the first plate of the first capacitor C1; because the power control transistor T7 is turned on, the potential of the second terminal of the driving transistor T5 (i.e., the second plate of the second capacitor) changes from Vref1-Vth to Vdd, and the change in potential of the second terminal of the driving transistor T5 is Vdd-Vref1+Vth. According to the law of conservation of charge, the potential of the control terminal of the driving transistor T5 becomes Vdata+Vdd-Vref1+Vth.

[0240] When driving the pixel circuit provided in the above embodiments using the driving method provided in this disclosure, in the first stage t31, the control electrode potential of the driving transistor T5 is changed to the first reference voltage Vref1, and the potential of the second electrode of the driving transistor T5 is changed to Vdd, so that the voltages of the control electrode and the second electrode of the driving transistor T5 are both in a fixed bias state, thereby initializing the driving transistor T5. Therefore, regardless of whether each pixel unit displays a black or white image in the previous frame, the driving transistor T5 starts the display of the next frame from a fixed bias state, thereby effectively improving the problem of short-term image retention caused by hysteresis.

[0241] In the second stage t32, by controlling the second terminal of the driving transistor T5 to be disconnected from the first power line VDD, the driving transistor T5 undergoes a discharge process until the driving transistor T5 is turned off.

[0242] In the third stage t33, the potential of the second terminal of the driving transistor T5 jumps from Vref1-Vth to the power supply voltage Vdd. Under the coupling control of the first capacitor C1 and the second capacitor C2, the potential of the control terminal of the driving transistor T5 jumps to Vdata+Vdd-Vref1+Vth, thereby turning on the driving transistor T5. At this time, the voltage difference between the control terminal and the second terminal of the driving transistor T5 is Vgs=Vdata-Vref1+Vth. The driving current I generated when the driving transistor T5 is turned on and working in saturation state is: I=k×(Vdata-Vref1)2, where k is a constant.

[0243] It should be noted that the operating range of the driving transistor T5 is related to the magnitude of the first reference voltage Vref1. The higher the first reference voltage Vref1, the larger the minimum value of the data signal Vdata_min. In addition, the threshold voltage compensation range of the driving transistor T5 can be adjusted by adjusting the magnitude of the first power supply voltage Vdd provided by the first power supply line VDD and the first initial voltage Vinit1 provided by the first initial signal line. The value of the first power supply voltage Vdd is greater than Vref1-Vth. The second power supply voltage provided by the second power supply line VSS is selected according to the characteristics of the light-emitting element EL to ensure that the driving transistor T5 operates in saturation.

[0244] On the other hand, the holding frame includes a fourth stage t34 and a fifth stage t35. The fourth stage t34 can also be called the holding emission stage, and the fifth stage t35 can also be called the reset stage. The potentials of each node in different stages are shown in Table 10.

[0245] Table 10

[0246] Referring to Figures 18 and 14, during the hold frame phase, the first scan signal provided by the first scan line GL1 remains at a low level, and no new data signal is written. That is, the light-emitting element EL displays the image using the grayscale values ​​written in the refresh frame. The second scan signal provided by the second scan line GL2 remains at a low level. In each fourth phase t34, when the first light-emitting control signal provided by the first light-emitting control line EM1 is low, the drive current generated by the drive transistor T5 is transmitted to the light-emitting element EL to drive it to emit light.

[0247] In the fourth stage t34, the first light-emitting control signal output from the first light-emitting control line EM1 is a low-level signal, and the first reset control signal output from the first reset control line Reset_H is a high-level signal. Under the action of the low-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned on, and the first power supply voltage signal provided by the first power supply line VDD is provided to the second node N2 through the turned-on power control transistor T7. Under the action of the low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on, and the data writing transistor T1, the first reset control transistor T3, the second reset control transistor T4, and the first reset transistor T6 are all turned off.

[0248] In the fourth stage t34, the output of the second scan line GL2 remains low, meaning that the coupling control transistor T2 remains on. Therefore, the voltage change of the second terminal of the driving transistor T5 is coupled to the first node N1 using the first capacitor C1, the second capacitor C2, and the coupling control transistor T2, so that the voltage of the first node N1 is Vdata+Vdd-Vref1+Vth, thereby driving the current.

[0249] In the fifth stage t35, the first light-emitting control signal output from the first light-emitting control line EM1 is a high-level signal, and the first reset control signal output from the first reset control line Reset_H is a low-level signal. Under the action of the high-level signal provided by the first light-emitting control line EM1, the power control transistor T7 is turned off, and the light-emitting element EL does not emit light. Under the action of the low-level signal provided by the second scan line GL2, the coupling control transistor T2 is turned on, and under the action of the low-level signal provided by the first reset control line Reset_H, the first reset transistor T6 is turned on, while the data writing transistor T1, the first reset control transistor T3, and the second reset control transistor T4 are all turned off.

[0250] The first initial voltage signal provided by the first initial voltage line INIT1 is written to the third node N3 through the first reset transistor T6, and the voltage of the third node N3 is reset to the first initial voltage Vinit1. Since the third node N3 is electrically connected to the anode of the light-emitting element EL, the light-emitting element EL is also reset.

[0251] As shown in Figure 15, the frequency of setting the reset phase during the hold frame phase does not correspond one-to-one with the hold light phase. That is, as shown in Figure 14, a reset phase can be set every other hold light phase, or a reset phase can be set every multiple hold light phases. Figure 15 exemplarily shows a reset phase set every two hold light phases, but the number of intervals can be set more as needed, which is not limited in this article.

[0252] The pixel circuit of this embodiment separates the data writing and threshold voltage compensation processes, ensuring the compensation time during high frame rate driving and thus achieving a better compensation effect. At the same time, the circuit can compensate for the IR drop of the first power line VDD, making the circuit a promising candidate for application in large-size display panels.

[0253] Figure 19 is a flowchart of a driving method for a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a power control sub-circuit, a coupling sub-circuit, and a reset control sub-circuit. The driving sub-circuit is connected to a first node, a second node, and a third node. The data writing sub-circuit is connected to a first scan line, a data line, and a fourth node. The power control sub-circuit is connected to a first light emission control line, a second node, and a first power supply line. The coupling sub-circuit is connected to the first node, the second node, and the fourth node. The reset control sub-circuit is connected to a second scan line, the first node, and a first reference voltage line.

[0254] In some examples, as shown in Figure 19, the display cycle of the pixel circuit in this example during driving includes a refresh frame, which at least includes a data writing phase, a threshold compensation phase, and a light emission phase performed sequentially, wherein:

[0255] During the data writing phase, the data writing sub-circuit, under the control of the first scan line, writes the data signal of the data line into the fourth node; the reset control sub-circuit, under the control of the second scan line, writes the first reference voltage signal of the first reference voltage line into the first node; and the power control sub-circuit, under the control of the first light emission control line, connects the first power line to the second node.

[0256] During the threshold compensation stage, the power control sub-circuit, under the control of the first light-emitting control line, disconnects the connection between the first power line and the second node, so that the driving sub-circuit can compensate for the threshold voltage.

[0257] During the light-emitting stage, the power control sub-circuit, under the control of the first light-emitting control line, connects the first power line to the second node. The coupling sub-circuit couples and boosts the voltage of the first node according to the voltage change of the second node and the voltage of the fourth node, so that the driving sub-circuit provides driving current according to the voltage difference between the first node and the second node.

[0258] In some examples, the coupling sub-circuit includes a coupling control sub-circuit, a first coupling sub-circuit, and a second coupling sub-circuit;

[0259] The coupling sub-circuit couples and boosts the voltage of the first node based on the voltage change of the second node and the voltage of the fourth node, including:

[0260] The coupling control sub-circuit, under the control of the coupling control line, connects the first node and the fourth node;

[0261] The first coupling sub-circuit and the second coupling sub-circuit couple and boost the voltage of the fourth node according to the voltage change of the second node.

[0262] In some examples, the reset control subcircuit includes a first reset control subcircuit and a second reset control subcircuit; the reset control subcircuit, under the control of the second scan line, writes the first reference voltage signal of the first reference voltage line into the first node, including:

[0263] Under the control of the second scan line, the first reset control sub-circuit writes the first reference voltage signal of the first reference voltage line into the fifth node; the second reset control sub-circuit, under the control of the second scan line, turns on the fifth node and the first node; or...

[0264] Under the control of the second scan line, the first reset control sub-circuit writes the first reference voltage signal of the first reference voltage line into the first node, and under the control of the second scan line, the second reset control sub-circuit turns on the first node and the fifth node.

[0265] In some examples, the pixel circuit further includes a first reset sub-circuit, and the driving method further includes:

[0266] During the data writing phase and / or the threshold compensation phase, the first reset sub-circuit resets the third node under the control of the first reset control line or the second scan line.

[0267] In some examples, the display cycle of the pixel circuitry further includes a holding frame, which comprises a holding phase and a reset phase, and the driving method further includes:

[0268] During the light-holding phase, the power control sub-circuit, under the control of the first light-holding control line, connects the first power line to the second node. The coupling sub-circuit couples and boosts the voltage of the first node according to the voltage change of the second node and the voltage of the fourth node, so that the driving sub-circuit provides driving current according to the voltage difference between the first node and the second node.

[0269] During the reset phase, the first reset sub-circuit, under the control of the first reset control line, resets the third node using the first initial voltage of the first initial voltage line.

[0270] The method further includes: adjusting the range of threshold voltage compensation by the driving sub-circuit by adjusting the first power supply voltage provided by the first power supply line and / or the first initial voltage of the first initial voltage line.

[0271] In some examples, the pixel circuit further includes a first reset sub-circuit, a second reset sub-circuit, and a light emission control sub-circuit, and the driving method further includes:

[0272] During the data writing phase and / or the threshold compensation phase, the first reset sub-circuit resets the third node under the control of the first reset control line; the second reset sub-circuit resets the sixth node under the control of the first reset control line.

[0273] During the light-emitting stage, the light-emitting control sub-circuit is turned on under the control of the second light-emitting control line to transmit the driving current generated by the driving sub-circuit to the light-emitting element.

[0274] In some examples, the driving cycle of the pixel circuit further includes a holding frame, which includes a holding emission phase and a reset phase, and the driving method further includes:

[0275] During the light-holding phase, the power control sub-circuit, under the control of the first light-holding control line, connects the first power line to the second node. The coupling sub-circuit couples and boosts the voltage of the first node according to the voltage change of the second node and the voltage of the fourth node, so that the driving sub-circuit provides driving current according to the voltage difference between the first node and the second node.

[0276] During the reset phase, the first reset sub-circuit resets the third node under the control of the first reset control line; the second reset sub-circuit resets the sixth node under the control of the first reset control line.

[0277] In some examples, the first power supply voltage provided by the first power line is greater than the difference between the first reference voltage of the first reference voltage line and the threshold voltage of the driving sub-circuit.

[0278] In some examples, the method further includes adjusting the voltage range of the data signal of the data line by adjusting the magnitude of the first reference voltage provided by the first reference voltage line.

[0279] The driving method for the pixel circuit in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0280] This embodiment also provides a display substrate, including: a plurality of sub-pixels, at least one of the plurality of sub-pixels including a light-emitting element and a pixel circuit for driving the light-emitting element to emit light; the pixel circuit is the pixel circuit as described in the foregoing embodiments.

[0281] In some examples, the display substrate may include an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device including this display substrate can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0282] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0283] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A pixel circuit, the pixel circuit comprising a driving sub-circuit, a data writing sub-circuit, a power control sub-circuit, a coupling sub-circuit, and a reset control sub-circuit, wherein the driving sub-circuit is connected to a first node, a second node, and a third node; the data writing sub-circuit is connected to a first scan line, a data line, and a fourth node; the power control sub-circuit is connected to a first light emission control line, a second node, and a first power supply line; the coupling sub-circuit is connected to the first node, the second node, and the fourth node; and the reset control sub-circuit is connected to a second scan line, the first node, and a first reference voltage line. The pixel circuit, during driving, includes a data writing stage, a threshold compensation stage, and a light emission stage performed sequentially. During the data writing phase, the data writing sub-circuit, under the control of the first scan line, writes the data signal of the data line into the fourth node; the reset control sub-circuit, under the control of the second scan line, writes the first reference voltage signal of the first reference voltage line into the first node; and the power control sub-circuit, under the control of the first light emission control line, connects the first power line to the second node. During the threshold compensation phase, the power control subcircuit, under the control of the first light-emitting control line, disconnects the connection between the first power line and the second node, so that the driving subcircuit compensates for the threshold voltage. During the light-emitting phase, the power control subcircuit, under the control of the first light-emitting control line, connects the connection between the first power line and the second node. The coupling subcircuit couples and boosts the voltage of the first node according to the voltage change of the second node and the voltage of the fourth node, so that the driving subcircuit provides driving current according to the voltage difference between the first node and the second node.

2. The pixel circuit of claim 1, wherein, The coupling sub-circuit includes a coupling control sub-circuit, a first coupling sub-circuit, and a second coupling sub-circuit. The coupling control sub-circuit is connected to the coupling control line, the fourth node, and the first node. The first coupling sub-circuit is connected to the fourth node and the fifth node. The second coupling sub-circuit is connected to the second node and the fifth node. The coupling sub-circuit couples and raises the voltage of the first node according to the voltage change of the second node and the voltage of the fourth node, including: the coupling control sub-circuit, under the control of the coupling control line, turns on the first node and the fourth node; The first coupling sub-circuit and the second coupling sub-circuit couple and boost the voltage of the fourth node according to the voltage change of the second node.

3. The pixel circuit of claim 2, wherein, The coupling control line is either a second light emission control line or a second scan line.

4. The pixel circuit of claim 2, wherein, The reset control subcircuit includes a first reset control subcircuit and a second reset control subcircuit. The first reset control subcircuit is connected to the second scan line, the first reference voltage line and the fifth node, and the second reset control subcircuit is connected to the second scan line, the fifth node and the first node. Under the control of the second scan line, the reset control sub-circuit writes the first reference voltage signal of the first reference voltage line into the first node, including: the first reset control sub-circuit, under the control of the second scan line, writes the first reference voltage signal of the first reference voltage line into the fifth node; and the second reset control sub-circuit, under the control of the second scan line, turns on the fifth node and the first node.

5. The pixel circuit of claim 4, wherein, The coupling control sub-circuit includes a coupling control transistor, the first reset control sub-circuit includes a first reset control transistor, and the second reset control sub-circuit includes a second reset control transistor. The control electrode of the coupling control transistor is connected to the second light-emitting control line, the first electrode of the coupling control transistor is connected to the fourth node, and the second electrode of the coupling control transistor is connected to the first node. The control electrode of the first reset control transistor is connected to the second scan line, the first electrode of the first reset control transistor is connected to the first reference voltage line, and the second electrode of the first reset control transistor is connected to the fifth node. The control electrode of the second reset control transistor is connected to the second scan line, the first electrode of the second reset control transistor is connected to the fifth node, and the second electrode of the second reset control transistor is connected to the first node; The coupling control transistor, the first reset control transistor, and the second reset control transistor are all P-type transistors.

6. The pixel circuit of claim 4, wherein, The coupling control sub-circuit includes a coupling control transistor, the first reset control sub-circuit includes a first reset control transistor, and the second reset control sub-circuit includes a second reset control transistor. The control electrode of the coupling control transistor is connected to the second scan line, the first electrode of the coupling control transistor is connected to the fourth node, and the second electrode of the coupling control transistor is connected to the first node; The control electrode of the first reset control transistor is connected to the second scan line, the first electrode of the first reset control transistor is connected to the first reference voltage line, and the second electrode of the first reset control transistor is connected to the fifth node. The control electrode of the second reset control transistor is connected to the second scan line, the first electrode of the second reset control transistor is connected to the fifth node, and the second electrode of the second reset control transistor is connected to the first node; The coupling control transistor is a P-type transistor, and both the first reset control transistor and the second reset control transistor are N-type transistors.

7. The pixel circuit of claim 2, wherein, The reset control subcircuit includes a first reset control subcircuit and a second reset control subcircuit. The first reset control subcircuit is connected to the second scan line, the first reference voltage line and the first node. The second reset control subcircuit is connected to the second scan line, the fifth node and the first node. Under the control of the second scan line, the reset control sub-circuit writes the first reference voltage signal of the first reference voltage line into the first node, including: the first reset control sub-circuit, under the control of the second scan line, writes the first reference voltage signal of the first reference voltage line into the first node; and the second reset control sub-circuit, under the control of the second scan line, turns on the first node and the fifth node.

8. The pixel circuit of claim 7, wherein, The coupling control sub-circuit includes a coupling control transistor, the first reset control sub-circuit includes a first reset control transistor, and the second reset control sub-circuit includes a second reset control transistor. The control electrode of the coupling control transistor is connected to the second scan line, the first electrode of the coupling control transistor is connected to the fourth node, and the second electrode of the coupling control transistor is connected to the first node; The control electrode of the first reset control transistor is connected to the second scan line, the first electrode of the first reset control transistor is connected to the first reference voltage line, and the second electrode of the first reset control transistor is connected to the first node. The control electrode of the second reset control transistor is connected to the second scan line, the first electrode of the second reset control transistor is connected to the first node, and the second electrode of the second reset control transistor is connected to the fifth node; The coupling control transistor is a P-type transistor, and both the first reset control transistor and the second reset control transistor are N-type transistors.

9. The pixel circuit of claim 1, wherein, The pixel circuit further includes a first reset sub-circuit, which is connected to the second scan line or the first reset control line, the first initial voltage line, and the third node. During the data writing phase and / or the threshold compensation phase, the first reset sub-circuit resets the third node under the control of the second scan line or the first reset control line.

10. The pixel circuit of claim 1, wherein, The pixel circuit further includes a light emission control sub-circuit, which is connected to the second light emission control line, the third node, and the sixth node. The sixth node is connected to the first electrode of the light emission element. During the light-emitting stage, the light-emitting control sub-circuit is turned on under the control of the second light-emitting control line to transmit the driving current generated by the driving sub-circuit to the light-emitting element.

11. The pixel circuit of claim 10, wherein, The pixel circuit further includes a second reset sub-circuit, which is connected to the reset control line, the second initial voltage line, and the sixth node. During the data writing phase and / or the threshold compensation phase, the second reset sub-circuit resets the sixth node under the control of the reset control line, wherein the reset control line is any one of the following: the first reset control line, the first scan line, and the second scan line.

12. A display substrate comprising the pixel circuitry as described in any one of claims 1 to 11.

13. A driving method for a pixel circuit, the pixel circuit comprising a driving sub-circuit, a data writing sub-circuit, a power control sub-circuit, a coupling sub-circuit, and a reset control sub-circuit, wherein the driving cycle of the pixel circuit includes a refresh frame, the refresh frame comprising a data writing stage, a threshold compensation stage, and a light emission stage performed sequentially, wherein: During the data writing phase, the data writing sub-circuit, under the control of the first scan line, writes the data signal of the data line into the fourth node; the reset control sub-circuit, under the control of the second scan line, writes the first reference voltage signal of the first reference voltage line into the first node; and the power control sub-circuit, under the control of the first light emission control line, connects the first power line and the second node. During the threshold compensation stage, the power control sub-circuit, under the control of the first light emission control line, disconnects the connection between the first power line and the second node, so that the driving sub-circuit can compensate for the threshold voltage. During the light-emitting stage, the power control sub-circuit, under the control of the first light-emitting control line, connects the first power line to the second node. The coupling sub-circuit couples and boosts the voltage of the first node according to the voltage change of the second node and the voltage of the fourth node, so that the driving sub-circuit provides driving current according to the voltage difference between the first node and the second node.

14. The driving method according to claim 13, wherein The coupling sub-circuit includes a coupling control sub-circuit, a first coupling sub-circuit, and a second coupling sub-circuit; The coupling sub-circuit couples and boosts the voltage of the first node based on the voltage change of the second node and the voltage of the fourth node, including: The coupling control sub-circuit, under the control of the coupling control line, connects the first node and the fourth node; The first coupling sub-circuit and the second coupling sub-circuit couple and boost the voltage of the fourth node according to the voltage change of the second node.

15. The driving method according to claim 14, wherein The reset control sub-circuit includes a first reset control sub-circuit and a second reset control sub-circuit; The reset control subcircuit, under the control of the second scan line, writes the first reference voltage signal of the first reference voltage line into the first node, including: Under the control of the second scan line, the first reset control sub-circuit writes the first reference voltage signal of the first reference voltage line into the fifth node; the second reset control sub-circuit, under the control of the second scan line, turns on the fifth node and the first node; or... Under the control of the second scan line, the first reset control sub-circuit writes the first reference voltage signal of the first reference voltage line into the first node, and under the control of the second scan line, the second reset control sub-circuit turns on the first node and the fifth node.

16. The driving method according to claim 13, wherein The pixel circuit further includes a first reset sub-circuit, and the driving method further includes: During the data writing phase and / or the threshold compensation phase, the first reset sub-circuit, under the control of the first reset control line or the second scan line, resets the third node using the first initial voltage of the first initial voltage line.

17. The driving method according to claim 16, the method further comprising: The range of threshold voltage compensation by the driving sub-circuit is adjusted by adjusting the first power supply voltage provided by the first power supply line and / or the first initial voltage of the first initial voltage line.

18. The driving method according to claim 16, wherein The driving cycle of the pixel circuit further includes a holding frame, which includes a holding emission phase and a reset phase. The driving method further includes: During the light-holding phase, the power control sub-circuit, under the control of the first light-holding control line, connects the first power line to the second node. The coupling sub-circuit couples and boosts the voltage of the first node according to the voltage change of the second node and the voltage of the fourth node, so that the driving sub-circuit provides driving current according to the voltage difference between the first node and the second node. During the reset phase, the first reset sub-circuit resets the third node under the control of the first reset control line.

19. The driving method according to claim 13, wherein The pixel circuit further includes a first reset sub-circuit, a second reset sub-circuit, and a light emission control sub-circuit; the driving method further includes: During the data writing phase and / or the threshold compensation phase, the first reset sub-circuit resets the third node under the control of the first reset control line; the second reset sub-circuit resets the sixth node under the control of the first reset control line. During the light-emitting stage, the light-emitting control sub-circuit is turned on under the control of the second light-emitting control line to transmit the driving current generated by the driving sub-circuit to the light-emitting element.

20. The driving method according to claim 19, wherein The driving cycle of the pixel circuit further includes a holding frame, which includes a holding emission phase and a reset phase. The driving method further includes: During the light-holding phase, the power control sub-circuit, under the control of the first light-emitting control line, connects the first power line to the second node. The coupling sub-circuit couples and boosts the voltage of the first node according to the voltage change of the second node and the voltage of the fourth node, so that the driving sub-circuit provides driving current according to the voltage difference between the first node and the second node. The light-emitting control sub-circuit is turned on under the control of the second light-emitting control line to transmit the driving current generated by the driving sub-circuit to the light-emitting element. During the reset phase, the first reset sub-circuit resets the third node under the control of the first reset control line; the second reset sub-circuit resets the sixth node under the control of the first reset control line.

21. The driving method according to claim 13, wherein The first power supply voltage provided by the first power supply line is greater than the difference between the first reference voltage of the first reference voltage line and the threshold voltage of the driving sub-circuit.

22. The driving method according to claim 13, further comprising: The voltage range of the data signal on the data line is adjusted by adjusting the magnitude of the first reference voltage provided by the first reference voltage line.

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