Array substrate, display panel, and display device

Abstract

An array substrate (10), a display panel (100), and a display device (1000). The array substrate (10) comprises a plurality of sub-pixels (1), the plurality of sub-pixels (1) constitute a plurality of pixel groups (11), and each pixel group (11) comprises two adjacent sub-pixels (1) in a row direction (X). The array substrate further comprises a source / drain metal layer (102) and a common electrode layer (103). The source / drain metal layer (102) comprises a plurality of first longitudinal lines (121) and a plurality of second longitudinal lines (122), the first longitudinal lines (121) are touch signal lines (TX), and the second longitudinal lines (122) comprise touch signal lines (TX) and common signal lines (COM) arranged at an interval in a column direction (Y). The common electrode layer (103) comprises a plurality of common electrodes (1031), the plurality of common electrodes (1031) constitute a plurality of touch units (20), and each touch unit (20) is connected to one touch signal line (TX). In each touch unit (20), a connecting portion (1032) is provided between two adjacent common electrodes (1031) in the row direction (X), the connecting portion (1032) between two common electrodes (1031) located on two sides of each touch signal line (TX) is provided with a hollow opening (K), the hollow opening (K) exposes the touch signal line (TX), and two portions of the connecting portion (1032) respectively located on the two sides of the hollow opening (K) in the row direction (X) overlap the touch signal line (TX).

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] In the field of display technology, display panels and display devices typically use thin-film transistors (TFTs) for driving. With the development of display technology, to reduce costs, dual-gate driving is commonly used to drive pixel arrays. Dual-gate driving halves the number of data lines compared to traditional driving methods, thereby reducing the number of source driver circuits, and consequently reducing the number of driver chips and lowering costs.

[0003] With the rapid development of the display industry, the demand for display products is increasing, among which low cost and high transmittance are new requirements. In smart display devices, effectively controlling low cost and high transmittance is also a major competitive advantage. Summary of the Invention

[0004] On one hand, an array substrate is provided. The array substrate includes a plurality of sub-pixels arranged in an array, the plurality of sub-pixels forming a plurality of pixel groups, each pixel group including two adjacent sub-pixels along a row direction. The array substrate includes: a substrate, a source / drain metal layer, and a common electrode layer. The source / drain metal layer is disposed on one side of the substrate, and includes a plurality of vertical lines extending along a column direction. Each of the vertical lines is located between two adjacent column pixel groups. The plurality of vertical lines includes a plurality of first vertical lines and a plurality of second vertical lines. The first vertical lines are touch signal lines, and the second vertical lines include touch signal lines and common signal lines spaced apart in the column direction. The common electrode layer is disposed on the side of the source / drain metal layer away from the substrate, and includes a plurality of common electrodes arranged in an array. Each sub-pixel includes one common electrode, the plurality of common electrodes forming a plurality of touch units. Each touch unit includes at least two connected common electrodes, and each touch unit is connected to one touch signal line. In the touch unit, a connecting portion is provided between two adjacent common electrodes along the row direction. The connecting portion is connected to the two common electrodes. The connecting portion between the two common electrodes located on both sides of the touch signal line has a hollow opening. The hollow opening exposes the touch signal line, and two parts of the connecting portion located on both sides of the hollow opening along the row direction overlap with the touch signal line.

[0005] In some embodiments, the connecting portion includes two first sub-parts located on both sides of the cutout opening along the row direction, and the portions of the two first sub-parts that overlap with the touch line are equal in size in the row direction.

[0006] In some embodiments, the vertical line includes a plurality of sub-vertical lines, each of the sub-vertical lines corresponding to a row of sub-pixels, and the sub-vertical line includes a first end and a second end; the connecting portion includes two second sub-parts located on both sides of the cutout opening along the column direction, the first end overlapping and connecting with one of the second sub-parts, and the second end overlapping with the other second sub-part; the two second sub-parts have the same size in the column direction.

[0007] In some embodiments, the array substrate further includes a gate layer disposed between the substrate and the source / drain metal layer. The gate layer includes a plurality of gate lines extending along a row direction. The plurality of gate lines form a plurality of gate line groups. Each of the plurality of gate line groups includes two gate lines located between two adjacent rows of common electrodes. The common electrode layer further includes a plurality of extensions located between two adjacent rows of common electrodes. Each of the plurality of extensions is connected to two common electrodes located on both sides of it in a column direction. The extensions overlap with one of the longitudinal lines. Between two adjacent rows of common electrodes, the extensions overlap with both of the gate lines.

[0008] In some embodiments, the plurality of extensions includes a first extension and a second extension, the first extension being located between two adjacent touch units along the column direction, and the second extension being located within the touch unit; the first extension includes a first break, the first extension being divided into two sub-extensions by the first break, the two sub-extensions being respectively connected to two common electrodes; the two sub-extensions overlap with the corresponding two gate lines respectively; the second extension overlaps with both corresponding two gate lines; wherein the overlap area of ​​the first extension with the corresponding two gate lines is equal to the overlap area of ​​the second extension with the corresponding two gate lines.

[0009] In some embodiments, the orthographic projection of the first break on the substrate is located between the orthographic projections of the corresponding two gate lines on the substrate.

[0010] In some embodiments, the ends of the two sub-extensions that are close to each other are closer to the common electrode connected to the sub-extensions than the sides of the two gate lines that are close to each other; the dimension of the portion of the sub-extension that overlaps with the corresponding gate line in the first direction is greater than the dimension of the portion of the second extension that overlaps with the corresponding gate line in the first direction; the first direction intersects the column direction.

[0011] In some embodiments, the longitudinal line that overlaps with the first extension is a first longitudinal line, and the first break exposes at least a portion of the first longitudinal line.

[0012] In some embodiments, the longitudinal line that overlaps with the first extension is a second longitudinal line, and the first break is located at the interval between the touch signal line and the common signal line of the second longitudinal line.

[0013] In some embodiments, the dimension of the first break in the column direction is smaller than the spacing between the touch signal line and the common signal line of the second longitudinal line in the column direction.

[0014] In some embodiments, the array substrate further includes: a pixel electrode layer disposed between the substrate and the source / drain metal layer, a gate dielectric layer disposed between the pixel electrode layer and the source / drain metal layer, and a passivation layer disposed between the source / drain metal layer and the common electrode layer; the array substrate includes a plurality of vias, each of the plurality of vias penetrating the passivation layer and the gate dielectric layer; the vias include a first portion and a second portion that are connected, the first portion penetrating the passivation layer, and the second portion penetrating the passivation layer and the gate dielectric layer.

[0015] In some embodiments, the pixel electrode layer includes a plurality of pixel electrodes, each pixel electrode overlapping a common electrode; each of the plurality of sub-pixels includes a first transistor, a pixel electrode, and a common electrode; the common electrode layer includes a transition electrode, the source-drain metal layer includes the drain pattern of the first transistor, and the plurality of vias includes a first via; the transition electrode is connected to the drain pattern of the first transistor through a first portion of the first via, and the transition electrode is connected to the pixel electrode through a second portion of the first via.

[0016] In some embodiments, the ratio of the area of ​​the orthographic projection of the portion of the adapter electrode located within the first portion of the first via on the substrate to the area of ​​the orthographic projection of the portion of the adapter electrode located within the first via on the substrate ranges from 0.4 to 0.6.

[0017] In some embodiments, the plurality of vias includes a second via; the longitudinal line and a corresponding common electrode are connected through the second via; the common electrode connected to the longitudinal line includes a first connecting block, the first connecting block being connected to the longitudinal line through a first portion of the second via, and the first connecting block being in contact with the substrate through a second portion of the second via.

[0018] In some embodiments, the ratio of the area of ​​the portion of the first connecting block located within the first portion of the second via, projected onto the substrate, to the area of ​​the portion of the first connecting block located within the second via, projected onto the substrate, ranges from 0.2 to 0.3.

[0019] In some embodiments, the longitudinal line includes a second connecting block corresponding to the first connecting block, the first connecting block including a portion overlapping the second connecting block and a portion not overlapping the second connecting block, and at least a portion of the boundary of the first connecting block matching the shape of at least a portion of the boundary of the second connecting block.

[0020] In some embodiments, the common electrode, which is not connected to the longitudinal line, includes a third connecting block located near the interval between two adjacent touch units, and the third connecting block has the same shape as the first connecting block.

[0021] On the other hand, a display panel is provided, including an array substrate as described in any of the above embodiments, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.

[0022] In another aspect, a display device is provided. The display device includes a display panel as described in the above embodiments. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1A is a planar structural diagram of an array substrate according to some embodiments of the present disclosure;

[0025] Figure 1B is an enlarged planar view of the array substrate shown in Figure 1A according to some embodiments of the present disclosure;

[0026] Figure 1C is a cross-sectional view of the array substrate shown in Figure 1B according to some embodiments of the present disclosure, obtained by making cross-sections at cross-section lines DD' and EE';

[0027] Figure 2 is a plan view of a display device according to some embodiments of the present disclosure;

[0028] Figure 3A is a structural diagram showing the arrangement of longitudinal lines according to some embodiments of the present disclosure;

[0029] Figure 3B is a structural diagram of the longitudinal line arrangement in some embodiments of related technologies;

[0030] Figure 4A is a structural diagram showing the positional relationship between the connection portion and the cutout opening of an array substrate according to some embodiments of the present disclosure;

[0031] Figure 4B is a partially enlarged structural view of the positional relationship between the connection portion and the cutout opening of the array substrate according to some embodiments of the present disclosure;

[0032] Figure 4C is a cross-sectional structure diagram obtained by taking a section along the section line CC' in Figure 4B according to some embodiments of the present disclosure;

[0033] Figure 5A is a structural diagram showing the positional relationship between the second sub-part in the connection portion of the array substrate and the touch signal line according to some embodiments of the present disclosure;

[0034] Figure 5B is another structural diagram showing the positional relationship between the second sub-part in the connection portion of the array substrate and the touch signal line according to some embodiments of the present disclosure;

[0035] Figure 6 is a structural diagram of a partial sub-pixel arrangement of an array substrate according to some embodiments of the present disclosure;

[0036] Figure 7A is a structural diagram showing the positional relationship between the first extension of the array substrate and the longitudinal line and the gate line according to some embodiments of the present disclosure.

[0037] Figure 7B is another structural diagram showing the positional relationship between the first extension of the array substrate and the longitudinal line and the gate line according to some embodiments of the present disclosure;

[0038] Figure 7C is a structural diagram showing the positional relationship between the second extension of the array substrate and the longitudinal line and the gate line according to some embodiments of the present disclosure;

[0039] Figure 7D is an enlarged structural view of the first extension of the array substrate of a board according to some embodiments of the present disclosure, along with longitudinal lines and gate lines;

[0040] Figure 7E is another enlarged structural view of the second extension of the array substrate of the board according to some embodiments of the present disclosure, along with the longitudinal lines and gate lines;

[0041] Figure 7F is another structural diagram of the second extension of the array substrate of the board according to some embodiments of the present disclosure, along with the longitudinal lines and gate lines.

[0042] Figure 8A is a diagram of a film stacking structure of an array substrate according to some embodiments of the present disclosure;

[0043] Figure 8B is a diagram of another film stacking structure of an array substrate according to some embodiments of the present disclosure;

[0044] Figure 8C is a diagram of another film layer stacking structure of an array substrate according to some embodiments of the present disclosure;

[0045] Figure 8D is a diagram of another film stacking structure of an array substrate according to some embodiments of the present disclosure;

[0046] Figure 8E is a diagram of another film stacking structure of an array substrate according to some embodiments of the present disclosure;

[0047] Figure 9A is a cross-sectional view of an array substrate according to some embodiments of the present disclosure, obtained by taking a section along section line AA' in Figure 7A;

[0048] Figure 9B is a cross-sectional view of the array substrate according to some embodiments of the present disclosure, obtained by taking a section along the section line BB' in Figure 7A;

[0049] Figure 10 is a process diagram of array substrate fabrication according to some embodiments of the present disclosure;

[0050] Figure 11 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0051] Figure 12 is a structural diagram of a display device according to some embodiments of the present disclosure. Detailed Implementation

[0052] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0053] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0054] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0055] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0056] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", and includes the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0057] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0058] As used herein, depending on the context, the term "if" may optionally be interpreted as meaning "when," "at," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrases "if it is determined..." or "if [the stated condition or event] is optionally interpreted as meaning "in response to determination..." or "in response to detection of [the stated condition or event]."

[0059] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0060] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0061] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0062] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0063] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0064] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] The transistors used in the circuits provided in the embodiments of this application can be thin-film transistors, field-effect transistors (e.g., oxide thin-film transistors), or other switching devices with the same characteristics. The embodiments of this application all use thin-film transistors as examples for illustration. Preferably, the thin-film transistors used in the embodiments of this disclosure can be oxide semiconductor transistors or low-temperature polycrystalline silicon (LTPS) thin-film transistors.

[0066] With the continuous advancement of display technology, liquid crystal display devices are being used more and more widely, such as in laptops, monitors, and televisions. Full-in-cell (FIC) touch display devices can combine touch with liquid crystal, featuring integration, low cost, low power consumption, and high image quality, and can achieve the advantage of multi-touch. However, for gaming monitors (Monitor, MNT), the requirements for low cost and high transmittance are also becoming increasingly stringent.

[0067] Based on this, some embodiments of the present disclosure provide an array substrate, a display panel, and a display device, which can reduce costs and increase transmittance, while improving the touch performance of the display device, thereby improving the yield and quality of the display device.

[0068] For ease of description below, an XYZ coordinate system is established. The third direction Z is perpendicular to the substrate, i.e., the thickness direction in this application. The XY plane is perpendicular to the Z direction, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0069] It should be noted that, for example, 121 / 12 in the accompanying drawings of this disclosure indicates that component 121 belongs to component 12, and 1031 (103) indicates that component 1031 is disposed within the film layer 103. Other similar reference numerals in the drawings also follow the above description.

[0070] The array substrate, display panel and display device provided in this disclosure are described below.

[0071] In this disclosure, FIG1A is a planar structural diagram of an array substrate according to some embodiments of the present disclosure, FIG1B is an enlarged planar structural diagram of the array substrate shown in FIG1A according to some embodiments of the present disclosure, and FIG1C is a cross-sectional structural diagram obtained by taking cross-sections at cross-section lines DD' and EE' of the array substrate shown in FIG1B according to some embodiments of the present disclosure, wherein the portion on the left side of the cross-sectional diagram shown in FIG1C is the cross-sectional structural diagram obtained by taking cross-sections at cross-section line DD', and the portion on the right side is the cross-sectional structural diagram obtained by taking cross-sections at cross-section line EE'. To facilitate a clear description of the structural changes of the array substrate, Figures 1A, 1B, and 1C all show partial structural diagrams of the array substrate. Figure 2 is a planar structural diagram of a display device according to some embodiments of the present disclosure. Figure 3A is a structural diagram of a vertical line arrangement according to some embodiments. Figure 3B is a structural diagram of a vertical line arrangement according to some embodiments in the related art. To facilitate a clear description of the structural change trend of the vertical line arrangement, Figures 3A and 3B show partial structural diagrams of the vertical line arrangement. Figures 4A-5B and 7A-7F are partially enlarged structural diagrams of the array substrate according to some embodiments of the present disclosure. Figure 6 is a structural diagram of a partial sub-pixel arrangement of the array substrate according to some embodiments of the present disclosure. Figures 8A-8E are film layer stacking structural diagrams of the array substrate according to some embodiments of the present disclosure. Figures 9A and 9B are cross-sectional structural diagrams of the array substrate according to some embodiments of the present disclosure. Figure 10 is a process diagram of the array substrate fabrication according to some embodiments of the present disclosure. Figure 11 is a structural diagram of a display panel according to some embodiments of the present disclosure. Figure 12 is a structural diagram of a display device according to some embodiments of the present disclosure.

[0072] Some embodiments of the present invention provide an array substrate 10, as shown in FIG1A. The array substrate 10 includes a plurality of sub-pixels 1 arranged in an array, the plurality of sub-pixels 1 forming a plurality of pixel groups 11, and each pixel group 11 including two adjacent sub-pixels 1 along the row direction X.

[0073] Referring to Figures 1A and 1B, and in conjunction with Figure 1C, the array substrate 10 includes a substrate 101, a source / drain metal layer 102 disposed on one side of the substrate 101, and a common electrode layer 103 disposed on the side of the source / drain metal layer 102 away from the substrate 101. The source / drain metal layer 102 includes a plurality of vertical lines 12 extending along the column direction Y, each of the plurality of vertical lines 12 being located between two adjacent columns of pixel groups 11. The plurality of vertical lines 12 includes a plurality of first vertical lines 121 and a plurality of second vertical lines 122. The first vertical lines 121 are touch signal lines TX, and the second vertical lines 122 include touch signal lines TX and common signal lines COM spaced apart in the column direction Y. The common electrode layer 103 includes a plurality of common electrodes 1031 arranged in an array. Each sub-pixel 1 includes one common electrode 1031. The plurality of common electrodes 1031 form a plurality of touch units 20. Each of the plurality of touch units 20 includes at least two common electrodes 1031 connected together. Referring to FIG. 2, each touch unit 20 is connected to a touch signal line TX. In the touch unit 20, a connecting portion 1032 is provided between two adjacent common electrodes 1031 along the row direction X (as shown in FIG. 4A). The connecting portion 1032 is connected to the two common electrodes 1031. The connecting portion 1032 between the two common electrodes 1031 located on both sides of the touch signal line TX has a cutout opening K. The cutout opening K exposes the touch signal line TX, and the two portions of the connecting portion 1032 located on both sides of the cutout opening K along the row direction X overlap with the touch signal line TX.

[0074] Referring to Figure 1A, multiple sub-pixels 1 are divided into multiple pixel groups 11. Each pixel group 11 includes two adjacent sub-pixels 1 arranged along the row direction X. Each sub-pixel 1 includes a transistor and an electrode group, wherein the electrode group consists of overlapping pixel electrodes and a common electrode. Exemplarily, each pixel group 11 includes a first sub-pixel 110 and a second sub-pixel 120. Continuing to refer to Figure 1A, the source / drain metal layer 102 includes multiple vertical lines 12 extending along the column direction Y, wherein each vertical line 12 is located between two adjacent columns of pixel groups 11. That is, each vertical line 12 can extend between the first sub-pixel 110 and the second sub-pixel 120 located in different pixel groups 11. The source / drain metal layer 102 also includes multiple data lines DT extending along the column direction. For example, each data line DT extends between the first sub-pixel 110 and the second sub-pixel 120 in the same pixel group 11, and each data line DT is connected to two sub-pixels in the same row of sub-pixels. The two sub-pixels connected by the data line do not necessarily belong to the same pixel group 11. For example, the first sub-pixel 110 of a pixel group 11 is connected to one data line DT, and the second sub-pixel 120 is connected to another data line DT. That is, every two sub-pixels in a row of sub-pixels 1 are controlled by the same data line DT. This configuration reduces the number of data lines DT, reduces the number of source drive channels for transmitting data signals, thereby reducing the number of driver chips and reducing costs.

[0075] For example, multiple data lines DT and multiple vertical lines 12 are alternately arranged along the row direction X.

[0076] The vertical line 12 includes a first vertical line 121 and a second vertical line 122. The first vertical line 121 is a touch signal line TX, and the second vertical line 122 includes touch signal lines TX and a common signal line COM spaced apart in the column direction Y. That is, the second vertical line 122 is divided into two disconnected parts, with the touch signal line TX and the common signal line COM being disconnected and receiving different signals. For example, the first vertical line 121 and the second vertical line 122 can be connected to the same driver chip 200.

[0077] Referring again to Figure 1A, the common electrode layer 103 includes multiple common electrodes 1031 arranged in an array. These multiple common electrodes 1031 form multiple touch units 20. Each touch unit 20 includes at least two connected common electrodes 1031. Referring to Figure 2, each touch unit 20 is connected to a touch signal line TX. Within each touch unit 20, the multiple common electrodes are connected to form a single unit. Common electrodes belonging to different touch units 20 are not connected to each other and are spaced apart. This arrangement divides the multiple common electrodes in the array substrate into multiple groups, each group belonging to one touch unit 20, and the common electrodes 1031 in each group are not connected to each other.

[0078] It is understood that in a touch unit 20, each common electrode 1031 receives the same signal. For example, during the touch phase, the touch signal line TX receives the touch signal provided by the touch chip and provides the touch signal to the corresponding common electrode 1031, thereby achieving touch control. During the display phase, the touch signal line TX receives the common voltage signal provided by the touch chip and provides the common voltage signal to the corresponding connected common electrode 1031, thereby achieving display on the display device. As can be seen from the above, compared to related technologies, the inventors of this application have used some common electrodes as touch electrodes, simplifying the structure of the display device.

[0079] Referring to Figures 3A and 3B, the array substrate 10 includes multiple touch units 20. Each touch unit 20 is connected to a touch signal line TX. The multiple touch signal lines TX are connected to the touch chip 400. The touch operation is implemented as follows: when a hand touches a certain area on the display panel, the capacitance between the touch unit at the contact position and the corresponding touch signal line TX changes. The touch signal line TX converts the capacitance change into a signal change and returns it to the touch chip 400. The touch chip 400 performs recognition and analysis to achieve the touch effect.

[0080] As shown in Figure 3A, there is a gap between the touch signal line TX and the common signal line COM on the same second vertical line 122. This gap is located between two adjacent touch units 20 along the column direction Y. The touch signal line TX is disconnected after being connected to the corresponding touch unit 20 and will not extend to other touch units 20 or transmit signals to them. The common signal line COM is electrically connected to the touch unit 20 to achieve signal transmission of a common voltage. This connection method of the touch signal line TX is called a non-equal capacitance design. In some embodiments, referring to Figure 3B, after the touch signal line TX extends to the touch unit 20 it controls and connects to that touch unit 20, it will continue to extend to other touch units 20 in the same column. This connection method of the touch signal line TX is called an equal capacitance design. This equal capacitance design results in a capacitance being generated between a single touch signal line TX and at least two touch units, leading to an increase in capacitance. In contrast to related technologies, this application adopts a non-equal capacitance circuit arrangement as shown in Figure 3A, which can reduce the capacitance between the touch signal line TX and the touch units. That is, the touch signal line TX will only overlap with the touch unit 20 it is connected to, and the touch signal line TX will only generate capacitance between itself and the touch unit 20 it is connected to, without introducing capacitance generated with other touch units 20. This reduces the capacitance load on the touch chip and thus improves touch performance.

[0081] It should be noted that the second vertical line 122 may not be required in practical applications. As described above, the second vertical line 122 in this application adopts the above wiring method. Specifically, there is a gap between the touch signal line TX and the common signal line COM of the second vertical line 122, and the gap is located between two adjacent touch units 20 along the column direction Y. This setting can prevent the second vertical line 122 from being in a free state, and can reduce the capacitance between the touch signal line TX and the touch unit.

[0082] Referring to Figure 4A, in the touch unit 20, multiple common electrodes 1031 are connected. For example, a connection portion 1032 is provided between two adjacent common electrodes 1031 along the row direction X. The two common electrodes 1031 are connected through the connection portion 1032. The connection portion 1032 between two common electrodes 1031 located on both sides of the touch signal line TX has a hollow opening K, which exposes the touch signal line TX. This arrangement can reduce the overlap area between the connection portion 1032 and the touch signal line TX while ensuring the connection performance of adjacent common electrodes in the same touch unit 20. This can reduce the capacitance between the touch signal line TX and the corresponding connection portion 1032, thereby reducing the capacitance between the touch unit 20 and the corresponding touch signal line. The capacitance between TX reduces the load on the touch chip and improves the touch effect. Meanwhile, referring to Figures 4A, 4B, and 4C, the connecting part 1032 is connected to the common electrodes 1031 on both sides. The connecting part 1032 and the common electrodes 1031 on both sides are considered as a whole. The two parts (two first sub-parts A1) on both sides of the hollow opening K along the X direction overlap with the touch signal line TX. This ensures that the touch signal line TX and the two first sub-parts A1 of the connecting part 1032 form a capacitor. That is, the touch signal line TX, the first sub-parts A1 on both sides, and the common electrode 1031 all form a capacitor, avoiding excessive capacitance differences on both sides that could affect touch performance. For example, the two portions of the connection portion 1032 located on both sides of the hollow opening K along the X direction have an equal overlapping area with the touch line TX, which ensures the consistency of capacitance between adjacent touch units 20, and the signal transmitted by the touch line TX is more stable, thereby improving the touch effect.

[0083] For example, referring to FIG1B, the substrate 101 has a supporting and protective function and can be a rigid substrate, such as a glass substrate or a silicon substrate; or it can be a flexible substrate, such as a polyethylene terephthalate (PET) substrate, a PI (Polyimide) substrate, etc., which are not limited here.

[0084] In some embodiments, referring to Figures 4B and 4C, the connecting portion 1032 includes two first sub-parts A1 located on both sides of the hollow opening K along the row direction, and the portions of the two first sub-parts A1 that overlap with the touch line number TX have the same size in the row direction X.

[0085] For example, referring to FIG4C, FIG4C is a cross-sectional structure diagram obtained by making a cross-section at the cross-section line CC' in FIG4B. The two sub-parts A1 of the connecting part 1032 overlap with the touch signal line TX, and the overlapping part has the same dimension S3 in the row direction X. For example, the dimension S3 of the overlapping part of each first sub-part A1 with the touch signal line TX in the row direction X is 1.7μm. This setting can prevent the touch signal line TX from overlapping with one first sub-part A1 but not with the other first sub-part A1 due to process fluctuations, resulting in inconsistent capacitance formed by the touch signal line TX and the common electrodes on both sides, which would affect the touch effect. On the other hand, the above-mentioned smaller size setting can minimize the capacitance between the touch unit 20 and the corresponding touch signal line TX, and reduce the capacitance load on the touch chip.

[0086] For example, referring to Figures 4B and 4C, the size S2 of the cutout opening K in the horizontal direction X is a set size, for example, the size S2 of the cutout opening K in the horizontal direction X is 4μm. The way to set the cutout opening K in the common electrode layer 103 is, for example, to remove the part corresponding to the cutout opening by exposure and development. The size S2 of the cutout opening K in the horizontal direction X is the minimum exposure distance of the common electrode layer 103 (for example, 4μm, which depends on the working capacity of the exposure machine). If it is less than 4μm, it may cause problems with successful exposure and the part corresponding to the cutout opening cannot be removed. When the size S2 of the cutout opening K in the horizontal direction X is greater than 4μm, that is, the size of the cutout opening is set to be large, since it is necessary to ensure that the two sub-parts A1 of the connecting part 1032 overlap with the touch signal line TX, and the overlap size S3 needs to be ensured, the size of the touch signal line TX needs to be increased to ensure the overlap size, which will cause a loss of pixel aperture ratio.

[0087] In some embodiments, referring to Figures 4A, 5A, and 5B, the vertical line 12 includes a plurality of sub-vertical lines 12a, each sub-vertical line 12a corresponding to a row of sub-pixels 1, and the sub-vertical line 12a includes a first end 12a1 and a second end 12a2; the connecting portion 1032 includes two second sub-parts A2 located on both sides of the cutout opening K along the column direction Y, the first end 12a1 overlaps with and is connected to one of the second sub-parts A2, and the second end 12a2 overlaps with the other second sub-part A2; the two second sub-parts A2 have the same size S in the column direction Y.

[0088] For example, as shown in FIG4A, the sub-vertical line 12a includes a first end 12a1 and a second end 12a2, wherein the dimension of the first end 12a1 in the row direction X is greater than the dimension of the second end 12a2 in the row direction X. For example, the shape of the first end 12a1 is a polygon and the shape of the second end 12a2 is a quadrilateral. In this way, the polygonal arrangement of the first end 12a1 of each sub-vertical line 12a can reduce the electrostatic interference generated when the vertical line 12 is in place.

[0089] Referring to Figures 5A and 5B, the second sub-parts A2 of the connecting portion 1032 have the same size in the column direction Y. For example, the size S of the second sub-parts A2 of the connecting portion 1032 in the column direction Y is 17μm to 22μm, which can increase the overlap area between the two second sub-parts A2 of the connecting portion 1032 and the first end 12a1 and the second end 12a2, respectively. Specifically, taking one of the second sub-parts A2 of the connecting portion 1032 as an example, this second sub-part A2 overlaps and is connected with the first end 12a1 and another second sub-part A2. That is to say, the position where the second sub-part A2 overlaps with the first end 12a1 and another second sub-part A2 is used to realize the conductivity between the sub-vertical line 12a and the connecting portion 1032. If the overlap area is too small, it will affect the electrical connection between the two, weaken the conductivity, and affect the quality of signal transmission. Therefore, by controlling the dimensions of the first sub-part A1 and the second sub-part A2 of the connecting part 1032, the size of the cutout opening K is limited so that the size of the cutout opening K is not too large or too small. If the size of the cutout opening K is too small, the capacitance between the touch unit 20 and the corresponding touch signal line TX will be large, and the capacitance will put a large load on the touch chip. At the same time, if the size of the cutout opening K is too large, the conductivity between the two second sub-parts A2 of the connecting part 1032 and the touch connection line TX will be deteriorated. Therefore, the size range of the second sub-parts A2 of the connecting part 1032 in the column direction Y is controlled to be 17, which will reduce the conductivity in the dimensional direction. In this way, the touch performance can be improved, and the conductivity of the two second sub-parts A2 of the connecting part 1032 can be enhanced, ensuring that the voltage of the common electrode 1031 located on both sides of the connecting part 1032 is more stable and improving the reliability of the display device.

[0090] It should be noted that, in conjunction with Figures 4A, 5A and 5B, a through hole is provided between the second sub-part A2 of the connecting portion 1032 and the corresponding first end 12a1, while no through hole is provided between the second sub-part A2 of the connecting portion 1032 in Figure 5B and the corresponding second end 12a2. In order to ensure electrical and optical consistency between each sub-pixel, the dimensions of the two second sub-parts A2 in the column direction Y are set to be equal.

[0091] In some embodiments, as shown in FIG6 and in conjunction with FIG1C, the array substrate 10 further includes a gate layer 108 disposed between the substrate 101 and the source / drain metal layer 102. The gate layer 108 includes multiple gate lines GT extending along the row direction X. The multiple gate lines GT form multiple gate line groups GT'. Each gate line group GT' includes two gate lines GT, and the two gate lines GT are located between two adjacent rows of common electrodes 1031.

[0092] The common electrode layer 103 also includes a plurality of extensions 1033 located between two adjacent rows of common electrodes 1031. Each of the plurality of extensions 1033 is connected to two common electrodes 1031 located on both sides of its column direction Y. The extensions 1033 overlap with a longitudinal line 12. Between two adjacent rows of common electrodes 1031, the extensions 1033 overlap with two gate lines GT.

[0093] For example, multiple gate lines GT form multiple gate line groups GT'. Each gate line group GT' includes a first gate line GT1 and a second gate line GT2. The first sub-pixel 110 of each pixel group GT' is connected to the first gate line GT1 of the gate line group GT' located on one side of it. The second sub-pixel 120 of each pixel group GT' is connected to the second gate line GT2 of the gate line group GT' located on the other side of it. The first sub-pixel 110 includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the first gate line GT2, and the second sub-pixel 120 includes a second transistor T2, the gate of the second transistor T2 is electrically connected to the first gate line GT1.

[0094] Referring again to Figure 6, a plurality of extensions 1033 are provided between two adjacent rows of common electrodes 1031. These extensions 1033 connect the two adjacent rows of common electrodes 1031, and each extension 1033 overlaps with a vertical line 12. That is, in the region between two adjacent rows of common electrodes 1031, the portion of the vertical line 12 projected onto the substrate 101 within the region between the two rows of common electrodes 1031 partially overlaps with the extensions 1033. Furthermore, between two adjacent rows of common electrodes 1031, the extensions 1033 overlap with both gate lines GT. Referring to Figure 6, the figure shows… The extension 1033 extends through the corresponding two gate lines GT. The extension 1033 extends along the column direction, and the two gate lines GT are arranged in parallel. The extension direction of the overlapping part of the two gate lines GT and the extension 1033 intersects both the row direction X and the column direction Y. That is, the shape of the overlapping part of each gate line GT and the extension 1033 can be a parallelogram, and the overlapping area is the same. This ensures that the capacitance between the gate line GT and the extension 1033 is consistent, thereby ensuring that the capacitance of each sub-pixel is consistent and preventing the capacitance deviation of the sub-pixels in the display, which would affect the display effect and touch effect.

[0095] In some embodiments, as shown in Figures 7A, 7B, and 7C, a plurality of extensions 1033 include a first extension 1033a and a second extension 1033b. The first extension 1033a is located between two adjacent touch units 20 along the column direction Y, and the second extension 1033b is located within the touch unit 20. The first extension 1033a includes a first break D1, which divides the first extension 1033a into two sub-extensions 1033a1. The two sub-extensions 1033a1 are respectively connected to two common electrodes 1031. The two sub-extensions 1033a1 overlap with two corresponding gate lines GT. The second extension 1033b overlaps with two corresponding gate lines GT. The overlap area of ​​the first extension 1033a with the two corresponding gate lines GT is equal to the overlap area of ​​the second extension 1033b with the two corresponding gate lines GT.

[0096] Referring to Figures 7A and 7B, the extension 1033 shown in Figure 7A is a first extension 1033a. The first extension 1033a includes a first break D1, which divides it into two sub-extensions 1033a1. Each sub-extension 1033a1 is connected to a common electrode 1031 in one of two different touch units 20. Referring to Figures 7A and 7B, each sub-extension 1033a1 is connected to the common electrode 1031 closest to it. It should be noted that since the two sub-extensions 1033a1 are connected to the two common electrodes 1031 located in different touch units 20, the signals received by the two common electrodes 1031 can be different. For example, one of the two common electrodes 1031 receives a first touch signal, and the other receives a second touch signal.

[0097] For example, referring to Figure 7A, the touch signal line TX in Figure 7A, after extending to and connecting with the touch unit 20 it controls, continues to extend to other touch units 20 in the same column. That is, as shown in Figure 7A, the touch signal line TX is continuous at the first break point D1. Referring to Figure 7B, the touch signal line TX in Figure 7B, after extending to and connecting with the touch unit 20 it controls, does not continue to extend to other touch units 20 in the same column. That is, as shown in Figure 7B, the touch signal line TX is disconnected at the first break point D1.

[0098] Referring to FIG7C, the extension 1033 shown in FIG7C includes a second extension 1033b, wherein the second extension 1033b is located within the touch unit 20, and the signals received by the two common electrodes 1031 connected to the second extension 1033b are the same, that is, the second extension 1033b in FIG7C has no break, and its corresponding longitudinal line also has no break, so as to ensure the continuity of the signal received by the common electrode 1031.

[0099] It should be noted that setting the overlap area of ​​the first extension 1033a and the corresponding two gate lines GT to be equal to the overlap area of ​​the second extension 1033b and the corresponding two gate lines GT can ensure that the capacitance between the gate line GT and the first extension 1033a or the second extension 1033b is consistent, thereby ensuring that the capacitance of each sub-pixel is consistent and preventing capacitance deviation of sub-pixels in the display, which would affect the display and touch effects.

[0100] In some embodiments, referring to FIG7D, the orthographic projection of the first break D1 on the substrate 101 is located between the orthographic projections of the corresponding two gate lines GT on the substrate 101.

[0101] For example, referring to FIG7D, the orthographic projection of the first break D1 on the substrate 101 is located between the orthographic projections of the corresponding two gate lines GT on the substrate 101. That is, the orthographic projection of the boundary of the first break D1 on the substrate 101 will exceed the orthographic projection boundary of the two gate lines GT on the substrate 101. Since the two gate lines GT are parallel and their extension directions are consistent at the overlapping positions of the two gate lines GT and the corresponding extensions 1033, the setting position of the first break D1 of the first extension 1033a can ensure that the overlapping areas of the two sub-extensions 1033a1 with the first gate line GT1 and the second gate line GT2 are consistent, thereby ensuring that the capacitance of each sub-pixel is consistent and preventing capacitance deviation of the sub-pixels in the display, which would affect the display and touch effects.

[0102] In some embodiments, referring to FIG7E and FIG7C, the ends of the two sub-extensions 1033a1 that are close to each other are closer to the common electrode 1031 connected to the sub-extensions 1033a1 than the sides of the two gate lines that are close to each other; the dimension H1 of the portion of the sub-extension 1033a1 that overlaps with the corresponding gate line GT in the first direction Z is greater than the dimension H2 of the portion of the second extension 1033b that overlaps with the corresponding gate line GT in the first direction Z; the first direction Z intersects the column direction Y.

[0103] For example, referring to FIG7E and in conjunction with FIG7C, the ends of the two sub-extensions 1033a1 that are close to each other are closer to the common electrode 1031 to which the sub-extensions 1033a1 are connected than the sides of the two gate lines that are close to each other. That is, the boundary of each of the two sub-extensions 1033a1 does not exceed the boundary of the corresponding overlapping gate line GT. For example, one of the two sub-extensions 1033a1 overlaps with the first gate line GT1, and the other sub-extension 1033a1 overlaps with the second gate line GT2. The boundary of the sub-extension 1033a1 that overlaps with the first gate line GT1 does not exceed the boundary of the first gate line GT1. The boundaries of the overlapping sub-extensions 1033a1 of the two gate lines GT2 do not exceed the boundaries of the second gate line GT2. That is, there is a certain gap between the boundary of each sub-extension 1033a1 and the corresponding gate line GT. In order to ensure that the capacitance between each sub-extension 1033a1 and the corresponding gate line GT is consistent with the capacitance between the extension 1033 at the position where the first disconnection D1 is not set and its corresponding gate line GT, the size of the part of the sub-extension 1033a1 that overlaps with the corresponding gate line GT in the first direction Z is set to be greater than the size of the part of the second extension 1033b that overlaps with the corresponding gate line GT in the first direction Z. For example, the first direction Z is the extension direction of the gate line GT.

[0104] In some embodiments, continuing to refer to FIG7A, the longitudinal line 12 that overlaps with the first extension 1033a is the first longitudinal line 121, and the first break D1 exposes at least a portion of the first longitudinal line 121.

[0105] For example, the first break D1 is located between the two touch units 20, the first vertical line 121 is the touch signal line TX, and the first vertical line 121 is uninterrupted between the two touch units 20, that is, the first vertical line 121 is located in the two touch units 20.

[0106] In some embodiments, referring to FIG7B, the longitudinal line that overlaps with the first extension 1033a is the second longitudinal line 122, and the first break D1 is located at the interval between the touch signal line TX and the common signal line COM of the second longitudinal line 122.

[0107] For example, referring to FIG7B, the first break D1 is located between the two touch units 20, and the second vertical line 122 includes a touch signal line TX and a common signal line COM. That is, the positions of the touch signal line TX and the common signal line COM are intersected with the first break D1, and the second vertical line 122 located above the first break D1 is the common signal line COM, and the second vertical line 122 located above the first break D1 is the touch signal line TX.

[0108] In some embodiments, continuing to refer to FIG7B, the dimension of the first break D1 in the column direction Y is smaller than the spacing of the touch signal line TX and the common signal line COM of the second longitudinal line 122 in the column direction Y.

[0109] For example, referring to FIG7D, the dimension d1 of the first break D1 in the column direction is 5um, which is smaller than the spacing d2 of the touch signal line TX and the common signal line COM in the column direction Y of the second vertical line 122, which is 7um. That is, the touch signal line TX and the common signal line COM are located at the boundary between the two gate lines GT, and are closer to the common electrode 1031 located on both sides of the boundary between the two sub-extensions 1033a1 and the two gate lines GT. The above-mentioned dimension setting can ensure that the overlap area between the second vertical line 122 and the corresponding extension 1033 is as consistent as possible at the interval position of the touch signal line TX and the common signal line COM, thereby improving the touch and display effect.

[0110] The specific structure of each film layer in the array substrate is described below.

[0111] In some embodiments, as shown in FIG1C and FIG8A-8E, FIG8A-8E are schematic diagrams of the film layers of multiple pixels. The array substrate 10 further includes a pixel electrode layer 104, a gate layer 108, a gate dielectric layer 105, a semiconductor layer 106, a source / drain metal layer 102, a passivation layer 107, and a common electrode layer 103, which are sequentially stacked on the substrate 101. The gate dielectric layer 105 and the passivation layer 107 are not shown in FIG8A-8E. The pixel electrode layer 104 and the gate layer 108 may be located in the same layer. As shown in FIG8A, the pixel electrode layer 104 includes multiple pixel electrodes 1041, which are arranged in an array and each pixel electrode 1041 is separated from each other; the pixel electrode layer 104 also includes multiple gate lines GT, and multiple transistor gates 1081 are uniformly connected on each gate line GT. As shown in Figure 8B, Figure 8B includes a structural diagram of a semiconductor layer 106. The semiconductor layer 106 includes an active layer pattern 1061 of multiple transistors, and the active layer pattern 1061 of multiple transistors overlaps with the gates of multiple transistors. The material of the semiconductor layer 106 can be, for example, amorphous silicon, low-temperature polycrystalline silicon, metal oxide semiconductor, etc., and is not limited here. Figure 8C shows a structural diagram including a source / drain metal layer 102. The source / drain metal layer 102 includes multiple data lines DT and multiple vertical lines 12, wherein the multiple data lines DT and multiple vertical lines 12 are arranged alternately in the row direction X. It can be seen from the figure that each data line 4 is located between the first sub-pixel 110 and the second sub-pixel 120 in a pixel group 11. In addition, the source / drain metal layer 102 also includes the first electrode and the second electrode of multiple transistors, wherein the first electrode of the transistor is connected to the data line DT. Figure 8D shows a structural diagram including multiple vias. The array substrate 10 includes multiple vias G, each of which penetrates the passivation layer 107 and the gate dielectric layer 105. Each via G includes a first portion G1 and a second portion G2 connected together. The first portion G1 penetrates the passivation layer 107, and the second portion G2 penetrates both the passivation layer 107 and the gate dielectric layer 105. Figure 8E is a structural diagram of the common electrode layer 103. In the diagram, the common electrodes 1031 are arranged in a mesh structure, and the common electrodes 1031 of each sub-pixel 1 in each touch unit 20 are electrically connected to form a whole. It can be understood that the common electrode 1031 in the sub-pixel 1 is the portion of the common electrode layer 103 that overlaps with the pixel electrode 1041 of that sub-pixel 1.

[0112] It is understandable that the first part G1 of the aforementioned via G penetrates the passivation layer 107, and the second part G2 penetrates the passivation layer 107 and the gate dielectric layer 105. That is to say, the depths of the first part G1 and the second part G2 connected by the via G are different, that is, the first part G1 and the second part G2 can form a height difference. In this way, during the process of forming an alignment film with polyimide (PI) liquid above the common electrode layer 103, it is beneficial to the diffusion of PI liquid, thereby improving the situation of periodic uneven display brightness caused by uneven diffusion of PI liquid, and improving the quality and yield of the display panel.

[0113] In some embodiments, referring to FIG9A and FIG7A, the pixel electrode layer 104 includes a plurality of pixel electrodes 1041, each pixel electrode 1041 overlapping with a common electrode 1031; each of the plurality of sub-pixels 1 includes a first transistor T1, a pixel electrode 1041 and a common electrode 1031; the common electrode layer 103 includes a transition electrode 1034, the source-drain metal layer 102 includes the drain pattern 1021 of the first transistor T1, and the plurality of vias G includes a first via G11; the transition electrode 1034 is connected to the drain pattern 1021 of the first transistor T1 through the first portion G11a of the first via G11, and the transition electrode 1034 is connected to the pixel electrode 1041 through the second portion G11b of the first via G11.

[0114] For example, referring to FIG9A, FIG9A is a cross-sectional structure diagram obtained by taking a section along the section line AA of FIG7A. As shown in FIG9A, a part of the transition electrode 1034 covers a part of the drain pattern 1021 of the first transistor T1, and another part of the transition electrode 1034 covers a part of the pixel electrode 1041. That is, by setting the transition electrode 1034, the pixel electrode 1041 can be electrically connected to the drain pattern 1021 of the first transistor T1. In conjunction with FIG6, the pixel electrode 1041 can receive the data signal transmitted by the data line DT through the drain pattern 1021 of the first transistor T1.

[0115] It should be noted that the first sub-pixel 110 and the second sub-pixel connected to the same data line DT do not necessarily belong to the same pixel group 11. As shown in Figure 6, each data line DT extends between the first sub-pixel 110 and the second sub-pixel 120 of the same pixel group 11. The two sub-pixels connected to the same data line do not necessarily belong to the same pixel group 11. For example, the data line in Figure 6 can connect the second sub-pixel 120 and the first sub-pixel 110 located to its left. The data line DT is configured to provide data signals to the pixel electrodes 1041 in the first sub-pixel 110 and the second sub-pixel 120 respectively through the first transistor T1 and the second transistor T2. These data signals can be voltage signals, the magnitude of which corresponds to the brightness of the sub-pixel. For example, referring to Figure 6, the first transistor T1 and the second transistor T2 can be located on the same side of the correspondingly connected data lines DT.

[0116] In some embodiments, referring to FIG6 and in conjunction with FIG1B, the first transistor T1 and the second transistor T2 are bottom-gate transistors. Both the first transistor T1 and the second transistor T2 include a gate 1081, an active layer pattern 1061, and a source / drain 1020 stacked sequentially. The source / drain 1020 includes a first electrode and a second electrode. The orthographic projection of the channel portion of the active layer pattern on the substrate 101 falls within the orthographic projection of the gate 1081 on the substrate 101. At least a portion of the orthographic projections of the first electrode and the second electrode on the substrate 101 fall within the orthographic projection of the active layer pattern 1061 on the substrate 101. The orthographic projection shape of the first electrode (e.g., the first electrode of the first transistor T1) is U-shaped, and the opening of the first electrode faces the second electrode.

[0117] For example, referring to FIG6 and in conjunction with FIG1B, the orthographic projection of the channel portion of the active layer pattern of the first transistor T1 and the second transistor T2 on the substrate 101 falls into the orthographic projection of the gate 1081 on the substrate 101. That is, the area of ​​the channel portion of the active layer pattern 1061 of the first transistor T1 and the channel portion of the active layer pattern 1061 of the second transistor T2 is smaller than the area of ​​the gate 1081 of the first transistor T1 and the gate 1081 of the second transistor T2 respectively. At least a portion of the orthographic projection of the first electrode 131 and the second electrode 132 on the substrate 101 falls into the orthographic projection of the active layer pattern 1061 on the substrate 101.

[0118] In some embodiments, referring to Figures 7A and 9A, the ratio of the area of ​​the orthogonal projection of the portion of the transition electrode 1034 located within the first portion G11a of the first via G11 onto the substrate 101 to the area of ​​the orthogonal projection of the portion of the transition electrode 1034 located within the first via G11 onto the substrate 101 ranges from 0.4 to 0.6.

[0119] For example, the ratio of the area of ​​the portion of the transition electrode 1034 located within the first portion G11a of the first via G11 projected onto the substrate 101 to the area of ​​the portion of the transition electrode 1034 located within the first via G11 projected onto the substrate 101 can be 0.4, 0.5, or 0.6, etc. This configuration ensures the height difference between the first portion G11a and the second portion G11b of the first via G11, i.e., a stepped structure is formed between the first portion G11a and the second portion G11b, which is beneficial to the diffusion of PI liquid. This improves the situation where uneven display brightness occurs periodically due to uneven diffusion of PI liquid, thereby improving the quality and yield of the display panel.

[0120] In some embodiments, referring to Figures 7A and 9B, the plurality of vias G include a second via G12; the longitudinal line 12 is connected to the corresponding common electrode 1031 through the second via G12; the common electrode 1031 connected to the longitudinal line 12 includes a first connecting block L1, the first connecting block L1 is connected to the longitudinal line 12 through a first portion G12a of the second via G12, and the first connecting block L1 is in contact with the substrate 101 through a second portion G12b of the second via G12.

[0121] For example, referring to FIG9B, FIG9B is a cross-sectional view of FIG7A obtained by making a cross-section along the cross-section line BB. In FIG7A, a part of the first connecting block L1 covers a part of the longitudinal line 12, and another part of the first connecting block L1 covers a part of the substrate 101. That is, by providing the second via G12, the first connecting block L1 can be electrically connected to the longitudinal line 12 so that the first connecting block L1 can receive the touch voltage signal or common voltage signal transmitted by the longitudinal line 12. For example, the longitudinal line 12 connected to the first connecting block L1 is the first longitudinal line 121, and the signal received by the first connecting block L1 is the touch voltage signal. The longitudinal line 12 connected to the first connecting block L1 is the second longitudinal line 122. Specifically, the second longitudinal line 122 connected to the first connecting block L1 is the touch signal line TX, and the signal received by the first connecting block L1 is the touch voltage signal. The second longitudinal line 122 connected to the first connecting block L1 is the common signal line COM, and the signal received by the first connecting block L1 is the common voltage signal.

[0122] It should be noted that the first connecting block L1 contacts the substrate 101 through the second part G12b of the second via G12, mainly to increase the contact area of ​​the second via G12, so that the first connecting block L1 and the longitudinal line 12 can be better electrically connected, thereby improving the signal transmission efficiency.

[0123] In some embodiments, referring to Figures 7A and 9B, the ratio of the area of ​​the portion of the first connecting block L1 located within the first portion G12a of the second via G12 projected onto the substrate 101 to the area of ​​the portion of the first connecting block L1 located within the second via G12 projected onto the substrate 101 ranges from 0.2 to 0.3.

[0124] For example, the ratio of the area of ​​the first portion G12a of the first connecting block L1 located within the second via G12 on the substrate 101 to the area of ​​the first portion G12 located within the second via G12 on the substrate 101 can be 0.2, 0.25, or 0.3, etc. This setting ensures that the first portion G12a and the second portion G12b of the second via G12 have a height difference, that is, a step structure is formed between the first portion G12a and the second portion G12b, which is beneficial to the diffusion of PI liquid and thus improves the situation of periodic uneven display brightness caused by uneven diffusion of PI liquid.

[0125] In some embodiments, referring to FIG7A, the longitudinal line 12 includes a second connecting block L2, which corresponds to a first connecting block L1. The first connecting block L1 includes a portion that overlaps with the second connecting block L2 and a portion that does not overlap with the second connecting block L2. At least a portion of the boundary of the first connecting block L1 matches the shape of at least a portion of the boundary of the second connecting block L2.

[0126] For example, the orthographic projection of the first connecting block L1 onto the substrate 101 is a polygon, such as an octagon, and the orthographic projection of the second connecting block L2 onto the substrate 101 is also, for example, an octagon, with at least a portion of the octagon removed. That is, the removed portion does not overlap with the second connecting block L2, and the boundary shape of the unremoved portion matches at least a portion of the boundary of the first connecting block L1, that is, the boundary shape of the unremoved portion is a part of the octagon. Referring to FIG7A, the overlapping portion of the first connecting block L1 and the second connecting block L2 is the first part L11, and the non-overlapping portion is the second part L12. The above configuration, while ensuring a good electrical connection between the first connecting block L1 and the second connecting block L2, avoids the vias connecting the first connecting block L1 and the second connecting block L2 being exposed to air. The first connecting block L1 completely encloses the vias, and the orthographic projection shapes of the second connecting block L2 and the first connecting block L1 on the substrate 101 match, with the second connecting block L2 having a polygonal shape. All angles of the orthographic projection shape of the second connecting block L2 are obtuse angles. This configuration reduces electrostatic interference generated during fabrication. For example, the orthographic projection of the second connecting block L2 on the substrate 101 can also be a circle with a portion removed. Furthermore, by matching the shape of at least a portion of the boundary of the first connecting block L1 with at least a portion of the boundary of the second connecting block L2, the circuit structure of the array substrate 10 becomes more orderly. Simultaneously, it ensures that the capacitance generated between each first connecting block L1 and the corresponding second connecting block L2 remains consistent, improving conductivity and making the voltage signal transmitted through the longitudinal line 12 more stable.

[0127] In some embodiments, referring to FIG7F, the common electrode 1031, which is not connected to the longitudinal line 12, includes a third connecting block L3. The third connecting block L3 is located near the interval between two adjacent touch units 20, and the shape of the third connecting block L3 is consistent with that of the first connecting block L1.

[0128] For example, as shown in FIG7F, the third connecting block L3 is located between two adjacent touch units 20, and the third connecting block L3 is connected to one of the two touch units 20 and has a gap with the other touch unit 20. Specifically, the third connecting block L3 in FIG7C is not connected to the touch unit 20 located to its left, and the shape of the boundary of the third connecting block L3 near the touch unit 20 to its left is consistent with the shape of the first connecting block L1, for example, it is a polygon.

[0129] It should be noted that the third connecting block L3 is configured to have the same shape as the first connecting block L1, ensuring electrical and optical consistency between each sub-pixel and improving the touch and display effects of the display device.

[0130] The following describes the fabrication method of the array substrate.

[0131] In some embodiments, as shown in FIG10, the steps for fabricating the array substrate 10 include:

[0132] S1. A transparent conductive material is deposited on a substrate 101, and the transparent conductive material is etched by exposure, development and etching processes to form a pixel electrode layer 104 including multiple pixel electrodes.

[0133] For example, the transparent conductive material can be indium tin oxide (ITO), and its thickness can be [missing information].

[0134] S2. A first metal material is deposited on the pixel electrode layer 104, and the transparent conductive material is etched by exposure, development and etching processes to form a gate layer 108 including multiple gate lines.

[0135] For example, the first metallic material is a molybdenum-aluminum-molybdenum (Mo / Al / Mo) material with thicknesses of [missing information].

[0136] It should be noted that the obtained pixel electrode layer 104 and gate layer 108 are both located on the substrate 101, that is, the pixel electrode layer 104 and gate layer 108 can be located on the same layer.

[0137] S3. Deposit an entire layer of insulating material on the gate layer 108 to form the gate dielectric layer 105.

[0138] For example, the insulating material described above can be silicon nitride (SiNx), with a thickness of [missing information].

[0139] S4. First, a semiconductor material is deposited on the gate dielectric layer 105, then a second metal material is deposited, and a photoresist layer is coated. The photoresist layer is exposed and developed using a mask to obtain a patterned photoresist layer.

[0140] It should be noted that the photomask includes multiple openings, as well as halftone and fulltone regions. The portion of the photoresist layer corresponding to the multiple openings is removed, and part of the second metal material is exposed. The portions corresponding to the halftone and fulltone regions are retained to form a patterned photoresist layer. The thickness of the portion corresponding to the halftone region in the patterned photoresist layer is less than the thickness of the portion corresponding to the fulltone region.

[0141] The active layer of the transistor is covered in the portion of the halftone region in the patterned photoresist layer.

[0142] For example, the semiconductor material can be amorphous silicon (A-Si) material with a thickness of [missing information].

[0143] For example, the second metallic material is a molybdenum-aluminum-molybdenum (Mo / Al / Mo) material, with thicknesses of [missing information].

[0144] S5. Etch the second metal material exposed to the developed photoresist layer to obtain a source / drain metal layer 103 with multiple vertical lines 12 and multiple data lines DT.

[0145] S6. Thin the patterned photoresist layer until the halftone region in the patterned photoresist layer is removed to form the semiconductor layer 106.

[0146] For example, the photoresist layer can be thinned using wet etching, dry etching, or laser etching processes. This example uses a dry etching process, also known as photoresist ashing, which is performed in an ECCP (Enhance Cathode Coupling Plasma) dry etching apparatus using NF3 and O2 as working gases.

[0147] S7. Remove the remaining photoresist.

[0148] S8. An insulating material is deposited on the source / drain metal layer 103, and the insulating material is etched by exposure, development and etching processes to form a passivation layer 107.

[0149] For example, the insulating material may be silicon nitride (SiNx) with a thickness of [missing information].

[0150] For example, the insulating material can also be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., and can be a single-layer, double-layer, or multi-layer structure to achieve the effects of blocking water and oxygen and blocking alkaline ions. The passivation layer 107 can be deposited using a plasma-enhanced chemical vapor deposition (PECVD) process.

[0151] S9. A transparent conductive material is deposited on the passivation layer 107, and the transparent conductive material is etched by exposure development and etching processes to form a common electrode layer 103.

[0152] For example, the transparent conductive material can be indium tin oxide (ITO), and its thickness can be [missing information].

[0153] It should be noted that, in some embodiments of the related technology, the steps of forming the semiconductor layer 106 and the source / drain metal layer 103 include:

[0154] R1. After depositing semiconductor material in the gate dielectric layer 105, the semiconductor material is patterned to form the active layer pattern of the semiconductor layer 106.

[0155] For example, semiconductor materials are etched through exposure, development, and etching processes.

[0156] R2. Deposit a second metal material on the semiconductor layer 106, and pattern the second metal material to form the source / drain metal layer 103.

[0157] For example, the second metallic material is etched by exposure development and etching processes.

[0158] Therefore, in the process of forming the semiconductor layer 106 and the source / drain metal layer 103, the material of each layer needs to be patterned, which means that it needs to be prepared by two masking processes.

[0159] Referring to Figure 10, in step S4 of this application, a semiconductor material is first deposited on the gate dielectric layer 105, followed by the deposition of a second metal material, and then a photoresist layer is coated. A photomask is used to expose and develop the photoresist layer to obtain a patterned photoresist layer. This setup, compared to related technologies, reduces the number of masking operations, allowing for a single masking process. A halftone mask can expose the semiconductor material in the region where the active layer pattern is formed. After etching away the second metal material to obtain multiple vertical lines 12 and multiple data lines DT, an ashing process is used to prepare the semiconductor layer 106.

[0160] It should be noted that the above materials are merely examples and this disclosure does not impose any limitations. Furthermore, Figure 1B illustrates an array substrate with a bottom-gate thin-film transistor (TFT) as an example; in other embodiments, the array substrate may also employ a top-gate TFT.

[0161] As shown in Figure 12, some embodiments of this disclosure also provide a display panel 100, including a display area AA and a peripheral area BB disposed around the display area AA; as shown in Figure 11, the display panel 100 includes an array substrate 10 provided in any of the above embodiments and a color filter substrate 50 disposed opposite to the array substrate 10; and a liquid crystal layer located between the array substrate 10 and the color filter substrate 50.

[0162] For example, the liquid crystal layer includes liquid crystal material located in the display area AA. The display panel 100 also includes a sealant 40 surrounding the liquid crystal material, which serves to connect the array substrate 10 and the color filter substrate 50.

[0163] For example, the display panel 100 also includes spacers, which can be disposed on the color filter substrate (CF) 50 or on the array substrate 10. The color filter substrate, also called the opposing substrate, has a liquid crystal layer disposed between it and the array substrate. A black matrix layer and a color filter layer 21 can be disposed on the color filter substrate. Referring to FIG11, the color filter layer 21 is disposed on the side of the color filter substrate 50 near the array substrate. The color filter layer 21 includes multiple filter units of different colors, such as red, green, and blue filter units formed using red, green, and blue photosensitive resins. Each filter unit corresponds to a sub-pixel. The black matrix layer is used to define the boundaries between the filter units to prevent light leakage between adjacent filter units.

[0164] For example, the material of the black matrix layer includes, but is not limited to, one or more of BM (Black matrix) material, RGB Resin material, or BPS (4,4'-dihydroxydiphenyl sulfone) material. BM can be Cr (chromium), CrOx (chromium oxide), or Black Resin.

[0165] For example, referring to FIG6, the display area AA of the display panel 100 includes a plurality of sub-pixels 1, and each sub-pixel 1 may include a pixel electrode 1041 and a common electrode 1031. The pixel electrode 1041 and the common electrode 1031 are disposed opposite to each other, and a pixel capacitor may be formed between the pixel electrode 1041 and the common electrode 1031.

[0166] For example, the material of the pixel electrode may include a transparent conductive material. For instance, the material of the pixel electrode may include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0167] The material of the common electrode can also include transparent conductive materials. For example, the material of the common electrode can include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0168] The materials used for the aforementioned pixel electrodes and common electrodes are transparent conductive materials such as indium tin oxide (ITO), which can reduce the impact on light emission.

[0169] For example, the pixel electrode 1041 is a block electrode and the common electrode 1031 is a strip electrode, as shown in FIG6. Each common electrode 1031 includes multiple slits, each slit extending along the column direction Y, and the area of ​​the slits in each common electrode is equal, so as to ensure that the aperture ratio of the first sub-pixel 110 is equal to that of the second sub-pixel 120, thereby ensuring that the light emission efficiency of the display panel is the same and the light is uniform.

[0170] An electric field can be generated within the display panel 100, causing the liquid crystal molecules in the liquid crystal layer 30 within the display panel 100 to deflect under the influence of the electric field. By adjusting the intensity of the electric field applied to the liquid crystal layer 30 within the display panel 100, the degree of deflection of the liquid crystal molecules within the liquid crystal layer 30 can be controlled, thereby controlling the amount of light transmitted in the area where the liquid crystal molecules are located within the liquid crystal layer 30, thus enabling the display panel 100 to display images.

[0171] For example, the electric field that drives the liquid crystal molecules in the liquid crystal layer 30 within the display panel 100 to deflect can be generated when a voltage is applied to the pixel electrode and the common electrode within the sub-pixel.

[0172] In some embodiments, the positional relationship between the pixel electrode and the common electrode included in the display panel 100 can be as follows: the pixel electrode can be located on the side of the common electrode away from the substrate 101; the pixel electrode can also be located on the side of the common electrode away from the substrate 101; or the pixel electrode and the common electrode can be located on the same layer; or the pixel electrode and the common electrode can be located on the array substrate 10 of the display panel simultaneously; or the pixel electrode can be located on the array substrate 10 of the display panel 100, and the common electrode can be located on the color filter substrate 50 of the display panel 100. In the embodiments of this application, both the pixel electrode and the common electrode are located on the array substrate 10 of the display panel 100.

[0173] Some embodiments of this disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0174] This disclosure does not impose any special restrictions on the specific form of the display device described above. The display device 1000 adopts the display panel 100 provided in the above embodiments. Therefore, the display device 1000 provided in this disclosure has all the beneficial effects of the display panel 100 provided in any of the above embodiments, which will not be elaborated here.

[0175] For example, as shown in FIG12, the display device 1000 is, for example, a rectangle or a rounded rectangle.

[0176] For example, the display device 1000 may be a thin film transistor liquid crystal display (TFT-LCD) device.

[0177] In one possible embodiment, referring to Figures 11 and 12, the display panel is a liquid crystal display panel, the display device including the display panel is a liquid crystal display device, and the liquid crystal display device further includes a backlight panel located on the side of the array substrate 10 away from the color filter substrate 50. Exemplarily, the liquid crystal display panel may be an Advanced Super Dimension Switch (ADS) liquid crystal display panel, or a High-Aperture Ratio and High-Advanced Dimension Switch (HADS) liquid crystal display panel. Exemplarily, the liquid crystal display device further includes a backlight panel and a power supply circuit; the backlight panel is located on the backlight surface of the display panel and is used to provide a light source for the liquid crystal display panel, and the power supply circuit is used to supply power to the display panel.

[0178] In some embodiments, referring to Figures 2 and 12, the display device 1000 includes a display panel 100 and a touch chip 400. The touch chip 400 is electrically connected to the display panel 100.

[0179] For example, the touch chip 400 within the display device 1000 can be packaged using a chip-on-film (COF) film. When the touch chip 400 within the display device 1000 is packaged using a COF film, the display device 1000 includes a COF film assembly, which may include a flexible printed circuit (FPC) and a driver chip bonded to the FPC. For example, one end of the flexible printed circuit connected to the COF film has gold fingers (not shown), and the gold fingers and the COF film 300 are connected via an anisotropic conductive film (ACF), which includes an adhesive layer and a plurality of metal balls (e.g., gold balls) distributed within the adhesive layer.

[0180] For example, the touch chip 400 of the display device 1000 is configured to drive the display panel 100 to display images and send touch signals to realize touch functions. The touch chip 400 can be packaged using a chip-on-glass film 300, chip-on-glass (COG), chip-on-pi (COP), or other similar materials and bonded to the display panel 100. This application uses a chip-on-glass film 300 as an example for illustration.

[0181] In some embodiments, the main structure of the display device 1000 includes a frame, a cover plate, a display panel 100, and other electronic components. The frame surrounds an accommodating space, the display panel 100 and other electronic components are disposed within this accommodating space, and the cover plate is disposed on the open side of the frame.

[0182] It should be noted that the dual-gate structure of the display panel 100 can reduce the number of data lines DT in the display panel 100, thereby reducing the cost of the corresponding touch chip. It can also reduce the fanout wiring space, thereby reducing the size of the peripheral area BB of the display panel 100, which is conducive to realizing the narrow bezel design of the display panel 100.

[0183] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0184] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate comprising a plurality of sub-pixels arranged in an array, the plurality of sub-pixels forming a plurality of pixel groups, each pixel group comprising two adjacent sub-pixels along a row direction; The array substrate includes: Substrate; A source / drain metal layer is disposed on one side of the substrate. The source / drain metal layer includes multiple vertical lines extending along the column direction. Each of the multiple vertical lines is located between two adjacent columns of pixels. The multiple vertical lines include multiple first vertical lines and multiple second vertical lines. The first vertical lines are touch signal lines, and the second vertical lines include touch signal lines and common signal lines spaced apart in the column direction. A common electrode layer is disposed on the side of the source / drain metal layer away from the substrate; the common electrode layer includes a plurality of common electrodes arranged in an array, each sub-pixel includes one common electrode, the plurality of common electrodes form a plurality of touch units, each of the plurality of touch units includes at least two common electrodes connected to each other, and each of the touch units is connected to a touch signal line. In the touch unit, a connecting portion is provided between two adjacent common electrodes along the row direction. The connecting portion is connected to the two common electrodes. The connecting portion between the two common electrodes located on both sides of the touch signal line has a hollow opening. The hollow opening exposes the touch signal line, and two parts of the connecting portion located on both sides of the hollow opening along the row direction overlap with the touch signal line.

2. The array substrate according to claim 1, wherein, The connecting portion includes two first sub-parts located on both sides of the hollow opening along the row direction, and the portions of the two first sub-parts that overlap with the touch line are equal in size in the row direction.

3. The array substrate according to claim 1 or 2, wherein, The vertical line includes multiple sub-vertical lines, each of which corresponds to a row of sub-pixels, and each sub-vertical line includes a first end and a second end. The connecting portion includes two second sub-parts located on both sides of the hollow opening along the column direction, the first end overlapping and connecting with one of the second sub-parts, and the second end overlapping with the other second sub-part; The two second sub-parts have equal dimensions in the column direction.

4. The array substrate according to any one of claims 1 to 3, wherein, The array substrate further includes a gate layer disposed between the substrate and the source / drain metal layer. The gate layer includes multiple gate lines extending along the row direction. The multiple gate lines form multiple gate line groups. Each gate line group includes two gate lines, and the two gate lines are located between two adjacent rows of the common electrode. The common electrode layer also includes a plurality of extensions located between two adjacent rows of common electrodes, each of the plurality of extensions being connected to two common electrodes located on either side of it in the column direction; the extensions overlap with one of the longitudinal lines; Between two adjacent rows of common electrodes, the extension overlaps with both of the gate lines.

5. The array substrate according to claim 4, wherein, The plurality of extensions includes a first extension and a second extension, wherein the first extension is located between two adjacent touch units along the column direction, and the second extension is located within the touch unit; The first extension includes a first break, which divides the first extension into two sub-extensions. The two sub-extensions are respectively connected to the two common electrodes. The two sub-extensions overlap with the corresponding two gate lines. The second extension overlaps with both corresponding gate lines; The overlap area between the first extension and the corresponding two gate lines is equal to the overlap area between the second extension and the corresponding two gate lines.

6. The array substrate according to claim 5, wherein, The orthographic projection of the first fracture on the substrate lies between the orthographic projections of the corresponding two gate lines on the substrate.

7. The array substrate according to claim 5, wherein, The ends of the two sub-extensions that are close to each other are closer to the common electrode connected to the sub-extensions than the sides of the two gate lines that are close to each other. The dimension of the portion of the sub-extension that overlaps with the corresponding gate line in the first direction is greater than the dimension of the portion of the second extension that overlaps with the corresponding gate line in the first direction; the first direction intersects the column direction.

8. The array substrate according to any one of claims 5 to 7, wherein, The longitudinal line that overlaps with the first extension is the first longitudinal line, and the first break exposes at least a portion of the first longitudinal line.

9. The array substrate according to any one of claims 5 to 7, wherein, The longitudinal line that overlaps with the first extension is the second longitudinal line, and the first break is located at the interval between the touch signal line and the common signal line of the second longitudinal line.

10. The array substrate according to claim 9, wherein, The dimension of the first break in the column direction is smaller than the spacing between the touch signal line and the common signal line of the second vertical line in the column direction.

11. The array substrate according to any one of claims 1 to 10, wherein, The array substrate further includes: A pixel electrode layer disposed between the substrate and the source / drain metal layer; A gate dielectric layer disposed between the pixel electrode layer and the source / drain metal layer; A passivation layer disposed between the source / drain metal layer and the common electrode layer; The array substrate includes a plurality of vias, each of which penetrates the passivation layer and the gate dielectric layer; the via includes a first portion and a second portion that are connected, the first portion penetrating the passivation layer and the second portion penetrating the passivation layer and the gate dielectric layer.

12. The array substrate according to claim 11, wherein, The pixel electrode layer includes multiple pixel electrodes, each pixel electrode overlapping a common electrode; each of the multiple sub-pixels includes a first transistor, a pixel electrode, and a common electrode; The common electrode layer includes a transition electrode, the source / drain metal layer includes the drain pattern of the first transistor, and the plurality of vias includes a first via. The adapter electrode is connected to the drain pattern of the first transistor through a first portion of the first via, and the adapter electrode is connected to the pixel electrode through a second portion of the first via.

13. The array substrate of claim 12, wherein, The ratio of the area of ​​the portion of the adapter electrode located within the first portion of the first via, projected onto the substrate, to the area of ​​the portion of the adapter electrode located within the first via, projected onto the substrate, is in the range of 0.4 to 0.

6.

14. The array substrate according to claim 11, wherein, The plurality of vias includes a second via; the longitudinal line is connected to the corresponding common electrode through the second via; The common electrode connected to the longitudinal line includes a first connecting block, which is connected to the longitudinal line through a first portion of the second via and contacts the substrate through a second portion of the second via.

15. The array substrate according to claim 14, wherein, The ratio of the area of ​​the portion of the first connecting block located within the first part of the second via, projected onto the substrate, to the area of ​​the portion of the first connecting block located within the second via, projected onto the substrate, is in the range of 0.2 to 0.

3.

16. The array substrate according to claim 14, wherein, The longitudinal line includes a second connecting block, which corresponds to the first connecting block. The first connecting block includes a portion that overlaps with the second connecting block and a portion that does not overlap with the second connecting block. At least a portion of the boundary of the first connecting block matches the shape of at least a portion of the boundary of the second connecting block.

17. The array substrate according to claim 16, wherein, The common electrode, which is not connected to the longitudinal line, includes a third connecting block located near the interval between two adjacent touch units, and the third connecting block has the same shape as the first connecting block.

18. A display panel comprising an array substrate as described in any one of claims 1 to 17, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.

19. A display device comprising the display panel as claimed in claim 18.

Images