Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a shielding layer (BSM) arranged on a substrate. The shielding layer (BSM) comprises multiple first shielding structures (BSM1) located in a display region (AA), and a first shielding connection structure (BSML1) and multiple shielding connection lines (BSMC) located in a bezel region (BB). The first shielding connection structure (BSML1) is located on the side of the multiple shielding connection lines (BSMC) away from the display region (AA); and the multiple first shielding structures (BSM1) are connected to the first shielding connection structure (BSML1) by means of the multiple shielding connection lines (BSMC). Multiple connection through holes (K0) and multiple bezel signal lines (BBL) are provided in the bezel region (BB). Multiple operating signal lines (AAL) are provided in the display region (AA). The bezel signal lines (BBL) are connected to the operating signal lines (AAL) by means of the connection through holes (K0). The first shielding connection structure (BSML1) and the multiple shielding connection lines (BSMC) do not overlap the multiple connection through holes (K0).

Description

Display substrate and its preparation method, display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, embodiments of this disclosure provide a display substrate, including a substrate and a shielding layer located on one side of the substrate. The substrate includes a display area and a border area surrounding the display area. The shielding layer includes a plurality of first shielding structures located in the display area, a first shielding connection structure located in the border area, and a plurality of shielding connection lines. The first shielding connection structures are located on the side of the plurality of shielding connection lines away from the display area, and the plurality of first shielding structures are connected to the first shielding connection structure through the plurality of shielding connection lines.

[0005] The frame area is provided with multiple connection vias and multiple frame signal lines, and the display area is provided with multiple working signal lines. At least some of the connection vias are configured to electrically connect at least some of the frame signal lines with at least some of the working signal lines. In a direction perpendicular to the plane of the substrate, the multiple frame signal lines, the multiple working signal lines, and the multiple connection vias are located on the side of the shielding layer away from the substrate. The orthographic projections of the first shielding connection structure and the multiple shielding connection lines on the substrate do not overlap with the orthographic projections of the multiple connection vias on the substrate.

[0006] In an exemplary embodiment, the at least part of the working signal lines include a plurality of first signal lines, and the at least part of the border signal lines include at least one first signal providing line. The first signal lines correspond to one of the first signal providing lines. In a direction perpendicular to the plane of the substrate, the plurality of first signal lines and the first signal providing line are located on the side of the shielding layer away from the substrate. The first signal lines and the first signal providing line are located in different conductive layers.

[0007] The plurality of connection vias includes a plurality of signal access vias, each of which corresponds one-to-one with the plurality of first signal lines. The plurality of signal access vias are located on the side of the first shielding connection structure closer to the display area, and the first signal lines are provided with linear connections to the corresponding first signals through the corresponding signal access vias.

[0008] In an exemplary embodiment, the frame signal line further includes a first power signal supply line, a plurality of first power connection structures, and a plurality of first power connection lines. The frame area also includes a plurality of multiplexing circuits. The first power signal supply line is located on the side of the plurality of multiplexing circuits away from the display area, and the plurality of first power connection lines are located on the side of the plurality of multiplexing circuits close to the display area. The plurality of first power connection lines are electrically connected to the first power signal supply line through the plurality of first power connection structures. In the direction in which the plurality of multiplexing circuits are arranged, the first power connection structure is located between two adjacent multiplexing circuits.

[0009] The plurality of connection vias includes a first power connection via, at least a portion of the first power connection structure corresponds one-to-one with at least a portion of the first power connection line, and the at least a portion of the first power connection structure is located on a different conductive layer from the first power signal supply line and the at least a portion of the first power connection line. The at least a portion of the first power connection structure is electrically connected to the first power signal supply line and the corresponding first power connection line through the first power connection via.

[0010] In an exemplary embodiment, the plurality of first power connection lines include a first type of first power connection line, the frame region is provided with a plurality of parallel connection vias, the frame region includes a first frame region, at least one parallel connection via is located in the first frame region, in a second direction, the first frame region is located on one side of the display area, at least a portion of the structure of the first shielding connection structure, the first type of first power connection line, and at least a portion of the multiplexing circuits in the plurality of multiplexing circuits are located in the first frame region, in the first frame region, at least a portion of the structure of the first shielding connection structure is located on the side of the plurality of multiplexing circuits closer to the display area, at least a portion of the structure of the first shielding connection structure at least partially overlaps with the orthographic projection of the first type of first power connection line on the substrate, and is electrically connected through the at least one parallel connection via;

[0011] The first signal line extends along the second direction, and the signal access via is located at one end of the corresponding first signal line near the first frame area. The at least one parallel connection via and the orthographic projection of the plurality of signal access vias on the substrate do not overlap.

[0012] In an exemplary embodiment, the plurality of first power connection structures include a plurality of first type first power connection structures, and at least a portion of the plurality of first type first power connection structures and the first power signal providing line are located in the first border area;

[0013] In the first frame region: the at least one parallel connection via includes a plurality of first vias, the plurality of signal access vias includes a plurality of second vias, the plurality of second vias are located on the side of the plurality of first vias away from the multiplexing circuit, at least a portion of the plurality of multiplexing circuits are arranged along a first direction, the plurality of first-type first power connection structures extend along a second direction and are spaced apart along the first direction, at least a portion of the structure of the first power signal supply line, the first-type first power connection line and the first shielding connection structure extend along the first direction; in the first direction, at least one first via and at least one second via are provided between two adjacent first-type first power connection structures, located on the same side of one of the first-type first power connection structures, the distances between the first via and the second via and the first-type first power connection structure are different, and in a direction parallel to the plane of the substrate, the first direction intersects the second direction.

[0014] In an exemplary embodiment, in the first border area, in the first direction, at least some of the multiplexing circuits among the plurality of multiplexing circuits have a first type of first power supply connection structure between two adjacent multiplexing circuits.

[0015] In the first border area: between two adjacent first-type first power connection structures, there are two first vias and two second vias. The two first vias and the two second vias located between two adjacent first-type first power connection structures form a first base unit. In the same first base unit, the first vias and the second vias are arranged alternately along the first direction. Two adjacent first base units are symmetrical with respect to the first-type first power connection structure located between the two first base units. Two adjacent first base units form a second base unit. Multiple second base units are arranged periodically along the first direction. Two adjacent second base units are symmetrical with respect to the first-type first power connection structure located between the two second base units.

[0016] In an exemplary embodiment, the display area is provided with a plurality of sub-pixel columns, which are arranged along the first direction. In a direction perpendicular to the plane of the substrate, the plurality of sub-pixel columns are located on the side of the shielding layer away from the substrate.

[0017] In the first direction: in the same second base unit, the distance between the two middle first vias is less than the size of a sub-pixel column; the distance between the two nearest first vias in two adjacent second base units is greater than the size of a sub-pixel column.

[0018] In an exemplary embodiment, the at least part of the frame signal line further includes a plurality of second power connection structures, the first signal providing line includes a second power signal providing line, and at least part of the plurality of second power connection structures and at least part of the second power signal providing line are located in the first frame region;

[0019] The plurality of first signal lines include a plurality of second power lines and a plurality of initial signal lines. The second power lines and the initial signal lines are arranged alternately along the first direction. Two second vias located in the same first base unit correspond to one second power line and one initial signal line, respectively.

[0020] In the first border area: the second power signal supply line is located on the side of the plurality of multiplexer circuits away from the display area; the plurality of second power connection structures correspond one-to-one with the plurality of second power lines; the second power lines are electrically connected to the second power signal supply line through the corresponding second power connection structure; at least a portion of the structure of the second power signal supply line and at least a portion of the structure of the first power signal supply line at least partially overlap on the orthographic projection of the first power signal supply line onto the substrate; in a direction perpendicular to the plane of the substrate, at least a portion of the structure of the second power connection structure and at least a portion of the structure of the second power signal supply line are located on the side of the first power signal supply line away from the substrate.

[0021] In an exemplary embodiment, the plurality of connection vias further includes a plurality of third vias and a plurality of fourth vias located in the first frame region, wherein in the first frame region, the plurality of third vias and the plurality of fourth vias are located on the side of the plurality of first vias away from the display area;

[0022] In the first border area: a second power connection structure is provided between two adjacent first-type first power connection structures. The second power connection structure includes a first structural part, a second structural part, and a third structural part. The main bodies of the first structural part and the third structural part extend along the second direction, and the second structural part extends along the first direction. In the first direction, the third structural part is located between two adjacent multiplexer circuits, and a multiplexer circuit is provided between two adjacent third structural parts. In the second direction, the second structural part is located between the multiplexer circuit and the first-type first power connection line.

[0023] The second structural part corresponds to one of the third vias and one of the fourth vias. In the same second power connection structure: one end of the second structural part is electrically connected to the end of the first structural part away from the display area through the corresponding third via, and the other end is electrically connected to the end of the third structural part near the display area through the corresponding fourth via. The end of the first structural part near the display area is electrically connected to the corresponding second power line through the corresponding second via. The end of the third structural part away from the display area is connected to the second power signal supply line.

[0024] In an exemplary embodiment, the at least some of the working signal lines further include a plurality of data signal lines, the main bodies of which extend along the second direction and are spaced apart along the first direction; the data signal lines extend to the first border area and are electrically connected to one of the multiplexing circuits; the same multiplexing circuit is electrically connected to at least two of the data signal lines.

[0025] In a direction perpendicular to the plane of the substrate, the second structural part and the first power signal supply line are disposed on the same layer. The first structural part, the third structural part and the data signal line are located on the side of the second structural part away from the substrate. In the first direction, between two adjacent first-type first power connection structures, at least a portion of the data signal lines are located between the two ends of the same second structural part. The data signal lines located between the two ends of the same second structural part at least partially overlap with the orthographic projection of the second structural part on the substrate.

[0026] In an exemplary embodiment, the border area further includes a first corner area and a fourth corner area. In a first direction, the first corner area and the fourth corner area are located on both sides of the first border area. In a second direction, the first corner area and the fourth corner area are located on the same side of the display area as the first border area. The first power signal supply line is located in the first border area and extends to the first corner area and the second corner area.

[0027] The at least part of the first power connection structure includes a plurality of second type first power connection structures, and the at least part of the first power connection line includes a plurality of second type first power connection lines. The plurality of second type first power connection structures correspond one-to-one with the plurality of second type first power connection lines. The second type first power connection structures and the second type first power connection lines are located in the first corner area and the fourth corner area.

[0028] The plurality of first power connection vias includes a plurality of first-type first power connection vias and a plurality of second-type first power connection vias. The first-type first power connection vias correspond to one of the second-type first power connection structures, and the second-type first power connection vias correspond to one of the second-type first power lines and one of the second-type first power connection structures. In a direction perpendicular to the plane of the substrate, the first power signal supply line and the first power connection line are located on the side of the second-type first power connection structure away from the shielding layer. The second-type first power connection structure is electrically connected to the first power signal supply line through the corresponding first-type first power connection via and electrically connected to the corresponding second-type first power connection line through the corresponding second-type first power connection via.

[0029] In an exemplary embodiment, the at least part of the frame signal lines further includes a plurality of second power connection structures, the plurality of connection vias further includes a plurality of second power connection vias, the first signal providing line includes a second power signal providing line, the plurality of first signal lines include a plurality of second power lines, the plurality of second power lines correspond one-to-one with the plurality of second power connection structures and the plurality of second power connection vias, the second power connection structure is connected to the corresponding second power line through the corresponding signal access via, and is electrically connected to the second power signal providing line through the corresponding second power connection via;

[0030] In the first corner region and the fourth corner region: the first shielding connection structure is located on the side of the plurality of multiplexer circuits away from the display area, the second power signal supply line is located on the side of the plurality of multiplexer circuits close to the display area, the edge of the first power signal supply line close to the display area and the second power signal supply line are stepped, the plurality of second type first power connection structures and the plurality of second type first power connection lines are arranged in a stepped manner along the extension direction of their respective corner regions; in the direction perpendicular to the plane of the base, the second power connection structure and the second power signal supply line are located on the side of the second power line and the first power connection line away from the base.

[0031] In an exemplary embodiment, the first corner region and the fourth corner region are arc-shaped structures, and the center of the circle containing the arc-shaped structure is located on the side of the arc-shaped structure closer to the display area. In the first corner region and the fourth corner region, the shape of the first shielding connection structure is consistent with the shape of the corner region in which it is located, and the first shielding connection structure at least partially overlaps with the orthographic projection of the first power signal supply line on the substrate.

[0032] In an exemplary embodiment, the border area further includes a second border area, a third border area, and a fourth border area. In the first direction, the third border area and the fourth border area are located on both sides of the display area. In the second direction, the first border area and the second border area are located on both sides of the display area. The first border area and the third border area are connected through the first corner area, and the first border area and the fourth border area are connected through the fourth corner area.

[0033] At least some of the multiplexer circuits are located in the first corner region and the fourth corner region. In the first corner region and the fourth corner region: the at least some multiplexer circuits are arranged in a stepped manner along the extension direction of the corner region where they are located. Multiple shielding connection lines are interconnected to form multiple first openings. The multiplexer circuits are located in the corresponding first openings. In at least some of the multiple first openings, each first opening accommodates at least one multiplexer circuit. In the first direction, the size of the first opening is the same as the size of m multiplexer circuits. In the second direction, the size of the first opening is the same as the size of n multiplexer circuits, where m and n are positive integers greater than or equal to 1.

[0034] In an exemplary embodiment, the plurality of occlusion connection lines include a plurality of first occlusion connection lines, a plurality of second occlusion connection lines, and a plurality of third occlusion connection lines located in the first corner region and the fourth corner region;

[0035] In the first corner region and the fourth corner region: the plurality of first blocking connecting lines and the plurality of second blocking connecting lines extend along the first direction and are arranged in a stepped manner along the extension direction of the corner region in which they are located; the plurality of third blocking connecting lines extend along the second direction and are arranged in a stepped manner along the extension direction of the corner region in which they are located; at least a portion of the structure of the third blocking connecting line is located between adjacent first blocking connecting lines and second blocking connecting lines; the first opening is formed by two adjacent third blocking connecting lines in the first direction and adjacent first blocking connecting lines and second blocking connecting lines in the second direction.

[0036] In an exemplary embodiment, in the first corner region and the fourth corner region, two adjacent first blocking connection lines and a neighboring third blocking connection line and two adjacent first blocking structures surround to form a second opening, and two adjacent second blocking connection lines and a first blocking connection structure and a neighboring third blocking connection line surround to form a third opening. A plurality of first openings, a plurality of second openings and a plurality of third openings are arranged in a stepped manner along the corner region where they are located. The plurality of third openings are located on the side of the plurality of first openings away from the display area, and the plurality of second openings are located on the side of the plurality of first openings close to the display area.

[0037] In an exemplary embodiment, the plurality of first blocking structures form multiple rows. In the first corner area and the fourth corner area, the side of the first blocking connecting line closer to the display area is connected to one row of blocking structures. In the second direction, the distance between two adjacent first blocking connecting lines is the same as the size of a first blocking structure, and the distance between two adjacent second blocking connecting lines is the same as the size of a first blocking structure. The side of the third blocking connecting line closer to the display area is connected to two adjacent rows of first blocking connecting structures through two first blocking connecting lines, and the side farther from the display area is connected to the first blocking connecting structure through two second blocking connecting lines.

[0038] In an exemplary embodiment, the first opening is rectangular in shape. In the first direction, the distance between two adjacent third blocking connection lines is the same as the size of m multiplex circuits, and the two adjacent third blocking connection lines form a pair of opposite sides of the rectangle. In the second direction, the distance between the first blocking connection line and one of the second blocking connection lines in the direction away from the display area is the same as the size of n multiplex circuits, and the first blocking connection line and the one of the second blocking connection lines form another pair of opposite sides of the rectangle.

[0039] In an exemplary embodiment, n is 1, and m is greater than or equal to 1. In the first corner region and the fourth corner region, the value of n is greater when it is closer to the first border region than when it is farther away from the first border region.

[0040] In an exemplary embodiment, in the first border area, a plurality of first spacings are formed between a plurality of occlusion connecting lines. The first spacing is the distance between two adjacent occlusion connecting lines along the first direction. In the first direction, at least one of the first spacings is greater than the size of the first opening, and at least one of the first spacings is less than the size of the first opening.

[0041] In an exemplary embodiment, the shielding layer further includes a second shielding connection structure and a plurality of second shielding structure groups. The second shielding connection structure and the plurality of second shielding structure groups are located in at least one of the third border area and the fourth border area. The plurality of second shielding structure groups located in the same border area are arranged along the direction from the display area to the border area where they are located, and the plurality of second shielding structures in the same second shielding structure group are arranged along the extension direction of the border area where they are located.

[0042] The extension direction of the second blocking connection structure is consistent with the extension direction of the border area where it is located. In the same border area, in the direction from the display area to the border area, the second blocking connection structure is located between two adjacent second blocking structure groups, and multiple second blocking structures in two adjacent second blocking structure groups are connected to their adjacent second blocking connection structures.

[0043] In an exemplary embodiment, the shielding layer further includes a third shielding connection structure, wherein at least a portion of the first shielding connection structure and the third shielding connection structure are located in at least one of the third border region and the fourth border region, the extension direction of the third shielding connection structure is consistent with the extension direction of the border region in which it is located, and in the same border region, in the direction from the display area to the border region, the third shielding connection structure is located on the side of the plurality of second shielding structure groups closer to the display area, and the third shielding connection structure is connected to a plurality of second shielding structures in an adjacent second shielding structure group;

[0044] In at least one of the third and fourth border regions, in a first direction, the size of the third occlusion connection structure is larger than the size of the second occlusion connection structure, and the size of the second occlusion connection structure is larger than the size of the first occlusion connection structure.

[0045] In an exemplary embodiment, the occlusion layer further includes a plurality of fourth occlusion connection structures. The plurality of fourth occlusion connection structures are located in at least one of the third border region and the fourth border region. In the same border region, the plurality of fourth occlusion connection structures are located between the first occlusion connection structure and the third occlusion connection structure. The plurality of fourth occlusion connection structures are arranged at intervals along the extension direction of their respective border regions. The main body of the fourth occlusion connection structure extends along the first direction, with one end connected to the third occlusion connection structure in its respective border region and the other end connected to the first occlusion connection structure.

[0046] In an exemplary embodiment, the display substrate further includes a plurality of gate driving circuit groups, which are located in at least one of the third and fourth frame regions. The plurality of gate driving circuit groups are arranged along the direction from the display area to the frame region in which they are located. In the same frame region, at least a portion of the gate driving circuit groups correspond one-to-one with the plurality of second shielding structure groups. The plurality of gate driving circuits in the same gate driving circuit group are arranged along the extension direction of the frame region in which they are located. The plurality of second shielding structures in the second shielding structure group correspond one-to-one with the plurality of gate driving circuits in the corresponding gate driving circuit group. The orthographic projections of the second shielding structure and the corresponding gate driving circuit on the substrate at least partially overlap.

[0047] In an exemplary embodiment, the gate driving circuit includes a plurality of transistors, and the second shielding structure at least partially overlaps with the orthographic projection of the channel of at least one transistor in the corresponding gate driving circuit onto the substrate.

[0048] In an exemplary embodiment, the plurality of occlusion connection lines include a plurality of fourth occlusion connection lines. The first occlusion connection structure is a ring structure surrounding the display area. The plurality of first occlusion structures form multiple rows and columns. The plurality of first occlusion structures in the same row are interconnected, and the plurality of first occlusion structures in the same column are interconnected. The plurality of fourth occlusion connection lines extend along a first direction X and are arranged at intervals along the extension direction of the border area in which they are located. In the first direction, the plurality of fourth occlusion connection lines are located on both sides of the plurality of first occlusion structures and on the side of the first occlusion connection structure closer to the display area. The plurality of first occlusion structures are connected to the first occlusion connection structures on both sides of them through the plurality of fourth occlusion connection structures on both sides of them.

[0049] In at least one row of the multiple rows of first occlusion structures, in a first direction, each row of occlusion structures is connected to the first occlusion connection structure via a fourth occlusion connection line located on both sides of the row of first occlusion structures.

[0050] In an exemplary embodiment, the display area includes a plurality of sub-pixels, the plurality of first occlusion structures correspond one-to-one with the plurality of sub-pixels, at least one of the sub-pixels includes a plurality of transistors, and the first occlusion structure and the orthographic projection of the channel region of at least one transistor in the corresponding sub-pixel on the substrate at least partially overlap.

[0051] Secondly, embodiments of this disclosure also provide a display device, including the display substrate described in any of the above embodiments.

[0052] Thirdly, embodiments of this disclosure also provide a method for preparing a display substrate, comprising:

[0053] A shielding layer is formed on one side of a substrate, the substrate including a display area and a border area surrounding the display area, the shielding layer including a plurality of first shielding structures located in the display area, a first shielding connection structure located in the border area and a plurality of shielding connection lines, the first shielding connection structures being located on the side of the plurality of shielding connection lines away from the display area, and the plurality of first shielding structures being connected to the first shielding connection structure through the plurality of shielding connection lines;

[0054] Multiple connection vias, multiple border signal lines, and multiple working signal lines are formed on the side of the shielding layer away from the substrate layer. The multiple connection vias and the multiple border signal lines are located in the border area, and the multiple working signal lines are located in the display area. The orthographic projection of the first shielding connection structure and the multiple shielding connection lines on the substrate does not overlap with the orthographic projection of the multiple connection vias on the substrate.

[0055] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0056] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0057] Figure 1 is a schematic diagram of a display device;

[0058] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0059] Figure 3 is a schematic cross-sectional view of a display substrate;

[0060] Figure 4a is an equivalent circuit diagram of a pixel driving circuit;

[0061] Figure 4b is a timing diagram of a pixel driving circuit.

[0062] Figure 5a shows a planar schematic diagram of a display substrate;

[0063] Figure 5b shows a cross-sectional structure along position M1-M1 in Figure 5a;

[0064] Figure 6a shows a schematic diagram of a planar structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0065] Figure 6b is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0066] Figure 7a shows an enlarged structural schematic diagram of position R1 in Figure 6b;

[0067] Figure 7b shows an enlarged structural diagram of the R2 position in Figure 6b;

[0068] Figure 7c shows an enlarged structural diagram of the R8 position in Figure 7b;

[0069] Figure 8a shows an enlarged structural diagram of the R3 position in Figure 6b;

[0070] Figure 8b shows an enlarged structural diagram of the R4 position in Figure 6b;

[0071] Figure 9a shows an enlarged schematic diagram of a shielding layer at position R5 in Figure 6a;

[0072] Figure 9b shows an enlarged schematic diagram of a shielding layer at position R5 in Figure 6b;

[0073] Figure 9c shows an enlarged schematic diagram of a shielding layer at position R6 in Figure 6b;

[0074] Figure 10a shows an enlarged schematic diagram of a shielding layer at position R7 in Figures 6a and 6b.

[0075] Figure 10b shows an enlarged schematic diagram of a shielding layer at position R7 in Figures 6a and 6b.

[0076] Figure 10c shows an enlarged schematic diagram of a shielding layer at position R7 in Figures 6a and 6b.

[0077] Figure 11 is a schematic diagram of a display device provided by an exemplary embodiment of the present disclosure. Detailed Implementation

[0078] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0079] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0080] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0081] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0082] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0083] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0084] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0085] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0086] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0087] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0088] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0089] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0090] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit connected to the circuit unit. The circuit unit may include a pixel driving circuit, which is connected to the scan signal lines, the data signal lines, and the light-emitting signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0091] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a circuit unit and a light-emitting unit. The circuit unit may include a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0092] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular pattern.

[0093] In another exemplary embodiment, the pixel unit P may include four sub-pixels, which may be arranged in a horizontal, vertical, diamond, or square manner, etc., and this disclosure does not limit the arrangement.

[0094] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels. As shown in Figure 3, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0095] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 (which can be referred to as the circuit structure layer) for each sub-pixel can include multiple circuit units. Each circuit unit can include a pixel driving circuit composed of multiple transistors and a storage capacitor. Figure 3 illustrates a pixel driving circuit comprising only one driving transistor and one storage capacitor. The light-emitting structure layer 103 for each sub-pixel can include multiple light-emitting units. Each light-emitting unit can include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the drain electrode of the driving transistor through a via. The organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, while the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer 103.

[0096] In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer, electron injection layer, hole transport layer, electron transport layer, hole blocking layer, and electron blocking layer of all light-emitting units may be a common layer connected together, and the light-emitting layers of adjacent light-emitting units may have a small amount of overlap, or may be isolated.

[0097] Figure 4a is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 4a, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to nine signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, light emission signal line E, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, and second power supply line VSS).

[0098] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C. The third node N3 is connected to the second terminals of the second transistor T2, the second terminals of the third transistor T3, and the first terminal of the sixth transistor T6. The fourth node N4 is connected to the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7.

[0099] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0100] The control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first terminal of the first transistor T1 is connected to the initial signal line Vinit1, and the second terminal of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the first reset control line Reset1, the first transistor T1 transmits the initial voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0101] The control electrode of the second transistor T2 is connected to the scan signal line Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the scan signal line Gate, the second transistor T2 causes the control electrode of the third transistor T3 to connect to its second electrode.

[0102] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0103] The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scan transistor, etc. When a conduction-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0104] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device EL to emit light.

[0105] The control electrode of the seventh transistor T7 is connected to the second reset control line Reset2, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device EL. When the on-level scan signal is applied to the second reset control line Reset2, the seventh transistor T7 transmits the initial voltage to the first electrode of the light-emitting device EL, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device EL.

[0106] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0107] In an exemplary embodiment, the second electrode of the light-emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0108] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0109] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0110] In an exemplary embodiment, taking an OLED where all seven transistors in the pixel driving circuit of Figure 4a are P-type transistors as an example, as shown in Figure 4b, the operation of the pixel driving circuit may include:

[0111] The first stage, A1, is called the reset stage. The signal on the first reset control line, Reset1, is low, while the signals on the scan signal line, Gate, the second reset control line, Reset2, and the light-emitting signal line, E, are high. The low signal on Reset1 turns on the first transistor, T1, and the initial signal line, INIT, is supplied to the second node, N2, to initialize the storage capacitor C and clear the existing data voltage. The high signals on the scan signal line, Gate, Reset2, and E turn off the second transistor, T2, the fourth transistor, T4, the fifth transistor, T5, the sixth transistor, T6, and the seventh transistor, T7. During this stage, the OLED does not emit light.

[0112] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the signals on the scan signal line Gate and the second reset control line Reset2 are low, while the signals on the first reset control line Reset1 and the light emission signal line E are high. The data signal line D outputs a data voltage. Because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signals on the scan signal line Gate and the second reset control line Reset2 turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal on the first reset control line Reset1 is a high-level signal, causing the first transistor T1 to turn off. The signal on the light emission signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0113] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line E is at a low level, while the scan signal line Gate, the second reset control line Reset2, and the first reset control line Reset1 are at high levels. The low level of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0114] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vd - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0115] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0116] To better meet people's needs for various functions and a better screen experience (such as displays with ultra-high screen-to-body ratios), narrow bezel displays have gradually become the mainstream form of display devices. However, in some implementations, the layout of some signal lines and circuits within the display panel makes it impossible to achieve a narrow bezel.

[0117] To maximize the display area and achieve an extremely narrow bezel in the display screen, a curved edge design can be used on large-size display panels. This means the GOA rotates along with the pixel circuit layout, as shown in Figure 5a, a schematic diagram of a display device. The display device may include a display panel, which may include a display substrate. The display substrate may include a display area AA and a bezel area BB surrounding the display area. The display area AA may include at least one corner area, and the bezel area BB may include at least one corner area. The at least one corner area of ​​the display area AA corresponds to the at least one corner area of ​​the bezel area BB. Multiple sub-pixels Pxij are located in the display area AA. At least some of the sub-pixels Px are located in the at least one corner area of ​​the display area AA and are arranged in a stepped manner. Multiple gate driving circuits 10 can be disposed in the at least one corner area of ​​the bezel area BB. The gate driving circuits 10 can drive the array substrate row (Gate Driver on) The array (abbreviated as GOA) circuit has a gate drive circuit configured to provide a gate drive signal to the sub-pixel Pxij in the display area AA (for example, the gate drive signal can be a signal provided to the scan signal line Gate, the first reset control line Reset1, the second reset control line Reset2, and the light emission signal line E in Figure 4a).

[0118] In some exemplary embodiments, as shown in FIG5a, the border area BB may further include: a first border area B1 and a second border area B2 located on both sides of the display area AA along the second direction Y, and a third border area B3 and a fourth border area B4 located on both sides of the display area AA along the first direction X; at least one corner area of ​​the border area BB may include: a first corner area C1 connecting the first border area B1 and the third border area B3, a second corner area C2 connecting the third border area B3 and the second border area B2, a third corner area C3 connecting the second border area B2 and the fourth border area B4, and a fourth corner area C4 connecting the fourth border area B4 and the first border area B1.

[0119] In some exemplary embodiments, as shown in FIG5a, a plurality of gate drive circuits 10 may be located in the third border region B3, the fourth border region B4, the first corner region C1, the second corner region C2, the third corner region C3, and the fourth corner region C4.

[0120] Figure 5b is a schematic cross-sectional view of sub-pixel Pxij along the M1-M1 position in the display area AA of the display substrate shown in Figure 5a. Figure 5b illustrates the structure of a single sub-pixel in the display area as an example. In this example, multiple transistors in the pixel circuit are of the same type; for example, the multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors (LTPS) or all be oxide thin-film transistors (OPS), as shown in Figure 5b. In other examples, the multiple transistors in the pixel circuit can be both LPS and OPS. Furthermore, this example illustrates the integration of a mutual capacitance touch structure into the display substrate to form an FMLOC structure.

[0121] In some examples, as shown in Figure 5b, in the direction Z perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 100, and a circuit structure layer 200, a light-emitting structure layer 300, an encapsulation structure layer 400, a touch structure layer 500, and a color filter layer 600 sequentially disposed on the substrate 100. The display structure layer may include at least the circuit structure layer 200 and the light-emitting structure layer 300. The circuit structure layer 200 may include at least pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 300 may include at least light-emitting elements for multiple sub-pixels.

[0122] In some examples, Figure 5b illustrates an example where each sub-pixel includes a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 200 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 202 may be disposed between the first gate metal layer and the second gate metal layer; an interlayer insulating layer 203 may be disposed between the second gate metal layer and the first source-drain metal layer; a passivation layer 204 and a first planarization layer 205 may be disposed between the first source-drain metal layer and the second source-drain metal layer; a second planarization layer 206 may be disposed between the second source-drain metal layer and the third source-drain metal layer; and a third planarization layer 207 may be disposed on the side of the third source-drain metal layer away from the substrate 100. The first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 may be inorganic insulating layers, while the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 may be organic insulating layers. However, this embodiment is not limited to these limitations. In some examples, a buffer layer 1501 may be disposed on the side of the semiconductor layer near the substrate. This buffer layer can prevent harmful substances in the substrate from penetrating the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) may be disposed on the side of the buffer layer 1501 near the substrate. The shielding structure BSM0 in the bottom shielding metal layer (which may be called a shielding layer) can be configured to at least partially cover the active layer of the thin-film transistor in the pixel circuit to prevent external light from affecting the performance of the thin-film transistor. In other examples, a passivation layer may be omitted between the first source-drain metal layer and the second source-drain metal layer, and only a first planarization layer may be disposed between the first source-drain metal layer and the second source-drain metal layer.

[0123] In some examples, as shown in FIG5b, the semiconductor layer of the display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 100 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 100. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 203 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 204 and the first planarization layer 205. The third source-drain metal layer may include at least a second transition electrode 232. The second transition electrode 232 can be electrically connected to the first transition electrode 231 located in the second source-drain metal layer through a fourth pixel via formed by the second planarization layer 206. The second transition electrode 232 can be electrically connected to the first electrode 301 (e.g., anode) of the light-emitting element through a fifth pixel via formed by the third planarization layer 207. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 231 and the second transition electrode 232.

[0124] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer or the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer or the third source-drain metal layer; and the high-potential power lines of the display area may be located, for example, in at least one of the second and third source-drain metal layers. This embodiment is not limited in this respect. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging too many traces in a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0125] In some examples, as shown in Figure 5b, the light-emitting structure layer 300 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on a third planarization layer 207 and electrically connected to a second transition electrode 232 through a fifth pixel via formed in the third planarization layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planarization layer 207, and the pixel definition layer 304 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 can be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer can also be set on the side of the pixel definition layer 304 away from the substrate 100. The isolation pillar layer can include multiple isolation pillars (PS).

[0126] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0127] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0128] In some examples, as shown in Figure 5b, the encapsulation structure layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked in the direction perpendicular to the substrate. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be made of organic materials and may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 402 may be made of organic materials, for example, a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 401 and the third encapsulation layer 403. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have intruded into the interior. However, this embodiment is not limited in this respect. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0129] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0130] In some examples, as shown in FIG5b, the touch structure layer 500 of the display area may include, in the direction perpendicular to the substrate, a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512 arranged sequentially. The touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, such as SiNx layers. For example, the first touch conductive layer 511 may include multiple first touch electrodes, multiple second touch electrodes, and multiple first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure interconnected. The second touch conductive layer 512 may include multiple second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited in this respect.

[0131] In some examples, the first and second touch electrodes may be rhomboid in shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first and second touch electrodes may be any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons, and other polygons, which are not limited to the embodiments disclosed herein.

[0132] In some examples, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by multiple interwoven metal wires. The metal mesh can include multiple mesh patterns, and the mesh pattern can be a polygon composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0133] In some examples, as shown in FIG5b, in the direction perpendicular to the substrate, the color filter on encapsulation (COE) 600 may include an insulating layer 601, a color filter layer, and an overcoat 602 disposed sequentially, wherein the color filter layer includes a black matrix 610 and color filter units 611 disposed between the black matrix 610, and the color filter units 611 may be, for example, red filter units, green filter units, or blue filter units. With the development of OLED display technology, the requirements for the image quality of display products are becoming increasingly stringent. In the display area AA, at least some transistors are shielded by a shielding structure located in the shielding layer BSM, which can improve the image display effect. The shielding layer BSM typically includes multiple shielding structures BSM0 located in the display area AA, multiple shielding connection lines located in the bezel area BB, and a shielding ring connection structure. The shielding structure BSM0 in the display area AA typically overlaps with the channel of at least one transistor in a sub-pixel. The shielding ring connection structure typically forms a closed structure around the multiple shielding structures BSM0. The multiple shielding structures BSM0 can be connected to the shielding ring connection structure through multiple shielding connection lines. In some embodiments, the shielding connection lines and the shielding ring connection structure located in the bezel area BB often connect to the connection vias located in the bezel area BB. The shielding layer BSM is typically electrically connected to constant voltage signal lines. The overlap between the shielding layer BSM and the connection vias is prone to electrostatic discharge (ESD) damage (i.e., BSM ESD damage), leading to poor display and reduced display effect.

[0134] An exemplary embodiment of this disclosure provides a display substrate, which may include a substrate and a shielding layer located on one side of the substrate. The substrate includes a display area and a border area surrounding the display area. The shielding layer includes a plurality of first shielding structures located in the display area, a first shielding connection structure located in the border area, and a plurality of shielding connection lines. The first shielding connection structures are located on the side of the plurality of shielding connection lines away from the display area, and the plurality of first shielding structures are connected to the first shielding connection structure through the plurality of shielding connection lines.

[0135] The frame area is provided with multiple connection vias and multiple frame signal lines, and the display area is provided with multiple working signal lines. At least some of the connection vias are configured to electrically connect at least some of the frame signal lines to at least some of the working signal lines. In a direction perpendicular to the plane of the substrate, the multiple frame signal lines, the multiple working signal lines, and the multiple connection vias are located on the side of the shielding layer away from the substrate. The orthographic projections of the first shielding connection structure and the multiple shielding connection lines on the substrate do not overlap with the orthographic projections of the multiple connection vias on the substrate.

[0136] The display substrate provided in this embodiment has a plurality of connection vias and a plurality of frame signal lines in the frame area and a plurality of working signal lines in the display area. At least some of the connection vias are configured to electrically connect at least some of the frame signal lines to at least some of the working signal lines. The orthographic projection of the first shielding connection structure and the plurality of shielding connection lines on the substrate does not overlap with the orthographic projection of the plurality of connection vias on the substrate. This can prevent the shielding layer from being damaged by electrostatic discharge due to overlapping with the connection vias, thereby reducing display defects and improving display effect.

[0137] As shown in Figures 6a to 7b, Figures 6a and 6b are schematic diagrams of the planar structure of the display substrate, Figure 7a shows an enlarged schematic diagram of the structure at position R1 in Figure 6b, and Figure 7b shows an enlarged schematic diagram of the structure at position R2 in Figure 6b. The display substrate may include a substrate and a shielding layer BSM located on one side of the substrate. The substrate may include a display area AA and a border area BB located around the display area AA. The shielding layer BSM may include a plurality of first shielding structures BSM1 located in the display area AA, a first shielding connection structure BSML1 located in the border area BB, and a plurality of shielding connection lines BSMC. ​​The first shielding connection structure BSML1 may be located on the side of the plurality of shielding connection lines BSMC away from the display area AA. The plurality of first shielding structures BSM1 may be connected to the first shielding connection structure BSML1 through the plurality of shielding connection lines BSMC.

[0138] The border area BB may have multiple connecting vias K0 and multiple border signal lines BBL, and the display area AA may have multiple working signal lines AAL. At least some of the connecting vias K0 are configured to electrically connect at least some of the border signal lines BBL and at least some of the working signal lines AAL. In the direction perpendicular to the plane of the substrate, the multiple border signal lines BBL, the multiple working signal lines AAL and the multiple connecting vias K0 are located on the side of the shielding layer BSM away from the substrate. The orthographic projection of the first shielding connection structure BSML1 and the multiple shielding connection lines BSMC on the substrate does not overlap with the orthographic projection of the multiple connecting vias K0 on the substrate.

[0139] In an exemplary embodiment, in the border area BB, the orthographic projections of the first shielding connection structure BSML1 and the multiple shielding connection lines BSMC on the substrate do not overlap with the orthographic projections of the multiple connection vias K0 on the substrate. This can prevent the shielding layer BSM from being damaged by electrostatic discharge due to overlapping with the connection vias K0, thereby reducing display defects and improving display effect.

[0140] In an exemplary embodiment, as shown in Figures 7a to 8b, Figure 7c is an enlarged schematic diagram of position R8 in Figure 7b, Figure 8a is an enlarged structural schematic diagram of position R3 in Figure 6b, and Figure 8b is an enlarged structural schematic diagram of position R4 in Figure 6b. The at least part of the working signal line AAL may include multiple first signal lines 30, and the at least part of the border signal line BBL may include at least one first signal providing line LT. The first signal line 30 corresponds to one of the first signal providing lines LT. In the direction perpendicular to the plane of the substrate, the multiple first signal lines 30 and the first signal providing line LT are located on the side of the shielding layer away from the substrate. The first signal lines 30 and the first signal providing line LT are located in different conductive layers.

[0141] Multiple connection vias K0 may include multiple signal access vias KR, each corresponding to a multiple first signal line 30. The multiple signal access vias KR are located on the side of the first shielding connection structure BSML1 near the display area AA (the multiple signal access vias KR may be located on the side of the corresponding first signal line 30 near the bezel area BB). The first signal line 30 can be electrically connected to the corresponding first signal providing line LT through the corresponding signal access via KR, thereby connecting the signal of the first signal providing line LT located in the bezel area BB to the corresponding first signal line 30.

[0142] In an exemplary embodiment, as shown in Figures 7a and 7b, the frame signal line BBL may further include a first power signal supply line VDD0, a plurality of first power connection structures VDDL, and a plurality of first power connection lines VDDC. The frame area BB may further include a plurality of multiplexer circuits 20. The first power signal supply line VDD0 may be located on the side of the plurality of multiplexer circuits 20 away from the display area, and the plurality of first power connection lines VDDC may be located on the side of the plurality of multiplexer circuits 20 closer to the display area. The plurality of first power connection lines VDDC are electrically connected to the first power signal supply line VDD0 through the plurality of first power connection structures VDDL. In the direction in which the plurality of multiplexer circuits 20 are arranged, the first power connection structure VDDL may be located between two adjacent multiplexer circuits 20.

[0143] In an exemplary embodiment, as shown in FIG7b, the plurality of connection vias K0 may include a first power connection via KVDD. At least a portion of the first power connection structure VDDL corresponds one-to-one with at least a portion of the first power connection line VDDC. Furthermore, at least a portion of the first power connection structure VDDL, the first power signal supply line VDD0, and at least a portion of the first power connection line VDDC are located on different conductive layers. At least a portion of the first power connection structure VDDL can be electrically connected to the first power signal supply line VDD0 and the corresponding first power connection line VDDC through the first power connection via KVDD. As shown in FIG7b, in the corner region, the first power connection structure VDDL may be located on the first gate metal layer, and the data selection line MUX, the first power signal supply line VDD0, and the first power connection line VDDC may be located on the first source-drain metal layer. A data selection line MUX for controlling the multiplexing circuit 20 is provided between the first power signal supply line VDD0 and the first power connection line VDDC. The data selection line MUX extends along the extension direction of the corner region. The first power connection structure VDDL being located on the first gate metal layer can avoid short-circuiting with the data selection line MUX.

[0144] In an exemplary embodiment, as shown in Figures 6a to 8b, the plurality of first power connection lines VDDC may include a first type of first power connection line VDDC1. The frame area BB may be provided with a plurality of parallel connection vias KL. The frame area BB may include a first frame area B1. At least one parallel connection via KL may be located in the first frame area B1. In the second direction Y, the first frame area B1 may be located on one side of the display area AA. At least a portion of the structure of the first shielding connection structure BSML1, the first type of first power connection line VDDC1, and at least a portion of the multiplexer circuits 20 may be located in the first frame area B1. In the first frame area B1, at least a portion of the structure of the first shielding connection structure BSML1 may be located on the side of the multiplexer circuits 20 closer to the display area AA. At least a portion of the structure of the first shielding connection structure BSML1 may at least partially overlap with the orthographic projection of the first type of first power connection line VDDC1 on the substrate and be electrically connected through at least one parallel connection via KL, so that the signal of the first power connection line VDDC1 is accessed by the first shielding connection structure BSML1.

[0145] The first signal line 30 can extend along the second direction Y, and the signal access via KR can be located at one end of the corresponding first signal line 30 near the first frame area B1. The orthogonal projections of the at least one connecting via KL and the multiple signal access via KR on the substrate do not overlap, which can avoid signal crosstalk caused by the parallel connecting via KL and the signal access via KR being connected and reduce via defects.

[0146] In an exemplary embodiment, as shown in Figures 8a to 8b, the plurality of first power connection structures VDDL may include a plurality of first type first power connection structures VDDL1, and at least a portion of the plurality of first type first power connection structures VDDL1 and the first power signal supply line VDD0 are located in the first border area B1.

[0147] In the first frame region B1: at least one parallel connection via KL may include multiple first vias K1, multiple signal access vias KR may include multiple second vias K2, the multiple second vias K2 may be located on the side of the multiple first vias K1 away from the multiplexing circuit 20, at least some of the multiplexing circuits 20 are arranged along the first direction X, multiple first type first power connection structures VDDL1 may extend along the second direction Y and be spaced apart along the first direction X, at least a portion of the structure of the first power signal supply line VDD0, the first type first power connection line VDDC1 and the first shielding connection structure BSML1 extend along the first direction X, the first power signal supply line VDD0 and the first type first power connection line VDDC1 may be electrically connected through multiple first type first power connection structures VDDL1; in the first direction X, the first type The first power connection structure VDDL1 can be located between two adjacent multiplexer circuits 20. At least one first via K1 and at least one second via K2 are provided between two adjacent first-type first power connection structures VDDL1, located on the same side of one of the first-type first power connection structures VDDL1. The distances between the first via K1 and the second via K2 and the first-type first power connection structure VDDL1 are different. In the direction parallel to the plane of the substrate, the first direction X intersects the second direction Y. For example, as shown in Figures 8a and 8b, in the first direction X, located on the same side of the same first-type first power connection structure VDDL1, the distance between the first via K1 and the first-type first power connection structure VDDL1 is M1, and the distance between the second via K2 and the first-type first power connection structure VDDL1 is M2. Then the values ​​of M1 and M2 are different.

[0148] In an exemplary embodiment, as shown in Figures 8a and 8b, in the first border region B1, in the first direction X, at least some of the multiplexing circuits 20 are provided with a first type of first power connection structure VDDL1 between two adjacent multiplexing circuits 20.

[0149] In the first border area B1: between two adjacent first-type first power connection structures VDDL1, there are two first vias K1 and two second vias K2. The two first vias K1 and the two second vias K2 located between two adjacent first-type first power connection structures VDDL1 constitute a first basic unit H1. In the same first basic unit H1, the first vias K1 and the second vias K2 are arranged alternately along the first direction X. The two adjacent first basic units H1 are symmetrical (or approximately symmetrical) with respect to the first-type first power connection structure VDDL1 located between the two first basic units H1. The two adjacent first basic units H1 constitute a second basic unit H2. Multiple second basic units H2 are arranged periodically along the first direction X. The two adjacent second basic units H2 can be symmetrical (or approximately symmetrical) with respect to the first-type first power connection structure VDDL1 located between the two second basic units H2.

[0150] In an exemplary embodiment, as shown in FIG8b, the display area AA may be provided with multiple sub-pixel columns PL, and the multiple sub-pixel columns PL may be arranged along the first direction X. In the first direction, two sub-pixel columns PL may be provided between two adjacent first type first power connection structures VDDL1. In the direction perpendicular to the plane where the substrate is located, the multiple sub-pixel columns may be located on the side of the shielding layer BSM away from the substrate.

[0151] In the first direction X: In the same second base unit H2, the distance M3 between the two middle first vias K1 can be less than the size M4 of a sub-pixel column PL; the distance M5 between the two closest first vias K1 in two adjacent second base units H2 is greater than the size M4 of a sub-pixel column PL.

[0152] In an exemplary embodiment, as shown in Figures 8a and 8b, the at least part of the border signal line BBL may further include a plurality of second power connection structures VSSL, the first signal supply line LT may include a second power signal supply line VSS0, and at least part of the second power connection structures VSSL and at least part of the second power signal supply line VSS0 are located in the first border area B1.

[0153] The multiple first signal lines 30 may include multiple second power lines VSS and multiple initial signal lines Vinit. The second power lines VSS and the initial signal lines Vinit may be arranged alternately along the first direction X. The two second vias K2 located in the same first basic unit H1 correspond to one second power line VSS and one initial signal line Vinit, respectively.

[0154] In the first border area B1, the second power signal supply line VSS0 can be located on the side of the multiple multiplexer circuits 20 away from the display area AA. The multiple second power connection structures VSSL can correspond one-to-one with the multiple second power lines VSS. The second power lines VSS can be electrically connected to the second power signal supply line VSS0 through the corresponding second power connection structure VSSL. At least a portion of the structure of the second power signal supply line VSS0 at least partially overlaps with the orthographic projection of at least a portion of the structure of the first power signal supply line VDD0 on the substrate. In the direction perpendicular to the plane of the substrate, at least a portion of the structure of the second power connection structure VSSL and at least a portion of the structure of the second power signal supply line VSS0 can be located on the side of the first power signal supply line VDD0 away from the substrate.

[0155] In an exemplary embodiment, as shown in Figures 8a and 8b, the plurality of connection vias may further include a plurality of third vias K3 and a plurality of fourth vias K4 located in the first border region B1. In the first border region B1, the plurality of third vias K3 and the plurality of fourth vias K4 may be located on the side of the plurality of first vias K1 away from the display region AA.

[0156] In the first border area B1: a second power connection structure VSSL can be provided between two adjacent first-type first power connection structures VDDL1. The second power connection structure VSSL may include a first structural part d1, a second structural part d2, and a third structural part d3. The main bodies of the first structural part d1 and the third structural part d3 can extend along the second direction Y, and the second structural part d2 can extend along the first direction X. In the first direction X, the third structural part d3 can be located between two adjacent multiplexer circuits 20, and a multiplexer circuit 20 is provided between two adjacent third structural parts d3. In the second direction Y, the second structural part d2 can be located between the multiplexer circuit 20 and the first-type first power connection line VDDC1.

[0157] The second structural part d2 corresponds to one of the third vias K3 and one of the fourth vias K4. In the same second power connection structure VSSL: one end of the second structural part d2 can be electrically connected to the end of the first structural part d1 away from the display area AA through the corresponding third via K3, and the other end can be electrically connected to the end of the third structural part d3 near the display area AA through the corresponding fourth via K4. The end of the first structural part d1 near the display area AA is electrically connected to the corresponding second power line through the corresponding second via K2. The end of the third structural part d3 away from the display area AA is connected to the second power signal supply line VSS0.

[0158] In an exemplary embodiment, as shown in Figures 8a and 8b, the at least part of the working signal lines may further include multiple data signal lines D, the main body of which extends along the second direction Y and is spaced apart along the first direction X; the data signal lines D may extend to the first frame region B1 and be electrically connected to one of the multiplexing circuits 20; the same multiplexing circuit 20 may be electrically connected to at least two data signal lines D, for example, as shown in Figure 8a, the same multiplexing circuit 20 may be electrically connected to four data signal lines D;

[0159] In a direction perpendicular to the plane of the substrate, the second structural part d2 can be disposed on the same layer as the first power signal supply line VDD0. The first structural part d1, the third structural part d3 and the data signal line D can be located on the side of the second structural part d2 away from the substrate. In the first direction X, between two adjacent first type first power connection structures VDDL1, at least a portion of the data signal line D can be located between the two ends of the same second structural part d2. The data signal line D located between the two ends of the same second structural part d2 at least partially overlaps with the orthographic projection of the second structural part d2 on the substrate.

[0160] In an exemplary embodiment, as shown in Figures 8a and 8b, in the first border area B1, the first power connection via KVDD may include a third type of first power connection via KVDD3, and the border signal line BBL may also include multiple third type of first power connection structures VDDL3. The multiple third type of first power connection structures VDDL3 correspond one-to-one with multiple first type of first power connection structures VDDL1. The third type of first power connection structure VDDL3 is electrically connected to the corresponding first type of first power connection structure VDDL1 through the third type of first power connection via KVDD3. The first type of first power connection structure VDDL1 can be connected to the first power signal supply line VDD0 through the corresponding third type of third power connection structure VDDL3. In the first border area B1, the data selection line MUX, the second structural part d2, the first type of first power connection structure VDDL1, the first type of first power connection line VDDC1, and the first power signal supply line VDD0 can be located in the first source-drain metal layer. The first structural part d1, the third structural part d3, the third type of first power connection line VDDL3, and the data signal line D can be located in the second source-drain metal layer. A data selection line MUX for the control multiplexing circuit 20 is provided between the first power signal supply line VDD0 and the first type of first power connection line VDDC1. The data selection line MUX extends along the first direction X. The first type of first power connection structure VDDL1 is located in the first source-drain metal layer and is connected to the first power signal supply line VDD0 through the corresponding third type of first power connection via KVDD3 located in the second source-drain metal layer, which can avoid short-circuit connection between the first type of first power connection structure VDDL1 and the data selection line MUX.

[0161] In an exemplary embodiment, in at least one first base unit H1, at least one first via K1 at least partially overlaps with the orthographic projection of one of the data signal lines onto the substrate.

[0162] In an exemplary embodiment, as shown in Figures 6a to 7c, the border area BB may further include a first corner area C1 and a fourth corner area C4. In the first direction X, the first corner area C1 and the fourth corner area C4 may be located on both sides of the first border area B1. In the second direction Y, the first corner area C1 and the fourth corner area C4 are located on the same side of the display area AA as the first border area B1. The first power signal supply line VDD0 may be located in the first border area B1 and extend to the first corner area C1 and the second corner area.

[0163] The at least part of the first power connection structure VDDL includes a plurality of second type first power connection structures VDDL2, and the at least part of the first power connection line VDDC includes a plurality of second type first power connection lines VDDC2. The plurality of second type first power connection structures VDDL2 and the plurality of second type first power connection lines VDDC2 correspond one-to-one. The second type first power connection structures VDDL2 and the second type first power connection lines VDDC2 are located in the first corner region C1 and the fourth corner region C4.

[0164] The plurality of first power connection vias KVDD may include a plurality of first-type first power connection vias KVDD1 and a plurality of second-type first power connection vias KVDD2. The first-type first power connection vias KVDD1 correspond to one of the second-type first power connection structures VDDL2, and the second-type first power connection vias KVDD2 correspond to one of the second-type first power connection lines VDDC2 and one of the second-type first power connection structures VDDL2. In the direction perpendicular to the plane of the substrate, the first power signal supply line VDD0 and the first power connection line VDDC may be located on the side of the second-type first power connection structure VDDL2 away from the shielding layer BSM. The second-type first power connection structure VDDL2 can be electrically connected to the first power signal supply line VDD0 through the corresponding first-type first power connection via KVDD1, and electrically connected to the corresponding second-type first power connection line VDDC2 through the corresponding second-type first power connection via KVDD2.

[0165] In an exemplary embodiment, as shown in Figures 7a to 7c, the at least part of the frame signal line BBL may further include multiple second power connection structures VSSL, multiple connection vias K0 may further include multiple second power connection vias KVSS, the first signal supply line LT may include a second power signal supply line VSS0, multiple first signal lines 30 may include multiple second power lines VSS, the multiple second power lines VSS correspond one-to-one with the multiple second power connection structures VSSL, the second power connection vias KVSS correspond to one of the second power connection structures VSSL, the second power connection structure VSSL is connected to the corresponding second power line VSS through the corresponding signal access via KR, and is electrically connected to the second power signal supply line VSS0 through the corresponding second power connection via KVSS;

[0166] In the first corner region C1 and the fourth corner region C4: the first shielding connection structure BSML1 can be located on the side of the multiple multiplexing circuits 20 away from the display area AA, the second power signal supply line VSS0 can be located on the side of the multiple multiplexing circuits 20 close to the display area AA, the edge of the first power signal supply line VDD0 close to the display area AA and the second power signal supply line VSS0 can be stepped, and the multiple second type first power connection structures VDDL2 and the multiple second type first power connection lines VDDC2 are arranged in a stepped manner along the extension direction of their respective corner regions; in the direction perpendicular to the plane of the substrate, the second power connection structure VSSL and the second power signal supply line VSS0 can be located on the side of the second power line VSS and the second type first power connection line VDDC2 away from the substrate. In the first direction X, a second type first power connection line VDDC2 and at least one second power connection structure VSSL can be set between two adjacent second type first power connection structures VDDL2. The second power connection structure VSSL overlaps with the second type first power connection line VDDC2. The second power connection structure VSSL and the second type first power connection line VDDC2 are located in different conductive layers, which can avoid signal short circuit.

[0167] In an exemplary embodiment, as shown in Figures 7b and 7c, in the first corner region C1 and the fourth corner region C4: the first power connection structure VDDL can be located in the first gate metal layer; the data selection line MUX, the second power signal supply line VSS0, the first power signal supply line VDD0, and the second type of first power connection line VDDC2 can be located in the first source-drain metal layer; the second power connection structure VSSL and the data signal line D are located in the second source-drain metal layer; a data selection line MUX for the control multiplexing circuit 20 is provided between the first power signal supply line VDD0 and the first power connection line VDDC; the data selection line MUX extends along the extension direction of the corner region; the second type of first power connection line VDDC2 and the first power connection structure VDDL being located in the first gate metal layer can avoid short-circuiting with the data selection line MUX; the second type of first power connection line VDDC2 being located in the first source-drain metal layer can avoid short-circuiting with the second power connection structure VSSL and the data signal line D located in the second source-drain metal layer, thus avoiding signal crosstalk.

[0168] In an exemplary embodiment, as shown in Figures 6a to 7b, the first corner region C1 and the fourth corner region C4 are arc-shaped structures. The center of the circle containing the arc-shaped structure is located on the side of the arc-shaped structure closest to the display area AA. In the first corner region C1 and the fourth corner region C4, the shape of the first shielding connection structure BSML1 is consistent with the shape of the corner region it is located in. The first shielding connection structure BSML1 and the orthographic projection of the first power signal supply line VDD0 on the substrate at least partially overlap. At least some of the parallel connection vias KL are located in the first corner region C1 and the fourth corner region C4.

[0169] In an exemplary embodiment, as shown in Figures 6a to 7c and 9b, Figure 9b is an enlarged schematic diagram of the occlusion layer at position R5 in Figure 6b. The border area BB may further include a second border area B2, a third border area B3, and a fourth border area B4. In the first direction X, the third border area B3 and the fourth border area B4 are located on both sides of the display area AA. In the second direction Y, the first border area B1 and the second border area B2 are located on both sides of the display area AA. The first border area B1 and the third border area B3 can be connected through the first corner area C1, and the first border area B1 and the fourth border area B4 can be connected through the fourth corner area C4.

[0170] At least some of the multiplexer circuits 20 can be located in the first corner region C1 and the fourth corner region C4. In the first corner region C1 and the fourth corner region C4, at least some of the multiplexer circuits 20 are arranged in a stepped manner along the extension direction of the corner region where they are located. Multiple shielding connection lines BSMC are interconnected to form multiple first openings w1. The multiplexer circuits 20 can be located in the corresponding first openings w1. In at least some of the multiple first openings w1, each first opening w1 accommodates at least one multiplexer circuit 20. In the first direction X, the size of the first opening w1 is the same as the size of m multiplexer circuits 20. In the second direction Y, the size of the first opening w1 is the same as the size of n multiplexer circuits 20. m and n are positive integers greater than or equal to 1.

[0171] In an exemplary embodiment, as shown in FIG7b, the plurality of connection vias K0 may further include vias K20 in the multiplexing circuit 20. The multiplexing circuit 20 may be located in the corresponding first opening w1, which can avoid the vias K20 in the multiplexing circuit 20 from overlapping with the shielding layer BSM, thereby avoiding electrostatic damage to the shielding layer caused by the vias K20 in the multiplexing circuit 20 hitting the shielding layer BSM.

[0172] In an exemplary embodiment, as shown in FIG9b, the plurality of occlusion connection lines BSMC may include a plurality of first occlusion connection lines BSMC1, a plurality of second occlusion connection lines BSMC2, and a plurality of third occlusion connection lines BSMC3 located in the first corner region C1 and the fourth corner region C4.

[0173] In the first corner region C1 and the fourth corner region C4: multiple first blocking connection lines BSMC1 and multiple second blocking connection lines BSMC2 extend along the first direction X and are arranged in a stepped manner along the extension direction of the corner region where they are located; multiple third blocking connection lines BSMC3 extend along the second direction Y and are arranged in a stepped manner along the extension direction of the corner region where they are located; at least a portion of the structure of the third blocking connection line BSMC3 is located between adjacent first blocking connection lines BSMC1 and second blocking connection lines BSMC2; and the first opening w1 is formed by two adjacent third blocking connection lines BSMC3 in the first direction X and adjacent first blocking connection lines BSMC1 and second blocking connection lines BSMC2 in the second direction Y.

[0174] In an exemplary embodiment, as shown in FIG9b, in the first corner region C1 and the fourth corner region C4, two adjacent first blocking connection lines BSMC1 and a neighboring third blocking connection line BSMC3 and two adjacent first blocking structures BSM1 surround to form a second opening w2. Two adjacent second blocking connection lines BSMC2 and a first blocking connection structure BSML1 and a neighboring third blocking connection line BSMC3 surround to form a third opening w3. Multiple first openings w1, multiple second openings w2 and multiple third openings w3 are arranged in a stepped manner along the corner region where they are located. Multiple third openings w3 are located on the side of multiple first openings w1 away from the display area AA, and multiple second openings w2 are located on the side of multiple first openings w1 close to the display area AA.

[0175] In an exemplary embodiment, as shown in FIG9b, multiple first occlusion structures BSM1 are arranged in multiple rows. In the first corner region C1 and the fourth corner region C4, the side of the first occlusion connection line BSMC1 near the display area AA is connected to one row of occlusion structures. In the second direction Y, the distance a between two adjacent first occlusion connection lines BSMC1 is consistent with the size a1 of one first occlusion structure BSM1. The distance a between two adjacent second occlusion connection lines BSMC2 is consistent with the size a1 of one first occlusion structure BSM1. The side of the third occlusion connection line BSMC3 near the display area AA is connected to two adjacent rows of first occlusion connection structures BSML1 through two first occlusion connection lines BSMC1, and the side away from the display area AA is connected to the first occlusion connection structure BSML1 through two second occlusion connection lines BSMC2.

[0176] In an exemplary embodiment, as shown in Figures 9a and 9b, the first opening w1 is approximately rectangular in shape. In the first direction X, the distance a2 between two adjacent third blocking connection lines BSMC3 is the same as the size (m*b1) of m multiplex circuits 20, and the two adjacent third blocking connection lines BSMC3 form a pair of opposite sides of the rectangle. In the second direction Y, the distance b between the first blocking connection line BSMC1 and one of the second blocking connection lines BSMC2 in the direction away from the display area AA is the same as the size (n*b2) of n multiplex circuits 20, and the first blocking connection line BSMC1 and one of the second blocking connection lines BSMC2 form another pair of opposite sides of the rectangle. Here, b1 is the size of a multiplex circuit 20 along the first direction X, and b2 is the size of a multiplex circuit 20 along the second direction Y.

[0177] In an exemplary embodiment, as shown in Figures 7a and 9b, in the second direction Y, the distance b between the first blocking connection line BSMC1 and the third second blocking connection line BSMC2 in the direction away from the display area AA is consistent with the size (n*b2) of the n multiplex circuits 20, and the first blocking connection line BSMC1 and the third second blocking connection line BSMC2 form another set of opposite sides of the rectangle.

[0178] In an exemplary embodiment, as shown in Figures 7a and 9b, n can be 1, meaning the dimension b of the first opening w1 along the second direction Y can be the same as the dimension b2 of a multiplexer circuit 20 along the second direction Y; m can be greater than or equal to 1, meaning the dimension a1 of the first opening w1 along the first direction X can be the same as the dimension of one or more multiplexer circuits 20 along the first direction X. In the first corner region C1 and the fourth corner region C4, the value of m is greater near the first border region B1 than far from the first border region B1 (i.e., the slope on the side near the first border region B1 is gentler than the slope on the side far from the first border region B1). For example, as shown in Figures 7a, 7b, and 9c, Figure 9c is an enlarged schematic diagram of the R6 position in Figure 6b. In the direction from the first border region B1 to the fourth corner region C1, the value of m can be 10, 3, 2, or 1.

[0179] In an exemplary embodiment, as shown in Figures 8a and 8b, in the first border region B1, a plurality of first spacings E1 are formed between a plurality of occlusion connection lines BSMC. ​​In the first direction X, the first spacing E1 is the distance between two adjacent occlusion connection lines BSMC along the first direction X. At least one first spacing E1 is greater than the size a2 of the first opening w1, and at least one first spacing E1 is less than the size a2 of the first opening w1.

[0180] In an exemplary embodiment, in the structure shown in FIG9b, multiple shielding connection lines BSMC in the corner areas (C1, C4) form a grid structure with a first opening w1, a second opening w2, and a third opening w3. On the one hand, the first opening w1 can accommodate the multiplexing circuit 20, avoiding the overlap between the via K20 in the multiplexing circuit 20 and the shielding layer BSM. On the other hand, the shielding layer is electrically connected to the constant voltage signal line, which can improve the uniformity of the constant voltage signal accessed to the display area, thereby improving the display uniformity.

[0181] In an exemplary embodiment, as shown in Figures 10a and 10b, which are enlarged schematic diagrams of the shielding layer at position R7 in Figures 6a and 6b, the shielding layer BSM may further include a second shielding connection structure BSML2 and a plurality of second shielding structure groups BSM20. The second shielding connection structure BSML2 and the plurality of second shielding structure groups BSM20 may be located in at least one of the third border area B3 and the fourth border area B4. The plurality of second shielding structure groups BSM20 located in the same border area are arranged along the direction from the display area AA to the border area where they are located, and the plurality of second shielding structures BSM2 in the same second shielding structure group BSM20 are arranged along the extension direction of the border area where they are located.

[0182] The extension direction of the second occlusion connection structure BSML2 is consistent with the extension direction of the border area it is located in. In the same border area, in the direction from the display area AA to the border area, the second occlusion connection structure BSML2 is located between two adjacent second occlusion structure groups BSM20. Multiple second occlusion structures BSM2 in two adjacent second occlusion structure groups BSM20 are connected to their adjacent second occlusion connection structures BSML2.

[0183] In an exemplary embodiment, as shown in Figures 10a and 10b, the shielding layer BSM may further include a third shielding connection structure BSML3. At least a portion of the structure of the first shielding connection structure BSML1 and the third shielding connection structure BSML3 may be located in at least one of the third border region B3 and the fourth border region B4. The extension direction of the third shielding connection structure BSML3 is consistent with the extension direction of the border region in which it is located. In the same border region, in the direction from the display region AA to the border region, the third shielding connection structure BSML3 is located on the side of the second shielding structure group BSM20 closer to the display region AA. The third shielding connection structure BSML3 is connected to a plurality of second shielding structures BSM2 in a neighboring second shielding structure group.

[0184] In at least one of the third border region B3 and the fourth border region, in the first direction X, the size g3 of the third blocking connection structure BSML3 is larger than the size g2 of the second blocking connection structure BSML2, and the size g2 of the second blocking connection structure BSML1 is larger than the size g1 of the first blocking connection structure BSML1. The larger size g3 of the second blocking connection structure BSML2 and the third blocking connection structure BSML3 can reduce the voltage drop of the constant voltage signals of the second blocking connection structure BSML2 and the third blocking connection structure BSML3, thereby improving display uniformity.

[0185] In an exemplary embodiment, as shown in Figures 10a and 10b, the occlusion layer BSM may further include a plurality of fourth occlusion connection structures BSML4. The fourth occlusion connection structures BSML4 may be located in at least one of the third border region B3 and the fourth border region B4. In the same border region, the plurality of fourth occlusion connection structures BSML4 are located between the first occlusion connection structure BSML1 and the third occlusion connection structure BSML3. The plurality of fourth occlusion connection structures BSML4 are arranged at intervals along the extension direction of their respective border regions. The main body of the fourth occlusion connection structure BSML4 extends along the first direction X, with one end connected to the third occlusion connection structure BSML3 in its respective border region and the other end connected to the first occlusion connection structure BSML1.

[0186] In an exemplary embodiment, as shown in FIG10c, which is an enlarged schematic diagram of another R6 position shielding layer BSM in FIG6a and FIG6b, in the structure shown in FIG10c, the first shielding connection structure BSML1, the second shielding connection structure BSML2, and the third shielding connection structure BSML3 can be connected to different constant voltage signal lines or to the same constant voltage signal line; in the structure shown in FIG10b, the first shielding connection structure BSML1, the second shielding connection structure BSML2, and the third shielding connection structure BSML3 are connected to the same constant voltage signal line, such as being electrically connected to the first power signal supply line VDD0; in the structure shown in FIG10a, the first shielding connection structure BSML1 is connected to a lateral signal line (such as the first power signal supply line VDD0), and the second shielding connection structure BSML2 and the third shielding connection structure BSML3 can be electrically connected to another constant voltage signal line or to the first power signal supply line VDD0.

[0187] In an exemplary embodiment, the display substrate further includes a plurality of gate driving circuits 10 groups, which are located in at least a general border region of the third border region B3 and the fourth border region B4 (refer to Figure 5a, the plurality of gate driving circuits 10 groups may be located in the third border region B3 and the fourth border region B4). The plurality of gate driving circuits 10 groups are arranged along the direction of the display region AA pointing to the border region where they are located. In the same border region, at least some of the gate driving circuits 10 groups correspond one-to-one with a plurality of second shielding structure groups BSM20. The plurality of gate driving circuits 10 in the same gate driving circuit 10 group are arranged along the extension direction of the border region where they are located. The plurality of second shielding structures BSM2 in the second shielding structure group BSM20 correspond one-to-one with the plurality of gate driving circuits 10 in the corresponding gate driving circuit group BSM20. The orthographic projections of the second shielding structure BSM2 and the corresponding gate driving circuit 10 on the substrate at least partially overlap.

[0188] In an exemplary embodiment, the gate drive circuit 10 may include a plurality of transistors, and the second shielding structure BSM2 may at least partially overlap with the orthogonal projection of the channel of at least one transistor in the corresponding gate drive circuit 10 onto the substrate.

[0189] In an exemplary embodiment, as shown in Figures 6a and 6b, the multiple occlusion connection lines BSMC may include multiple fourth occlusion connection lines BSMC4. The first occlusion connection structure BSML1 is a ring structure surrounding the display area AA. The multiple first occlusion structures BSM1 form multiple rows and columns. The multiple first occlusion structures BSM1 located in the same row are interconnected, and the multiple first occlusion structures BSM1 located in the same column are interconnected. The multiple fourth occlusion connection lines BSMC4 may extend along the first direction X and be arranged at intervals along the extension direction of the border area where they are located. In the first direction, the multiple fourth occlusion connection lines BSMC4 may be located on both sides of the multiple first occlusion structures BSM1 and on the side of the first occlusion connection structure BSML1 closer to the display area AA. The multiple first occlusion structures BSM1 can be connected to the first occlusion connection structures BSML1 located on both sides through the multiple fourth occlusion connection structures BSMC4 located on both sides of them.

[0190] In at least one row of the first occlusion structure BSM1 in the multi-row first occlusion structure BSM1, in the first direction X, each row of occlusion structure is connected to the first occlusion connection structure BSML1 through the fourth occlusion connection line BSMC4 located on both sides of the row of first occlusion structure BSM1.

[0191] In an exemplary embodiment, multiple first shielding structures BSM1 can be interconnected to form a grid-like structure. The multiple first shielding structures BSM1 are connected to a first shielding connection structure BSML1, and the first shielding connection structure BSML1 is connected to a constant voltage signal line (such as a first power signal supply line VDD0). Thus, the signals of the multiple grid-like first shielding structures BSM1 are consistent with the signals of the first shielding connection structure BSML1 (for example, both are first power signals provided by the first power signal supply line VDD0).

[0192] In an exemplary embodiment, as shown in Figures 6a and 9a, Figure 9a is an enlarged schematic diagram of the occlusion layer at position R7 in Figure 6a. In the structure shown in Figure 6a, the border area BB is not provided with a multiplexing circuit 20, and multiple first occlusion structures BSM1 can be connected to the first occlusion connection structure BSML1 through the fourth occlusion connection line BSMC4. As shown in Figures 6b and 9b, Figure 9b is an enlarged schematic diagram of the occlusion layer at position R7 in Figure 6b. The first border area B1, the first corner area C1, and the fourth corner area C4 are provided with multiplexing circuits 20. In the first corner area C1 and the fourth corner area C4, multiple first occlusion structures BSM1 are connected through the first occlusion connection line BSMC1 and the second occlusion connection line BSML1. MC2 and the third shielding connection line BSMC3 are connected to the first shielding connection structure BSML1. The multiplexing circuit 20 is located in the first open w1 to avoid the overlap of the first shielding connection line BSMC1, the second shielding connection line BSMC2, the third shielding connection line BSMC3 and the multiplexing circuit 20. This avoids the vias in the multiplexing circuit 20 (as shown in Figure 7b, the connecting via K0 can include the via K20 in the multiplexing circuit 20). It also avoids the overlap of via K20 with the first shielding connection line BSMC1, the second shielding connection line BSMC2, the third shielding connection line BSMC3 and the first shielding connection structure BSML1, thereby preventing the shielding layer BSM from being damaged by via K20. In the third border area B3 and the fourth border area B4 shown in Figure 6b, the multiplexing circuit 20 is not provided. Then, multiple first shielding structures BSM1 can be connected to the first shielding connection structure BSML1 through the fourth shielding connection line BSMC4. That is, in Figure 6a (without multiplexing circuit 20), the first blocking structure BSM1 can be connected to the first blocking connection structure BSML1 only through the fourth blocking connection line BSMC4. In Figure 6b (with multiplexing circuit 20), the first blocking structure BSM1 needs to be connected to the first blocking connection structure BSML1 through the first blocking connection line BSMC1, the second blocking connection line BSMC2, the third blocking connection line BSMC3, and the fourth blocking connection line BSMC4. Specifically, in the third border area B3 and the fourth border area B4 without multiplexing circuit 20, they are connected to the first blocking connection structure BSML1 through the fourth blocking connection line BSMC4. In the first corner area C1 and the fourth corner area C4 with multiplexing circuit 20, they are connected to the first blocking connection structure BSML1 through the first blocking connection line BSMC1, the second blocking connection line BSMC2, and the third blocking connection line BSMC3.

[0193] In an exemplary embodiment, the display area AA may include multiple sub-pixels, and multiple first occlusion structures BSM1 correspond one-to-one with the multiple sub-pixels. At least one sub-pixel may include multiple transistors. The first occlusion structure BSM1 and the orthographic projection of the channel region of at least one transistor in the corresponding sub-pixel on the substrate at least partially overlap. For example, the orthographic projection of the first occlusion structure BSM1 on the substrate may cover the orthographic projection of the channel region of at least one transistor in the corresponding sub-pixel on the substrate. The transistors in the sub-pixel are occluded by the corresponding first occlusion structure BSM1, which can improve the stability of the transistors.

[0194] In an exemplary embodiment, multiple sub-pixels can form multiple rows and multiple columns, and multiple first occlusion structures BSM1 can form multiple rows and multiple columns. Multiple rows of sub-pixels correspond to multiple rows of first occlusion structures BSM1, and one column of sub-pixels corresponds to one column of first occlusion structures BSM1.

[0195] In an exemplary embodiment, as shown in Figures 7b and 8b, the multiplexing circuit 20 can be connected to multiple data selection lines (MUX), multiple data signal lines (D), and one data output line (DT). For example, one multiplexing circuit 20 can be connected to four data selection lines (MUX) and four data signal lines (D). Under the control of the four data selection MUX, the multiplexing circuit 20 provides the signal output from the data output line DT to the four data signal lines (D) connected to it in a time-division manner. The signal of one data output line DT can be provided to four data signal lines (D), which can reduce the number of data signal lines (D) in the first border area B1, thus facilitating border narrowing.

[0196] The structures described above in this disclosure are merely illustrative. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced as needed. The display substrates in this disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays. This disclosure does not limit the application of these substrates.

[0197] This disclosure also provides a display device, as shown in FIG11, which may include the display substrate of any of the foregoing embodiments. The display device may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame or navigator, or vehicle display.

[0198] This disclosure also provides a method for preparing a display substrate, which may include:

[0199] A shielding layer is formed on one side of a substrate, the substrate including a display area and a border area surrounding the display area, the shielding layer including a plurality of first shielding structures located in the display area, a first shielding connection structure located in the border area and a plurality of shielding connection lines, the first shielding connection structures being located on the side of the plurality of shielding connection lines away from the display area, and the plurality of first shielding structures being connected to the first shielding connection structure through the plurality of shielding connection lines;

[0200] Multiple connection vias, multiple border signal lines, and multiple working signal lines are formed on the side of the shielding layer away from the substrate layer. The multiple connection vias and the multiple border signal lines are located in the border area, and the multiple working signal lines are located in the display area. The orthographic projection of the first shielding connection structure and the multiple shielding connection lines on the substrate does not overlap with the orthographic projection of the multiple connection vias on the substrate.

[0201] The display substrate and its preparation method and display device provided in this disclosure have a plurality of connection vias and a plurality of frame signal lines in the frame area of ​​the display substrate, and a plurality of working signal lines in the display area. At least some of the connection vias are configured to electrically connect at least some of the frame signal lines with at least some of the working signal lines. The orthographic projection of the first shielding connection structure and the plurality of shielding connection lines on the substrate does not overlap with the orthographic projection of the plurality of connection vias on the substrate, which can avoid electrostatic damage caused by the shielding layer overlapping with the connection vias, thereby reducing display defects and improving display effect.

[0202] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0203] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0204] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit the scope of these embodiments. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a substrate and a shielding layer located on one side of the substrate, the substrate comprising a display area and a border area surrounding the display area, the shielding layer comprising a plurality of first shielding structures located in the display area, a first shielding connection structure located in the border area, and a plurality of shielding connection lines, the first shielding connection structures being located on the side of the plurality of shielding connection lines away from the display area, the plurality of first shielding structures being connected to the first shielding connection structure via the plurality of shielding connection lines; The frame area is provided with multiple connection vias and multiple frame signal lines, and the display area is provided with multiple working signal lines. At least some of the connection vias are configured to electrically connect at least some of the frame signal lines with at least some of the working signal lines. In a direction perpendicular to the plane of the substrate, the multiple frame signal lines, the multiple working signal lines, and the multiple connection vias are located on the side of the shielding layer away from the substrate. The orthographic projections of the first shielding connection structure and the multiple shielding connection lines on the substrate do not overlap with the orthographic projections of the multiple connection vias on the substrate. 2.The display substrate of claim 1, wherein, The at least part of the working signal lines include a plurality of first signal lines, and the at least part of the frame signal lines include at least one first signal providing line. The first signal lines correspond to one of the first signal providing lines. In a direction perpendicular to the plane of the substrate, the plurality of first signal lines and the first signal providing line are located on the side of the shielding layer away from the substrate. The first signal lines and the first signal providing line are located in different conductive layers. The plurality of connection vias includes a plurality of signal access vias, each of which corresponds one-to-one with the plurality of first signal lines. The plurality of signal access vias are located on the side of the first shielding connection structure closer to the display area, and the first signal lines are provided with linear connections to the corresponding first signals through the corresponding signal access vias.

3. The display substrate according to claim 2, wherein, The frame signal line also includes a first power signal supply line, a plurality of first power connection structures, and a plurality of first power connection lines. The frame area also includes a plurality of multiplexing circuits. The first power signal supply line is located on the side of the plurality of multiplexing circuits away from the display area. The plurality of first power connection lines are located on the side of the plurality of multiplexing circuits close to the display area. The plurality of first power connection lines are electrically connected to the first power signal supply line through the plurality of first power connection structures. In the direction in which the plurality of multiplexer circuits are arranged, the first power connection structure is located between two adjacent multiplexer circuits; The plurality of connection vias includes a first power connection via, at least a portion of the first power connection structure corresponds one-to-one with at least a portion of the first power connection line, and the at least a portion of the first power connection structure is located on a different conductive layer from the first power signal supply line and the at least a portion of the first power connection line. The at least a portion of the first power connection structure is electrically connected to the first power signal supply line and the corresponding first power connection line through the first power connection via.

4. The display substrate according to claim 3, wherein, The plurality of first power connection lines include a first type of first power connection line. The frame area is provided with a plurality of parallel connection vias. The frame area includes a first frame area. At least one parallel connection via is located in the first frame area. In the second direction, the first frame area is located on one side of the display area. At least a portion of the structure of the first shielding connection structure, the first type of first power connection line, and at least a portion of the multiplexing circuits in the plurality of multiplexing circuits are located in the first frame area. In the first frame area, at least a portion of the structure of the first shielding connection structure is located on the side of the plurality of multiplexing circuits closer to the display area. At least a portion of the structure of the first shielding connection structure at least partially overlaps with the orthographic projection of the first type of first power connection line on the substrate and is electrically connected through the at least one parallel connection via. The first signal line extends along the second direction, and the signal access via is located at one end of the corresponding first signal line near the first frame area. The at least one parallel connection via and the orthographic projection of the plurality of signal access vias on the substrate do not overlap.

5. The display substrate according to claim 4, wherein, The plurality of first power connection structures include a plurality of first type first power connection structures, and at least a portion of the plurality of first type first power connection structures and the first power signal supply line are located in the first border area; In the first frame region: the at least one parallel connection via includes a plurality of first vias, the plurality of signal access vias includes a plurality of second vias, the plurality of second vias are located on the side of the plurality of first vias away from the multiplexing circuit, at least a portion of the plurality of multiplexing circuits are arranged along a first direction, the plurality of first-type first power connection structures extend along a second direction and are spaced apart along the first direction, at least a portion of the structure of the first power signal supply line, the first-type first power connection line and the first shielding connection structure extend along the first direction; in the first direction, at least one first via and at least one second via are provided between two adjacent first-type first power connection structures, located on the same side of one of the first-type first power connection structures, the distances between the first via and the second via and the first-type first power connection structure are different, and in a direction parallel to the plane of the substrate, the first direction intersects the second direction.

6. The display substrate according to claim 5, wherein, In the first border area, in the first direction, at least some of the multiplexer circuits in the plurality of multiplexer circuits are provided with a first type of first power supply connection structure between two adjacent multiplexer circuits. In the first border area: between two adjacent first-type first power connection structures, there are two first vias and two second vias. The two first vias and the two second vias located between two adjacent first-type first power connection structures form a first base unit. In the same first base unit, the first vias and the second vias are arranged alternately along the first direction. Two adjacent first base units are symmetrical with respect to the first-type first power connection structure located between the two first base units. Two adjacent first base units form a second base unit. Multiple second base units are arranged periodically along the first direction. Two adjacent second base units are symmetrical with respect to the first-type first power connection structure located between the two second base units.

7. The display substrate according to claim 6, wherein, The display area is provided with multiple sub-pixel columns, which are arranged along the first direction. In a direction perpendicular to the plane of the substrate, the multiple sub-pixel columns are located on the side of the shielding layer away from the substrate. In the first direction: in the same second base unit, the distance between the two middle first vias is less than the size of a sub-pixel column; the distance between the two nearest first vias in two adjacent second base units is greater than the size of a sub-pixel column.

8. The display substrate according to claim 6, wherein, The at least part of the frame signal line also includes a plurality of second power connection structures, the first signal supply line includes a second power signal supply line, and at least part of the plurality of second power connection structures and at least part of the second power signal supply line are located in the first frame area; The plurality of first signal lines include a plurality of second power lines and a plurality of initial signal lines. The second power lines and the initial signal lines are arranged alternately along the first direction. Two second vias located in the same first base unit correspond to one second power line and one initial signal line, respectively. In the first border area: the second power signal supply line is located on the side of the plurality of multiple selection circuits away from the display area, the plurality of second power connection structures correspond one-to-one with the plurality of second power lines, the second power lines are electrically connected to the second power signal supply line through the corresponding second power connection structure, and at least a portion of the structure of the second power signal supply line at least partially overlaps with the orthographic projection of at least a portion of the structure of the first power signal supply line on the substrate. In a direction perpendicular to the plane of the substrate, at least a portion of the second power connection structure and at least a portion of the second power signal supply line are located on the side of the first power signal supply line away from the substrate.

9. The display substrate according to claim 8, wherein, The plurality of connection vias also includes a plurality of third vias and a plurality of fourth vias located in the first frame area, wherein the plurality of third vias and the plurality of fourth vias are located on the side of the plurality of first vias away from the display area in the first frame area; In the first border area: a second power connection structure is provided between two adjacent first-type first power connection structures. The second power connection structure includes a first structural part, a second structural part, and a third structural part. The main bodies of the first structural part and the third structural part extend along the second direction, and the second structural part extends along the first direction. In the first direction, the third structural part is located between two adjacent multiplexer circuits, and a multiplexer circuit is provided between two adjacent third structural parts. In the second direction, the second structural part is located between the multiplexer circuit and the first-type first power connection line. The second structural part corresponds to one of the third vias and one of the fourth vias. In the same second power connection structure: one end of the second structural part is electrically connected to the end of the first structural part away from the display area through the corresponding third via, and the other end is electrically connected to the end of the third structural part near the display area through the corresponding fourth via. The end of the first structural part near the display area is electrically connected to the corresponding second power line through the corresponding second via. The end of the third structural part away from the display area is connected to the second power signal supply line.

10. The display substrate according to claim 9, wherein, The at least part of the working signal lines also includes a plurality of data signal lines, the main body of which extends along the second direction and is spaced apart along the first direction; the data signal lines extend to the first frame area and are electrically connected to one of the multiplexing circuits; the same multiplexing circuit is electrically connected to at least two of the data signal lines. In a direction perpendicular to the plane of the substrate, the second structural part and the first power signal supply line are disposed on the same layer. The first structural part, the third structural part and the data signal line are located on the side of the second structural part away from the substrate. In the first direction, between two adjacent first-type first power connection structures, at least a portion of the data signal lines are located between the two ends of the same second structural part. The data signal lines located between the two ends of the same second structural part at least partially overlap with the orthographic projection of the second structural part on the substrate.

11. The display substrate according to claim 4, wherein, The border area further includes a first corner area and a fourth corner area. In a first direction, the first corner area and the fourth corner area are located on both sides of the first border area. In a second direction, the first corner area and the fourth corner area are located on the same side of the display area as the first border area. The first power signal supply line is located in the first border area and extends to the first corner area and the second corner area. The at least part of the first power connection structure includes a plurality of second type first power connection structures, and the at least part of the first power connection line includes a plurality of second type first power connection lines. The plurality of second type first power connection structures correspond one-to-one with the plurality of second type first power connection lines. The second type first power connection structures and the second type first power connection lines are located in the first corner area and the fourth corner area. The plurality of first power connection vias includes a plurality of first-type first power connection vias and a plurality of second-type first power connection vias. The first-type first power connection vias correspond to one of the second-type first power connection structures, and the second-type first power connection vias correspond to one of the second-type first power lines and one of the second-type first power connection structures. In a direction perpendicular to the plane of the substrate, the first power signal supply line and the first power connection line are located on the side of the second-type first power connection structure away from the shielding layer. The second-type first power connection structure is electrically connected to the first power signal supply line through the corresponding first-type first power connection via and electrically connected to the corresponding second-type first power connection line through the corresponding second-type first power connection via.

12. The display substrate according to claim 11, wherein, The at least part of the frame signal line also includes a plurality of second power connection structures, the plurality of connection vias also includes a plurality of second power connection vias, the first signal providing line includes a second power signal providing line, the plurality of first signal lines include a plurality of second power lines, the plurality of second power lines correspond one-to-one with the plurality of second power connection structures and the plurality of second power connection vias, the second power connection structure is connected to the corresponding second power line through the corresponding signal access via, and is electrically connected to the second power signal providing line through the corresponding second power connection via; In the first corner region and the fourth corner region: the first shielding connection structure is located on the side of the plurality of multiplexer circuits away from the display area, the second power signal supply line is located on the side of the plurality of multiplexer circuits close to the display area, the edge of the first power signal supply line close to the display area and the second power signal supply line are stepped, the plurality of second type first power connection structures and the plurality of second type first power connection lines are arranged in a stepped manner along the extension direction of their respective corner regions; in the direction perpendicular to the plane of the base, the second power connection structure and the second power signal supply line are located on the side of the second power line and the first power connection line away from the base.

13. The display substrate according to claim 11, wherein, The first corner region and the fourth corner region are arc-shaped structures. The center of the circle containing the arc-shaped structure is located on the side of the arc-shaped structure closer to the display area. In the first corner region and the fourth corner region: the shape of the first shielding connection structure is consistent with the shape of the corner region in which it is located, and the first shielding connection structure and the orthographic projection of the first power signal supply line on the substrate at least partially overlap.

14. The display substrate according to claim 11, wherein, The border area further includes a second border area, a third border area, and a fourth border area. In the first direction, the third border area and the fourth border area are located on both sides of the display area. In the second direction, the first border area and the second border area are located on both sides of the display area. The first border area and the third border area are connected through the first corner area, and the first border area and the fourth border area are connected through the fourth corner area. At least some of the multiplexer circuits are located in the first corner region and the fourth corner region. In the first corner region and the fourth corner region: the at least some multiplexer circuits are arranged in a stepped manner along the extension direction of the corner region where they are located. Multiple shielding connection lines are interconnected to form multiple first openings. The multiplexer circuits are located in the corresponding first openings. In at least some of the multiple first openings, each first opening accommodates at least one multiplexer circuit. In the first direction, the size of the first opening is the same as the size of m multiplexer circuits. In the second direction, the size of the first opening is the same as the size of n multiplexer circuits, where m and n are positive integers greater than or equal to 1.

15. The display substrate according to claim 14, wherein, The plurality of occlusion connection lines include a plurality of first occlusion connection lines, a plurality of second occlusion connection lines, and a plurality of third occlusion connection lines located in the first corner area and the fourth corner area; In the first corner region and the fourth corner region: the plurality of first blocking connecting lines and the plurality of second blocking connecting lines extend along the first direction and are arranged in a stepped manner along the extension direction of the corner region in which they are located; the plurality of third blocking connecting lines extend along the second direction and are arranged in a stepped manner along the extension direction of the corner region in which they are located; at least a portion of the structure of the third blocking connecting line is located between adjacent first blocking connecting lines and second blocking connecting lines; the first opening is formed by two adjacent third blocking connecting lines in the first direction and adjacent first blocking connecting lines and second blocking connecting lines in the second direction.

16. The display substrate according to claim 15, wherein, In the first corner region and the fourth corner region, two adjacent first blocking connection lines and a neighboring third blocking connection line and two adjacent first blocking structures surround to form a second opening, and two adjacent second blocking connection lines and a first blocking connection structure and a neighboring third blocking connection line surround to form a third opening. Multiple first openings, multiple second openings and multiple third openings are arranged in a stepped manner along the corner region where they are located. The multiple third openings are located on the side of the multiple first openings away from the display area, and the multiple second openings are located on the side of the multiple first openings close to the display area.

17. The display substrate according to claim 15 or 16, wherein, The plurality of first blocking structures form multiple rows. In the first corner area and the fourth corner area, the side of the first blocking connecting line closer to the display area is connected to one row of blocking structures. In the second direction, the distance between two adjacent first blocking connecting lines is the same as the size of a first blocking structure, and the distance between two adjacent second blocking connecting lines is the same as the size of a first blocking structure. The side of the third blocking connecting line closer to the display area is connected to two adjacent rows of first blocking connecting structures through two first blocking connecting lines, and the side farther from the display area is connected to the first blocking connecting structure through two second blocking connecting lines.

18. The display substrate according to claim 15 or 16, wherein, The first opening is rectangular in shape. In the first direction, the distance between two adjacent third blocking connection lines is the same as the size of m multiplex circuits, and the two adjacent third blocking connection lines form a pair of opposite sides of the rectangle. In the second direction, the distance between the first blocking connection line and one of the second blocking connection lines in the direction away from the display area is the same as the size of n multiplex circuits, and the first blocking connection line and the one of the second blocking connection lines form another pair of opposite sides of the rectangle.

19. The display substrate according to claim 18, wherein, n takes the value of 1, and m takes the value of 1 or greater. In the first corner region and the fourth corner region, the value of n is greater when it is closer to the first border region than when it is farther away from the first border region.

20. The display substrate according to claim 18, wherein, In the first border area, multiple first gaps are formed between multiple occlusion connecting lines. The first gap is the distance between two adjacent occlusion connecting lines along the first direction. In the first direction, at least one first gap is greater than the size of the first opening, and at least one first gap is smaller than the size of the first opening.

21. The display substrate according to claim 14, wherein, The shielding layer further includes a second shielding connection structure and a plurality of second shielding structure groups. The second shielding connection structure and the plurality of second shielding structure groups are located in at least one of the third border area and the fourth border area. The plurality of second shielding structure groups located in the same border area are arranged along the direction from the display area to their respective border area. The plurality of second shielding structures in the same second shielding structure group are arranged along the extension direction of their respective border area. The extension direction of the second blocking connection structure is consistent with the extension direction of the border area where it is located. In the same border area, in the direction from the display area to the border area, the second blocking connection structure is located between two adjacent second blocking structure groups, and multiple second blocking structures in two adjacent second blocking structure groups are connected to their adjacent second blocking connection structures.

22. The display substrate according to claim 21, wherein, The shielding layer further includes a third shielding connection structure. At least a portion of the first shielding connection structure and the third shielding connection structure are located in at least one of the third border region and the fourth border region. The extension direction of the third shielding connection structure is consistent with the extension direction of the border region in which it is located. In the same border region, in the direction from the display area to the border region, the third shielding connection structure is located on the side of the plurality of second shielding structure groups closer to the display area. The third shielding connection structure is connected to a plurality of second shielding structures in an adjacent second shielding structure group. In at least one of the third and fourth border regions, in a first direction, the size of the third occlusion connection structure is larger than the size of the second occlusion connection structure, and the size of the second occlusion connection structure is larger than the size of the first occlusion connection structure.

23. The display substrate according to claim 22, wherein, The shielding layer further includes a plurality of fourth shielding connection structures, which are located in at least one of the third and fourth border regions. In the same border region, the plurality of fourth shielding connection structures are located between the first and third shielding connection structures. The plurality of fourth shielding connection structures are arranged at intervals along the extension direction of their respective border regions. The main body of each fourth shielding connection structure extends along the first direction, with one end connected to the third shielding connection structure in its respective border region and the other end connected to the first shielding connection structure.

24. The display substrate according to any one of claims 21 to 23, further comprising a plurality of gate driving circuit groups, wherein the plurality of gate driving circuit groups are located in at least one of the third frame region and the fourth frame region, and the plurality of gate driving circuit groups are arranged along the direction of the display region toward the frame region in which they are located; in the same frame region, at least a portion of the gate driving circuit groups correspond one-to-one with the plurality of second shielding structure groups, the plurality of gate driving circuits in the same gate driving circuit group are arranged along the extension direction of the frame region in which they are located, the plurality of second shielding structures in the second shielding structure group correspond one-to-one with the plurality of gate driving circuits in the corresponding gate driving circuit group, and the orthographic projections of the second shielding structure and the corresponding gate driving circuit on the substrate at least partially overlap.

25. The display substrate according to claim 24, wherein, The gate driving circuit includes a plurality of transistors, and the second shielding structure at least partially overlaps with the orthographic projection of the channel of at least one transistor in the corresponding gate driving circuit onto the substrate.

26. The display substrate according to any one of claims 1 to 16, 21 to 23, wherein, The plurality of shielding connection lines include a plurality of fourth shielding connection lines. The first shielding connection structure is a ring structure surrounding the display area. The plurality of first shielding structures form multiple rows and columns. The plurality of first shielding structures in the same row are interconnected, and the plurality of first shielding structures in the same column are interconnected. The plurality of fourth shielding connection lines extend along a first direction X and are arranged at intervals along the extension direction of the border area in which they are located. In the first direction, the plurality of fourth shielding connection lines are located on both sides of the plurality of first shielding structures and on the side of the first shielding connection structure closer to the display area. The plurality of first shielding structures are connected to the first shielding connection structures on both sides of them through the plurality of fourth shielding connection structures on both sides of them. In at least one row of the multiple rows of first occlusion structures, in a first direction, each row of occlusion structures is connected to the first occlusion connection structure via a fourth occlusion connection line located on both sides of the row of first occlusion structures.

27. The display substrate according to claim 26, wherein, The display area includes multiple sub-pixels, and the multiple first occlusion structures correspond one-to-one with the multiple sub-pixels. At least one of the sub-pixels includes multiple transistors, and the first occlusion structure and the orthographic projection of the channel region of at least one transistor in the corresponding sub-pixel on the substrate at least partially overlap.

28. A display device comprising a display substrate as described in any one of claims 1 to 27.

29. A method for preparing a display substrate, comprising: A shielding layer is formed on one side of a substrate, the substrate including a display area and a border area surrounding the display area, the shielding layer including a plurality of first shielding structures located in the display area, a first shielding connection structure located in the border area and a plurality of shielding connection lines, the first shielding connection structures being located on the side of the plurality of shielding connection lines away from the display area, and the plurality of first shielding structures being connected to the first shielding connection structure through the plurality of shielding connection lines; Multiple connection vias, multiple border signal lines, and multiple working signal lines are formed on the side of the shielding layer away from the substrate layer. The multiple connection vias and the multiple border signal lines are located in the border area, and the multiple working signal lines are located in the display area. The orthographic projection of the first shielding connection structure and the multiple shielding connection lines on the substrate does not overlap with the orthographic projection of the multiple connection vias on the substrate.

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