Display substrate and display device

Abstract

Provided are a display substrate and a display device. The display substrate comprises a base substrate and a first electrode layer, and the first electrode layer comprises a plurality of first electrodes. The orthographic projections of at least some of the first electrodes on the base substrate each have a first projection shape, the first projection shape has a plurality of vertices, the plurality of vertices include a first vertex, a second vertex, a fourth vertex and an sixth vertex that are sequentially connected, and lines connecting the first vertex, the second vertex, the fourth vertex and the sixth vertex form a virtual quadrilateral. The first projection shape also comprises a plurality of protruding portions and a plurality of recessed portions, at least a part of each protruding portion is located outside the virtual quadrilateral, at least a part of each recessed portion has an inwardly recessed structure relative to the virtual quadrilateral, and on a sequential connection path of the plurality of vertices, at least one recessed portion is arranged between two adjacent protruding portions.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are microdisplays that have emerged in recent years. Using mature silicon-based semiconductor processes, high-PPI (pixel density) and high-refresh-rate OLED displays can be fabricated for applications in VR (Virtual Reality) and AR (Augmented Reality). The display panels in these technologies consist of multiple pixel units to achieve high-resolution display effects. However, limitations in high resolution and wiring spacing requirements result in a relatively low pixel aperture ratio. How to maximize the pixel aperture ratio while meeting high resolution and wiring spacing requirements, and ensuring the display substrate's display performance and lifespan, is one of the important research topics for researchers.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In one aspect of this disclosure, a display substrate is provided, comprising:

[0005] Substrate;

[0006] A first electrode layer is located on one side of the substrate. The first electrode layer includes a plurality of first electrodes arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect.

[0007] Wherein, at least a portion of the first electrode has a first projection shape on the substrate, the first projection shape including a plurality of vertices, the plurality of vertices including a first vertex, a second vertex, a fourth vertex and a sixth vertex connected in sequence, and the line connecting the first vertex, the second vertex, the fourth vertex and the sixth vertex forms a virtual quadrilateral;

[0008] The first projected shape further includes: a plurality of protrusions, at least a portion of which is located outside the virtual quadrilateral; and a plurality of recesses, at least a portion of which has an inwardly recessed structure relative to the virtual quadrilateral.

[0009] In particular, on the sequential connection path along the plurality of vertices, at least one recess is provided between two adjacent protrusions.

[0010] According to some exemplary embodiments, the plurality of vertices further includes a third vertex and a fifth vertex, the third vertex being connected to both the second vertex and the fourth vertex, and the fifth vertex being connected to both the fourth vertex and the sixth vertex; the lines connecting the first vertex, the second vertex, the third vertex, the fourth vertex, the fifth vertex, and the sixth vertex form a virtual hexagon; at least a portion of the protrusions are located outside the virtual hexagon, and at least a portion of the recesses have an inward concave structure relative to the virtual hexagon.

[0011] According to some exemplary embodiments, the plurality of protrusions includes: a first protrusion and a second protrusion, a first vertex located on the first protrusion, and a fourth vertex located on the second protrusion and connected to the fourth vertex; and

[0012] The display substrate further includes a pixel defining layer located on the side of the first electrode layer away from the substrate. The pixel defining layer defines a plurality of pixel openings. Each pixel opening includes a pixel opening center and is symmetrical about the pixel opening center. The first protrusion and the second protrusion are located on opposite sides of the pixel opening center.

[0013] According to some exemplary embodiments, the plurality of recesses include: a first recess, a second recess, a third recess, and a fourth recess, wherein the second vertex is located in the first recess; the third vertex is located in the second recess; the fifth vertex is located in the third recess; and the sixth vertex is located in the fourth recess.

[0014] The first recess and the third recess are located on opposite sides of the center of the pixel opening, and the second recess and the fourth recess are located on opposite sides of the center of the pixel opening.

[0015] According to some exemplary embodiments, the display substrate further includes: a driving circuit layer located between the substrate and the first electrode layer; and an insulating layer located between the driving circuit layer and the first electrode layer, the insulating layer including a plurality of first vias, through which the first electrode is electrically connected to a pixel driving circuit located in the driving circuit layer.

[0016] Wherein, the orthographic projection of the first via on the substrate and the orthographic projection of the first protrusion on the substrate at least partially overlap.

[0017] According to some exemplary embodiments, the first electrode layer includes: a first electrode first sub-layer located on one side of the substrate; an interlayer insulating layer located on the side of the first electrode first sub-layer away from the substrate; and a first electrode second sub-layer located on the side of the interlayer insulating layer away from the substrate.

[0018] The interlayer insulating layer includes a plurality of second vias, and the first sub-layer of the first electrode and the second sub-layer of the first electrode are electrically connected through the second vias; and

[0019] The orthographic projection of the second via on the substrate and the orthographic projection of the second protrusion on the substrate at least partially overlap.

[0020] According to some exemplary embodiments, the orthographic projection of the first via on the substrate has a second projection shape, and the orthographic projection of the second via on the substrate has a third projection shape, wherein the second projection shape and the third projection shape include circles, and the diameter of the second projection shape is smaller than the diameter of the third projection shape.

[0021] According to some exemplary embodiments, the diameter of the second projected shape is in the range of 0.2 micrometers to 0.45 micrometers; and / or,

[0022] The diameter of the third projected shape is in the range of 0.35 micrometers to 0.65 micrometers.

[0023] According to some exemplary embodiments, at least a portion of the plurality of protrusions includes an arcuate curved edge; and / or,

[0024] At least a portion of the plurality of said recesses includes an arc-shaped curved edge.

[0025] According to some exemplary embodiments, the arcuate edge of the protrusion has a first radius of curvature, and the arcuate edge of the recess has a second radius of curvature, wherein the first radius of curvature is smaller than the second radius of curvature.

[0026] According to some exemplary embodiments, the first electrode layer includes a plurality of electrode rows extending along the first direction, each electrode row including a plurality of spaced-apart first electrodes, and the plurality of electrode rows including an i-th electrode row and an (i+1)-th electrode row adjacent in the second direction, where i is a positive integer greater than or equal to 1.

[0027] Wherein, the i-th electrode row and the (i+1)-th electrode row are at least partially aligned in the second direction;

[0028] The first protrusions of the plurality of first electrodes located in the i-th electrode row face the (i+1)-th electrode row; and

[0029] The first protrusions of the plurality of first electrodes located in the (i+1)th electrode row face the i-th electrode row.

[0030] According to some exemplary embodiments, the plurality of electrode rows further includes an i+2 electrode row adjacent to the i+1 electrode row in a second direction, wherein the i+2 electrode row and the i+1 electrode row are at least partially aligned in the second direction;

[0031] The second protrusions of the plurality of first electrodes located in the (i+1)th electrode row face the (i+2)th electrode row; and

[0032] The second protrusions of the plurality of first electrodes located in the (i+2)th electrode row face the (i+1)th electrode row.

[0033] According to some exemplary embodiments, the protrusion of the first electrode is located between the recesses of two adjacent first electrodes.

[0034] According to some exemplary embodiments, the display substrate includes a plurality of sub-pixels, the plurality of sub-pixels including a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, the first color sub-pixel emits light of a first wavelength, the second color sub-pixel emits light of a second wavelength, and the third color sub-pixel emits light of a third wavelength, wherein the first wavelength is smaller than the third wavelength and the third wavelength is smaller than the second wavelength.

[0035] The plurality of first electrodes include a first electrode portion, a second electrode portion, and a third electrode portion. The first color sub-pixel includes a first electrode portion, the second color sub-pixel includes a second electrode portion, and the third color sub-pixel includes a third electrode portion. The first electrode portion includes a first interlayer insulating portion located in the interlayer insulating layer, the second electrode portion includes a second interlayer insulating portion located in the interlayer insulating layer, and the third electrode portion includes a third interlayer insulating portion located in the interlayer insulating layer.

[0036] In the third direction, the first interlayer insulating portion has a first thickness, the second interlayer insulating portion has a second thickness, and the third interlayer insulating portion has a third thickness. The third direction is parallel to the light emission direction of the display substrate, and the first thickness is greater than the second thickness, and the second thickness is greater than the third thickness.

[0037] According to some exemplary embodiments, in a first planar direction, the first via is spaced apart from the first vertex by a first spacing distance, the first spacing distance being greater than or equal to 0.15 micrometers, the first planar direction being perpendicular to the light emission direction of the display substrate; and the ratio of the first spacing distance to the spacing distance between the first vertex and the fourth vertex is less than or equal to 1 / 4.

[0038] According to some exemplary embodiments, the pixel defining layer includes: a pixel defining first sub-layer located on the side of the first electrode layer away from the substrate; a pixel defining second sub-layer located on the side of the pixel defining first sub-layer away from the substrate; and a pixel defining third sub-layer located on the side of the pixel defining second sub-layer away from the substrate.

[0039] Wherein, the pixel-defined second sub-layer is recessed relative to the pixel-defined first sub-layer and the pixel-defined third sub-layer in a direction away from the pixel opening; and

[0040] In the same sub-pixel, in the first planar direction, the first via and the pixel define a second spacing distance between the side of the second sub-layer near the pixel opening, the second spacing distance being greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer.

[0041] According to some exemplary embodiments, in the same sub-pixel, in the second planar direction, the pixel opening is separated from the side of the first electrode by a third spacing distance, the third spacing distance being greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer, and the second planar direction is perpendicular to the light emission direction of the display substrate and intersects with the first planar direction.

[0042] According to some exemplary embodiments, in the third plane direction, two adjacent first electrodes are spaced by a fourth spacing distance, the fourth spacing distance being greater than or equal to 0.25 micrometers and less than or equal to 1 micrometer. The third plane direction is perpendicular to the light emission direction of the display substrate, and the third plane direction intersects both the first plane direction and the second plane direction.

[0043] According to some exemplary embodiments, in a first planar direction, the second via is spaced a fifth interval distance from the fourth vertex, the fifth interval distance being greater than or equal to 0.15 micrometers, the first planar direction being perpendicular to the light emission direction of the display substrate; and the ratio of the fifth interval distance to the interval distance between the first vertex and the fourth vertex is less than or equal to 1 / 4.

[0044] According to some exemplary embodiments, in the same sub-pixel, in the first planar direction, the second via is separated from the pixel opening by a sixth spacing distance, the sixth spacing distance being greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer.

[0045] According to some exemplary embodiments, in the same first electrode, the area of ​​the first protrusion is smaller than the area of ​​the second protrusion; and / or,

[0046] The first vertex is spaced a seventh interval distance from the center of the pixel opening, and the fourth vertex is spaced an eighth interval distance from the center of the pixel opening, wherein the seventh interval distance is less than the eighth interval distance.

[0047] According to some exemplary embodiments, at least one of the first protrusion and the second protrusion has a rectangular shape.

[0048] According to some exemplary embodiments, at least a portion of the sidewalls of the protrusion include straight lines; and / or,

[0049] At least a portion of the recessed portion has straight sides; and

[0050] In the fourth plane direction, the distance between the side of the protrusion and the side of the recess is greater than or equal to 0.25 micrometers and less than or equal to 1 micrometer, and the fourth plane direction is perpendicular to the light emission direction of the display substrate.

[0051] In another aspect of this disclosure, a display device is provided, comprising a display substrate as described in any of the preceding claims. Attached Figure Description

[0052] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0053] Figure 1 is a plan view of a display substrate according to an embodiment of the present disclosure;

[0054] Figure 2 is a schematic diagram of the cross section taken along line AA' in Figure 1;

[0055] Figure 3 is a schematic diagram of the structure of a light-emitting device according to an embodiment of the present disclosure;

[0056] Figure 4 is a partial plan view of a display substrate according to an embodiment of the present disclosure;

[0057] Figure 5 is a schematic diagram of the cross section taken along line BB' in Figure 4;

[0058] Figure 6 is a schematic diagram of the cross section taken along line CC' in Figure 4;

[0059] Figure 7 is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0060] Figure 8 is a partial planar schematic diagram of a display substrate according to an embodiment of the present disclosure, showing a first electrode, a first via, a second via, and a pixel opening;

[0061] Figure 9 is a partial plan view of the first electrode according to an embodiment of the present disclosure;

[0062] Figures 10A and 10B are enlarged schematic diagrams of a first electrode, a first via, a second via, and a pixel opening in a single sub-pixel according to some embodiments of the present disclosure.

[0063] Figure 11 is a partial planar schematic diagram of a display substrate according to an embodiment of the present disclosure, showing a first electrode, a first via, a second via, and a pixel opening;

[0064] Figures 12A and 12B are schematic diagrams comparing pixel aperture sizes of display substrates with different first electrode shapes according to embodiments of the present disclosure.

[0065] Figure 13 is a partial arrangement diagram of the first electrode according to some embodiments of the present disclosure;

[0066] Figure 14 is a partial arrangement diagram of the first electrode according to some other embodiments of the present disclosure;

[0067] Figure 15 is a schematic structural diagram of a display panel provided according to some embodiments of the present disclosure; and

[0068] Figure 16 is a schematic diagram of the structure of a display device provided according to some embodiments of the present disclosure.

[0069] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of the present invention may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0071] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0072] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0073] In this document, unless otherwise specified, directional terms such as "up," "down," "left," "right," "inner," and "outer" are used to indicate orientation or positional relationships based on the accompanying drawings, and are used only for the convenience of describing this disclosure, and are not intended to indicate or imply that the device, element, or component referred to must have a specific orientation, or be constructed or operated in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationships they represent may also change accordingly. Therefore, these directional terms should not be construed as limitations on this disclosure.

[0074] In this document, the directional terms "first direction" and "second direction" are used to describe different orientations of the display substrate or display panel, such as the row and column directions of pixel units. It should be understood that such representations are merely exemplary descriptions and not limitations of this disclosure.

[0075] In this document, unless otherwise stated, the term "electrical connection" can mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and an electrical signal can be transmitted between them; it can also mean that two components or elements are electrically connected through a conductive medium, such as a conductive wire, for example, component or element A is electrically connected to component or element B through a conductive wire to transmit an electrical signal between the two components or elements; it can also mean that two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin-film transistor to transmit an electrical signal between the two components or elements.

[0076] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0077] The technical terms used in this disclosure are briefly described below to help those interested in the subject matter better understand this solution.

[0078] Gamma adjustment: Gamma adjustment involves modifying parameters such as brightness and color of the display panel to achieve optimal display performance. Gamma value is a parameter that measures the relationship between a monitor's brightness and its input voltage; it significantly impacts color reproduction and contrast. Due to variations in the manufacturing process, environmental factors, and monitor aging, the display panel's gamma value may deviate from the ideal value, leading to issues such as color distortion and insufficient contrast. Therefore, performing gamma adjustment is a crucial step in optimizing the display panel's performance.

[0079] Distortion: Due to the significant height difference at the partition structure, the vapor-deposited material film in the OLED device may experience rapid changes in film morphology at the partition structure, resulting in distortion. It should be understood that the probability of leakage current is higher at distorted locations.

[0080] OLED display panels are widely used in various display products due to their advantages such as self-emissiveness, low power consumption, wide color gamut, wide viewing angle, and short response time. In particular, silicon-based organic light-emitting microdisplay panels (Micro-OLED display panels), which have the characteristics of small pixel size and high pixel density, have wide applications in military applications, display products for augmented reality (AR) and virtual reality (VR) technologies, and autonomous driving.

[0081] Compared to conventional displays, silicon-based microdisplays boast ultra-high resolutions, typically between 3000 and 5000 PPI (pixels per inch). This dictates the precision of their critical dimension (CD), with the smallest controllable CD around 0.1 micrometers. Traditional fine metal masks (FMMs) can achieve a maximum PPI of around 800, meaning it's difficult to use the side-by-side (SBS) method for OLED deposition in silicon-based OLEDs. Consequently, silicon-based OLED microdisplays generally employ white light-emitting devices. Current silicon-based Micro-OLED displays mostly utilize a structure of white light-emitting devices plus a color film (CF) to achieve full-color display.

[0082] Some silicon-based OLED microdisplays use a single light-emitting layer to achieve white light emission. Their light-emitting layer architecture uses a combination of different light-emitting materials to achieve white light. Their module brightness is generally between 80-600 nits, which is considered a medium-low brightness display. If this single-layer structure is used to achieve high brightness (greater than 1000 nits), power consumption and lifespan will be sacrificed.

[0083] To improve the performance, brightness, and lifespan of silicon-based OLED microdisplays, some silicon-based OLED microdisplays employ stacked OLED devices comprising two or more light-emitting layers. Stacked OLED devices utilize a charge-generating layer to connect two upper and lower light-emitting units in series, achieving a superimposed light emission effect on the device, which can improve current efficiency, output brightness, and display product lifespan. However, in addition to connecting two upper and lower light-emitting units in series, the charge-generating layer in stacked OLEDs also has strong lateral transmission capabilities, easily causing color crosstalk between pixels. Therefore, other methods are needed to separate the charge-generating layer and OLED pixels. For example, separation methods may include, but are not limited to, high separator pillars, inter-pixel vias, and undercut structures. However, these separations can cause punctures in the cathode morphology, forming leakage paths, resulting in a decrease in the luminous efficiency of light-emitting devices (e.g., blue light-emitting devices), and a loss in the overall device luminous efficiency.

[0084] In some embodiments, full-color display is achieved by using three-color color filter layers in conjunction with a white OLED light-emitting device. However, the transmittance of the current color filter layers is only about 20%, especially the blue filter layer, which often has a transmittance of less than 20%. Therefore, when fabricating OLED devices, it is necessary to prioritize improving the efficiency of blue light. Furthermore, during the subsequent electrical tuning after module fabrication, it is necessary to perform Gamma tuning on the RGB pixels, giving the RGB pixels different current densities to ensure that the final synthesized white light color point is around (0.31, 0.33).

[0085] Due to the ultra-high resolution of silicon-based display substrates, the pixel size is too small, with a single pixel size of approximately 2.0µm to 8µm. Therefore, it is difficult to use the FMM (Front-Mounted Mirror) method for OLED deposition on silicon-based OLEDs. Furthermore, the structure of a white light-emitting device with a color filter layer deposited over the entire surface suffers from significant brightness loss because the color filter layer has a transmittance of only about 20%, resulting in a bottleneck in the upper limit of product brightness.

[0086] This disclosure provides a display substrate. Specifically, the display substrate includes: a substrate; and a first electrode layer located on one side of the substrate. The first electrode layer includes a plurality of first electrodes arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting. At least a portion of the first electrodes have a first projection shape on the substrate. The first projection shape includes a plurality of vertices, including a first vertex, a second vertex, a third vertex, a fourth vertex, a fifth vertex, and a sixth vertex connected sequentially. The lines connecting the first vertex, the second vertex, the third vertex, the fourth vertex, the fifth vertex, and the sixth vertex form a virtual hexagon. The first projection shape further includes: a plurality of protrusions, at least a portion of which is located outside the virtual hexagon; and a plurality of recesses, at least a portion of which has an inwardly recessed structure relative to the virtual hexagon. At least one recess is provided between two adjacent protrusions along the sequential connection path of the plurality of vertices.

[0087] By designing the first electrode in an irregular shape, sufficient wiring space can be provided for the connection vias between the first electrode and the underlying driving circuit layer, and / or for the connection vias within the first electrode layer, which is beneficial for improving the pixel aperture ratio. This design, on the one hand, helps to improve the brightness of the display panel, giving the display substrate more room for Gamma adjustment; on the other hand, at the same brightness, a lower driving voltage can be used, which helps to extend the lifespan of the display substrate.

[0088] Figure 1 is a plan view of a display substrate according to an embodiment of the present disclosure.

[0089] Exemplary examples, in some embodiments of this disclosure, referring to FIG1, show substrate 100 includes substrate 1. Substrate 1 includes a display area AA and a non-display area NA. Show substrate 100 includes a plurality of sub-pixels SP located in display area AA, the plurality of sub-pixels SP being arranged in an array along a first direction X and a second direction Y.

[0090] For example, the display substrate 100 further includes a plurality of first electrodes 20, such as the first electrodes 20 being the anodes of light-emitting devices in the sub-pixels SP. The plurality of first electrodes 20 are arranged in an array along a first direction X and a second direction Y. The display substrate 100 also includes a pixel defining layer PDL located on the side of the first electrodes 20 away from the substrate 1, the pixel defining layer PDL having a plurality of pixel openings VH. The plurality of pixel openings VH define the light-emitting regions of the plurality of sub-pixels SP.

[0091] For example, the orthographic projection of the pixel defining layer PDL on the substrate at least partially overlaps with the orthographic projection of the plurality of first electrodes 20 on the substrate, such that the first electrodes 20 of adjacent sub-pixels SP are disconnected from each other. The orthographic projections of the plurality of pixel openings VH on the substrate fall within the orthographic projections of the plurality of first electrodes 20 on the substrate, defining the light-emitting area of ​​the sub-pixel SP.

[0092] For example, a plurality of first electrodes 20 correspond one-to-one with a plurality of sub-pixel SP positions, and the area of ​​the first electrode 20 is larger than the light-emitting area of ​​the sub-pixel.

[0093] Figure 2 is a schematic diagram of the cross section taken along line AA' in Figure 1.

[0094] Exemplary examples, in some embodiments of this disclosure, referring to Figures 1 and 2, show that the substrate 100 includes a substrate 1 and a first electrode layer 2 disposed on the substrate 1. The first electrode layer 2 may include a plurality of first electrodes 20 disposed at intervals.

[0095] The display substrate 100 may further include: a pixel defining layer PDL located on the side of the first electrode layer 2 away from the substrate, the pixel defining layer defining a plurality of pixel openings VH; a light-emitting functional layer 3 located on the side of the pixel defining layer PDL away from the substrate 1; a second electrode layer 4 located on the side of the light-emitting functional layer 3 away from the substrate 1; and an encapsulation layer 5 located on the side of the second electrode layer 4 away from the substrate 1. For example, the second electrode layer 4 may be the cathode of a light-emitting device.

[0096] In some embodiments, the encapsulation layer 5 may include a plurality of sub-encapsulation layers stacked sequentially away from the substrate 1. For example, the encapsulation layer 5 may include a first sub-encapsulation layer 51, a second sub-encapsulation layer 52, and a third sub-encapsulation layer 53. For example, the material of the first sub-encapsulation layer 51 may include an inorganic material, the material of the second sub-encapsulation layer 52 may include an organic material, and the material of the third sub-encapsulation layer 53 may include an inorganic material. By alternating between inorganic and organic materials, the ability of the encapsulation layer 5 to isolate water and oxygen can be improved, thereby increasing the lifespan of the display substrate.

[0097] In some embodiments, the substrate 1 may be a silicon substrate. The light-emitting device in the display substrate 100 may be an OLED light-emitting device. To improve the efficiency, brightness, and lifespan of the light-emitting device, the OLED light-emitting device may include an OLED device employing a stacked design.

[0098] For example, a stacked OLED device structure includes two or more light-emitting layers, which are connected in series by charge-generating layers (CGLs) to improve the luminous efficiency of the device. For instance, in a silicon-based OLED device, a yellow light-emitting layer and a blue light-emitting layer can be connected in series, or a red-green light-emitting layer and a blue light-emitting layer can be connected in series to form white light.

[0099] For example, continuing to refer to FIG2, the display substrate may further include: a planarization layer 6 located on the side of the encapsulation layer 5 away from the substrate; and a color filter layer 7 located on the side of the planarization layer 6 away from the substrate.

[0100] For example, the color filter layer 7 may include multiple color filter structures of different colors. For instance, the color filter layer 7 may include a first color filter structure 71, a second color filter structure 72, and a third color filter structure 73. For example, the first color filter structure 71 may include a red filter film, the second color filter structure 72 may include a green filter film, and the third color filter structure 73 may include a blue filter film. By combining a white OLED light-emitting device with the color filter layer 7, three colors of light can be formed, thereby achieving color display.

[0101] However, in some cases, the low transmittance of the color filter layer 7 results in a significant loss of light output brightness in the display substrate.

[0102] In some embodiments, continuing to refer to FIG2, the display substrate further includes: an optical adhesive layer 8 located on the side of the color filter layer 7 away from the substrate; and a lens layer 9 located on the side of the optical adhesive layer 8 away from the substrate. Exemplarily, the lens layer 9 includes a plurality of lens structures 91, for example, the shape of the lens structures 91 includes a hemispherical shape. By providing the lens layer, light emitted by the light-emitting device can be extracted (e.g., reducing total internal reflection at the film interface), which is beneficial to improving the luminous efficiency and brightness of the display substrate.

[0103] Figure 3 is a schematic diagram of the structure of a light-emitting device according to an embodiment of the present disclosure.

[0104] In some embodiments, to improve the brightness of the light-emitting device, the display substrate may employ a stacked structure design. Referring to FIG3, the light-emitting functional layer 3 may include a plurality of film layers stacked sequentially away from the substrate. For example, the light-emitting functional layer 3 may include: a first light-emitting functional layer 31, for example, the first light-emitting functional layer 31 is a hole injection layer; a second light-emitting functional layer 32, for example, the second light-emitting functional layer 32 is a hole transport layer; a third light-emitting functional layer 33, for example, the third light-emitting functional layer 33 is a red organic light-emitting layer; a fourth light-emitting functional layer 34, for example, the fourth light-emitting functional layer 34 is a green organic light-emitting layer; a fifth light-emitting functional layer 35, for example, the fifth light-emitting functional layer 35 is a CGL electron transport layer; a sixth light-emitting functional layer 36, for example, the sixth light-emitting functional layer 36 is a charge generation layer CGL; a seventh light-emitting functional layer 37, for example, the seventh light-emitting functional layer 37 is a hole injection layer; an eighth light-emitting functional layer 38, for example, the eighth light-emitting functional layer 38 is a hole transport layer; a ninth light-emitting functional layer 39, for example, the ninth light-emitting functional layer 39 is a blue organic light-emitting layer; a tenth light-emitting functional layer 310, for example, the tenth light-emitting functional layer 310 is an electron transport layer; and an eleventh light-emitting functional layer 311, for example, the eleventh light-emitting functional layer 311 is an electron injection layer.

[0105] In some embodiments, the charge generation layer CGL may include an N-type charge generation layer and a P-type charge generation layer.

[0106] It should be noted that although the embodiments of this disclosure schematically show that the light-emitting functional layer 3 in the stacked OLED device includes the first light-emitting functional layer 31 to the eleventh light-emitting functional layer 311, the embodiments of this disclosure are not limited to this. The light-emitting functional layer of this disclosure can be designed according to actual needs, and some film layers can be reduced or some film layers can be added.

[0107] It should also be noted that although the embodiments of this disclosure schematically illustrate a dual-layer OLED light-emitting device including a charge-generating layer and two light-emitting layers located on both sides of the charge-generating layer, the embodiments of this disclosure are not limited thereto. The light-emitting functional layer of this disclosure may also include a greater number of charge-generating layers and a greater number of light-emitting layers located between the charge-generating layers or between the charge-generating layers and the upper and lower electrodes (e.g., anode and cathode), thereby forming a multi-layer stacked OLED light-emitting device. For example, the stacked OLED light-emitting device may include a triple-layer, quadruple-layer, or more stacked OLED light-emitting device.

[0108] In stacked OLED devices, due to the high conductivity of the charge generation layer CGL, when the charge generation layers between adjacent pixels are not separated, lateral crosstalk between pixels is likely to occur, which may also cause leakage loss and affect the brightness of the light-emitting device.

[0109] In some embodiments, in order to reduce or eliminate lateral crosstalk in the charge generation layer CGL, the pixel confinement layer adopts an undercut structure design, thereby improving the isolation effect of the pixel confinement layer.

[0110] Figure 4 is a partial plan view of a display substrate according to an embodiment of the present disclosure, Figure 5 is a cross-sectional view taken along line BB' in Figure 4, and Figure 6 is a cross-sectional view taken along line CC' in Figure 4.

[0111] For example, referring to Figures 4 and 5, the display substrate may further include a driving circuit layer 10 located between the substrate 1 and the first electrode layer 2, the driving circuit layer 10 including a plurality of pixel driving circuits 101.

[0112] Exemplarily, the display substrate may further include an insulating layer 11 located between the driving circuit layer 10 and the first electrode layer 2. The pixel driving circuit 101 can be connected to the first electrode 20 through a conductive connection portion 102 penetrating the insulating layer 11, thereby enabling driving control of the light-emitting device. Exemplarily, the conductive connection portion 102 may include tungsten metal.

[0113] For example, the insulating layer 11 includes a plurality of first vias VO1, and at least a portion of the conductive connection portion 102 is located in the first vias VO1.

[0114] In some embodiments, referring to FIG5, the side L201 of the first electrode 20 away from the pixel opening VH protrudes a first protrusion distance d10 relative to the first via VO1 in a direction away from the pixel opening VH. For example, the first protrusion distance d10 is greater than or equal to 0.15 micrometers. With this design, it can be ensured that the conductive connection portion 102 and the first electrode 20 have sufficient contact area, which is beneficial to improving the electrical connection effect between the conductive connection portion 102 and the first electrode 20.

[0115] In some embodiments, the side PDL11 of the pixel definition layer PDL that is close to the pixel opening protrudes a certain distance relative to the side L201 of the first electrode 20 that is far from the pixel opening in the direction of approaching the pixel opening VH, thereby ensuring that the edge region of the first electrode is covered by the pixel definition layer PDL, so that the pixel definition layer PDL can define multiple pixel openings VH.

[0116] In some embodiments, continuing to refer to FIG5, the pixel defining layer PDL may include multiple film layers. For example, the pixel defining layer PDL may include: a pixel defining first sub-layer PDL1 located on the side of the first electrode layer 2 away from the substrate; a pixel defining second sub-layer PDL2 located on the side of the pixel defining first sub-layer PDL1 away from the substrate; and a pixel defining third sub-layer PDL3 located on the side of the pixel defining second sub-layer PDL2 away from the substrate. The multiple film layers in the pixel defining layer PDL can be used to form an undercut structure UDC. For example, the pixel defining second sub-layer PDL2 is recessed relative to the pixel defining first sub-layer PDL1 and the pixel defining third sub-layer PDL3 in a direction away from the pixel opening VH to form the undercut structure UDC. For example, the pixel defining second sub-layer PDL2 is recessed relative to the pixel defining third sub-layer PDL3 in a direction away from the pixel opening VH by a fifth recess distance d50, where the fifth recess distance d50 is in the range of 0.05 micrometers to 0.06 micrometers.

[0117] By designing an undercut structure UDC in the pixel limiting layer (PDL), the charge generation layer (CGL) between adjacent pixels can be disconnected at the undercut structure UDC, thereby reducing lateral crosstalk between pixels and improving the display effect of the display substrate.

[0118] In some embodiments, multiple undercut structures can be provided in the region near the pixel opening VH in the pixel limiting layer PDL to further improve the isolation effect of the pixel limiting layer, which is beneficial to reduce the leakage probability of the display substrate and improve the display effect of the display substrate.

[0119] In some embodiments of this disclosure, the display substrate may employ a microcavity design, which allows for the control of the brightness of sub-pixels of different colors, thereby achieving a better display effect.

[0120] By way of example, referring to Figures 2 and 6, the display substrate further includes a reflective layer 15 located between the substrate 1 and the first electrode layer 2. The reflective layer 15 may include a single layer of metal or a stack of multiple metals. For example, the reflective layer 15 may include a stack of titanium and aluminum.

[0121] For example, for at least one sub-pixel, assuming the spacing between the reflective layer 15 and the second electrode layer 4 in the sub-pixel is h, when the spacing h between the reflective layer 15 and the second electrode layer 4 in the light-emitting region satisfies:

[0122] Where h is the cavity length, n is a positive integer, N is the effective refractive index in the microcavity, and λ is the center wavelength of the corresponding sub-pixel, the luminous intensity of the sub-pixel can be enhanced. Therefore, by adjusting the spacing h between the reflective layer 15 and the second electrode layer 4, the luminous intensity of the sub-pixel can be adjusted.

[0123] For example, the first electrode layer 2 can adopt a stacked design. The first electrode layer 2 may include: a first electrode first sub-layer 21 located on one side of the substrate; an interlayer insulating layer 22 located on the side of the first electrode first sub-layer 21 away from the substrate; and a first electrode second sub-layer 23 located on the side of the interlayer insulating layer 22 away from the substrate. The interlayer insulating layer 22 can serve as a microcavity adjustment layer. By optimizing the thickness of the interlayer insulating layer 22 for different sub-pixels, the spacing h between the reflective layer 15 and the second electrode layer 4 of different sub-pixels can be adjusted, thereby adjusting the luminous intensity of the sub-pixels and improving the display effect of the display panel.

[0124] For example, the material of the first sub-layer 21 of the first electrode may include metals such as silver and aluminum, or alloys such as magnesium-aluminum alloys and magnesium-silver alloys. The material of the interlayer insulating layer 22 may include silicon oxide. The material of the second sub-layer 23 of the first electrode may include transparent conductive materials such as ITO. The material of the second electrode layer 4 may include metals such as silver and aluminum, or alloys such as magnesium-aluminum alloys and magnesium-silver alloys.

[0125] For example, referring to FIG6, the display substrate includes a plurality of sub-pixels, the plurality of sub-pixels including a first color sub-pixel sp1, a second color sub-pixel sp2, and a third color sub-pixel sp3. The first color sub-pixel sp1 emits light of a first wavelength, the second color sub-pixel sp2 emits light of a second wavelength, and the third color sub-pixel sp3 emits light of a third wavelength, wherein the first wavelength is less than the third wavelength, and the third wavelength is less than the second wavelength. For example, the first wavelength of light includes blue light, that is, the first color sub-pixel sp1 is a blue sub-pixel; the second wavelength of light includes red light, that is, the second color sub-pixel sp2 is a red sub-pixel; and the third wavelength of light includes green light, that is, the third color sub-pixel sp3 is a green sub-pixel.

[0126] For example, the plurality of first electrodes 20 include a first electrode portion 2001, a second electrode portion 2002, and a third electrode portion 2003. A first color sub-pixel sp1 includes the first electrode portion 2001, a second color sub-pixel sp2 includes the second electrode portion 2002, and a third color sub-pixel sp3 includes the third electrode portion 2003. The first electrode portion 2001 includes a first interlayer insulating portion 221 located in the interlayer insulating layer, the second electrode portion 2002 includes a second interlayer insulating portion 222 located in the interlayer insulating layer, and the third electrode portion 2003 includes a third interlayer insulating portion 223 located in the interlayer insulating layer.

[0127] In the third direction Z, the first interlayer insulating portion 221 has a first thickness h1, the second interlayer insulating portion 222 has a second thickness h2, and the third interlayer insulating portion 223 has a third thickness h3. The third direction Z is parallel to the light emission direction of the display substrate. For example, the first thickness h1 is greater than the second thickness h2, and the second thickness h2 is greater than the third thickness h3.

[0128] By optimizing the design of the thickness of the interlayer insulation portion in sub-pixels of different colors, the light emission intensity of the sub-pixels can be improved, thereby enhancing the brightness of the display substrate.

[0129] Since the interlayer insulating layer 22 is an insulating material, in order to achieve electrical connection between the first sublayer 21 of the first electrode and the second sublayer 23 of the first electrode, multiple second vias VO2 need to be formed in the interlayer insulating layer 22, thereby forming the stacked first electrode layer 2.

[0130] In some embodiments, since the distance between the first via VO1 and / or the second via VO2 and the pixel opening VH is too close, the unevenness of the first via VO1 and / or the second via VO2 may further increase the step difference of the film layer in the region where the undercut structure adjacent to the pixel opening is located, causing distortion of part of the film layer (e.g., cathode) in this region, thereby resulting in lateral leakage and reduced luminous efficiency of the light-emitting device.

[0131] Figure 7 is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure.

[0132] For example, in some embodiments, referring to FIG7, when the film layer step difference near the pixel opening VH region is large, the upper part of the film layer may be distorted, for example, the second electrode layer 4 may have a puncture 41. For example, the distance d5 between the puncture 41 in the second electrode layer 4 and the lower first electrode layer 20 is smaller than the distance d2 between the main body portion 42 in the second electrode layer and the lower first electrode layer 20, for example, d5 / d2 is about 0.7. This may cause the lateral resistance to be less than the forward resistance, and the current can more easily flow from the side to the second electrode layer.

[0133] For example, d2 is in the range of 1000 nm to 3000 nm, the vertical distance d3 between the puncture 41 and the first electrode layer 20 is about 400 nm, the horizontal spacing distance d4 between the puncture 41 and the side of the second electrode 20 away from the pixel opening is about 550 nm, and d5 is about 680 nm.

[0134] In some display substrates employing a dual-layer OLED structure, referring to Figures 3 and 7, the blue light-emitting layer is located above the red and green light-emitting layers. For example, the third light-emitting functional layer 33 is a red organic light-emitting layer, the fourth light-emitting functional layer 34 is a green organic light-emitting layer, and the ninth light-emitting functional layer 39 is a blue organic light-emitting layer. This makes the blue light-emitting layer more susceptible to the puncture effect in the second electrode layer than the red light-emitting layer, forming a leakage path. This reduces the blue light-emitting efficiency, further widening the light emission difference between the red, green, and blue pixels, and further narrowing the maximum brightness range that can be adjusted by Gamma.

[0135] For example, in a high-resolution display substrate, due to the limitation of wiring space, the pixel aperture VH and the first via VO1, as well as the pixel aperture VH and the second via VO2, are close to each other. The undercut structure UDC is arranged adjacent to the pixel aperture VH. Therefore, the flatness of the film layer in the region near the first via VO1 and / or the second via VO2 has a significant impact on the blocking effect of the undercut structure UDC. For example, when the region near the first via VO1 and / or the second via VO2 is too close to the pixel aperture, the unevenness of the film layer in the region near the first via VO1 and / or the second via VO2 may cause damage or even collapse of the undercut structure above, thus resulting in the inability to achieve the pixel blocking effect.

[0136] To balance the electrical connection between the conductive connection 102 and the first electrode layer 2, the electrical connection within the first electrode layer, and the isolation effect of the undercut structure UDC, the spacing between multiple components, such as the first via VO1, the second via VO2, the pixel opening VH, and the side of the first electrode, needs to be optimized. For example, referring to Figure 5, to avoid the conductive connection 102 in the area where the first via VO1 is located from adversely affecting the adjacent undercut structure, the first via VO1 and the undercut structure UDC are spaced at a certain distance. For example, the spacing D2 between the first via VO1 and the side PDL21 near the pixel opening in the second sub-layer PDL2 defined by the pixel is greater than or equal to 0.2 micrometers.

[0137] This design reduces the impact of the conductive connection portion 102 located in the first via VO1 on the undercut structure UDC, thereby improving the pixel separation effect of the display substrate.

[0138] The inventors discovered that when the first electrode adopts a regular shape design, such as a square, rectangle, triangle, rhombus, or polygon, to avoid poor contact, UDC collapse, or cathode puncture, the spacing between multiple components, including the first via, the second via, the pixel opening, and the side of the first electrode, needs to be greater than a certain range. This ensures that the corresponding electrical connection effect is achieved through the first and / or second vias while minimizing the impact on the isolation effect of the undercut structure. However, this may result in a smaller pixel opening size, leading to a lower aperture ratio of the display substrate, which in turn results in a lower maximum brightness and a reduced Gamma adjustment range.

[0139] In order to balance the yield of the display substrate and ensure a safe distance between multiple components such as the first via, the second via, the pixel aperture, and the side of the first electrode, while maximizing the aperture ratio of the display substrate, the first electrode in some embodiments of this disclosure adopts an irregular shape design, with at least two protrusions in the first electrode. The first via and the second via are offset towards the positions of the two protrusions, respectively. This allows for the increase of the pixel aperture size while ensuring a safe distance between multiple components such as the first via, the second via, the pixel aperture, and the side of the first electrode, thereby increasing the pixel aperture ratio and the maximum adjustable brightness of the display substrate.

[0140] Figure 8 is a partial plan view of a display substrate according to an embodiment of the present disclosure, showing a first electrode, a first via, a second via, and a pixel opening. Figure 9 is a partial plan view of a first electrode according to an embodiment of the present disclosure. Figures 10A and 10B are enlarged schematic diagrams of the first electrode, the first via, the second via, and the pixel opening in a single sub-pixel according to some embodiments of the present disclosure.

[0141] Exemplarily, in embodiments of this disclosure, referring to Figures 6 and 8, a plurality of first electrodes 20 are arranged in an array in a first direction X and a second direction Y. At least a portion of the sub-pixels include a first electrode 20, a first via VO1, a second via VO2, and a pixel opening VH. Exemplarily, the first via VO1 can be used to realize the electrical connection between the first electrode 20 and the pixel driving circuit 101. The second via VO2 can be an in-layer via of the first electrode. For example, referring to Figure 6, the first electrode includes a first sub-layer 21, an interlayer insulating layer 22, and a second sub-layer 23, and the second via VO2 can be located in the interlayer insulating layer 22.

[0142] For example, the orthographic projection of the first via VO1 onto the substrate has a second projection shape, which includes a circle. For instance, the first via VO1 may include a tungsten via, where "tungsten via" refers to filling the first via VO1 with tungsten metal to form a conductive connection post 102.

[0143] Exemplarily, the orthogonal projection of the second via VO2 onto the substrate has a third projection shape, which includes a circle. Exemplarily, the second via VO2 includes silicon oxide vias, where "silicon oxide via" refers to the interlayer insulating layer 22 being made of silicon oxide, and the plurality of second vias VO2 formed in the interlayer insulating layer 22 are silicon oxide vias.

[0144] For example, referring to FIG8, the diameter d11 of the second projection shape is smaller than the diameter d12 of the third projection shape.

[0145] According to some exemplary embodiments, the diameter d11 of the second projected shape is in the range of 0.2 micrometers to 0.45 micrometers. For example, the diameter d11 of the second projected shape can be approximately 0.2 micrometers, 0.25 micrometers, 0.3 micrometers, 0.4 micrometers, or 0.45 micrometers.

[0146] For example, the diameter d12 of the third projected shape is in the range of 0.35 micrometers to 0.65 micrometers. For instance, the diameter d12 of the third projected shape can be approximately 0.35 micrometers, 0.4 micrometers, 0.48 micrometers, 0.55 micrometers, or 0.65 micrometers.

[0147] This design improves the electrical connection between the first electrode and the pixel driving circuit, as well as the internal electrical connection of the first electrode.

[0148] For example, referring to FIG10A, at least a portion of the first electrode 20 has a first projection shape on the substrate. The first projection shape includes a plurality of vertices, including a first vertex P1, a second vertex P2, a fourth vertex P4, and a sixth vertex P6 connected in sequence. The lines connecting the first vertex P1, the second vertex P2, the fourth vertex P4, and the sixth vertex P6 form a virtual quadrilateral M1.

[0149] For example, the first projected shape further includes a plurality of protrusions 210. For instance, the plurality of protrusions 210 include a first protrusion 201 and a second protrusion 202. At least a portion of the protrusions is located outside the virtual quadrilateral M1.

[0150] For example, the first projected shape further includes a plurality of recesses 220. At least a portion of the recesses has a concave structure relative to the virtual quadrilateral M1. Here, "concave structure" means that at least a portion of the recesses 220 are located within the virtual quadrilateral M1, and that there is a blank area between the recesses 220 and the virtual quadrilateral M1 that is not partially covered by the first electrode 20.

[0151] For example, in a sequential connection path along multiple vertices, at least one recess is provided between two adjacent protrusions. For instance, the sequential connection path of multiple vertices includes a path in which the first vertex P1, the second vertex P2, the fourth vertex P4, and the sixth vertex P6 are connected in sequence.

[0152] For example, referring to FIG10B, the plurality of vertices may further include a third vertex P3 and a fifth vertex P5. The third vertex P3 is connected to both the second vertex P2 and the fourth vertex P4. The fifth vertex P5 is connected to both the fourth vertex P4 and the sixth vertex P6. The lines connecting the first vertex P1, the second vertex P2, the third vertex P3, the fourth vertex P4, the fifth vertex P5, and the sixth vertex P6 form a virtual hexagon M0.

[0153] For example, the first projected shape further includes a plurality of protrusions 210. For instance, the plurality of protrusions 210 include a first protrusion 201 and a second protrusion 202. At least a portion of the protrusions is located outside the virtual hexagon M0.

[0154] For example, the first projected shape further includes a plurality of recesses 220. For instance, the plurality of recesses 220 include: a first recess 203, a second recess 204, a third recess 205, and a fourth recess 206. At least a portion of the recesses has a concave structure relative to the virtual hexagon M0. Here, "concave structure" refers to at least a portion of the recess 220 being located within the virtual hexagon, and the space between the recess and the virtual hexagon including a partially uncovered blank area not covered by the first electrode 20.

[0155] For example, in a sequential connection path along multiple vertices, at least one recess is provided between two adjacent protrusions. For instance, the sequential connection path of multiple vertices includes a path in which first vertex P1, second vertex P2, third vertex P3, fourth vertex P4, fifth vertex P5, and sixth vertex P6 are connected in sequence.

[0156] With this design, on the one hand, the first and second vias can be placed in the area close to the protrusion, which helps to improve the pixel aperture; on the other hand, the combination of the protrusion and the recess can adjust the spacing between adjacent first electrodes, which helps to reduce the probability of short circuits.

[0157] Increasing the pixel aperture ratio has two advantages: firstly, it improves the brightness of the display panel, allowing for greater adjustment range in the Gamma tuning of the display substrate; secondly, it allows for driving with lower voltage at the same brightness, thus extending the lifespan of the display substrate.

[0158] For example, the first vertex P1 is located in the first protrusion 201, and the fourth vertex P4 is located in the second protrusion 202.

[0159] For example, the shape of the orthographic projection of the pixel opening VH onto the substrate can include a centrally symmetrical shape, which is beneficial for improving the uniformity of light emitted by the sub-pixel in all directions. Referring to FIG10B, the shape of the orthographic projection of the pixel opening VH onto the substrate includes a circle, the pixel opening VH includes a pixel opening center Z1, and the pixel opening VH is symmetrical about the pixel opening center Z1.

[0160] By way of example, in some other embodiments of this disclosure, the shape of the pixel opening may also include a variety of shapes such as square and hexagon.

[0161] For example, the first protrusion 201 and the second protrusion 202 are located on opposite sides of the pixel opening center Z1.

[0162] For example, the orthographic projection of the first via VO1 on the substrate at least partially overlaps with the orthographic projection of the first protrusion 201 on the substrate. With this design, while ensuring that the spacing between the first via VO1 and the side of the first electrode meets the safety spacing distance, it is beneficial to increase the size of the pixel aperture, thereby improving the pixel aperture ratio.

[0163] For example, the orthographic projection of the second via VO2 on the substrate at least partially overlaps with the orthographic projection of the second protrusion 202 on the substrate.

[0164] This design ensures that the spacing between the second via VO2 and the side of the first electrode meets the safety spacing requirement, while also allowing for a further increase in the pixel aperture size, which is beneficial for improving the pixel aperture ratio.

[0165] In addition, the first protrusion and the second protrusion are located on opposite sides of the pixel opening center Z1, which can reduce the mutual interference or restriction between the first via VO1 and the second via VO2, reduce the process difficulty, and improve the yield of the display substrate.

[0166] For example, referring to Figures 9 and 10B, the second vertex P2 is located in the first recess 203, the third vertex P3 is located in the second recess 204, the fifth vertex P5 is located in the third recess 205, and the sixth vertex P6 is located in the fourth recess 206. The first recess 203 and the third recess 205 are located on opposite sides of the pixel opening center Z1, and the second recess 204 and the fourth recess 206 are located on opposite sides of the pixel opening center Z1.

[0167] By utilizing the staggered design of protrusions and recesses, the consistency of the spacing between adjacent first electrodes can be improved when multiple first electrodes are arranged, which is beneficial for the alignment design of subsequent processes and helps to reduce the probability of short circuits.

[0168] For example, continuing to refer to FIG10B, at least a portion of the plurality of protrusions 210 includes an arcuate curved edge. For example, the first protrusion 201 includes an arcuate curved edge; and / or, the second protrusion 202 includes an arcuate curved edge.

[0169] At least a portion of the plurality of recesses 220 includes an arcuate curved edge. For example, the first recess 203 includes an arcuate curved edge; and / or, the second recess 204 includes an arcuate curved edge; and / or, the third recess 205 includes an arcuate curved edge; and / or, the fourth recess 206 includes an arcuate curved edge.

[0170] For example, the arc-shaped edge of the protrusion 210 has a first radius of curvature, and the arc-shaped edge of the recess 220 has a second radius of curvature, wherein the first radius of curvature is smaller than the second radius of curvature.

[0171] This design reduces the number of sharp points in the first electrode, which helps to lower the probability of sharp discharge in the first electrode and thus improves the yield of the display substrate.

[0172] For example, referring to FIG8, the first electrode layer may include a plurality of electrode rows extending along a first direction X, and the electrode rows include a plurality of first electrodes 20 arranged at intervals. The plurality of electrode rows include adjacent i-th electrode rows K in the second direction Y. i and the (i+1)th electrode row K i+1 , where i is a positive integer greater than or equal to 1.

[0173] For example, the i-th electrode row K i and the (i+1)th electrode row K i+1 At least partially aligned in the second direction Y.

[0174] For example, located in the i-th electrode row K i The first protrusion 201 of the multiple first electrodes moves towards the (i+1)th electrode. i+1 ; and the K located in the (i+1)th electrode row i+1 The first protrusions 201 of the multiple first electrodes are directed toward the i-th electrode. i .

[0175] For example, the plurality of electrode rows also includes the (i+1)th electrode row K along the second direction Y. i+1 Adjacent (i+2)th electrode row K i+2 Among them, the (i+2)th electrode row K i+2 and the (i+1)th electrode row K i+1 At least partially aligned in the second direction Y.

[0176] For example, located in the (i+1)th electrode row K i+1 The second protrusions 202 of the multiple first electrodes are directed toward the (i+2)th electrode.i+2 ; and the K located in the (i+2)th electrode row i+2 The second protrusions 202 of the multiple first electrodes are directed toward the (i+1)th electrode. i+1 .

[0177] For example, the protrusion 210 of the first electrode is located between the recesses 220 of the two first electrodes adjacent to the first electrode.

[0178] This design allows for full utilization of wiring space and increases pixel density. Furthermore, the nearly equal dimensions of adjacent first protrusions and adjacent second protrusions ensure more consistent spacing between adjacent first electrodes, facilitating alignment design in subsequent processes and reducing the likelihood of interference or short circuits between adjacent pixels.

[0179] Figure 11 is a partial planar schematic diagram of a display substrate according to an embodiment of the present disclosure, showing a first electrode, a first via, a second via, and a pixel opening.

[0180] For example, in the first planar direction X1, the first via VO1 is separated from the first vertex P1 by a first spacing distance D1, the first spacing distance D1 being greater than or equal to 0.15 micrometers, and the first planar direction X1 is perpendicular to the light emission direction of the display substrate. For example, the first spacing distance D1 is approximately 0.15 micrometers, 0.25 micrometers, 0.4 micrometers, 0.5 micrometers, or 0.6 micrometers.

[0181] For example, the distance between the first vertex P1 and the fourth vertex P4 is D20. The ratio of the first distance D1 to the distance D20 between the first vertex P1 and the fourth vertex P4 is less than or equal to 1 / 4.

[0182] This design improves the electrical connection performance between the conductive connecting post located in the first via VO1 and the first electrode. Specifically, the first planar direction X1 can be parallel to the shortest connection line between the first vertex P1 and the first via VO1.

[0183] Referring to Figures 5 and 11, within the same sub-pixel, in the first planar direction X1, the first via VO1 is separated from the side edge PDL21 of the second sub-layer PDL2 near the pixel opening by a second spacing distance D2. This second spacing distance D2 is greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer. The first planar direction X1 can be parallel to the shortest connecting line between the first via VO1 and the pixel opening VH. For example, the second spacing distance D2 is approximately 0.2 micrometers, 0.3 micrometers, 0.5 micrometers, 0.8 micrometers, or 1 micrometer.

[0184] This design reduces the impact of uneven film layers in the area where the first via is located on the undercut structure (UDC) in the pixel limiting layer, preventing damage or even collapse of the undercut structure. It also helps reduce the probability of cathode puncture in the vicinity of the undercut structure and improves the yield of the display substrate.

[0185] In some embodiments, referring to Figures 5 and 11, the shape of the pixel opening VH can be defined by the pixel-defined first sub-layer PDL1. Since the pixel-defined second sub-layer PDL2 is recessed relative to the pixel-defined first sub-layer PDL1 in a direction away from the pixel opening, the spacing distance D21 between the pixel opening VH and the first via VO1 is greater than the second spacing distance D2, that is, D21 is greater than 0.2 micrometers. For example, the spacing distance D21 between the pixel opening VH and the first via VO1 is approximately 0.26 micrometers, and the second spacing distance D2 is approximately 0.2 micrometers.

[0186] In some embodiments of this disclosure, referring to FIG11, within the same sub-pixel, in the second planar direction X2, the pixel opening VH is spaced from the side of the first electrode 20 by a third spacing distance D3. The second planar direction X2 is perpendicular to the light-emitting direction of the display substrate and intersects with the first planar direction X1. For example, the third spacing distance D3 is greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer. For example, the third spacing distance D3 can be approximately 0.2 micrometers, 0.4 micrometers, 0.6 micrometers, 0.8 micrometers, or 1 micrometer. This design ensures that the pixel limiting layer can better enclose the side of the first electrode, avoiding defects such as short circuits.

[0187] For example, in the first planar direction X1, the second via VO2 is separated from the fourth vertex P4 by a fifth spacing distance D5, which is greater than or equal to 0.15 micrometers. The first planar direction X1 is perpendicular to the light emission direction of the display substrate. For example, the fifth spacing distance is approximately 0.15 micrometers, 0.3 micrometers, 0.5 micrometers, 0.75 micrometers, or 1 micrometer. For example, the ratio of the fifth spacing distance D5 to the spacing distance D20 between the first vertex P1 and the fourth vertex P4 is less than or equal to 1 / 4.

[0188] This design improves the electrical connection between the upper and lower conductive layers in the first electrode of the stack.

[0189] For example, within the same sub-pixel, in the first planar direction X1, the second via VO2 is separated from the pixel opening VH by a sixth spacing distance D6, which is greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer. For example, the sixth spacing distance D6 is approximately 0.2 micrometers, 0.4 micrometers, 0.6 micrometers, 0.8 micrometers, or 1 micrometer. This design reduces the impact of uneven film layers in the region where the second via is located on the undercut structure UDC in the pixel definition layer, preventing damage or even collapse of the undercut structure. This helps reduce the probability of cathode punctures in the vicinity of the undercut structure and improves the yield of the display substrate.

[0190] For example, referring back to FIG9, in the third planar direction X3, two adjacent first electrodes 20 are spaced apart by a fourth spacing distance D4, which is greater than or equal to 0.25 micrometers and less than or equal to 1 micrometer. The third planar direction X3 is perpendicular to the light emission direction of the display substrate, and the third planar direction X3 intersects both the first planar direction X1 and the second planar direction X2. For example, the fourth spacing distance D4 can be approximately 0.25 micrometers, 0.45 micrometers, 0.65 micrometers, 0.85 micrometers, or 1 micrometer. This design facilitates the alignment design and fabrication of subsequent process steps, avoiding defects such as short circuits and crosstalk caused by process deviations.

[0191] It should be noted that the "first plane direction," "second plane direction," and "third plane aspect" are all parallel to the plane formed by the first and second directions. For different sub-pixels, the "first plane direction," "second plane direction," and "third plane aspect" can be the same or different.

[0192] For example, in an embodiment of this disclosure, referring to FIG10B, in the same first electrode, the area of ​​the first protrusion 201 is smaller than the area of ​​the second protrusion 202.

[0193] For example, the first vertex P1 is separated from the pixel opening center Z1 by a seventh interval distance D7, and the fourth vertex P4 is separated from the pixel opening center Z1 by an eighth interval distance D8. The seventh interval distance D7 is less than the eighth interval distance D8.

[0194] Since the diameter of the first via VO1 is smaller than the diameter of the second via VO2, the first via VO1 is located on the side closer to the first protrusion 201, and the second via VO2 is located on the side closer to the second protrusion 202. By designing the area of ​​the second protrusion 202 to be larger than the area of ​​the first protrusion 201, it can be adapted to the size of the first via VO1 and the second via VO2. This allows for more efficient and full utilization of the wiring space on the first electrode, which is beneficial for improving the pixel aperture ratio while ensuring high resolution, thereby improving the brightness of the display substrate.

[0195] Figures 12A and 12B are schematic diagrams comparing pixel aperture sizes of display substrates with different first electrode shapes according to embodiments of the present disclosure.

[0196] For example, in an embodiment of this disclosure, referring to FIG12A, the first electrode 20 is a regular hexagon, and the pixel opening VH is circular. When the spacing between the pixel opening VH, the first via VO1, the second via VO2, and the first electrode 20 meets the safety spacing distance, the pixel opening VH may include the first pixel opening VH1.

[0197] Referring to Figure 12B, the first electrode 20 has a hexagonal irregular shape, and the pixel opening VH is circular. For example, the first electrode 20 includes two protrusions disposed opposite each other and a plurality of recesses located between the two protrusions. When the spacing between the pixel opening VH, the first via VO1, the second via VO2, and the first electrode 20 meets the safety spacing distance, the pixel opening VH may include a second pixel opening VH2.

[0198] By comparing Figures 12A and 12B, it can be seen that, with other parameters (such as pixel density, size of a single pixel, and spacing between multiple components) being the same, the size of the second pixel opening VH2 is larger than the size of the first pixel opening VH1, and the area of ​​the orthographic projection of the second pixel opening VH2 onto the substrate is larger than the area of ​​the orthographic projection of the first pixel opening VH1 onto the substrate. In other words, with other parameters remaining constant, the irregular design of the first electrode in the embodiments of this disclosure, offsetting the first via towards the side closer to the first protrusion and the second via towards the side closer to the second protrusion, helps to increase the pixel opening size, thereby increasing the aperture ratio of the display substrate and improving the brightness of the display substrate.

[0199] It should be noted that, in the embodiments of this disclosure, "the spacing between the pixel opening VH, the first via VO1, the second via VO2 and the first electrode 20 meets the safe spacing distance" means that the first spacing distance D1 is greater than or equal to 0.15 micrometers, the second spacing distance D2 is greater than or equal to 0.2 micrometers, the third spacing distance D3 is greater than or equal to 0.2 micrometers, the fourth spacing distance D4 is greater than or equal to 0.25 micrometers, the fifth spacing distance D5 is greater than or equal to 0.15 micrometers, and the sixth spacing distance D6 is greater than or equal to 0.2 micrometers.

[0200] In embodiments of this disclosure, the shape of the plurality of protrusions may include at least one of circles and rectangles. Alternatively, a portion of the plurality of protrusions may be circular in shape, while another portion may be rectangular in shape.

[0201] Figure 13 is a partial arrangement diagram of the first electrode according to some embodiments of the present disclosure, and Figure 14 is a partial arrangement diagram of the first electrode according to other embodiments of the present disclosure.

[0202] For example, at least one of the first protrusion 201 and the second protrusion 202 has a rectangular shape. For instance, referring to FIG13, the first protrusion 201 has a rectangular shape, and the second protrusion 202 has at least a portion of a circle.

[0203] In some embodiments, the first protrusion 201 has a shape including at least a circular portion, and the second protrusion 202 has a shape including a rectangle.

[0204] In some embodiments, both the first protrusion 201 and the second protrusion 202 are rectangular in shape.

[0205] In some embodiments of this disclosure, when at least a portion of the protrusions are rectangular in shape, the recesses adjacent to the protrusions can be designed accordingly.

[0206] For example, referring to FIG14, at least a portion of the protrusion 210 has a side L210 that includes a straight line; and / or, at least a portion of the recess 220 has a side L220 that includes a straight line.

[0207] For example, in the fourth planar direction X4, the distance D10 between the side edge L210 of the protrusion and the side edge L220 of the recess is greater than or equal to 0.25 micrometers and less than or equal to 1 micrometer, and the fourth planar direction X4 is perpendicular to the light emission direction of the display substrate. For example, the distance D10 between the side edge L210 of the protrusion and the side edge L220 of the recess can be approximately 0.25 micrometers, 0.5 micrometers, 0.65 micrometers, 0.8 micrometers, or 1 micrometer.

[0208] This design improves the consistency of the spacing between adjacent first electrodes, facilitates the alignment design of subsequent processes, and reduces the probability of short circuits.

[0209] Figure 15 is a schematic diagram of the structure of a display panel provided according to some embodiments of the present disclosure.

[0210] Optionally, embodiments of this disclosure provide a display panel. Referring to FIG15, the display panel 200 may include the display substrate 100 described above.

[0211] Figure 16 is a schematic diagram of the structure of a display device provided according to some embodiments of the present disclosure.

[0212] Optionally, embodiments of this disclosure also provide a display device 300. Referring to FIG16, the display device 300 may include the aforementioned display substrate 100 or the aforementioned display panel 200. The display device may include, but is not limited to, any product or component with display function such as electronic paper, mobile phone, tablet computer, monitor, laptop computer, digital photo frame, and navigator. It should be understood that this display device has the same beneficial effects as the display substrate provided in the foregoing embodiments.

[0213] While some embodiments of the general concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized by, include: Substrate; A first electrode layer is located on one side of the substrate. The first electrode layer includes a plurality of first electrodes arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect. Wherein, at least a portion of the first electrode has a first projection shape on the substrate, the first projection shape including a plurality of vertices, the plurality of vertices including a first vertex, a second vertex, a fourth vertex and a sixth vertex connected in sequence, and the line connecting the first vertex, the second vertex, the fourth vertex and the sixth vertex forms a virtual quadrilateral; The first projected shape further includes: a plurality of protrusions, at least a portion of which is located outside the virtual quadrilateral; and a plurality of recesses, at least a portion of which has an inwardly recessed structure relative to the virtual quadrilateral. In particular, on the sequential connection path along the plurality of vertices, at least one recess is provided between two adjacent protrusions. 2.The display substrate of claim 1, wherein, The plurality of vertices also includes a third vertex and a fifth vertex, wherein the third vertex is connected to both the second vertex and the fourth vertex, and the fifth vertex is connected to both the fourth vertex and the sixth vertex; the lines connecting the first vertex, the second vertex, the third vertex, the fourth vertex, the fifth vertex, and the sixth vertex form a virtual hexagon; At least a portion of the protrusions is located outside the virtual hexagon, and at least a portion of the recesses has an inward structure relative to the virtual hexagon. 3.The display substrate of claim 2, wherein, The plurality of protrusions includes: a first protrusion and a second protrusion, wherein the first vertex is located on the first protrusion and the fourth vertex is located on the second protrusion; and The display substrate further includes a pixel defining layer located on the side of the first electrode layer away from the substrate. The pixel defining layer defines a plurality of pixel openings. Each pixel opening includes a pixel opening center and is symmetrical about the pixel opening center. The first protrusion and the second protrusion are located on opposite sides of the pixel opening center.

4. The display substrate according to claim 3, wherein, The plurality of recessed portions include: a first recessed portion, a second recessed portion, a third recessed portion, and a fourth recessed portion, wherein the second vertex is located in the first recessed portion; the third vertex is located in the second recessed portion; the fifth vertex is located in the third recessed portion; and the sixth vertex is located in the fourth recessed portion. The first recess and the third recess are located on opposite sides of the center of the pixel opening, and the second recess and the fourth recess are located on opposite sides of the center of the pixel opening.

5. The display substrate according to claim 3 or 4, wherein, The display substrate further includes: a driving circuit layer located between the substrate and the first electrode layer; and an insulating layer located between the driving circuit layer and the first electrode layer, the insulating layer including a plurality of first vias, the first electrode being electrically connected to a pixel driving circuit located in the driving circuit layer through the first vias. Wherein, the orthographic projection of the first via on the substrate and the orthographic projection of the first protrusion on the substrate at least partially overlap.

6. The display substrate according to claim 5, wherein, The first electrode layer includes: a first electrode first sub-layer located on one side of the substrate; an interlayer insulating layer located on the side of the first electrode first sub-layer away from the substrate; and a first electrode second sub-layer located on the side of the interlayer insulating layer away from the substrate. The interlayer insulating layer includes a plurality of second vias, and the first sub-layer of the first electrode and the second sub-layer of the first electrode are electrically connected through the second vias; and The orthographic projection of the second via on the substrate and the orthographic projection of the second protrusion on the substrate at least partially overlap.

7. The display substrate according to claim 6, wherein, The first via has a second projection shape when projected onto the substrate, and the second via has a third projection shape when projected onto the substrate. Both the second and third projection shapes are circular, wherein the diameter of the second projection shape is smaller than the diameter of the third projection shape. 8.The display substrate of claim 7, wherein, The diameter of the second projected shape is in the range of 0.2 micrometers to 0.45 micrometers; and / or, The diameter of the third projected shape is in the range of 0.35 micrometers to 0.65 micrometers.

9. The display substrate according to any one of claims 1-8, wherein, At least a portion of the plurality of protrusions includes an arcuate curved edge; and / or, At least a portion of the plurality of said recesses includes an arc-shaped curved edge. 10.The display substrate of claim 9, wherein, The arc-shaped edge of the protruding part has a first radius of curvature, and the arc-shaped edge of the recessed part has a second radius of curvature, wherein the first radius of curvature is smaller than the second radius of curvature.

11. The display substrate according to any one of claims 3-10, wherein, The first electrode layer includes a plurality of electrode rows extending along the first direction, each electrode row including a plurality of spaced-apart first electrodes, and the plurality of electrode rows including an i-th electrode row and an (i+1)-th electrode row adjacent in the second direction, where i is a positive integer greater than or equal to 1. Wherein, the i-th electrode row and the (i+1)-th electrode row are at least partially aligned in the second direction; The first protrusions of the plurality of first electrodes located in the i-th electrode row face the (i+1)-th electrode row; and The first protrusions of the plurality of first electrodes located in the (i+1)th electrode row face the i-th electrode row.

12. The display substrate according to claim 11, wherein, The plurality of electrode rows also includes an (i+2)th electrode row adjacent to the (i+1)th electrode row in a second direction, wherein the (i+2)th electrode row and the (i+1)th electrode row are at least partially aligned in the second direction; The second protrusions of the plurality of first electrodes located in the (i+1)th electrode row face the (i+2)th electrode row; and The second protrusions of the plurality of first electrodes located in the (i+2)th electrode row face the (i+1)th electrode row.

13. The display substrate according to any one of claims 1-12, wherein, The protrusion of the first electrode is located between the recesses of the two first electrodes adjacent to it.

14. The display substrate according to any one of claims 1-13, wherein, The display substrate includes a plurality of sub-pixels, the plurality of sub-pixels including a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, the first color sub-pixel emits light of a first wavelength, the second color sub-pixel emits light of a second wavelength, the third color sub-pixel emits light of a third wavelength, the first wavelength is smaller than the third wavelength, and the third wavelength is smaller than the second wavelength; The plurality of first electrodes include a first electrode portion, a second electrode portion, and a third electrode portion. The first color sub-pixel includes a first electrode portion, the second color sub-pixel includes a second electrode portion, and the third color sub-pixel includes a third electrode portion. The first electrode portion includes a first interlayer insulating portion located in the interlayer insulating layer, the second electrode portion includes a second interlayer insulating portion located in the interlayer insulating layer, and the third electrode portion includes a third interlayer insulating portion located in the interlayer insulating layer. In the third direction, the first interlayer insulating portion has a first thickness, the second interlayer insulating portion has a second thickness, and the third interlayer insulating portion has a third thickness. The third direction is parallel to the light emission direction of the display substrate, and the first thickness is greater than the second thickness, and the second thickness is greater than the third thickness.

15. The display substrate according to claim 5, wherein, In a first planar direction, the first via is spaced apart from the first vertex by a first spacing distance, the first spacing distance being greater than or equal to 0.15 micrometers, the first planar direction being perpendicular to the light emission direction of the display substrate; and the ratio of the first spacing distance to the spacing distance between the first vertex and the fourth vertex is less than or equal to 1 / 4.

16. The display substrate according to claim 15, wherein, The pixel defining layer includes: a first pixel defining sub-layer located on the side of the first electrode layer away from the substrate; a second pixel defining sub-layer located on the side of the first pixel defining sub-layer away from the substrate; and a third pixel defining sub-layer located on the side of the second pixel defining sub-layer away from the substrate. Wherein, the pixel-defined second sub-layer is recessed relative to the pixel-defined first sub-layer and the pixel-defined third sub-layer in a direction away from the pixel opening; and In the same sub-pixel, in the first planar direction, the first via and the pixel define a second spacing distance between the side of the second sub-layer near the pixel opening, the second spacing distance being greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer.

17. The display substrate according to claim 16, wherein, In the same sub-pixel, in the second planar direction, the pixel opening is separated from the side of the first electrode by a third spacing distance, the third spacing distance being greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer, and the second planar direction is perpendicular to the light emission direction of the display substrate and intersects with the first planar direction.

18. The display substrate according to claim 17, wherein, In the third plane direction, two adjacent first electrodes are spaced by a fourth spacing distance, the fourth spacing distance being greater than or equal to 0.25 micrometers and less than or equal to 1 micrometer, and the third plane direction is perpendicular to the light emission direction of the display substrate.

19. The display substrate according to claim 6, wherein, In the first planar direction, the second via is spaced a fifth interval distance from the fourth vertex, the fifth interval distance being greater than or equal to 0.15 micrometers, the first planar direction being perpendicular to the light emission direction of the display substrate; and the ratio of the fifth interval distance to the interval distance between the first vertex and the fourth vertex is less than or equal to 1 / 4.

20. The display substrate according to claim 19, wherein, In the same sub-pixel, in the first planar direction, the second via is separated from the pixel opening by a sixth spacing distance, the sixth spacing distance being greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer.

21. The display substrate according to any one of claims 2-20, wherein, In the same first electrode, the area of ​​the first protrusion is smaller than the area of ​​the second protrusion; and / or, The first vertex is spaced a seventh interval distance from the center of the pixel opening, and the fourth vertex is spaced an eighth interval distance from the center of the pixel opening. The seventh interval distance is less than the eighth interval distance.

22. The display substrate according to any one of claims 3-8, wherein, The shape of at least one of the first protrusion and the second protrusion includes a rectangle.

23. The display substrate according to claim 22, wherein, At least part of the protrusion's side edge includes a straight line; and / or, At least a portion of the recessed portion has straight sides; and In the fourth plane direction, the distance between the side of the protrusion and the side of the recess is greater than or equal to 0.25 micrometers and less than or equal to 1 micrometer, and the fourth plane direction is perpendicular to the light emission direction of the display substrate.

24. A display device, wherein, Includes the display substrate as described in any one of claims 1-23.

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