Display panel and display apparatus

Abstract

The present invention relates to the technical field of display. Provided are a display panel and a display apparatus, in which the design of a pixel circuit thereof is optimized. The display panel comprises a pixel circuit. The pixel circuit comprises: a driving transistor, the driving transistor being an N-type transistor; a first light emission control transistor and a second light emission control transistor, a gate electrode of the first light emission control transistor and a gate electrode of the second light emission control transistor being electrically connected to a same light emission control line, a first electrode of the first light emission control transistor being electrically connected to a first power line, a second electrode thereof being electrically connected to a first electrode of the driving transistor, a first electrode of the second light emission control transistor being electrically connected to a second electrode of the driving transistor, and a second electrode thereof being electrically connected to a light-emitting element; and a first transistor, a gate electrode of the first transistor being electrically connected to a first scan line, a first electrode thereof being electrically connected to the first power line, and a second electrode thereof being electrically connected to the driving transistor.

Description

Display panel and display device

[0001] This invention claims priority to Chinese Patent Application No. 202411959053.6, filed with the State Intellectual Property Office of China on December 27, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs), as current-driven light-emitting elements, are increasingly used in various display devices. The display panels of these devices consist of pixel circuits and the OLED itself; the pixel circuits provide driving current to the OLED to drive it to emit light. However, the design of current pixel circuits still needs further optimization. Summary of the Invention

[0004] This invention provides a display panel and display device with a superior pixel circuit design.

[0005] In a first aspect, embodiments of the present invention provide a display panel, including a pixel circuit, the pixel circuit comprising:

[0006] A driving transistor, wherein the driving transistor is an N-type transistor;

[0007] A first light-emitting control transistor and a second light-emitting control transistor, wherein the gates of the first light-emitting control transistor and the second light-emitting control transistor are electrically connected to the same light-emitting control line, the first terminal of the first light-emitting control transistor is electrically connected to the first power line and the second terminal is electrically connected to the first terminal of the driving transistor, and the first terminal of the second light-emitting control transistor is electrically connected to the second terminal of the driving transistor and the second terminal is electrically connected to the light-emitting element.

[0008] The first transistor has its gate electrically connected to the first scan line, its first electrode electrically connected to the first power line, and its second electrode electrically connected to the driving transistor.

[0009] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the aforementioned display panel.

[0010] The technical solution provided by the embodiments of the present invention has the following beneficial effects:

[0011] In this embodiment of the invention, the pixel circuit includes a first transistor connected between a first power line and a driving transistor. Before charging the driving transistor, the first transistor can be used to open a signal transmission path between the first power line and the driving transistor, allowing the signal from the first power line to be written into the driving transistor, setting at least one node of the driving transistor to a specific initial potential. In this way, it is no longer necessary to rely on a first light-emitting control transistor to write the signal from the first power line into the driving transistor; the first light-emitting control transistor only performs the function of light emission control. Therefore, the first light-emitting control transistor and the second light-emitting control transistor can be electrically connected to the same light emission control line.

[0012] Connecting the first and second light-emitting control transistors to the same light-emitting control line means that only one set of light-emitting control signals is needed to synchronously control the two light-emitting control transistors in the pixel circuit. This simplifies the path and method of the light-emitting control signal, making dimming more convenient. For example, in PWM (Pulse Width Modulation) dimming, the duty cycle of the light-emitting control signal pulses is used to finely adjust the brightness. If the two light-emitting control transistors are connected to two different light-emitting control lines, separate dimming PWM signals need to be generated for each of these lines, resulting in more complex control logic and increasing the difficulty of control. However, when the two light-emitting control transistors are connected to a single light-emitting control line, only one dimming PWM signal is needed to complete the dimming control, greatly reducing the number of control signals and the complexity of adjustment. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0014] Figure 1 is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0015] Figure 2 is a timing diagram corresponding to Figure 1;

[0016] Figure 3 is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0017] Figure 4 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0018] Figure 5 is a timing diagram corresponding to Figure 4;

[0019] Figure 6 is another timing diagram corresponding to Figure 4;

[0020] Figure 7 is a timing diagram of a light emission control line provided in an embodiment of the present invention;

[0021] Figure 8 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0022] Figure 9 shows another timing diagram corresponding to Figure 4;

[0023] Figure 10 shows another timing diagram corresponding to Figure 4;

[0024] Figure 11 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0025] Figure 12 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0026] Figure 13 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0027] Figure 14 is a timing diagram corresponding to Figure 13;

[0028] Figure 15 is another timing diagram corresponding to Figure 13;

[0029] Figure 16 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0030] Figure 17 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0031] Figure 18 is a timing diagram corresponding to Figure 17;

[0032] Figure 19 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0033] Figure 20 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0034] Figure 21 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0035] Figure 22 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0036] Figure 23 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0037] Figure 24 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0038] Figure 25 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0039] Figure 26 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0040] Figure 27 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0041] Figure 28 is a timing diagram corresponding to Figure 27;

[0042] Figure 29 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0043] Figure 30 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0044] Figure 31 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0045] Figure 32 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0046] Figure 33 is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0047] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0049] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0050] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0051] The pixel circuit includes a driving transistor and multiple switching transistors, wherein the driving transistor is used to switch the driving current required by the light-emitting element.

[0052] In traditional designs, both the driving transistor and the switching transistor in a pixel circuit are P-type transistors, such as low-temperature polycrystalline silicon (LTPS) transistors. However, this invention proposes a novel pixel circuit design where the driving transistor is an N-type transistor, such as an indium gallium zinc oxide (IGaZO) transistor.

[0053] When the driving transistor is an N-type transistor, the signal of the first power line can be written into the driving transistor before the gate of the driving transistor is charged, so as to set the node of the driving transistor to a specific initial potential.

[0054] In response, this invention proposes a circuit design, as shown in Figure 1. Figure 1 is a schematic diagram of a pixel circuit provided by this invention. The pixel circuit 1' includes a driving transistor T0', a threshold compensation transistor T1', a first light-emitting control transistor T2', and a second light-emitting control transistor T3'.

[0055] Specifically, the gate of the driving transistor T0' is electrically connected to the first node N1', the first electrode is electrically connected to the second node N2', and the second electrode is electrically connected to the third node N3'; the threshold compensation transistor T1' is electrically connected between the second node N2' and the first node N1'; the first light-emitting control transistor T2' is electrically connected between the first power line PVDD' and the second node N2'; and the second light-emitting control transistor T3' is electrically connected between the third node N3' and the light-emitting element 2'.

[0056] Based on the above structure, before charging the gate of the driving transistor T0', the first light-emitting control transistor T2' and the threshold compensation transistor T1' can be turned on, thereby writing the signal of the first power line PVDD' into the second node N2' and the first node N1'.

[0057] However, in this implementation, before charging the gate of the driving transistor T0', a signal transmission path between the first power line PVDD' and the driving transistor T0' needs to be constructed using the first light-emitting control transistor T2'. Therefore, the conduction times of the first light-emitting control transistor T2' and the second light-emitting control transistor T3' are different, and they need to be connected to two different light-emitting control signal lines respectively: the gate of the first light-emitting control transistor T2' is electrically connected to the first light-emitting control line Emit1', and the gate of the second light-emitting control transistor T3' is electrically connected to the second light-emitting control line Emit2'. As shown in Figure 2, which is a timing diagram corresponding to Figure 1, during the m1' period, the first light-emitting control line Emit1' provides an enable level to control the first light-emitting control transistor T2' to conduct, opening the signal transmission path between the first power line PVDD' and the driving transistor T0', allowing the first power signal to be written into the driving transistor T0'. Meanwhile, the second light-emitting control line Emit2' provides a non-enable level to control the second light-emitting control transistor T3' to turn off, cutting off the current path between the driving transistor T0' and the light-emitting element 2'.

[0058] However, the structure driven by the two light-emitting control lines makes the dimming design of the light-emitting control signal more complicated, which is not conducive to achieving precise control of the light-emitting brightness.

[0059] In response, this invention further proposes a technical solution:

[0060] This invention provides a display panel, as shown in FIG3. FIG3 is a schematic diagram of a structure of the display panel provided in this invention, which includes a pixel circuit 1.

[0061] As shown in Figure 4, Figure 4 is another structural schematic diagram of the pixel circuit provided in the embodiment of the present invention. The pixel circuit 1 includes a driving transistor T0, a first light-emitting control transistor T1, a second light-emitting control transistor T2, and a first transistor T3.

[0062] Among them, the driving transistor T0 is an N-type transistor, such as an IGZO transistor.

[0063] The gates of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are electrically connected to the same light-emitting control line Emit. The first terminal of the first light-emitting control transistor T1 is electrically connected to the first power supply line PVDD, and the second terminal is electrically connected to the first terminal of the driving transistor T0. The first terminal of the second light-emitting control transistor T2 is electrically connected to the second terminal of the driving transistor T0, and the second terminal is electrically connected to the light-emitting element 2.

[0064] The gate of the first transistor T3 is electrically connected to the first scan line S1, the first electrode is electrically connected to the first power supply line PVDD, and the second electrode is electrically connected to the driving transistor T0.

[0065] The pixel circuit includes a first transistor T3 connected between a first power line PVDD and a driving transistor T0. Before charging the driving transistor T0, the first transistor T3 can open a signal transmission path between the first power line PVDD and the driving transistor T0, allowing the signal from the first power line PVDD to be written into the driving transistor T0, setting at least one node of the driving transistor T0 to a specific initial potential. In this way, it is no longer necessary to rely on the first light-emitting control transistor T1 to write the signal from the first power line PVDD into the driving transistor T0. The first light-emitting control transistor T1 only performs the function of light emission control. Therefore, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 can be electrically connected to the same light emission control line, Emit.

[0066] The first light-emitting control transistor T1 and the second light-emitting control transistor T2 are connected to the same light-emitting control line, Emit. This means that only one set of light-emitting control signals is needed to synchronously control the two light-emitting control transistors in the pixel circuit. This simplifies the path and method of the light-emitting control signal, making dimming more convenient. For example, in PWM (Pulse Width Modulation) dimming, the duty cycle of the light-emitting control signal pulses is used to finely adjust the brightness. If the two light-emitting control transistors are connected to two different light-emitting control lines, dimming PWM signals need to be generated separately for each of these two different light-emitting control lines, resulting in more complex control logic and increasing the difficulty of control. However, when the two light-emitting control transistors are connected to a single light-emitting control line, only one dimming PWM signal is needed to complete the dimming control, greatly reducing the number of control signals and the complexity of adjustment.

[0067] In one feasible implementation, as shown in Figures 5 and 6, where Figure 5 is a timing diagram corresponding to Figure 4 and Figure 6 is another timing diagram corresponding to Figure 4, the driving cycle DC of pixel circuit 1 includes at least one frame, and one frame includes a non-emitting phase T-ne and an emitting phase Te. More specifically, one frame may include at least one emitting cycle EC, and the emitting cycle EC includes a non-emitting phase T-ne and an emitting phase T-ne.

[0068] During the non-light-emitting phase T-ne, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned off. The second light-emitting control transistor T2 cuts off the current path between the driving transistor T0 and the light-emitting element 2, and the light-emitting element 2 does not emit light. During at least a portion of the light-emitting phase Te, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned on. The second light-emitting control transistor T2 opens the current path between the driving transistor T0 and the light-emitting element 2, and the light-emitting element 2 emits light.

[0069] The frames in the drive cycle DC include the write frame WF. When the first transistor T3 is set, during a portion of the non-light-emitting phase T-ne of the write frame WF, the first transistor T3 is turned on, writing the signal of the first power line PVDD into the drive transistor T0.

[0070] Regarding the definition of "one frame," in one driving mode of a display panel, the display panel has a base frequency f and a first frequency f1. The first frequency f1 is less than the base frequency f, and the first frequency f1 is achieved by downclocking the base frequency f. For example, if the base frequency f is 120Hz, the first frequency f1 may include 60Hz, 40Hz, 30Hz, 20Hz, 10Hz, 1Hz, etc. One frame is the duration of one data refresh cycle at the base frequency f. For example, if the base frequency f is 120Hz, then one frame is 8.33ms.

[0071] Referring to Figure 5, at the base frequency f, the driving cycle DC of pixel circuit 1 includes 1 frame, which is the write frame WF, and the duration of the write frame WF is 8.33ms.

[0072] Referring to Figure 6, at the first frequency f1, the driving cycle DC of pixel circuit 1 includes multiple frames. One of the multiple frames is the write frame WF, and the remaining frames are the hold frames HF. The duration of both the write frame WF and the hold frame HF is 8.33ms.

[0073] During the non-light-emitting phase T-ne of the written frame WF, the first scan line S1 provides an enable level to control the first transistor T3 to turn on, opening the signal transmission path between the first power line PVDD and the driving transistor T0. This allows the signal from the first power line PVDD to be written into the driving transistor T0, thereby setting at least one node of the driving transistor T0 to a specific initial potential. As mentioned earlier, in this design, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 can be driven using a set of light-emitting control signals, which helps simplify dimming control.

[0074] In one feasible implementation, as shown in FIG7, FIG7 is a timing diagram of a light emission control line provided in an embodiment of the present invention. The driving cycle DC of the pixel circuit 1 includes at least one frame, and one frame includes a non-light emission phase T-ne and a light emission phase Te. More specifically, one frame may include at least one light emission cycle EC, and the light emission cycle EC includes a non-light emission phase T-ne and a light emission phase T-ne.

[0075] During the non-light-emitting phase T-ne, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned off. The second light-emitting control transistor T2 cuts off the current path between the driving transistor T0 and the light-emitting element 2, and the light-emitting element 2 does not emit light. During the light-emitting phase Te, the light-emitting control line Emit provides at least two pulses. For example, one frame includes three light-emitting cycles EC, and during the light-emitting phase Te, the light-emitting control line Emit provides 12 pulses.

[0076] PWM (Pulse Width Modulation) dimming uses the duty cycle of the light emission control signal to finely adjust brightness. Increasing the number of pulses in the light emission control signal allows for a wider range of adjustable duty cycles. During the light emission phase Te, multiple pulses are provided by controlling the light emission control line Emit, enabling finer duty cycle adjustment. This allows for more precise control of the light emission time of the light-emitting element 2, resulting in more subtle brightness variations.

[0077] In one feasible implementation, referring to Figures 4 and 8, Figure 8 is a schematic diagram of another structure of the pixel circuit provided in the embodiment of the present invention. The driving transistor T0 includes at least one gate, and the at least one gate includes a first gate. The first gate of the driving transistor T0 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3.

[0078] In this embodiment of the invention, the driving transistor T0 can be a single-gate transistor or a dual-gate transistor including a top gate and a bottom gate. When the driving transistor T0 is a single-gate transistor, its gate is understood as the aforementioned first gate; when the driving transistor T0 is a dual-gate transistor, its top gate is understood as the aforementioned first gate.

[0079] The pixel circuit 1 also includes a data writing transistor T4 and a second transistor T5. The gate of the data writing transistor T4 is electrically connected to the second scan line S2, and its first electrode is electrically connected to the data line Data. The gate of the second transistor T5 is electrically connected to the third scan line S3, and its second electrode is electrically connected to the first node N1. One of the second electrode of the data writing transistor T4 and the first electrode of the second transistor T5 is electrically connected to the second node N2, and the other is electrically connected to the third node N3.

[0080] That is, in one structure, referring to Figure 4, the second terminal of the data writing transistor T4 is electrically connected to the third node N3, and the first terminal of the second transistor T5 is electrically connected to the second node N2. Alternatively, in another structure, referring to Figure 8, the second terminal of the data writing transistor T4 is electrically connected to the second node N2, and the first terminal of the second transistor T5 is electrically connected to the third node N3.

[0081] The second terminal of the first transistor T3 is electrically connected to the second transistor T5.

[0082] The aforementioned scheme specifies that the second terminal of the first transistor T3 is electrically connected to the driving transistor T0. When the second terminal of the first transistor T3 is also electrically connected to the second transistor T5, it means that the first transistor T3 is either connected to the first node N1, or connected to the second node N2 or the third node N3 connected to the second terminal of the second transistor T5.

[0083] In this structure, before charging the gate of the driving transistor T0, the first transistor T3 and the second transistor T5 can be turned on, thereby writing the signal of the first power line PVDD into the first node N1 and the second node N2, or into the first node N1 and the third node N3, to reset at least two nodes of the driving transistor T0, making the reset of the driving transistor T0 more thorough.

[0084] Furthermore, as shown in Figures 9 and 10, Figure 9 is another timing diagram corresponding to Figure 4, and Figure 10 is yet another timing diagram corresponding to Figure 4. The driving cycle DC of the pixel circuit 1 includes the write frame WF, and the write frame WF includes the reset phase t1 and the data writing and compensation phase t2.

[0085] During the reset phase t1, the first transistor T3 and the second transistor T5 are turned on, writing the signal of the first power line PVDD to the first node N1, and to the second node N2 or the third node N3 connected to the second transistor T5, thereby resetting the first node N1 and the second node N2, or resetting the first node N1 and the third node N3 using the first power signal.

[0086] It should be noted that during the reset phase t1, the turn-on times of the first transistor T3 and the second transistor T4 can be the same or different. For example, referring to Figure 9, the first transistor T3 can be turned on earlier than the second transistor T4. That is, after the first power supply signal starts to be written to the first node N1, the second transistor T5 is then turned on to further write the first power supply signal of the first node N1 to the second node N2 or the third node N3.

[0087] During the data writing and compensation phase t2, data writing transistor T4 and the second transistor T5 are turned on, writing the signal of the data line Data to the first node N1 and performing threshold compensation on the driving transistor T0. That is, during the data writing and compensation phase t2, data writing and threshold compensation are performed simultaneously.

[0088] In the above process, the second transistor T5 is used not only for threshold compensation in the data writing and compensation stage t2, but also for resetting the first or second terminal of the driving transistor T0 in the reset stage t1. This allows the device state of the driving transistor T0 to be configured to a more definite initial state before charging, which helps to improve charging uniformity.

[0089] Furthermore, referring to Figures 10 and 9, a first intermediate stage t3 is also included between the reset stage t1 and the data writing and compensation stage t2.

[0090] In one feasible implementation, referring to Figures 4 and 10, in the first intermediate stage t3, the first transistor T3 and the data writing transistor T4 are turned off, and the second transistor T5 is turned on, so that during this stage, the second transistor T5 continuously writes the first power supply signal of the first node N1 to the second node N2 or the third node N3, thereby strengthening the reset of the second node N2 or the third node N3.

[0091] Alternatively, in another feasible implementation, referring to Figures 4 and 9, in the first intermediate stage t3, the first transistor T3 and the second transistor T5 are turned off, and the data writing transistor T4 is turned on, writing the signal of the data line Data to the second node N2 or the third node N3 connected to the data writing transistor T4.

[0092] During this stage, the data writing transistor T4 is turned on, writing the signal of the data line Data into the second node N2 or the third node N3 connected to it. This enables the pre-writing of the data signal, preparing for subsequent data writing and threshold compensation. Then, when the second transistor T5 is turned on during the data writing and compensation stage t2, the data signal can be written into the first node N1 more quickly, resulting in more complete charging.

[0093] Regarding the aforementioned "the second terminal of the first transistor T3 is electrically connected to the second transistor T5", in one feasible implementation, referring to Figures 4 and 9, the second terminal of the first transistor T3 is electrically connected to the first node N1.

[0094] In this structure, during the reset phase t1, the signal of the first power line PVDD is written to the first node N1 via the first transistor T3, and then to the second node N2 or the third node N3 via the second transistor T5.

[0095] Alternatively, in another feasible implementation, as shown in Figures 11 and 12, Figure 11 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention, and Figure 12 is a schematic diagram of yet another structure of the pixel circuit provided in an embodiment of the present invention. The second terminal of the first transistor T3 is electrically connected to the first terminal of the second transistor T5. That is, when the first terminal of the second transistor T5 is electrically connected to the second node N2, the second terminal of the first transistor T3 is electrically connected to the second node N2; when the first terminal of the second transistor T5 is electrically connected to the third node N3, the second terminal of the first transistor T3 is electrically connected to the third node N3.

[0096] In this structure, during the reset phase t1, the signal of the first power line PVDD is written to the second node N2 or the third node N3 via the second transistor T5, and then written to the first node N1 via the first transistor T3.

[0097] In addition, pixel circuit 1 may also include a second reset transistor T6 and a storage capacitor Cst. The first terminal of the second reset transistor T6 receives a reset signal, and the second terminal is electrically connected to the light-emitting element 2. The connection node between the second reset transistor T6, the second light-emitting control transistor T2, and the light-emitting element 2 is the fourth node N4. The storage capacitor Cst is electrically connected between the first node N1 and the fourth node N4.

[0098] The following explanation, using Figures 4 and 9 as examples and assuming that all transistors in pixel circuit 1 are N-type transistors, illustrates the operation of pixel circuit 1:

[0099] During the reset phase t1, the first scan line S1 provides a high level to control the first transistor T3 to turn on, and the third scan line S3 provides a high level to control the second transistor T5 to turn on, writing the signal from the first power line PVDD into the first node N1 and the second node N2; the fourth scan line S4 provides a high level to control the second reset transistor T6 to turn on, writing the reset signal received by the second reset transistor T6 into the fourth node N4. During this phase, V N1 =V N2 =V PVDD V N4 =V ref V ref The voltage of the reset signal received by the second reset transistor T6.

[0100] In the first intermediate stage t3, the second scan line S2 provides a high level to control the data write transistor T4 to turn on, writing the data line Data signal to the second node N2 and the third node N3; the second reset transistor T6 remains on. During this stage, V... N2 =V N3 =V Data V N4 =V ref .

[0101] During the data writing and compensation phase t2, the data writing transistor T4 remains on, the third scan line S3 provides a high level to control the second transistor T5 to turn on, writing the data line Data signal to the first node N1 and performing threshold compensation on the driving transistor T0; the second reset transistor T6 remains on. During this phase, V... N1 =V Data +Vth, where Vth is the threshold voltage of the driving transistor T0, V N4 =V ref .

[0102] During the light-emitting stage Te, the light-emitting control line Emit provides a high level, turning on the first light-emitting control transistor T1 and the second light-emitting control transistor T2, allowing the driving current to flow into the light-emitting element 2. The driving current flowing into the light-emitting element 2 is I = k × (V gs -Vth) 2 .in, μ n To drive the electron migration rate of transistor T0, C ox The gate oxide capacitance per unit area for driving transistor T0, To drive transistor T0, V gs To drive the gate-source voltage of transistor T0, V gs =V N1 -V N3 =V Data +Vth-V ref Therefore, we can derive I = k × (V) Data -V ref ) 2 .

[0103] In one feasible implementation, as shown in FIG13, FIG13 is another structural schematic diagram of the pixel circuit provided in the embodiment of the present invention. The driving transistor T0 includes at least one gate, the at least one gate includes a first gate, the first gate of the driving transistor T0 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3.

[0104] In this embodiment of the invention, the driving transistor T0 can be a single-gate transistor or a dual-gate transistor including a top gate and a bottom gate. When the driving transistor T0 is a single-gate transistor, its gate is understood as the aforementioned first gate; when the driving transistor T0 is a dual-gate transistor, its top gate is understood as the aforementioned first gate.

[0105] The pixel circuit 1 also includes a data writing transistor T4, whose gate is electrically connected to the second scan line S2, its first electrode is electrically connected to the data line Data, and its second electrode is electrically connected to the first node N1.

[0106] The pixel circuit 1 also includes a control unit 3, which includes a first transistor T3 and a second transistor T5. The gate of the second transistor T5 is electrically connected to the third scan line S3, and its first and / or second terminals are electrically connected to the driving transistor T0. The control unit 3 is used to write constant voltage signals to the first node N1 and the second node N2.

[0107] Based on this structure, before charging, a constant voltage signal can be written to the first node N1 and the second node N2 using the control unit 3, configuring the device state of the driving transistor T0 to a more defined initial state. It is understood that the control unit 3 includes the first transistor T3; therefore, the constant voltage signal written to at least one of the first node N1 and the second node N2 is the first power signal provided by the first power line PVDD.

[0108] In one feasible implementation, referring to Figure 13, the pixel circuit 1 further includes a first capacitor C1 and a second capacitor C2. The first plate of the first capacitor C1 is electrically connected to a first node N1, and the second plate is electrically connected to a third node N3. The first plate of the second capacitor C2 receives a constant voltage signal for at least a portion of the time, and the second plate is electrically connected to the third node N3.

[0109] When the first gate of the driving transistor T0 is charged, the potential of the first node N1 will change. When the potential of the first node N1 changes, the potential of the third node N3 will also change accordingly based on the effect of the first capacitor C1 and the second capacitor C2. The amount of potential change of the third node N3 will be related to the capacitance values ​​of the first capacitor C1 and the second capacitor C2, so that the driving current flowing into the light-emitting element 2 will also be related to the capacitance values ​​of the first capacitor C1 and the second capacitor C2. Thus, the setting range of the data voltage can be adjusted by using the first capacitor C1 and the second capacitor C2.

[0110] Alternatively, in other optional embodiments of the present invention, the pixel circuit 1 may only include a first capacitor C1, with its first plate electrically connected to the first node N1 and its second plate electrically connected to the third node N3. When the potential of the first node N1 changes, the potential of the third node N3 changes accordingly based on the effect of the first capacitor C1. At this time, the amount of potential change of the third node N3 is related to the capacitance value of the first capacitor C1.

[0111] Regarding control unit 3, in one feasible implementation, referring to Figure 13, the first transistor T3 is electrically connected to the second node N2. The first terminal of the second transistor T5 is electrically connected to the first reset line Ref1, and the second terminal is electrically connected to the first node N1.

[0112] Based on this structure, the constant voltage signal written by the control unit 3 to the first node N1 and the second node N2 specifically refers to: using the first transistor T3 to write the first power signal provided by the first power line PVDD to the second node N2, and using the second transistor T5 to write the first reset signal provided by the first reset line Ref1 to the first node N1. In this structure, the constant voltage signals written to the first node N1 and the second node N2 are different.

[0113] Further, as shown in Figure 14, which is a timing diagram corresponding to Figure 13, the driving cycle DC of the pixel circuit 1 includes a write frame WF, which includes a reset phase t1', a threshold compensation phase t2', and a data writing phase t3'.

[0114] During the reset phase t1', the second transistor T5 is turned on, writing the constant voltage signal of the first reset line Ref1 into the first node N1, thus resetting the first node N1.

[0115] During the threshold compensation phase t2', the second transistor T5 is turned on, writing the constant voltage signal of the first reset line Ref1 into the first node N1, which continues to reset the first node N1. The first transistor T3 is turned on, writing the constant voltage signal of the first power line PVDD into the second node N2. The third node N3 captures the threshold voltage and performs threshold compensation on the driving transistor T0.

[0116] During the data writing phase t3', the data writing transistor T4 is turned on, writing the voltage of the data line Data to the first node N1.

[0117] It should be noted that during the reset phase t1', the first transistor T3 can also be turned on, and the turn-on time of the first transistor T3 can be earlier than, later than, or equal to the turn-on time of the second transistor T5. For example, as shown in Figure 15, which is another timing diagram corresponding to Figure 13, during the reset phase t1', the first scan line S1 provides an enable level to control the first transistor T3 to turn on, and the time when the first scan line S1 provides the enable level is earlier than the time when the third scan line S3 provides the enable level.

[0118] In the above structure, during the threshold compensation stage t2', the third node N3 captures the threshold voltage and performs threshold compensation on the driving transistor T0. During the data line writing stage, the data signal is written to the first node N1. This design allows for step-by-step threshold compensation and data writing, ensuring sufficient time for both processes and enabling more thorough charging and compensation.

[0119] In one feasible implementation, as shown in FIG16, FIG16 is another structural schematic diagram of the display panel provided in the embodiment of the present invention. The display panel includes a plurality of circuit rows 4 arranged along a first direction x, and the circuit rows include a plurality of pixel circuits 1 arranged along a second direction y. The first direction x and the second direction y intersect.

[0120] Referring to Figures 15 and 16, the first scan line S1 connected to the i-th circuit row is electrically connected to the third scan line S3 connected to the ix-th circuit row, where x ≥ 1. For example, x = 1, 2, 3, 4, 5… Figure 16 illustrates this with x = 2 as an example. In this structure, the first scan line S1 corresponding to the same circuit row 4 provides the enable level earlier than the third scan line S3 provides the enable level.

[0121] Alternatively, the third scan line S3 connected to the i-th circuit row is electrically connected to the first scan line S1 connected to the ix-th circuit row. In this structure, the third scan line S3 corresponding to the same circuit row 4 provides the enable level earlier than the first scan line S1 provides the enable level.

[0122] Taking the electrical connection of the first scan line S1 connected to the i-th circuit row and the third scan line S3 connected to the ix-th circuit row as an example, in this design, the first scan line S1 connected to the i-th circuit row and the third scan line S3 connected to the ix-th circuit row can be electrically connected to the same level shift register. This allows only one shift register to be configured for the first scan line S1 and the third scan line S3, simplifying the panel structure design. Alternatively, the first scan line S1 and the third scan line S3 can also be driven on both sides. That is, the first scan line S1 and the third scan line S3 are connected to a shift register on one side and a shift register on the other side. Compared to configuring different shift registers for the first scan line S1 and the third scan line S3 respectively, this dual-sided driving does not increase the bezel width and can also enhance the driving capability of the first scan signal and the third scan signal.

[0123] Referring to Figure 13, the pixel circuit 1 also includes a second reset transistor T6. The gate of the second reset transistor T6 is electrically connected to the fourth scan line S4, the first terminal receives the reset signal, and the second terminal is electrically connected to the fourth node N4.

[0124] The following explanation, using Figures 13 and 14 as examples, illustrates the operation of pixel circuit 1, with all transistors in pixel circuit 1 being N-type transistors and the first terminal of the second reset transistor T6 electrically connected to the second reset line Ref2:

[0125] During the reset phase t1', the third scan line S3 provides a high level to control the second transistor T5 to conduct, writing the first reset signal of the first reset line Ref1 into the first node N1; the fourth scan line S4 provides a high level to control the second reset transistor T6 to conduct, writing the second reset signal of the second reset line Ref2 into the fourth node N4, and simultaneously coupling downwards to the third node N3. During this phase, V N1 =V ref1 V N4 =V ref2 .

[0126] During the threshold compensation phase t2', the second transistor T5 and the second reset transistor T6 remain on; the first scan line S3 provides a high level to control the first transistor T3 to turn on, writing the signal from the first power line PVDD into the second node, and the third node N3 captures the threshold voltage to perform threshold compensation on the driving transistor T0. During this phase, V N1 =V ref1 V N2 =V PVDD V N4 =V ref2 V N3 =V ref1 -Vth.

[0127] During the data writing phase t3', the second scan line S2 provides a high level to control the data writing transistor T4 to turn on, writing the data line Data signal to the first node N1. During this phase, V... N1 =V Data The voltage at the first node N1 is determined by V. ref1 It changed to V Data Due to the influence of the first capacitor C1 and the second capacitor C2, the potential of the third node N3 changes synchronously with the potential of the first node N1.

[0128] During the light-emitting stage Te, the light-emitting control line Emit provides a high level to control the first light-emitting control transistor T1 and the second light-emitting control transistor T2 to conduct, allowing the driving current to flow into the light-emitting element 2. The driving current flowing into the light-emitting element 2 during this stage is I = k × (V gs -Vth) 2 , Therefore, it can be concluded that

[0129] Regarding control unit 3, in another feasible implementation, as shown in FIG17, FIG17 is a schematic diagram of another structure of the pixel circuit provided in the embodiment of the present invention. The first transistor T3 is electrically connected to the first node N1. The first terminal of the second transistor T5 is electrically connected to the first node N1, and the second terminal is electrically connected to the second node N2.

[0130] Based on this structure, the control unit 3 writing constant voltage signals to the first node N1 and the second node N2 specifically means: using the first transistor T3 to write the first power signal provided by the first power line PVDD to the first node N1, and then using the second transistor T5 to further write the first power signal of the first node N1 to the second node N2. In this structure, the constant voltage signals written to the first node N1 and the second node N2 are the same.

[0131] Furthermore, as shown in Figure 18, which is a timing diagram corresponding to Figure 17, the driving cycle DC of the pixel circuit 1 includes a write frame WF, which includes a reset phase t1', a threshold compensation phase t2', and a data writing phase t3'.

[0132] During the reset phase t1', the first transistor T3 is turned on, and the constant voltage signal of the first power line PVDD is written into the first node N1, and the first node N1 is reset using the first reset signal.

[0133] During the threshold compensation stage t2', the first transistor T3 and the second transistor T5 are turned on, writing the constant voltage signal of the first power line PVDD into the first node N1 and the second node N2. The third node N3 captures the threshold voltage and performs threshold compensation on the driving transistor T0.

[0134] During the data writing phase t3', the data writing transistor T4 is turned on, writing the signal of the data line Data to the first node N1.

[0135] In the above structure, during the threshold compensation stage t2', the third node N3 captures the threshold voltage and performs threshold compensation on the driving transistor T0. During the data line writing stage, the data signal is written to the first node N1. This design allows for step-by-step threshold compensation and data writing, ensuring sufficient time for both processes and enabling more thorough charging and compensation.

[0136] In one feasible implementation, referring to Figures 17 and 19, Figure 19 is a schematic diagram of another structure of the pixel circuit provided in the embodiment of the present invention. The pixel circuit 1 further includes a first reset transistor T7. The gate of the first reset transistor T7 is electrically connected to the fourth scan line S4, the first electrode receives a reset signal at least when it is turned on, and the second electrode is electrically connected to the third node N3 or the second node N2.

[0137] By setting a first reset transistor T7, the received reset signal can be written to the third node N3 or the second node N2, thereby resetting the third node N3 or the second node N2 before charging. This makes the reset of the driving transistor T0 more thorough, configuring it to a more definite initial state, which helps to improve charging uniformity.

[0138] Furthermore, referring to Figures 17 and 18, the driving cycle DC of pixel circuit 1 includes a write frame WF, which includes a reset phase t1'. In the reset phase t1', the first transistor T3 is turned on, writing the constant voltage signal of the first power line PVDD to the first node N1, thus resetting the first node N1; the first reset transistor T7 is turned on, writing the reset signal it receives to the third node N3 or the second node N2 connected to it, thus resetting the third node N3 or the second node N2.

[0139] Referring to Figure 17, the pixel circuit 1 also includes a second reset transistor T6. The gate of the second reset transistor T6 is electrically connected to the fourth scan line S4, the first terminal receives the reset signal, and the second terminal is electrically connected to the fourth node N4.

[0140] The following explanation, using Figures 17 and 18 as examples, illustrates the operation of pixel circuit 1, with all transistors in pixel circuit 1 being N-type transistors and the first terminal of the second reset transistor T6 electrically connected to the second reset line Ref2:

[0141] During the reset phase t1', the first scan line S1 provides a high level to control the first transistor T3 to conduct, writing the signal of the first power line PVDD into the first node N1; the fourth scan line S4 provides a high level to control the first reset transistor T6 and the second reset transistor T6 to conduct, writing the signal of the first reset line Ref1 into the third node N3, and the signal of the second reset line Ref2 into the fourth node N4. During this phase, V N1 =V PVDD V N3 =V ref1 V N4 =V ref2 .

[0142] During the threshold compensation phase t2', the first transistor T3 remains on; the third scan line S3 provides a high level to control the second transistor T5 to turn on, and the third node N3 captures the threshold voltage to perform threshold compensation on the driving transistor T0. During this phase, V N1 =V N2 =V PVDD V N3 =V PVDD -Vth.

[0143] During the data writing phase t3', the second scan line S2 provides a high level to control the data writing transistor T4 to turn on, writing the data line Data signal to the first node N1. During this phase, V... N1 =V Data The voltage at the first node N1 is determined by V. PVDD It changed to V DataDue to the influence of the first capacitor C1 and the second capacitor C2, the potential of the third node N3 changes synchronously with the potential of the first node N1.

[0144] During the light-emitting stage Te, the light-emitting control line Emit provides a high level to control the first light-emitting control transistor T1 and the second light-emitting control transistor T2 to conduct, allowing the driving current to flow into the light-emitting element 2. The driving current flowing into the light-emitting element 2 during this stage is I = k × (V gs -Vth) 2 .in, Therefore, it can be concluded that

[0145] In one possible implementation, the first terminal of the first reset transistor T7 is electrically connected to a reset line for providing a reset signal. For example, referring to Figures 17 and 19, the first terminal of the first reset transistor T7 is electrically connected to the first reset line Ref1.

[0146] With this configuration, the first terminal of the first reset transistor T7 continuously receives a stable reset signal, which allows for better reset of the second node N2 or the third node N3 when it is turned on.

[0147] Further, as shown in Figures 20 and 21, Figure 20 is a schematic diagram of another structure of the pixel circuit provided in the embodiment of the present invention, and Figure 21 is a schematic diagram of another structure of the pixel circuit provided in the embodiment of the present invention. The pixel circuit 1 further includes a second reset transistor T6, the gate of the second reset transistor T6 is electrically connected to the fourth scan line, and the second electrode is electrically connected to the light-emitting element 2.

[0148] In this configuration, the first terminals of the second reset transistor T6 and the first reset transistor T7 are electrically connected to the same reset line. For example, both the first reset transistor T7 and the second reset transistor T6 are electrically connected to the first reset line Ref1.

[0149] With this setup, only one reset line is needed for the first reset transistor T7 and the second reset transistor T6. The same reset voltage is used to reset the anode of the light-emitting element 2 and the second node N2 or the third node N3, which can save the number of signal lines in the display panel.

[0150] Alternatively, referring to Figures 17 and 18, the second reset transistor T6 and the first reset transistor T7 can also be electrically connected to different reset lines. The first reset transistor T7 is electrically connected to the first reset line Ref1, and the gate of the second reset transistor T6 is electrically connected to the second reset line Ref2. This allows for setting different reset voltages for the light-emitting element 2 and the driving transistor T0, making the reset of the light-emitting element 2 and the driving transistor T0 more flexible.

[0151] In one feasible implementation, as shown in Figures 22 and 23, Figure 22 is a schematic diagram of another structure of the pixel circuit provided in the embodiment of the present invention, and Figure 23 is a schematic diagram of another structure of the pixel circuit provided in the embodiment of the present invention. The pixel circuit 1 further includes a second reset transistor T6. The gate of the second reset transistor T6 is electrically connected to the fourth scan line S4, the first electrode receives a reset signal, and the second electrode is electrically connected to the light-emitting element 2.

[0152] The first terminal of the first reset transistor T7 is electrically connected to the second terminal of the second reset transistor T6, that is, the first terminal of the first reset transistor T7 is electrically connected to the fourth node N4.

[0153] During the reset phase t1', the second reset transistor T6 is turned on, and the reset signal it receives is written to the fourth node N4, and then written to the second node N2 or the third node N3 via the first reset transistor T7, thus still achieving normal reset of the second node N2 or the third node N3.

[0154] In one feasible implementation, as shown in FIG24, which is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention, the second plate of the second capacitor C2 is electrically connected to the first power supply line PVDD. Alternatively, the second plate of the second capacitor C2 receives a reset signal, for example, the second plate of the second capacitor C2 is electrically connected to the first reset line Ref1 connected to the second transistor T5.

[0155] In this structure, the second plate of the second capacitor C2 receives a stable constant voltage signal, and the second capacitor C2 can better control the potential of the third node N3.

[0156] Alternatively, in another feasible implementation, referring to FIG13, the pixel circuit 1 further includes a second reset transistor T6. The gate of the second reset transistor T6 is electrically connected to the fourth scan line S4, the first electrode receives a reset signal, and the second electrode is electrically connected to the light-emitting element 2. The second plate of the second capacitor C2 is electrically connected to the second electrode of the second reset transistor T6, that is, the second plate of the second capacitor C2 is electrically connected to the fourth node N4.

[0157] In this structure, when the second reset transistor T6 is turned on, it writes the reset signal it receives into the fourth node N4, so that the second plate of the second capacitor C2 can receive a stable constant voltage signal, and the second capacitor C2 can better control the potential of the third node N3.

[0158] In one feasible implementation, as shown in Figures 25 and 26, Figure 25 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention, and Figure 26 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention. At least one gate of the driving transistor T0 further includes a second gate. That is, the driving transistor T0 is a dual-gate transistor including a top gate and a bottom gate, wherein the top gate is a first gate and the bottom gate is a second gate.

[0159] Referring to Figure 25, the second gate is electrically connected to the first power supply line PVDD, or the second gate receives a reset signal, for example, the second gate is electrically connected to the first reset line Ref1 connected to the second transistor T5.

[0160] Alternatively, referring to Figure 26, the pixel circuit 1 further includes a second reset transistor T6. The gate of the second reset transistor T6 is electrically connected to the fourth scan line S4, the first terminal receives a reset signal, and the second terminal is electrically connected to the light-emitting element 2. The second gate is electrically connected to the second terminal of the second reset transistor T6, that is, the second gate is electrically connected to the fourth node N4.

[0161] The driving transistor T0 adopts a dual-gate transistor design, which helps to improve the stability and mobility of the driving transistor T0, and its device characteristics are better.

[0162] In this embodiment of the invention, the other transistors in the pixel circuit 1 besides the driving transistor T0 can also be dual-gate transistors. That is, at least one of the first light-emitting control transistor T1, the second light-emitting control transistor T2, the first transistor T3, the data writing transistor T4, the second transistor T5, and the second reset transistor T6 is a single-gate transistor, and / or at least one of the first light-emitting control transistor T1, the second light-emitting control transistor T2, the first transistor T3, the data writing transistor T4, the second transistor T5, and the second reset transistor T6 is a dual-gate transistor.

[0163] For example, referring to Figure 27, the second transistor T5 can be designed as a dual-gate transistor to reduce the leakage current of the first node N1, the data write transistor T4 can be designed as a dual-gate transistor to reduce the leakage current of the third node N3, and the second reset transistor T6 can be designed as a dual-gate transistor to reduce the leakage current of the fourth node N4.

[0164] When at least one of the first light-emitting control transistor T1, the second light-emitting control transistor T2, the first transistor T3, the data writing transistor T4, the second transistor T5, and the second reset transistor T6 is a dual-gate transistor, the connection method of the gates of these transistors described above is the top gate connection method, and the bottom gate can be electrically connected to the top gate, the first electrode, or the second electrode of the transistor.

[0165] In one feasible implementation, in conjunction with Figures 4, 9 and 10, Figures 13 to 15, and Figures 17 and 18, the pixel circuit 1 further includes a second reset transistor T6, the gate of which is electrically connected to the fourth scan line S4, the first electrode of which is connected to the receiving reset signal, and the second electrode of which is electrically connected to the light-emitting element 2.

[0166] At the first frequency f1, the driving cycle DC of pixel circuit 1 includes a write frame WF and a hold frame HF. During the hold frame HF, the second reset transistor T6 is turned on at least once, writing the received reset signal into the light-emitting element 2. Specifically, the second reset transistor T6 is turned on at least once during the non-light-emitting phase T-ne of the hold frame HF.

[0167] While holding frame HF, the fourth scan line S4 provides an enable level to control the second reset transistor T6 to turn on, resetting the fourth node N4. This eliminates the influence of residual charge on the anode, avoids interference with current injection during the next light emission, and improves the reliability of light emission.

[0168] It should be noted that the duration of the enable level provided by the fourth scan line S4 in the write frame WF and the hold frame HF can be equal or unequal. For example, the duration of the enable level provided by the fourth scan line S4 in the hold frame HF can be less than the duration of the enable level provided by the fourth scan line S4 in the write frame WF.

[0169] Furthermore, referring to Figures 17 and 18, when the pixel circuit includes the first reset transistor T7, while holding frame HF, the first reset transistor T7 can be controlled to conduct at least once to reset the third node N3 or the second node N2 at least once, adjust the bias voltage of the driving transistor T0, and thus adjust the bias state of the driving transistor T0, thereby improving the problems of brightness difference and afterimage in the first frame caused by transistor hysteresis effect, as well as improving the flicker problem at low frequency.

[0170] In particular, when both the first reset transistor T7 and the second reset transistor T6 are electrically connected to the fourth scan line S4, in the holding frame HF, the fourth scan line S4 provides at least one enable level, which can simultaneously achieve at least one reset of the fourth node N4, the third node N3, or the second node N2.

[0171] In one feasible implementation, referring to Figures 4, 9, and 10, at the first frequency f1, the drive cycle DC of pixel circuit 1 includes a write frame WF and a hold frame HF. During the hold frame HF, the data write transistor T4 is turned on at least once, writing the signal of the data line Data to its connected second node N2 or third node N3. Specifically, the data write transistor T4 is turned on at least once during the non-light-emitting phase T-ne of the hold frame HF.

[0172] While maintaining frame HF, the second scan line S2 provides an enable level to control the data writing transistor T4 to turn on, writing the signal of the data line Data to the second node N2 or the third node N3 connected to it. This can adjust the bias state of the driving transistor T0, thereby improving problems such as brightness difference and afterimage in the first frame caused by transistor hysteresis, as well as improving flickering at low frequencies.

[0173] It should be noted that the duration of the enable level provided by the second scan line S2 in the write frame WF and the hold frame HF may be equal or unequal. For example, referring to Figure 9, the duration of the enable level provided by the second scan line S2 in the hold frame HF is less than the duration of the enable level provided by the second scan line S2 in the write frame WF; or, referring to Figure 10, the duration of the enable level provided by the second scan line S2 in the hold frame HF is equal to the duration of the enable level provided by the second scan line S2 in the write frame WF.

[0174] Furthermore, it should be noted that during the hold frame HF, when the fourth scan line S4 provides an enable level to control the second reset transistor T6 to also conduct, the duration of the enable level provided by the second scan line S2 can be equal to or unequal to the duration of the enable level provided by the fourth scan line S4. For example, referring to Figure 9, the duration of the enable level provided by the fourth scan line S4 can be greater than the duration of the enable level provided by the second scan line S2, so as to perform a longer reset of the anode of the light-emitting element 2. Furthermore, during the hold frame HF, the enable levels provided by the second scan line S2 and the fourth scan line S4 can overlap or not. For example, referring to Figure 9, the enable levels provided by the second scan line S2 and the fourth scan line S4 do not overlap.

[0175] In one feasible implementation, referring to FIG4, the pixel circuit 1 further includes a data writing transistor T4, a second transistor T5, and a second reset transistor T6.

[0176] In this configuration, the gate of the data writing transistor T4 is electrically connected to the second scan line S2, the first terminal is electrically connected to the data line Data, and the second terminal is electrically connected to the driving transistor T0. The second terminal of the data writing transistor T4 can be electrically connected to the first node N1, the second node N2, or the third node N3; these structures have been described in the above embodiments and will not be repeated here.

[0177] The gate of the second transistor T5 is electrically connected to the third scan line S3, and its first and / or second terminals are electrically connected to the driving transistor T0. The second transistor T5 can have its second terminal electrically connected to the first node N1, or its first terminal connected to the first node N1 and its second terminal connected to either the second node N2 or the third node N3. These structures have been described in the above embodiments and will not be repeated here.

[0178] The first terminal of the second reset transistor T6 receives the reset signal, and the second terminal is electrically connected to the light-emitting element 2.

[0179] In one feasible implementation, referring to Figure 4, both the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are N-type transistors, such as IGZO transistors. These transistors have lower leakage current, resulting in superior circuit characteristics for pixel circuit 1. In this case, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned on when the light-emitting control line Emit provides a high-level signal and turned off when the light-emitting control line Emit provides a low-level signal.

[0180] Furthermore, referring to Figure 4, the first transistor T3, the data writing transistor T4, the second transistor T5, and the second reset transistor T6 are all N-type transistors, such as IGZO transistors.

[0181] In this design, all transistors in pixel circuit 1 are N-type transistors, and the transistor film layer design is consistent, resulting in better panel uniformity. Moreover, these transistors have lower leakage current, which can effectively improve the leakage current problem of driving transistor T0 and stabilize the node voltage of driving transistor T0.

[0182] Alternatively, in another feasible implementation, as shown in Figures 27 and 28, Figure 27 is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, and Figure 28 is a timing diagram corresponding to Figure 27. Both the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are P-type transistors, for example, both are LTPS transistors. In this structure, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 have higher electron mobility and faster transistor response speed. In this case, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned on when the light-emitting control line Emit is low-level and turned off when the light-emitting control line Emit is high-level.

[0183] Further, as shown in FIG29, which is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention, the first light-emitting control transistor T1 includes two first sub-transistors T01 connected in series, and the gates of the two first sub-transistors T01 are electrically connected. The second light-emitting control transistor T2 includes two second sub-transistors T02 connected in series, and the gates of the two second sub-transistors T02 are electrically connected.

[0184] When the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are designed as P-type transistors, having each of these two light-emitting control transistors include two sub-transistors connected in series can help reduce the leakage current of these two light-emitting control transistors and optimize the circuit characteristics of pixel circuit 1.

[0185] In one feasible implementation, as shown in FIG30, which is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention, the type of the second reset transistor T6 is opposite to that of the first light-emitting control transistor T1 and the second light-emitting control transistor T2. The gate of the second reset transistor T6 is electrically connected to the light-emitting control signal line.

[0186] That is, when the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are N-type transistors, the second reset transistor T6 is a P-type transistor. When the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are P-type transistors, the second reset transistor T6 is an N-type transistor.

[0187] When the type of the second reset transistor T6 is opposite to that of the two light-emitting control transistors, the second reset transistor T6 can be connected to the light-emitting control line Emit. During the non-light-emitting phase T-ne, the light-emitting control line Emit controls the two light-emitting control transistors to be off and controls the second reset transistor T6 to be on, thus continuously resetting the anode of the light-emitting element 2. During the light-emitting phase Te, the light-emitting control line Emit controls the two light-emitting control transistors to be on and the second reset transistor T6 to be off, preventing the second reset transistor T6 from affecting the anode potential of the light-emitting element 2.

[0188] With this configuration, while ensuring the normal operation of pixel circuit 1, there is no need to configure additional scan lines for the second reset transistor T6, thus reducing the number of signal lines in the panel.

[0189] In one feasible implementation, referring to Figure 30, the second transistor T5 is an N-type transistor, such as an IGZO transistor. The second transistor T5 is electrically connected to the driving transistor T0. Designing it as an N-type transistor can reduce the impact of leakage current on the node voltage of the driving transistor T0.

[0190] Further, referring to Figures 4 and 32, at least one of the data writing transistor T4 and the first transistor T3 is an N-type transistor, and / or, at least one of the data writing transistor T4 and the first transistor T3 is a P-type transistor.

[0191] When the data writing transistor T4 and / or the first transistor T3 are P-type transistors, the data writing transistor T4 and / or the first transistor T3 have high electron mobility and fast transistor response speed. At this time, the data writing transistor T4 turns on when the second scan line S2 is low and turns off when the second scan line S2 is high, and / or the first transistor T3 turns on when the first scan line S1 is low and turns off when the first scan line S1 is high.

[0192] When the data writing transistor T4 and / or the first transistor T3 are N-type transistors, the leakage current of the data writing transistor T4 and / or the first transistor T3 is small, which can reduce the impact of leakage current on the node potential of the driving transistor T0. At this time, the data writing transistor T4 is turned on when the second scan line S2 passes through a high level and turned off when the second scan line S2 passes through a low level, and / or the first transistor T3 is turned on when the first scan line S1 passes through a high level and turned off when the first scan line S1 passes through a low level.

[0193] In one feasible implementation, as shown in FIG31, FIG31 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, wherein the gate of the second reset transistor T6 is electrically connected to the fourth scan line S4.

[0194] The display panel also includes a first shift register 01, a second shift register 02, a third shift register 03, a fourth shift register 04, a fifth shift register 05, and a sixth shift register 06.

[0195] Specifically, the first shift register 01 is electrically connected to the first scan line S1, the second shift register 02 and the third shift register 03 are both electrically connected to the second scan line S2, the fourth shift register 04 is electrically connected to the third scan line S3, the fifth shift register 05 is electrically connected to the fourth scan line, and the sixth shift register 06 is electrically connected to the light emission control line Emit.

[0196] The display panel also includes a display area AA. The second shift register 02 and the third shift register 03 are located on opposite sides of the display area AA, respectively. Two of the first shift register 01, the fourth shift register 04, the fifth shift register 05, and the sixth shift register 06 are located on one side of the display area AA, and the other two are located on the other side of the display area AA.

[0197] The second scan line S2 controls data writing, and its signal stability has a greater impact on brightness. Therefore, the second scan line S2 can be driven bilaterally using the second shift register 02 and the third shift register 03 to improve the driving capability of the second scan signal. Based on this, two of the first shift register 01, the fourth shift register 04, the fifth shift register 05, and the sixth shift register 06 are located on one side of the display area AA along with the second shift register 02, while the other two of the fourth shift register 04, the fifth shift register 05, and the sixth shift register 06 are located on the other side of the display area AA along with the third shift register 03. This ensures that the number of shift registers on both sides of the display area AA is equal, which helps optimize the left and right bezel design of the display panel.

[0198] Furthermore, as shown in Figure 32, which is another structural schematic diagram of the display panel provided in the embodiment of the present invention, the display panel may also include a seventh shift register 07, an eighth shift register 08, a ninth shift register 09, and a tenth shift register 010.

[0199] The seventh shift register 07 is electrically connected to the light emission control line Emit, and the seventh shift register 07 and the sixth shift register 06 are located on opposite sides of the display area AA.

[0200] The eighth shift register 08 is electrically connected to the first scan line S1. The eighth shift register 08 and the first shift register 01 are located on opposite sides of the display area AA, respectively.

[0201] The ninth shift register 09 is electrically connected to the third scan line S3. The ninth shift register 09 and the fourth shift register 04 are located on opposite sides of the display area AA, respectively.

[0202] The tenth shift register 010 is electrically connected to the fourth scan line S4. The tenth shift register 010 and the fifth shift register 05 are located on opposite sides of the display area AA.

[0203] In the above structure, the first scan line S1, the third scan line S3, the fourth scan line S4, and the emission control line Emit are all driven on both sides, thus improving the driving capability of these signals. Furthermore, the number of shift registers on both sides of the display area AA is equal, which helps optimize the left and right bezel design of the display panel. This design is more suitable for large-size display panels, which have ample space on the left and right bezels to accommodate a larger number of shift registers.

[0204] Based on the same inventive concept, this embodiment of the invention also provides a display device, as shown in FIG33. FIG33 is a schematic diagram of a structure of the display device provided in this embodiment of the invention, which includes the aforementioned display panel 100. Of course, the display device shown in FIG33 is merely illustrative, and the display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, or television.

[0205] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0206] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, Includes a pixel circuit, the pixel circuit comprising: A driving transistor, wherein the driving transistor is an N-type transistor; A first light-emitting control transistor and a second light-emitting control transistor, wherein the gates of the first light-emitting control transistor and the second light-emitting control transistor are electrically connected to the same light-emitting control line, the first terminal of the first light-emitting control transistor is electrically connected to the first power line and the second terminal is electrically connected to the first terminal of the driving transistor, and the first terminal of the second light-emitting control transistor is electrically connected to the second terminal of the driving transistor and the second terminal is electrically connected to the light-emitting element. The first transistor has its gate electrically connected to the first scan line, its first electrode electrically connected to the first power line, and its second electrode electrically connected to the driving transistor.

2. The display panel according to claim 1, characterized in that, The driving cycle of the pixel circuit includes at least one frame, and one frame includes a non-light-emitting phase and a light-emitting phase; in the non-light-emitting phase, the first light-emitting control transistor and the second light-emitting control transistor are turned off, and in at least a portion of the time period of the light-emitting phase, the first light-emitting control transistor and the second light-emitting control transistor are turned on. The frames in the driving cycle include write frames, during a portion of the non-light-emitting phase of the write frame, the first transistor is turned on to write the signal of the first power line into the driving transistor.

3. The display panel according to claim 1, characterized in that, The driving cycle of the pixel circuit includes at least one frame, and one frame includes a non-light-emitting phase and a light-emitting phase; in the non-light-emitting phase, the first light-emitting control transistor and the second light-emitting control transistor are turned off, and in the light-emitting phase, the light-emitting control line provides at least two pulses.

4. The display panel according to claim 1, characterized in that, The driving transistor includes at least one gate, the at least one gate includes a first gate, the first gate of the driving transistor is electrically connected to a first node, the first electrode is electrically connected to a second node, and the second electrode is electrically connected to a third node; The pixel circuit further includes a data writing transistor and a second transistor; wherein, the gate of the data writing transistor is electrically connected to the second scan line and the first electrode is electrically connected to the data line, the gate of the second transistor is electrically connected to the third scan line and the second electrode is electrically connected to the first node, and one of the second electrode of the data writing transistor and the first electrode of the second transistor is electrically connected to the second node and the other is electrically connected to the third node. The second terminal of the first transistor is electrically connected to the second transistor.

5. The display panel according to claim 4, characterized in that, The driving cycle of the pixel circuit includes a write frame, which includes a reset phase and a data writing and compensation phase. During the reset phase, the first transistor and the second transistor are turned on, writing the signal of the first power line to the first node, and writing to the second node or the third node connected to the second transistor; During the data writing and compensation phase, the data writing transistor and the second transistor are turned on to write the signal of the data line into the first node and perform threshold compensation on the driving transistor.

6. The display panel according to claim 5, characterized in that, The reset phase and the data writing and compensation phase also include a first intermediate phase; During the first intermediate stage, the first transistor and the data write transistor are turned off, and the second transistor is turned on.

7. The display panel according to claim 5, characterized in that, The reset phase and the data writing and compensation phase also include a first intermediate phase; In the first intermediate stage, the first transistor and the second transistor are turned off, and the data writing transistor is turned on, so that the signal of the data line is written to the second node or the third node connected to the data writing transistor.

8. The display panel according to claim 4, characterized in that, The second terminal of the first transistor is electrically connected to the first node.

9. The display panel according to claim 4, characterized in that, The second terminal of the first transistor is electrically connected to the first terminal of the second transistor.

10. The display panel according to claim 1, characterized in that, The driving transistor includes at least one gate, the at least one gate includes a first gate, the first gate of the driving transistor is electrically connected to a first node, the first electrode is electrically connected to a second node, and the second electrode is electrically connected to a third node; The pixel circuit further includes a data writing transistor, wherein the gate of the data writing transistor is electrically connected to the second scan line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first node. The pixel circuit further includes a control unit, which includes the first transistor and the second transistor, wherein the gate of the second transistor is electrically connected to the third scan line, and the first electrode and / or the second electrode are electrically connected to the driving transistor. The control unit is used to write constant voltage signals to the first node and the second node.

11. The display panel according to claim 10, characterized in that, The pixel circuit further includes a first capacitor and a second capacitor; wherein, the first plate of the first capacitor is electrically connected to the first node, the second plate is electrically connected to the third node, the first plate of the second capacitor receives a constant voltage signal for at least a portion of the time period, and the second plate is electrically connected to the third node.

12. The display panel according to claim 10, characterized in that, The first transistor is electrically connected to the second node, and the first terminal of the second transistor is electrically connected to the first reset line, and the second terminal is electrically connected to the first node.

13. The display panel according to claim 12, characterized in that, The driving cycle of the pixel circuit includes a write frame, which includes a reset phase, a threshold compensation phase, and a data writing phase. During the reset phase, the second transistor is turned on, writing the constant voltage signal of the first reset line into the first node; During the threshold compensation stage, the second transistor is turned on, and the constant voltage signal of the first reset line is written to the first node. The first transistor is turned on, and the constant voltage signal of the first power line is written to the second node to perform threshold compensation on the driving transistor. During the data writing phase, the data writing transistor is turned on, and the voltage of the data line is written to the first node.

14. The display panel according to claim 12, characterized in that, The display panel includes a plurality of circuit rows arranged along a first direction, and the circuit rows include a plurality of pixel circuits arranged along a second direction, wherein the first direction intersects the second direction; Wherein, the third scan line connected to the i-th circuit row is electrically connected to the first scan line connected to the ix-th circuit row, x≥1; Alternatively, the first scan line connected to the i-th circuit row is electrically connected to the third scan line connected to the ix-th circuit row.

15. The display panel according to claim 10, characterized in that, The first transistor is electrically connected to the first node, and the first electrode of the second transistor is electrically connected to the first node, and the second electrode is electrically connected to the second node.

16. The display panel according to claim 15, characterized in that, The driving cycle of the pixel circuit includes a write frame, which includes a reset phase, a threshold compensation phase, and a data writing phase. During the reset phase, the first transistor is turned on, and the constant voltage signal of the first power line is written to the first node. During the threshold compensation stage, the first transistor and the second transistor are turned on, and the constant voltage signal of the first power line is written into the first node and the second node to perform threshold compensation on the driving transistor. During the data writing phase, the data writing transistor is turned on, and the signal of the data line is written to the first node.

17. The display panel according to claim 15, characterized in that, The pixel circuit further includes a first reset transistor, the gate of which is electrically connected to the fourth scan line, the first electrode of which receives a reset signal at least when it is turned on, and the second electrode of which is electrically connected to the third node or the second node.

18. The display panel according to claim 17, characterized in that, The driving cycle of the pixel circuit includes a write frame, and the write frame includes a reset phase; During the reset phase, the first transistor is turned on, writing the constant voltage signal of the first power line into the first node, and the first reset transistor is turned on, writing the reset signal it receives into the third node or the second node to which it is connected.

19. The display panel according to claim 17, characterized in that, The first terminal of the first reset transistor is electrically connected to the reset line used to provide the reset signal.

20. The display panel according to claim 19, characterized in that, The pixel circuit further includes a second reset transistor, the gate of which is electrically connected to the fourth scan line and the second electrode of which is electrically connected to the light-emitting element; The first terminal of the second reset transistor and the first terminal of the first reset transistor are electrically connected to the same reset line.

21. The display panel according to claim 17, characterized in that, The pixel circuit further includes a second reset transistor, the gate of which is electrically connected to the fourth scan line, the first terminal of which receives a reset signal, and the second terminal of which is electrically connected to the light-emitting element; The first terminal of the first reset transistor is electrically connected to the second terminal of the second reset transistor.

22. The display panel according to claim 11, characterized in that, The second plate of the second capacitor is electrically connected to the first power line, or the second plate of the second capacitor receives a reset signal.

23. The display panel according to claim 11, characterized in that, The pixel circuit further includes a second reset transistor, the gate of which is electrically connected to the fourth scan line, the first terminal of which receives a reset signal, and the second terminal of which is electrically connected to the light-emitting element. The second plate of the second capacitor is electrically connected to the second electrode of the second reset transistor.

24. The display panel according to claim 1, characterized in that, The at least one gate of the driving transistor further includes a second gate; wherein, The second gate is electrically connected to the first power line; Alternatively, the second gate receives a reset signal; Alternatively, the pixel circuit may further include a second reset transistor, wherein the gate of the second reset transistor is electrically connected to the fourth scan line, the first terminal receives a reset signal, and the second terminal is electrically connected to the light-emitting element; the second gate is electrically connected to the second terminal of the second reset transistor.

25. The display panel according to claim 1, characterized in that, The pixel circuit further includes a second reset transistor, the gate of which is electrically connected to the fourth scan line, the first terminal of which is connected to the receiving reset signal, and the second terminal of which is electrically connected to the light-emitting element. At the first frequency, the driving cycle of the pixel circuit includes a write frame and a hold frame. In the hold frame, the second reset transistor is turned on at least once to write the reset signal it receives into the light-emitting element.

26. The display panel according to claim 4, characterized in that, At the first frequency, the driving cycle of the pixel circuit includes a write frame and a hold frame. In the hold frame, the data write transistor is turned on at least once to write the signal of the data line to the second or third node to which it is connected.

27. The display panel according to claim 1, characterized in that, The pixel circuit also includes: A data writing transistor, wherein the gate of the data writing transistor is electrically connected to the second scan line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the driving transistor; The second transistor has its gate electrically connected to the third scan line, and its first and / or second terminals electrically connected to the driving transistor. The second reset transistor has a first terminal that receives a reset signal and a second terminal that is electrically connected to the light-emitting element.

28. The display panel according to claim 27, characterized in that, Both the first light-emitting control transistor and the second light-emitting control transistor are N-type transistors.

29. The display panel according to claim 28, characterized in that, The first transistor, the data write transistor, the second transistor, and the second reset transistor are all N-type transistors.

30. The display panel according to claim 27, characterized in that, Both the first light-emitting control transistor and the second light-emitting control transistor are P-type transistors.

31. The display panel according to claim 30, characterized in that, The first light-emitting control transistor includes two first sub-transistors connected in series, and the gates of the two first sub-transistors are electrically connected. The second light-emitting control transistor includes two second sub-transistors connected in series, and the gates of the two second sub-transistors are electrically connected.

32. The display panel according to claim 28 or 30, characterized in that, The type of the second reset transistor is opposite to that of the first light-emitting control transistor and the second light-emitting control transistor, and the gate of the second reset transistor is electrically connected to the light-emitting control signal line.

33. The display panel according to claim 28 or 30, characterized in that, The second transistor is an N-type transistor; At least one of the data writing transistor and the first transistor is an N-type transistor, and / or at least one of the data writing transistor and the first transistor is a P-type transistor.

34. The display panel according to claim 27, characterized in that, The gate of the second reset transistor is electrically connected to the fourth scan line; The display panel also includes: The first shift register is electrically connected to the first scan line; Both the second shift register and the third shift register are electrically connected to the second scan line; The fourth shift register is electrically connected to the third scan line; The fifth shift register is electrically connected to the fourth scan line; The sixth shift register is electrically connected to the light-emitting control line; The display panel further includes a display area, and the second shift register and the third shift register are located on opposite sides of the display area. Two of the first shift register, the fourth shift register, the fifth shift register, and the sixth shift register are located on one side of the display area, and the other two are located on the other side of the display area.

35. The display panel according to claim 34, characterized in that, The display panel also includes: The seventh shift register is electrically connected to the light-emitting control line and is located on opposite sides of the display area, respectively, as is the sixth shift register. The eighth shift register is electrically connected to the first scan line and is located on opposite sides of the display area, respectively, as the first shift register. The ninth shift register is electrically connected to the third scan line and is located on opposite sides of the display area, respectively, as is the fourth shift register. The tenth shift register is electrically connected to the fourth scan line and is located on opposite sides of the display area, respectively, as is the fifth shift register.

36. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 35.

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