Switch transistor drive circuit and energy storage device

Abstract

A switch transistor drive circuit (200) and an energy storage device, configured to drive a buck-boost circuit (100), comprising: a logic module (210), a first output module (220), and a second output module (230); the logic module (210) being separately connected to the first output module (220) and the second output module (230), the first output module (220) being further connected to a buck bridge arm (110) of the buck-boost circuit (100), and the second output module (230) being further connected to a boost bridge arm (120) of the buck-boost circuit (100); and the logic module (210) being configured to receive a drive signal and a boost-buck switching signal. By means of using one switch transistor drive circuit (200) to drive the buck-boost circuit (100) to operate, there is no need to separately provide drive software logic for each switch transistor, so that the structure of the drive circuit (200) can be simplified and the cost of the drive circuit (200) can be reduced.

Description

[Amended according to Rule 26, 14.11.2025] A switching transistor drive circuit and an energy storage device. [Amended according to Rule 26, 2014.11.2025] Technical Field

[0001] [Amended according to Rule 26, 14.11.2025] Embodiments of this application relate to the field of electronic power technology, and particularly to a switching transistor drive circuit and an energy storage device. [Amended according to Rule 26, 14.11.2025] Background Technology

[0002] [Amended according to Rule 26, 14.11.2025] At present, new energy products utilizing clean energy such as solar or wind energy are developing rapidly. For example, energy storage products developed in combination with lithium battery technology usually require voltage conversion using a step-up / step-down circuit because the input voltage is usually lower or higher than the lithium battery system voltage.

[0003] [Amended according to Rule 26 14.11.2025] However, in buck-boost circuits, it is usually necessary to equip input / output (I / O) ports that match the number of power switching transistors, so that the independent I / O ports output the corresponding drive signals to the corresponding power switching transistors. This method requires software resources to handle complex control logic, which leads to increased circuit cost. [Amended according to Rule 26, 14.11.2025] Summary of the Invention

[0004] [Amended according to Rule 26, 14.11.2025] This application provides a switching transistor driving circuit and an energy storage device, which can drive a buck-boost circuit based on a single driving signal, reducing software resources and lowering costs.

[0005] [Amended according to Rule 26, 14.11.2025] In a first aspect, embodiments of this application provide a switching transistor driving circuit for driving a buck-boost circuit, comprising: a logic module, a first output module, and a second output module; the logic module is connected to the first output module and the second output module respectively, the first output module is also connected to a first driving module of the buck bridge arm of the buck-boost circuit, and the second output module is also connected to a second driving module of the boost bridge arm of the buck-boost circuit; the logic module is configured to receive a driving signal and a buck-boost switching signal, and when the buck-boost switching signal is a buck switching signal, output the driving signal to the first output module and output a control signal to the second output module to make the buck-boost circuit operate in buck mode; when the buck-boost switching signal is a boost switching signal, output the driving signal to the second output module and output the control signal to the first output module to make the buck-boost circuit operate in boost mode.

[0006] [Amended according to Rule 26, 14.11.2025] In some embodiments, the logic module includes a first logic unit and a second logic unit; the first logic unit is connected to the first output module, and the second logic unit is connected to the second output module; the first logic unit is configured to output the drive signal to the first output module in response to the buck switching signal, and to output the control signal to the first output module in response to the boost switching signal; the second logic unit is configured to output the control signal to the second output module in response to the buck switching signal, and to output the drive signal to the second output module in response to the boost switching signal.

[0007] [Amended according to Rule 26, 14.11.2025] In some embodiments, the first logic unit includes a first AND gate, a first OR gate, and a first NOT gate; the first input terminal of the first AND gate and the input terminal of the first NOT gate are both used to receive the buck-boost switching signal, the second input terminal of the first AND gate is used to receive the drive signal, the output terminal of the first AND gate is connected to the first input terminal of the first OR gate, the second input terminal of the first OR gate is connected to the output terminal of the first NOT gate, and the output terminal of the first OR gate is connected to the first output module.

[0008] [Amended according to Rule 26, 14.11.2025] In some embodiments, the second logic unit includes a second NOT gate, a second OR gate, and a second AND gate; the input terminal of the second NOT gate and the first input terminal of the second OR gate are both used to receive the buck-boost switching signal, the output terminal of the second NOT gate is connected to the first input terminal of the second AND gate, the second input terminal of the second AND gate is used to receive the drive signal, the output terminal of the second AND gate is connected to the second input terminal of the second OR gate, and the output terminal of the second OR gate is connected to the second output module.

[0009] [Amended according to Rule 26, 14.11.2025] In some embodiments, the first output module includes a first output unit and a second output unit, the second output module includes a third output unit and a fourth output unit, the buck bridge arm includes a buck upper transistor and a buck lower transistor, the first drive module includes a first drive submodule for the buck upper transistor and a second drive submodule for the buck lower transistor, the boost bridge arm includes a boost upper transistor and a boost lower transistor, the second drive module includes a third drive submodule for the boost upper transistor and a fourth drive submodule for the boost lower transistor; the first output terminal of the logic module is respectively connected to the first... The first output unit and the second output unit are connected. The second output terminal of the logic module is connected to the third output unit and the fourth output unit respectively. The first output unit is also connected to the first driver submodule, the second output unit is also connected to the second driver submodule, the third output unit is also connected to the third driver submodule, and the fourth output unit is also connected to the fourth driver submodule. When the buck-boost switching signal is a buck switching signal, the first output unit is configured to output a first pulse width modulation signal to the first driver submodule based on the driving signal, causing the buck upper diode to periodically switch on and off. The second output unit is configured to output a second pulse width modulation signal to the second driving submodule based on the driving signal, causing the buck lower transistor to periodically turn on and off, wherein the buck upper transistor and the buck lower transistor are turned on at different times; the third output unit is configured to output a first level signal to the third driving submodule based on the control signal, causing the boost upper transistor to turn on; the fourth output unit is configured to output a second level signal to the fourth driving submodule based on the control signal, causing the boost lower transistor to turn off; when the buck-boost switching signal is a boost switching signal, the first output unit is configured to output a second level signal to the second driving submodule based on the control signal, causing the buck lower transistor to turn off; The control signal outputs a third-level signal to the first driving submodule to turn on the buck upper transistor. The second output unit is configured to output a fourth-level signal to the second driving submodule based on the control signal to turn off the buck lower transistor. The third output unit is configured to output a third pulse width modulation signal to the third driving submodule based on the driving signal to periodically turn the boost upper transistor on and off. The fourth output unit is configured to output a fourth pulse width modulation signal to the fourth driving submodule based on the driving signal to periodically turn the boost lower transistor on and off. The boost upper transistor and the boost lower transistor are turned on at different times.

[0010] [Amended according to Rule 26, 14.11.2025] In some embodiments, the first output module is further configured to adjust the duty cycle of the first pulse width modulation signal through the first output unit and to adjust the duty cycle of the second pulse width modulation signal through the second output unit, such that the buck lower transistor is turned on after a first dead time delay and the buck upper transistor is turned on after a first dead time delay; the second output module is further configured to adjust the duty cycle of the third pulse width modulation signal through the third output unit and to adjust the duty cycle of the second pulse width modulation signal through the fourth output unit, such that the boost lower transistor is turned on after a second dead time delay and the boost upper transistor is turned on after a second dead time delay.

[0011] [Amended according to Rule 26, 14.11.2025] In some embodiments, the first output unit includes a first resistor, a first capacitor, and a first diode; the second output unit includes a third NOT gate, a second resistor, a second capacitor, and a second diode; the third output unit includes a third resistor, a third capacitor, and a third diode; and the fourth output unit includes a fourth NOT gate, a fourth resistor, a fourth capacitor, and a fourth diode. The first terminal of the first resistor is connected to the first output terminal of the logic module and the cathode of the first diode, respectively. The second terminal of the first resistor is connected to the anode of the first diode, the first terminal of the first capacitor, and the first driving submodule, respectively. The second terminal of the first capacitor is grounded. The first terminal of the third NOT gate is connected to the first output terminal of the logic module, and the second terminal of the third NOT gate is connected to the first terminal of the second resistor, the first output terminal of the first capacitor, and the cathode of the first diode, respectively. The cathode of the second diode is connected to the ground. The second end of the second resistor is connected to the anode of the second diode, the first end of the second capacitor, and the second driving submodule. The second end of the second capacitor is grounded. The first end of the third resistor is connected to the second output terminal of the logic module and the cathode of the third diode. The second end of the third resistor is connected to the anode of the third diode, the first end of the third capacitor, and the third driving submodule. The second end of the third capacitor is grounded. The first end of the fourth NOT gate is connected to the second output terminal of the logic module. The second end of the fourth NOT gate is connected to the first end of the fourth resistor and the cathode of the fourth diode. The second end of the fourth resistor is connected to the anode of the fourth diode, the first end of the fourth capacitor, and the fourth driving submodule. The second end of the fourth capacitor is grounded.

[0012] [Amended according to Rule 26, 14.11.2025] In some embodiments, the switching transistor driving circuit further includes a comparison module; the comparison module is connected to the third driving submodule; the comparison module is configured to receive a first sampling signal of the output current of the buck-boost circuit, and when the voltage of the first sampling signal is less than a first voltage, output a first turn-off signal to the third driving submodule to turn off the boost transistor.

[0013] [Amended according to Rule 26, 14.11.2025] In some embodiments, the switching transistor drive circuit further includes an overcurrent protection module; the overcurrent protection module is connected to the first drive module and the second drive module respectively; the overcurrent protection module is configured to receive a second sampling signal of the input current of the buck-boost circuit, and when the voltage of the second sampling signal is greater than the second voltage, output a second shutdown signal to the first drive module and the second drive module to stop the buck-boost circuit from working.

[0014] [Amended according to Rule 26, 14.11.2025] In a second aspect, embodiments of this application also provide an energy storage device, which includes a buck-boost circuit and a switching transistor drive circuit as described in any embodiment of the first aspect; the switching transistor drive circuit is connected to the buck-boost circuit.

[0015] [Amended according to Rule 26, 14.11.2025] The beneficial effects of the power switch circuit provided in the embodiments of this application are as follows: This application provides a switching transistor driving circuit and an energy storage device for driving a buck-boost circuit, including: a logic module, a first output module and a second output module; the logic module is connected to the first output module and the second output module respectively, the first output module is also connected to the first driving module of the buck bridge arm of the buck-boost circuit, and the second output module is also connected to the second driving module of the boost bridge arm of the buck-boost circuit; the logic module is configured to receive a driving signal and a buck-boost switching signal, and when the buck-boost switching signal is a buck switching signal, output a driving signal to the first output module and output a control signal to the second output module to make the buck-boost circuit work in buck mode; when the buck-boost switching signal is a boost switching signal, output a driving signal to the second output module and output a control signal to the first output module to make the buck-boost circuit work in boost mode. By using a single-channel switching transistor driver circuit to drive the buck-boost circuit, there is no need to set up separate software logic or equip each switching transistor in the buck-boost circuit with an I / O port, which simplifies the structure of the driver circuit and reduces its cost. [Revised according to Rule 26, 2014.11.2025] Attachment Description

[0016] [Amended according to Rule 26, 14.11.2025] One or more embodiments are illustrated by way of example with reference to the corresponding figures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] [Amended according to Rule 26, 14.11.2025] Figure 1 is a structural block diagram of a switching transistor driving circuit provided in an embodiment of this application;

[0018] [Amended according to Rule 26, 14.11.2025] Figure 2 is a structural diagram of a buck-boost circuit provided in an embodiment of this application;

[0019] [Amended according to Rule 26, 14.11.2025] Figure 3 is a structural block diagram of another switching transistor driving circuit provided in an embodiment of this application;

[0020] [Amended according to Rule 26, 14.11.2025] Figure 4 is a structural diagram of a first logic unit provided in an embodiment of this application;

[0021] [Amended according to Rule 26, 14.11.2025] Figure 5 is a structural diagram of a second logic unit provided in an embodiment of this application;

[0022] [Amended according to Rule 26, 14.11.2025] Figure 6 is a structural block diagram of another switching transistor driving circuit provided in an embodiment of this application;

[0023] [Amended according to Rule 26, 14.11.2025] Figure 7 is a partial structural diagram of a switching transistor driving circuit provided in an embodiment of this application;

[0024] [Amended according to Rule 26, 14.11.2025] Figure 8 is a structural diagram of a comparison module provided in an embodiment of this application;

[0025] [Amended according to Rule 26, 14.11.2025] Figure 9 is a partial structural block diagram of a switching transistor driving circuit provided in an embodiment of this application;

[0026] [Amended according to Rule 26, 14.11.2025] Figure 10 is a partial structural diagram of another switching transistor driving circuit provided in an embodiment of this application;

[0027] [Amended according to Rule 26, 14.11.2025] Figure 11 is a partial structural diagram of another switching transistor driving circuit provided in an embodiment of this application. [Revised according to Rule 26, 14.11.2025] Detailed Implementation Method

[0028] [Amended according to Rule 26, 14.11.2025] To facilitate understanding of this application, the following description, in conjunction with the accompanying drawings and specific embodiments, will provide a more detailed account of the application. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "electrically connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings. They are used only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0029] [Amended according to Rule 26, 14.11.2025] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. Furthermore, technical features involved in the different embodiments of this application described below may be combined with each other as long as they do not conflict with each other.

[0030] [Amended according to Rule 26, 14.11.2025] Currently, in buck-boost circuits, the number of I / O ports equipped with input drive signals is equal to the number of switching transistors to be driven. For example, in a four-transistor buck-boost circuit, four independent I / O ports are required to output drive signals to drive the four switching transistors respectively. This results in a complex system structure, large size and high cost.

[0031] [Amended according to Rule 26, 14.11.2025] In order to solve the above-mentioned technical problems, the embodiments of this application provide a switching transistor driving circuit and an energy storage device. By inputting a driving signal and a buck-boost switching signal to the switching transistor driving circuit, control signals can be provided for the boost bridge arm and buck bridge arm in the buck-boost circuit. There is no need to set up software logic for each switching transistor separately, which can simplify the structure of the driving circuit and thus save the cost of the driving circuit.

[0032] [Amended according to Rule 26, 14.11.2025] In a first aspect, embodiments of this application provide a switching transistor driving circuit for driving a buck-boost circuit 100. Referring to FIG1, the switching transistor driving circuit 200 includes: a logic module 210, a first output module 220, and a second output module 230. The logic module 210 is connected to the first output module 220 and the second output module 230 respectively. The first output module 220 is also connected to the first driving module 130 of the buck bridge arm 110 of the buck-boost circuit 100, and the second output module 230 is also connected to the second driving module 140 of the boost bridge arm 120 of the buck-boost circuit 100. The logic module 210 is configured to receive a driving signal MCU_PWM and a buck-boost switching signal BUCK-BOOST, and when the buck-boost switching signal BUCK-BOOST is a buck switching signal, output the driving signal MCU_PWM to the first output module 220 and output a control signal to the second output module 230, so that the buck-boost circuit 100 operates in buck mode. When the buck-boost switching signal BUCK-BOOST is the boost switching signal, the drive signal MCU_PWM is output to the second output module 230, and the control signal is output to the first output module 220, so that the buck-boost circuit 100 works in boost mode.

[0033] [Amended according to Rule 26, 14.11.2025] A buck-boost circuit refers to a circuit that can be used to increase or decrease the input voltage. In this application, a four-transistor buck-boost circuit is used as an example. Referring to Figures 1 and 2, the buck-boost circuit includes a buck bridge arm 110, a boost bridge arm 120, a first drive module 130, a second drive module 140, and an inductor L1. The buck bridge arm 110 includes a buck upper transistor 111 and a buck lower transistor 112. The boost bridge arm 120 includes a boost upper transistor 121 and a boost lower transistor 122. The first drive module 130 includes a first drive submodule 131 for driving the buck upper transistor 111 and a second drive submodule 132 for driving the buck lower transistor 112. The second drive module 140 includes a third drive submodule 141 for driving the boost upper transistor 121 and a fourth drive submodule 142 for driving the boost lower transistor 122. In boost mode, the four transistors operate as follows: buck converter 111 is normally on, buck converter 112 is normally off, and boost converters 121 and 122 are complementary in switching on and off. In buck mode, the four transistors operate as follows: boost converter 121 is normally on, boost converter 122 is normally off, and buck converters 111 and 112 are complementary in switching on and off. Buck converters 111, 112, 121, and 122 can be the same type of switching transistor, such as NMOS transistors. They turn on when they receive a high-level signal from the corresponding driver submodule and turn off when they receive a low-level signal from the driver submodule. The first driver submodule 131, second driver submodule 132, third driver submodule 141, and fourth driver submodule 142 can include electrical isolation components, such as optocouplers, opto-relays, and opto-field-effect transistors. For example, the driver submodule can turn on when it receives a high-level signal and output a high-level signal to the corresponding switch, and turn off when it receives a low-level signal and output a low-level signal to the corresponding switch.

[0034] [Revised according to Rule 26, 14.11.2025] Logic module 210 refers to the ability to output the drive signal MCU_PWM or control signal to a specific output module according to a preset logic rule when receiving a boost switching signal or a buck switching signal. This enables the first output module 220 and the second output module 230 to output specific signals to the first drive module 130 and the second drive module 140 based on the output signal of logic module 210. This allows the first drive module 130 to control the boost bridge arm 120 to work in boost mode or buck mode, and the second drive module 140 to control the buck bridge arm 110 to work in boost mode or buck mode.

[0035] [Amended according to Rule 26, 14.11.2025] The drive signal MCU_PWM can be a signal with a specific waveform and frequency, such as a pulse width modulation signal. This drive signal MCU_PWM can be issued by the controller or generated by a waveform generator. The waveform, frequency, and duty cycle of the drive signal MCU_PWM can be set according to actual needs and are not limited here.

[0036] [Amended according to Rule 26, 14.11.2025] Control signals can be signals with a certain level, such as high-level signals or low-level signals.

[0037] [Amended according to Rule 26, 14.11.2025] The buck-boost switching signal BUCK-BOOST refers to a signal that can be used to instruct the drive circuit to output different drive signals MCU_PWM to the buck-boost circuit 100, so that the buck-boost circuit 100 is in boost mode or buck mode. The buck-boost switching signal BUCK-BOOST includes a boost switching signal and a buck switching signal. The boost switching signal can be used to instruct the switch driver circuit to output a boost drive signal to the buck-boost circuit 100, so that the buck-boost circuit 100 is in boost mode. The buck switching signal can be used to instruct the switch driver circuit to output a buck drive signal to the buck-boost circuit 100, so that the buck-boost circuit 100 is in buck mode. The boost switching signal can be a low-level signal, and the buck switching signal can be a high-level signal. In practical applications, the boost switching signal can also be a high-level signal, and the buck switching signal can be a low-level signal. More specifically, the buck-boost switching signal can be output by a buck-boost switching signal output module. Whether to output a boost switching signal or a buck switching signal can be determined according to the relationship between the input voltage and the output voltage of the buck-boost circuit. For example, when the input voltage is greater than the output voltage, the buck-boost switching signal output module outputs a buck-boost switching signal as a buck switching signal; conversely, when the input voltage is less than the output voltage, the buck-boost switching signal output module outputs a buck-boost switching signal as a boost switching signal. In one embodiment, the buck-boost switching signal module can be implemented using a comparator. In another embodiment, the buck-boost switching signal module can output the buck-boost switching signal through a controller.

[0038] [Amended according to Rule 26, 14.11.2025] The first output module 220 refers to a device that, upon receiving the drive signal MCU_PWM, can control the first drive module 130 to operate, so that the upper step-down transistor 111 and the lower step-down transistor 112 in the step-down bridge arm 110 are periodically complementary in switching on and off, that is, the upper step-down transistor 111 and the lower step-down transistor 112 will not be turned on simultaneously within a complete working cycle, and upon receiving the control signal, can control the first drive module 130 to operate, so that the upper step-down transistor 111 in the step-down bridge arm 110 is continuously turned on and the lower step-down transistor 112 in the step-down bridge arm 110 is continuously turned off.

[0039] [Amended according to Rule 26, 14.11.2025] The second output module 230 refers to a device that, upon receiving the drive signal MCU_PWM, can control the second drive module 140 to operate, so that the boost upper transistor 121 and boost lower transistor 122 in the boost bridge arm 120 are periodically complementary in switching on and off, that is, the boost upper transistor 121 and boost lower transistor 122 will not be turned on simultaneously within a complete working cycle, and upon receiving the control signal, can control the second drive module 140 to operate, so that the boost upper transistor 121 in the boost bridge arm 120 is continuously turned on and the boost lower transistor 122 in the boost bridge arm 120 is continuously turned off.

[0040] [Amended according to Rule 26, 14.11.2025] In this switching transistor drive circuit 200, when the buck-boost switching signal BUCK-BOOST is a buck switching signal, the logic module 210 outputs the drive signal MCU_PWM to the first output module 220 and outputs a control signal to the second output module 230. The signal output by the first output module 220 through the first drive module 130 controls the buck upper transistor 111 and buck lower transistor 112 in the buck bridge arm 110 to periodically and complementaryly turn on and off. The signal output by the second output module 230 through the second drive module 140 controls the boost upper transistor 121 in the boost bridge arm 120 to be continuously turned on and controls the boost lower transistor 122 in the boost bridge arm 120 to be continuously turned off. That is, the buck-boost circuit 100 operates in buck mode; when the buck-boost switching signal BUCK-BOOST is the boost switching signal, the logic module 210 outputs a control signal to the first output module 220 and outputs a drive signal MCU_PWM to the second output module 230. The signal output by the first output module 220 through the first drive module 130 controls the upper buck transistor 111 in the buck bridge arm 110 to be continuously turned on and the lower buck transistor 112 in the buck bridge arm 110 to be continuously turned off. The signal output by the second output module 230 through the second drive module 140 controls the upper boost transistor 121 and the lower boost transistor 122 in the boost bridge arm 120 to be periodically and complementaryly turned on. That is, the buck-boost circuit 100 operates in boost mode.

[0041] [Revised according to Rule 26, 14.11.2025] As can be seen, in this embodiment, the logic module 210 outputs the drive signal MCU_PWM to the first output module 220 or the second output module 230 under the instruction of the buck-boost switching signal BUCK-BOOST, and outputs the control signal to the second output module 230 or the first output module 220. After receiving the corresponding signal, the first output module 220 or the second output module 230 can control the buck bridge arm 110 or the boost bridge arm 120 to work, so that the buck-boost circuit 100 works in boost mode or buck mode. Compared with the method of using four drive signals to drive the switching transistors in the buck-boost circuit 100 to work separately, this embodiment can drive the four switching transistors in the buck-boost circuit 100 to work with one drive signal. There is no need to set up software logic for each switching transistor in the buck-boost circuit 100, which can make the structure of the drive circuit simpler and reduce the cost of the drive circuit.

[0042] [Amended according to Rule 26, 14.11.2025] In some embodiments, referring to FIG3, logic module 210 includes a first logic unit 211 and a second logic unit 212. The first logic unit 211 is connected to the first output module 220, and the second logic unit 212 is connected to the second output module 230. The first logic unit 211 is configured to output a drive signal MCU_PWM to the first output module 220 in response to a buck switching signal, and to output a control signal to the first output module 220 in response to a boost switching signal. The second logic unit 212 is configured to output a control signal to the second output module 230 in response to a buck switching signal, and to output a drive signal MCU_PWM to the second output module 230 in response to a boost switching signal.

[0043] [Amended according to Rule 26, 14.11.2025] The first logic unit 211 and the second logic unit 212 simultaneously receive the drive signal MCU_PWM and the buck-boost switching signal BUCK-BOOST. When the buck-boost switching signal BUCK-BOOST is a buck switching signal, the first logic unit 211 outputs the drive signal MCU_PWM to the first output module 220, and the second logic unit 212 outputs the control signal to the second output module 230. In this way, the first output module 220 and the second output module 230 can control the buck-boost circuit to work in buck mode based on the corresponding signals. When the buck-boost switching signal BUCK-BOOST is a boost switching signal, the first logic unit 211 outputs the control signal to the first output module 220, and the second logic unit 212 outputs the drive signal MCU_PWM to the second output module 230. In this way, the first output module 220 and the second output module 230 can control the buck-boost circuit to work in boost mode based on the corresponding signals.

[0044] [Amended according to Rule 26, 14.11.2025] Compared to the embodiment that uses a single logic unit for processing, in this embodiment, by setting up two dedicated logic units to process the input signal and output the corresponding signal to the corresponding output module, it is convenient to repair the logic unit when a fault occurs.

[0045] [Amended according to Rule 26, 14.11.2025] In some embodiments, referring to FIG4, the first logic unit 211 includes a first AND gate AND1, a first OR gate OR1, and a first NOT gate NOT1. The first input of the first AND gate AND1 and the input of the first NOT gate NOT1 are both used to receive the buck-boost switching signal BUCK-BOOST. The second input of the first AND gate AND1 is used to receive the drive signal MCU_PWM. The output of the first AND gate AND1 is connected to the first input of the first OR gate OR1. The second input of the first OR gate OR1 is connected to the output of the first NOT gate NOT1. The output of the first OR gate OR1 is connected to the first output module 220.

[0046] [Amended according to Rule 26, 14.11.2025] The first AND gate AND1 is a logic device that outputs a high-level signal when both the first and second input signals are high-level signals, and outputs a low-level signal when both the first and / or second input signals are low-level signals. The first OR gate OR1 is a logic device that outputs a high-level signal when both the first and / or second input signals are high-level signals, and outputs a low-level signal when both the first and second input signals are low-level signals. The first NOT gate NOT1 is a logic device whose output signal is the inverted version of the input signal.

[0047] [Revised according to Rule 26, 14.11.2025] Specifically, taking the boost switching signal as a low-level signal and the buck switching signal and control signal as high-level signals as an example, when the buck-boost switching signal BUCK-BOOST is a high-level signal, the output signal of the first AND gate AND1 is consistent with the drive signal MCU_PWM, and the output signal of the first NOT gate NOT1 is a low-level signal. Then the output signal of the first OR gate OR1 is consistent with the output signal of the first AND gate AND1, that is, the output signal of the first OR gate OR1 is consistent with the drive signal MCU_PWM. In other words, at this time, the first logic unit 211 outputs the drive signal MCU_PWM to the first output module 220. When the buck-boost switching signal BUCK-BOOST is a low-level signal, the output signal of the first AND gate AND1 is a low-level signal, the output signal of the first NOT gate NOT1 is a high-level signal, and the output signal of the first OR gate OR1 is a high-level signal. In other words, at this time, the first logic unit 211 outputs a high-level signal to the first output module 220.

[0048] [Revised according to Rule 26, 14.11.2025] It can be seen that in this embodiment, by setting the above-mentioned logic device, different signals can be output to the first output module 220 under different buck-boost switching signals.

[0049] [Amended according to Rule 26, 14.11.2025] In some embodiments, referring to FIG5, the second logic unit 212 includes a second NOT gate NOT2, a second OR gate OR2, and a second AND gate AND2. The input terminal of the second NOT gate NOT2 and the first input terminal of the second OR gate OR2 are both used to receive the buck-boost switching signal BUCK-BOOST. The output terminal of the second NOT gate NOT2 is connected to the first input terminal of the second AND gate AND2. The second input terminal of the second AND gate AND2 is used to receive the drive signal MCU_PWM. The output terminal of the second AND gate AND2 is connected to the second input terminal of the second OR gate OR2. The output terminal of the second OR gate OR2 is connected to the second output module 230.

[0050] [Amended according to Rule 26, 14.11.2025] The second NOT gate (NOT2) is a logic device whose output signal is the inverted version of the input signal. The second OR gate (OR2) is a logic device that outputs a high-level signal when the input signals at the first and / or second input terminals are high-level signals, and outputs a low-level signal when both the input signals at the first and / or second input terminals are low-level signals. The second AND gate (AND2) is a logic device that outputs a high-level signal when both the input signals at the first and second input terminals are high-level signals, and outputs a low-level signal when both the input signals at the first and / or second input terminals are low-level signals.

[0051] [Revised according to Rule 26, 14.11.2025] Specifically, taking the boost switching signal as a low-level signal and the buck switching signal and control signal as high-level signals as an example, when the buck-boost switching signal BUCK-BOOST is a high-level signal, the output signal of the second NOT gate NOT2 is a low-level signal, the output signal of the second AND gate AND2 is a low-level signal, and the output signal of the second OR gate OR2 is a high-level signal. That is, at this time, the second logic unit 212 will output a high-level signal to the second output module 230. When the buck-boost switching signal BUCK-BOOST is a low-level signal, the output signal of the second NOT gate NOT2 is a high-level signal, the output signal of the second AND gate AND2 is consistent with the drive signal MCU_PWM, and the output signal of the second OR gate OR2 is consistent with the output signal of the second AND gate AND2. That is, the output signal of the second OR gate OR2 is consistent with the drive signal MCU_PWM. That is, at this time, the second logic unit 212 will output the drive signal MCU_PWM to the second output module 230.

[0052] [Revised according to Rule 26, 14.11.2025] It can be seen that in this embodiment, by setting the above-mentioned logic device, different signals can be output to the second output module 230 under different buck-boost switching signals.

[0053] [Revised according to Rule 26, 14.11.2025] In some embodiments, referring to FIG6, the first output module 220 includes a first output unit 221 and a second output unit 222, and the second output module 230 includes a third output unit 231 and a fourth output unit 232.

[0054] [Revised according to Rule 26, 14.11.2025] The first output terminal of logic module 210 is connected to the first output unit 221 and the second output unit 222 respectively. The second output terminal of logic module 210 is connected to the third output unit 231 and the fourth output unit 232 respectively. The first output unit 221 is also connected to the first driver submodule 131. The second output unit 222 is also connected to the second driver submodule 132. The third output unit 231 is also connected to the third driver submodule 141. The fourth output unit 232 is also connected to the fourth driver submodule 142.

[0055] [Amended according to Rule 26, 14.11.2025] When the buck-boost switching signal BUCK-BOOST is the buck switching signal, the first output unit 221 is configured to output a first pulse width modulation signal to the first drive submodule 131 based on the drive signal MCU_PWM, causing the buck upper transistor 111 to periodically turn on and off. The second output unit 222 is configured to output a second pulse width modulation signal to the second drive submodule 132 based on the drive signal MCU_PWM, causing the buck lower transistor 112 to periodically turn on and off. The buck upper transistor 111 and the buck lower transistor 112 are turned on at different times. The third output unit 231 is configured to output a first level signal to the third drive submodule 141 based on the control signal, causing the boost upper transistor 121 to turn on. The fourth output unit 232 is configured to output a second level signal to the fourth drive submodule 142 based on the control signal, causing the boost lower transistor 122 to turn off.

[0056] [Amended according to Rule 26, 14.11.2025] When the buck-boost switching signal BUCK-BOOST is the boost switching signal, the first output unit 221 is configured to output a third level signal to the first drive submodule 131 based on the control signal, so that the buck upper transistor 111 is turned on; the second output unit 222 is configured to output a fourth level signal to the second drive submodule 132 based on the control signal, so that the buck lower transistor 112 is turned off; the third output unit 231 is configured to output a third pulse width modulation signal to the third drive submodule 141 based on the drive signal MCU_PWM, so that the boost upper transistor 121 is periodically turned on and off; the fourth output unit 232 is configured to output a fourth pulse width modulation signal to the fourth drive submodule 142 based on the drive signal MCU_PWM, so that the boost lower transistor 122 is periodically turned on and off. The boost upper transistor 121 and the boost lower transistor 122 are turned on at different times.

[0057] [Revised according to Rule 26, 14.11.2025] Specifically, the first output unit 221 and the second output unit 222 are both connected to the first logic unit 211, the third output unit 231 and the fourth output unit 232 are both connected to the second logic unit 212, the first driving submodule 131 is connected to the control terminal of the step-down upper transistor 111, the second driving submodule 132 is connected to the control terminal of the step-down lower transistor 112, the third driving submodule 141 is connected to the control terminal of the boost upper transistor 121, and the fourth driving submodule 142 is connected to the control terminal of the boost lower transistor 122.

[0058] [Amended according to Rule 26, 14.11.2025] The duty cycle of each pulse width modulation signal may or may not be the same as the duty cycle of the drive signal MCU_PWM, and the frequency of each pulse width modulation signal may or may not be the same as the frequency of the drive signal MCU_PWM. To ensure stable operation of the buck-boost circuit, the duty cycle and frequency of the first pulse width modulation signal should be the same as the duty cycle and frequency of the second pulse width modulation signal, and the duty cycle and frequency of the third pulse width modulation signal should be the same as the duty cycle and frequency of the fourth pulse width modulation signal. In the embodiment shown in Figure 2, the first level signal and the third level signal can be high level signals, and the second level signal and the fourth level signal can be low level signals.

[0059] [Amended according to Rule 26, 14.11.2025] In this switching transistor drive circuit, when the buck-boost switching signal BUCK-BOOST is the buck switching signal, the first output unit 221 receives the drive signal MCU_PWM from the logic module 210 and generates a first pulse width modulation signal based on the signal. The first pulse width modulation signal is output to the control terminal of the buck upper transistor 111 through the first drive submodule 131, causing the buck upper transistor 111 to periodically turn on and off. The second output unit 222 also receives the drive signal MCU_PWM and generates a second pulse width modulation signal. The signal, the second pulse width modulation signal, is output to the control terminal of the buck lower transistor 112 through the second drive submodule 132, causing the buck lower transistor 112 to periodically turn on and off. The buck upper transistor 111 and the buck lower transistor 112 will not be turned on at the same time. At the same time, the third output unit 231 outputs a first level signal (such as a high level signal) based on the control signal, so that the boost upper transistor 121 is continuously turned on. The fourth output unit 232 outputs a second level signal (such as a low level signal) based on the control signal, so that the boost lower transistor 122 is continuously turned off, so that the buck-boost circuit 100 operates in buck mode.

[0060] [Amended according to Rule 26, 14.11.2025] When the buck-boost switching signal BUCK-BOOST is the boost switching signal, the first output unit 221 outputs a third-level signal (e.g., a high-level signal) based on the control signal, causing the buck upper transistor 111 to remain on. The second output unit 222 outputs a fourth-level signal (e.g., a low-level signal) based on the control signal, causing the buck lower transistor 112 to remain off. The third output unit 231 receives the drive signal MCU_PWM from the logic module 210 and generates a third pulse width modulation signal based on this signal. The third pulse width modulation signal is output to the boost upper transistor 121 through the third drive submodule 141. The control terminal periodically switches the boost transistor 121 on and off. The fourth output unit 232 also receives the drive signal and generates a fourth pulse width modulation signal. The fourth pulse width modulation signal is output to the control terminal of the boost transistor 122 through the fourth drive submodule 142, causing the boost transistor 122 to periodically switch on and off. The boost transistor 121 and the boost transistor 122 will not be turned on at the same time. In this embodiment, each output unit can output a corresponding signal to the corresponding switch transistor under different input signals, so as to accurately make each switch transistor work in the required state, thereby realizing flexible switching of the working mode of the boost-buck circuit under the control of the buck-boost switching signal BUCK-BOOST.

[0061] [Amended according to Rule 26, 14.11.2025] In some embodiments, the first output module 220 is further configured to adjust the duty cycle of the first pulse width modulation signal via the first output unit 221 and the duty cycle of the second pulse width modulation signal via the second output unit 222, such that after the buck lower transistor 112 is turned off, the buck upper transistor 111 is turned on after a first dead time delay, and the buck lower transistor 112 is turned on after the buck upper transistor 111 is turned off after a first dead time delay. The second output module 230 is further configured to adjust the duty cycle of the third pulse width modulation signal via the third output unit 231 and the duty cycle of the second pulse width modulation signal via the fourth output unit 232, such that after the boost lower transistor 122 is turned off, the boost upper transistor 121 is turned on after a second dead time delay, and the boost upper transistor 121 is turned on after the boost lower transistor 122 is turned off after a second dead time delay.

[0062] [Revised according to Rule 26, 14.11.2025] Duty cycle refers to the ratio of the high-level time to the total cycle time within a working cycle.

[0063] [Revised according to Rule 26, 14.11.2025] The first dead time refers to the time interval between the moment when the lower step-down tube 112 is turned off and the moment when the upper step-down tube 111 is turned on in step-down mode, and also the time interval between the moment when the upper step-down tube 111 is turned off and the moment when the lower step-down tube 112 is turned on.

[0064] [Revised according to Rule 26, 14.11.2025] The second dead time refers to the time interval between the moment when the lower boost tube 122 is turned off and the moment when the upper boost tube 121 is turned on in boost mode, and also the time interval between the moment when the upper boost tube 121 is turned off and the moment when the lower boost tube 122 is turned on.

[0065] [Revised according to Rule 26, 14.11.2025] Specifically, when the first output unit 221 outputs the first pulse width modulation signal based on the drive signal MCU_PWM, it can reduce the duty cycle of the first pulse width modulation signal by adjusting the duty cycle of the first pulse width modulation signal; at the same time, when the second output unit 222 outputs the second pulse width modulation signal based on the drive signal MCU_PWM, it can reduce the duty cycle of the second pulse width modulation signal by adjusting the duty cycle of the second pulse width modulation signal; since the upper step-down transistor 111 and the lower step-down transistor 112 periodically and complementaryly turn on and off under the control of the first pulse width modulation signal and the second pulse width modulation signal, by adjusting the duty cycle of the first pulse width modulation signal and the second pulse width modulation signal, the conduction time of the upper step-down transistor 111 and the lower step-down transistor 112 is shortened simultaneously within one working cycle, so that there is a first dead time when the upper step-down transistor 111 and the lower step-down transistor 112 switch conduction. Similarly, by adjusting the duty cycle of the third pulse width modulation signal and the fourth pulse width modulation signal, a second dead time can be created when the boost upper tube 121 and the boost lower tube 122 switch on.

[0066] [Revised according to Rule 26, 14.11.2025] In this embodiment, by adjusting the duty cycle of each pulse width modulation signal, a dead time is created when the upper and lower transistors in the same bridge arm switch on, preventing the upper and lower transistors in the same bridge arm from conducting simultaneously during the switching process, thereby avoiding short circuits and damage to circuit components and improving the reliability of the circuit during operation.

[0067] [Amended according to Rule 26, 14.11.2025] In some embodiments, referring to FIG7, the first output unit 221 includes a first resistor R1, a first capacitor C1 and a first diode D1. The first end of the first resistor R1 is connected to the first output terminal of the logic module 210 and the cathode of the first diode D1, respectively. The second end of the first resistor R1 is connected to the anode of the first diode D1, the first end of the first capacitor C1 and the first driving submodule 131, respectively. The second end of the first capacitor C1 is grounded.

[0068] [Amended according to Rule 26, 14.11.2025] The third output unit 231 includes a third resistor R3, a third capacitor C3 and a third diode D7. The first end of the third resistor R3 is connected to the second output terminal of the logic module 210 and the cathode of the third diode D7, respectively. The second end of the third resistor R3 is connected to the anode of the third diode D7, the first end of the third capacitor C3 and the third driving submodule 141, respectively. The second end of the third capacitor C3 is grounded.

[0069] [Amended according to Rule 26, 14.11.2025] The second output unit 222 includes a third NOT gate NOT3, a second resistor R2, a second capacitor C2, and a second diode D2. The first terminal of the third NOT gate NOT3 is connected to the first output terminal of the logic module 210. The second terminal of the third NOT gate NOT3 is connected to the first terminal of the second resistor R2 and the cathode of the second diode D2. The second terminal of the second resistor R2 is connected to the anode of the second diode D2, the first terminal of the second capacitor C2, and the second driving submodule 132. The second terminal of the second capacitor C2 is grounded.

[0070] [Amended according to Rule 26, 14.11.2025] The fourth output unit 232 includes a fourth NOT gate NOT4, a fourth resistor R4, a fourth capacitor C4 and a fourth diode D8. The first terminal of the fourth NOT gate NOT4 is connected to the second output terminal of the logic module 210. The second terminal of the fourth NOT gate NOT4 is connected to the first terminal of the fourth resistor R4 and the cathode of the fourth diode D8. The second terminal of the fourth resistor R4 is connected to the anode of the fourth diode D8, the first terminal of the fourth capacitor C4 and the fourth driving submodule 142. The second terminal of the fourth capacitor C4 is grounded.

[0071] [Amended according to Rule 26, 14.11.2025] Specifically, the first terminal of the first resistor R1 can be connected to the output terminal of the first OR gate OR1 in Figure 4. The first terminal of the third resistor R3 is connected to the output terminal of the second OR gate OR2. The first terminal of the third NOT gate NOT3 can be connected to the output terminal of the first OR gate OR1 in Figure 4. The first terminal of the fourth NOT gate NOT4 is connected to the output terminal of the second OR gate OR2.

[0072] [Amended according to Rule 26, 14.11.2025] For the first output unit 221, when the output signal of the first logic unit 211 is at the rising edge, that is, when the output signal of the first logic unit 211 switches from a low level signal to a high level signal, the first resistor R1 and the first capacitor C1 form an RC delay circuit, so that the output signal switches from a low level signal to a high level signal after a first delay; when the output signal of the first logic unit 211 is at the falling edge, that is, when the output signal of the first logic unit 211 switches from a high level signal to a low level signal, the first resistor R1 and the first capacitor C1 make the output signal switch from a high level signal to a low level signal after a second delay. Since the first capacitor C1 will accelerate the discharge of energy through the first diode D1, the second time is less than the first time. The first time is related to the parameters of the first resistor R1 and the first capacitor C1, and the second time is related to the parameters of the first capacitor C1 and the first diode D1.

[0073] [According to Rule 26, amended 14.11.2025] Similarly, for the third output unit 231, when the output signal of the second logic unit 212 is at the rising edge, the output signal of the third output unit 231 switches from a low level signal to a high level signal after a third delay. When the output signal of the second logic unit 212 is at the falling edge, the output signal of the third output unit 231 switches from a high level signal to a low level signal after a fourth delay. The fourth time is less than the third time, and the third time is related to the parameters of the third resistor R3 and the third capacitor C3, while the second time is related to the parameters of the third capacitor C3 and the third diode D7.

[0074] [Amended according to Rule 26, 14.11.2025] For the second output unit 222, when the output signal of the first logic unit 211 is at the falling edge, the output signal of the third NOT gate is at the rising edge, that is, when the output signal of the third NOT gate switches from a low level signal to a high level signal, the second resistor R2 and the second capacitor C2 form an RC delay circuit, so that the output signal switches from a low level signal to a high level signal after a fifth delay; when the output signal of the first logic unit 211 is at the rising edge, the output signal of the third NOT gate is at the falling edge, that is, when the output signal of the third NOT gate switches from a high level signal to a low level signal, the second resistor R2 and the second capacitor C2 make the output signal switch from a high level signal to a low level signal after a sixth delay. Since the first capacitor C1 will accelerate the energy discharge through the second diode D2, the sixth time is less than the fifth time. The fifth time is related to the parameters of the second resistor R2 and the second capacitor C2, and the sixth time is related to the parameters of the second capacitor C2 and the second diode D2.

[0075] [According to Rule 26, amended 14.11.2025] Similarly, for the fourth output unit 232, when the output signal of the second logic unit 212 is at the falling edge, the output signal of the fourth output unit 232 switches from a low level signal to a high level signal after a delay of seven times. When the output signal of the second logic unit 212 is at the rising edge, the output signal of the fourth output unit 232 switches from a high level signal to a low level signal after a delay of eight times. The seventh time is less than the eighth time, and the seventh time is related to the parameters of the fourth resistor R4 and the fourth capacitor C4, while the eighth time is related to the parameters of the fourth capacitor C4 and the fourth diode D8.

[0076] [Revised according to Rule 26, November 14, 2025] To ensure normal system operation, the first time equals the fifth time, the second time equals the sixth time, the third time equals the seventh time, and the fourth time equals the eighth time. Taking the buck bridge arm as an example, when the first logic unit 211 is at the rising edge, the output signal of the first output unit 221 switches from a low-level signal to a high-level signal after a delay of the first time, that is, the buck upper transistor 111 is turned on after a delay of the first time. The output signal of the second output unit 222 switches from a high-level signal to a low-level signal after a delay of the sixth time, that is, the buck lower transistor 112 is turned off after a delay of the sixth time. Since the first time equals the fifth time and the sixth time is less than the fifth time, the sixth time is less than the first time. Therefore, after the buck lower transistor 112 is turned off, the buck upper transistor 111 only turns off after a delay of the first dead time. It will conduct; when the first logic unit 211 is at the falling edge, the output signal of the first output unit 221 switches from a high level signal to a low level signal after a second delay, that is, the buck upper transistor 111 is turned off after a second delay, while the output signal of the second output unit 222 switches from a low level signal to a high level signal after a fifth delay, that is, the buck lower transistor 112 is turned on after a fifth delay. Since the second time is equal to the sixth time, and the sixth time is less than the fifth time, the second time is less than the fifth time. Therefore, after the buck upper transistor 112 is turned off, the buck lower transistor 112 will only turn on after a first dead time delay.

[0077] [Revised according to Rule 26, 14.11.2025] It can be seen that in this embodiment, by setting the above-mentioned device, the upper and lower transistors in the same bridge arm can have a dead time when switching on, and no software logic implementation is required, thus reducing costs.

[0078] [Amended according to Rule 26, 14.11.2025] In some embodiments, referring to FIG8, the switch driver circuit 200 further includes a comparison module 240. The comparison module 240 is connected to the third driver submodule 141. The comparison module 240 is configured to receive a first sampling signal S1 of the output current of the buck-boost circuit 100, and when the voltage of the first sampling signal S1 is less than the first voltage Vref1, output a first turn-off signal to the third driver submodule 141 to turn off the boost transistor 121.

[0079] [Revised according to Rule 26, 14.11.2025] Output current refers to the current on the output side of the step-up / step-down circuit 100. The first sampling signal can be sampled by a dedicated current sampling module. The specific sampling process can be referred to the existing technology, and is not limited here.

[0080] [Amended according to Rule 26, 14.11.2025] Comparison module 240 refers to a device that can compare the magnitude relationship between the voltage of the first sampled signal S1 and the first voltage Vref1, and output different signals to the control terminal of the boost transistor 121. As shown in Figure 8, comparison module 240 may include comparator AMP2. The positive input terminal of comparator AMP2 is used to receive the first sampled signal S1, and the negative input terminal of comparator AMP2 is used to receive the first voltage Vref1. The voltage amplitude of the first voltage Vref1 can be set according to actual needs. In this comparison module 240, when the voltage of the first sampled signal S1 is less than the first voltage Vref1, comparator AMP2 will output a low-level signal, thereby turning off the boost transistor 121. At this time, the third output unit 231 cannot control the boost transistor 121 to work. When the voltage of the first sampled signal S1 is greater than the second voltage Vref1, comparator AMP2 will output a high-level signal. At this time, the working state of the boost transistor 121 will be controlled by the output signal of the third output unit 231.

[0081] [Revised according to Rule 26, 14.11.2025] By setting the comparison module 240, when the buck-boost circuit 100 is working, if the output current is less than the set first sampling point, that is, when the voltage of the first sampling signal S1 is less than the first voltage Vref1, the boost transistor 121 will be in the off state, and the current will first flow through the body diode of the boost transistor 121 to prevent the current from flowing from the output side of the buck-boost circuit to the input side, thus achieving the reverse current prevention function. When the output current is greater than the set first sampling point, that is, when the voltage of the first sampling signal S1 is greater than the first voltage Vref1, the comparison module 240 stops outputting the low-level signal to ensure that the circuit works normally.

[0082] [Amended according to Rule 26, 14.11.2025] In some embodiments, referring to FIG9, the switch drive circuit 200 further includes an overcurrent protection module 250. The overcurrent protection module 250 is connected to the first drive module 130 and the second drive module 140, respectively. The overcurrent protection module 250 is configured to receive a second sampling signal of the input current of the buck-boost circuit 100, and when the voltage of the second sampling signal is greater than a second voltage, output a second shutdown signal to the first drive module 130 and the second drive module 140, causing the buck-boost circuit 100 to stop working.

[0083] [Revised according to Rule 26, 14.11.2025] The input current refers to the current on the input side of the step-up / step-down circuit 100. The second sampling signal can be sampled by a dedicated current sampling module. The specific sampling process can be referred to the existing technology, and is not limited here.

[0084] [According to Rule 26, amended 14.11.2025] In the switching transistor drive circuit 200, when the input current is greater than the set second sampling point, that is, when the voltage of the second sampling signal is greater than the second voltage, the overcurrent protection module 250 will control the buck-boost circuit 100 to stop working, thereby realizing overcurrent protection and improving the safety of the circuit.

[0085] [Amended according to Rule 26, 14.11.2025] In some embodiments, referring to FIG10, the overcurrent protection module 250 includes a comparator AMP3, a resistor R6, an AND gate AND3, a NOT gate NOT5, a MOS switch 5, diodes D3, D4, D5, and D6; the positive input terminal of comparator AMP3 is used to receive the second voltage Vref2, the negative input terminal of comparator AMP3 is used to receive the second sampling signal S2, the output terminal of comparator AMP3 is connected to one end of resistor R6 and the first input terminal of AND gate AND3, the other end of resistor R6 is connected to power supply Vcc1, and the first input terminal of AND gate AND3 is connected to the first input terminal of AND gate AND3. The two input terminals are used to receive the enable signal EN from the switching transistor drive circuit 100. The output terminal of AND gate AND3 is connected to the input terminal of NOT gate NOT5. The output terminal of NOT gate NOT5 is connected to the first terminal of switching transistor Q5. The second terminal of switching transistor Q5 is connected to the cathodes of diodes D3, D4, D5, and D6, respectively. The third terminal of switching transistor Q5 is grounded to GND. The anode of diode D3 is connected to the first driving submodule 131, the anode of diode D4 is connected to the second driving submodule 132, the anode of diode D5 is connected to the third driving submodule 141, and the anode of diode D6 is connected to the fourth driving submodule 142.

[0086] [Amended according to Rule 26, 14.11.2025] The enable signal EN of the switching transistor drive circuit 100 is a signal used to indicate whether the switching transistor drive circuit 100 is working. It may include a high-level signal indicating that the switching transistor drive circuit 100 is working and a low-level signal indicating that the switching transistor drive circuit 100 is not working. The switching transistor Q5 may be a suitable switching device such as an N-type MOSFET or an NPN transistor.

[0087] [Amended according to Rule 26, 14.11.2025] In this circuit, when the enable signal EN is low, AND gate AND3 outputs a low-level signal, NOT gate NOT5 outputs a high-level signal, and switch Q5 is turned on. Each driving sub-module is pulled low through the corresponding diode and switch Q5. The buck converter 111, buck converter 112, boost converter 121, and boost converter 122 are all turned off. The switch driving circuit 100 cannot control the buck converter 111, buck converter 112, boost converter 121, and boost converter 122.

[0088] [Revised according to Rule 26, 14.11.2025] When the enable signal EN is high and the input current is less than the set second sampling point, i.e., the voltage of the second sampling signal S2 is less than the second voltage Vref2, the comparator AMP3 outputs a high-level signal, the AND gate AND3 outputs a high-level signal, the NOT gate NOT5 outputs a low-level signal, the switch Q5 is turned off, and the overcurrent protection module 250 does not affect the operation of the switch drive circuit 200; when the enable signal EN is high and the input current is greater than the set second sampling point, i.e., the voltage of the second sampling signal S2 is greater than the second voltage Vref2, the comparator AMP3 outputs a low-level signal, the AND gate AND3 outputs a low-level signal, the NOT gate NOT5 outputs a high-level signal, the switch Q5 is turned on, and each drive submodule is pulled low through the corresponding diode and switch Q5, and the buck upper transistor 111, buck lower transistor 112, boost upper transistor 121 and boost lower transistor 122 are all turned off, realizing overcurrent protection.

[0089] [Revised according to Rule 26, 14.11.2025] It can be seen that in this embodiment, overcurrent protection can be achieved by setting the above-mentioned device.

[0090] [Amended according to Rule 26, 14.11.2025] In some embodiments, referring to FIG11, the switching transistor drive circuit 200 further includes a buck-boost switching signal output module 260, which is used to receive the input voltage sampling signal V1 and the output voltage sampling signal V2 of the buck-boost circuit 100, respectively, compare the magnitudes of the sampling signals V1 and V2, and output a boost switching signal or a buck switching signal.

[0091] [Amended according to Rule 26, 14.11.2025] The voltage of the input voltage sampling signal V1 has a first ratio with the input voltage, and the voltage of the output voltage sampling signal V2 has a second ratio with the output voltage. The first ratio equals the second ratio. In this circuit, when the input voltage sampling signal V1 is less than the output voltage sampling signal V2, the buck-boost switching signal output module 260 outputs a boost switching signal; when the input voltage sampling signal V1 is greater than the output voltage sampling signal V2, the buck-boost switching signal output module 260 outputs a buck switching signal.

[0092] [Amended according to Rule 26, 14.11.2025] Taking a boost switching signal as low and a buck switching signal as high as an example, the boost-buck switching signal output module 260 includes a comparator AMP1, a resistor R5, and a power supply Vcc2. The positive input terminal of the comparator AMP1 is used to receive the input voltage sampling signal V1, and the negative input terminal of the comparator AMP1 is used to receive the output voltage sampling signal V2. The output terminal of the comparator AMP1 is connected to the power supply Vcc2 through the resistor R5. The output terminal of the comparator AMP1 is also connected to the logic module 210. In this circuit, when the input voltage sampling signal V1 is less than the output voltage sampling signal V2, the comparator AMP1 outputs a low-level signal (boost switching signal); when the input voltage sampling signal V1 is greater than the output voltage sampling signal V2, the boost-buck switching signal output module 260 outputs a high-level signal (buck switching signal).

[0093] [Revised according to Rule 26, 14.11.2025] It can be seen that in this embodiment, the buck-boost switching signal output module 260 can be set to realize the hardware output of the buck-boost switching signal.

[0094] [Amended according to Rule 26, 14.11.2025] The specific working process of the switching transistor drive circuit provided in this application will be described below with reference to the embodiments shown in Figures 4, 5, 8, 10 and 11.

[0095] [Revised according to Rule 26, 14.11.2025] When the sampling signal V1 of the input voltage is greater than the sampling signal V2 of the output voltage, the buck-boost switching signal output module 260 outputs a high-level signal (buck-boost switching signal) to the logic module 210. The first logic unit 211 outputs the drive signal MCU_PWM to the first output unit 221 and the second output unit 222. The second logic unit 212 outputs a high-level signal (control signal) to the third output unit 231 and the fourth output unit 232. The first output unit 221 outputs the first pulse width modulation signal, which is transmitted to the buck upper transistor 111 via the first drive submodule 131. The second output unit... Unit 222 outputs a second pulse width modulation signal, which is transmitted to the lower buck transistor 112 via the second driver submodule 132, causing the upper buck transistor 111 and the lower buck transistor 112 to periodically switch on and off complementaryly. Due to the action of the resistors, capacitors and diodes in the first output unit 221 and the second output unit 222, there is a first dead time when the upper buck transistor 111 and the lower buck transistor 112 switch on. The third output unit 231 outputs a high-level signal to the upper boost transistor 121, turning on the upper boost transistor 121. The fourth output unit 232 outputs a low-level signal to the lower boost transistor 122, turning off the lower boost transistor 122. That is, the buck-boost circuit 100 is in buck mode.

[0096] [Amended according to Rule 26, 14.11.2025] When the sampling signal V1 of the input voltage is less than the sampling signal V2 of the output voltage, comparator AMP1 outputs a low-level signal (boost switching signal) to logic module 210. The first logic unit 211 outputs a high-level signal (control signal) to the first output unit 221 and the second output unit 222. The second logic unit 212 outputs the drive signal MCU_PWM to the third output unit 231 and the fourth output unit 232. The third output unit 231 outputs the third pulse width modulation signal, which is transmitted to the boost transistor 121 via the third drive submodule 141. The fourth output unit 231... 2. Output a fourth pulse width modulation signal. The fourth pulse width modulation signal is transmitted to the boost lower transistor 122 through the fourth driver submodule 142, so that the boost upper transistor 121 and the boost lower transistor 122 are periodically complementary in switching on and off. Due to the action of the resistors, capacitors and diodes in the third output unit 231 and the fourth output unit 232, there is a second dead time when the boost upper transistor 121 and the boost lower transistor 122 switch on. The first output unit 221 outputs a high-level signal to the buck upper transistor 111, so that the buck upper transistor 111 is turned on. The second output unit 222 outputs a low-level signal to the buck lower transistor 112, so that the buck lower transistor 112 is turned off. That is, the buck-boost circuit 100 is in boost mode.

[0097] [Amended according to Rule 26, 14.11.2025] It can be seen that the switching transistor driving circuit 200 provided in the embodiments of this application can drive the four switching transistors in the buck-boost circuit 100 to work, without having to set up separate software logic for each switching transistor in the buck-boost circuit 100, which can make the structure of the driving circuit simpler and reduce the cost of the driving circuit.

[0098] [Amended according to Rule 26, 14.11.2025] In a second aspect, embodiments of this application also provide an energy storage device, which includes a buck-boost circuit and a switching transistor drive circuit as described in any embodiment of the first aspect; the switching transistor drive circuit is connected to the buck-boost circuit.

[0099] [Amended according to Rule 26, 14.11.2025] Energy storage devices refer to devices capable of storing energy in the form of electrical energy and releasing it to supply power systems or other equipment when needed. In this embodiment, the switch driving circuit has the same structure and function as the switch driving circuit described in any embodiment of the first aspect, and will not be repeated here.

[0100] [Amended 14.11.2025 according to Rule 26] In some implementations, the energy storage device may also include a battery, which is typically located on the output side of the buck-boost circuit.

[0101] [Amended according to Rule 26, 14.11.2025] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0102] [Amended according to Rule 26, 14.11.2025] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in the details for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A switching transistor driving circuit for driving a buck-boost circuit, characterized in that, include: Logic module, first output module and second output module; The logic module is connected to the first output module and the second output module respectively. The first output module is also connected to the first driving module of the buck bridge arm of the buck-boost circuit, and the second output module is also connected to the second driving module of the boost bridge arm of the buck-boost circuit. The logic module is configured to receive a drive signal and a buck-boost switching signal, and when the buck-boost switching signal is a buck switching signal, output the drive signal to the first output module and output a control signal to the second output module to make the buck-boost circuit work in buck mode; when the buck-boost switching signal is a boost switching signal, output the drive signal to the second output module and output the control signal to the first output module to make the buck-boost circuit work in boost mode.

2. The switching transistor driving circuit according to claim 1, characterized in that, The logic module includes a first logic unit and a second logic unit; The first logic unit is connected to the first output module, and the second logic unit is connected to the second output module; The first logic unit is configured to output the drive signal to the first output module in response to the buck switching signal, and to output the control signal to the first output module in response to the boost switching signal; The second logic unit is configured to output the control signal to the second output module in response to the buck switching signal, and to output the drive signal to the second output module in response to the boost switching signal.

3. The switching transistor driving circuit according to claim 2, characterized in that, The first logic unit includes a first AND gate, a first OR gate, and a first NOT gate; The first input terminal of the first AND gate and the input terminal of the first NOT gate are both used to receive the buck-boost switching signal. The second input terminal of the first AND gate is used to receive the drive signal. The output terminal of the first AND gate is connected to the first input terminal of the first OR gate. The second input terminal of the first OR gate is connected to the output terminal of the first NOT gate. The output terminal of the first OR gate is connected to the first output module.

4. The switching transistor driving circuit according to claim 2, characterized in that, The second logic unit includes a second NOT gate, a second OR gate, and a second AND gate; The input terminal of the second NOT gate and the first input terminal of the second OR gate are both used to receive the buck-boost switching signal. The output terminal of the second NOT gate is connected to the first input terminal of the second AND gate. The second input terminal of the second AND gate is used to receive the drive signal. The output terminal of the second AND gate is connected to the second input terminal of the second OR gate. The output terminal of the second OR gate is connected to the second output module.

5. The switching transistor driving circuit according to any one of claims 1-4, characterized in that, The first output module includes a first output unit and a second output unit, the second output module includes a third output unit and a fourth output unit, the step-down bridge arm includes a step-down upper tube and a step-down lower tube, the first drive module includes a first drive submodule of the step-down upper tube and a second drive submodule of the step-down lower tube, the step-up bridge arm includes a step-up upper tube and a step-up lower tube, and the second drive module includes a third drive submodule of the step-up upper tube and a fourth drive submodule of the step-up lower tube. The first output terminal of the logic module is connected to the first output unit and the second output unit respectively, the second output terminal of the logic module is connected to the third output unit and the fourth output unit respectively, the first output unit is also connected to the first driving submodule, the second output unit is also connected to the second driving submodule, the third output unit is also connected to the third driving submodule, and the fourth output unit is also connected to the fourth driving submodule. When the buck-boost switching signal is a buck switching signal, the first output unit is configured to output a first pulse width modulation signal to the first driving submodule based on the driving signal, causing the buck upper transistor to periodically turn on and off; the second output unit is configured to output a second pulse width modulation signal to the second driving submodule based on the driving signal, causing the buck lower transistor to periodically turn on and off, wherein the buck upper transistor and the buck lower transistor are turned on at different times; the third output unit is configured to output a first level signal to the third driving submodule based on the control signal, causing the boost upper transistor to turn on; and the fourth output unit is configured to output a second level signal to the fourth driving submodule based on the control signal, causing the boost lower transistor to turn off. When the buck-boost switching signal is a boost switching signal, the first output unit is configured to output a third-level signal to the first driving submodule based on the control signal, so that the buck upper transistor is turned on; the second output unit is configured to output a fourth-level signal to the second driving submodule based on the control signal, so that the buck lower transistor is turned off; the third output unit is configured to output a third pulse width modulation signal to the third driving submodule based on the driving signal, so that the boost upper transistor is periodically turned on and off; and the fourth output unit is configured to output a fourth pulse width modulation signal to the fourth driving submodule based on the driving signal, so that the boost lower transistor is periodically turned on and off. The boost upper transistor and the boost lower transistor are turned on at different times.

6. The switching transistor driving circuit according to claim 5, characterized in that, The first output module is further configured to adjust the duty cycle of the first pulse width modulation signal through the first output unit and adjust the duty cycle of the second pulse width modulation signal through the second output unit, so that the upper buck transistor is turned on after a first dead time after the lower buck transistor is turned off, and the lower buck transistor is turned on after a first dead time after the upper buck transistor is turned off. The second output module is further configured to adjust the duty cycle of the third pulse width modulation signal through the third output unit and the duty cycle of the second pulse width modulation signal through the fourth output unit, so that the boost lower transistor is turned on after a second dead time delay, and the boost upper transistor is turned on after the boost upper transistor is turned on after a second dead time delay.

7. The switching transistor driving circuit according to claim 6, characterized in that, The first output unit includes a first resistor, a first capacitor, and a first diode; the second output unit includes a third NOT gate, a second resistor, a second capacitor, and a second diode; the third output unit includes a third resistor, a third capacitor, and a third diode; and the fourth output unit includes a fourth NOT gate, a fourth resistor, a fourth capacitor, and a fourth diode. The first end of the first resistor is connected to the first output terminal of the logic module and the cathode of the first diode, respectively. The second end of the first resistor is connected to the anode of the first diode, the first end of the first capacitor and the first driving submodule, respectively. The second end of the first capacitor is grounded. The first terminal of the third NOT gate is connected to the first output terminal of the logic module, the second terminal of the third NOT gate is connected to the first terminal of the second resistor and the cathode of the second diode, the second terminal of the second resistor is connected to the anode of the second diode, the first terminal of the second capacitor and the second driving submodule, and the second terminal of the second capacitor is grounded. The first end of the third resistor is connected to the second output terminal of the logic module and the cathode of the third diode, the second end of the third resistor is connected to the anode of the third diode, the first end of the third capacitor and the third driving submodule, and the second end of the third capacitor is grounded. The first terminal of the fourth NOT gate is connected to the second output terminal of the logic module. The second terminal of the fourth NOT gate is connected to the first terminal of the fourth resistor and the cathode of the fourth diode. The second terminal of the fourth resistor is connected to the anode of the fourth diode, the first terminal of the fourth capacitor, and the fourth driving submodule. The second terminal of the fourth capacitor is grounded.

8. The switching transistor driving circuit according to claim 5, characterized in that, The switching transistor driving circuit also includes a comparison module; The comparison module is connected to the third driving submodule; The comparison module is configured to receive a first sampling signal of the output current of the buck-boost circuit, and when the voltage of the first sampling signal is less than a first voltage, output a first shutdown signal to the third drive submodule to turn off the boost transistor.

9. The switching transistor driving circuit according to any one of claims 1-4, characterized in that, The switching transistor drive circuit also includes an overcurrent protection module; The overcurrent protection module is connected to the first drive module and the second drive module respectively; The overcurrent protection module is configured to receive a second sampling signal of the input current of the buck-boost circuit, and when the voltage of the second sampling signal is greater than the second voltage, output a second shutdown signal to the first drive module and the second drive module to stop the buck-boost circuit from working.

10. An energy storage device, characterized in that, Includes a step-up / step-down circuit and a switching transistor drive circuit as described in any one of claims 1-9; The switching transistor drive circuit is connected to the buck-boost circuit.

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