Circuit device and memory device

Abstract

This circuit device comprises: a power supply selection circuit that outputs VDDH or VPP, which are two types of power supply voltages, as VDDRDC in accordance with the magnitude relationship between the VDDH and the VPP; and a cell selection circuit that selects any cell from among a plurality of cells arranged in a two-dimensional array. The cell selection circuit includes a drive circuit that drives a signal line connected to the plurality of cells using the VPP, and a logic circuit that controls the drive circuit using the VDDRDC. The drive circuit includes a P-type transistor, and the P-type transistor of the drive circuit includes a current terminal connected to the VPP, a current terminal connected to the signal line, and a gate to which the VDDRDC is supplied from the logic circuit.

Description

Circuit device and memory device

[0001] The present disclosure relates to a circuit device and a memory device.

[0002] A cell selection circuit for selecting a desired cell from a plurality of cells arranged in a two-dimensional array is known. For example, Patent Documents 1 and 2 disclose a memory device including such a cell selection circuit.

[0003] Japanese Patent Application Laid-Open No. 2010-244616, Japanese Patent Application Laid-Open No. 2013-218753

[0004] The cell selection circuit includes a drive circuit that drives a signal line connected to the cell and a logic circuit that controls the drive circuit. In a conventional device, both the drive circuit and the logic circuit always operate using a charge pump voltage. As a result, the power consumption increases.

[0005] One aspect of the present disclosure suppresses an increase in power consumption.

[0006] A circuit device according to one aspect of the present disclosure includes a power supply selection circuit that outputs VDDHR or VPP as VDDRDC according to the magnitude relationship between two types of power supply voltages, VDDH and VPP, and a cell selection circuit that selects an arbitrary cell from a plurality of cells arranged in a two-dimensional array. The cell selection circuit includes a drive circuit that drives a signal line connected to the plurality of cells using VPP and a logic circuit that controls the drive circuit using VDDRDC. The drive circuit includes a P-type transistor, and the P-type transistor of the drive circuit includes a current terminal connected to VPP, a current terminal connected to the signal line, and a gate to which VDDRDC from the logic circuit is supplied.

[0007] One aspect of this disclosure is a memory device comprising: a power supply selection circuit that outputs VDDH or VPP as VDDRDDC depending on the relative magnitudes of two types of power supply voltages, VDDH and VPP; a plurality of cells arranged in a two-dimensional array; and a cell selection circuit that selects any cell from the plurality of cells. The cell selection circuit includes a drive circuit that drives signal lines connected to the plurality of cells using VPP, and a logic circuit that controls the drive circuit using VDDRDDC. The drive circuit includes a P-type transistor, and the P-type transistor of the drive circuit includes a current terminal connected to VPP, a current terminal connected to the signal line, and a gate to which VDDRDDC from the logic circuit is supplied.

[0008] This figure shows an example of the schematic configuration of the memory device 200 according to the embodiment. This figure shows an example of VDDH and VPP. This figure shows an example of VDDH, VPP and VDDRDDC. This figure shows an example of the schematic configuration of the row selection circuit 4. This figure shows an example of the schematic configuration of the power supply selection circuit 2. This figure shows an example of the simultaneous on-up of transistors TP91 and TP92. This figure shows an example of the relationship between the channel width W and the simultaneous on-up region R1. This figure shows an example of the relationship between the channel width W and the simultaneous on-up region R1. This figure shows an example of the schematic configuration of the power supply selection circuit 2.

[0009] Embodiments of this disclosure will be described in detail below with reference to the drawings. In each of the following embodiments, the same elements will be denoted by the same reference numerals to avoid redundant descriptions.

[0010] This disclosure will be described in the following order of items: 0. Introduction 1. Embodiments 2. Modifications 3. Conclusion

[0011] 0. Introduction In conventional memory devices, for example, both the drive circuit and logic circuit included in the row selection circuit that drives word lines operate using the charge pump voltage. Using the voltage before the charge pump directly would suppress the decrease in power efficiency associated with the generation of the charge pump voltage and suppress the increase in power consumption, but this is difficult to implement due to the following constraints.

[0012] In other words, to prevent forward current from flowing to the body of a P-type transistor included in the drive circuit, the body of that transistor needs to have a voltage greater than or equal to the charge pump voltage. Furthermore, when turning the transistor off (to a non-conducting state), a voltage greater than or equal to the charge pump voltage must be supplied to the gate of that transistor to suppress leakage current. This voltage is supplied to the drive circuit by the logic circuit.

[0013] Due to the constraints mentioned above, configurations have so far employed in which both the drive circuit and the logic circuit operate using the charge pump voltage. However, this leaves the challenges of reduced power efficiency and increased power consumption associated with the generation of the charge pump voltage.

[0014] 1. Figure 1 of the Embodiment shows an example of the schematic configuration of a memory device 200 according to an embodiment. The memory device 200 includes a circuit device 100 and a cell array circuit 6. The circuit device 100 includes a voltage generation circuit 1, a power supply selection circuit 2, and a cell selection circuit 3. Multiple types of power supply voltages are used in the circuit device 100. In Figure 1, two of these power supply voltages are shown as VDDH and VPP. However, in this disclosure, VDDH and VPP may simply be names to distinguish them from other voltages, and may be read as names such as the first voltage and the second voltage, for example. The same applies to the names of the other voltages.

[0015] In the following explanation, when an element is said to be connected to a certain voltage, it should be understood as meaning that the element is connected to wiring, terminals, etc., that have that voltage. Also, a low or high voltage is expressed as a small or large voltage.

[0016] Voltage generation circuit 1 is connected to VDDH. Voltage generation circuit 1 generates VPP based on VDDH. For example, voltage generation circuit 1 may be a charge pump circuit that boosts or buckles VDDH and outputs it as VPP. VPP can also be called the charge pump voltage. VDDH can also be called the voltage before the charge pump.

[0017] VPP is a variable voltage, and the voltage generation circuit 1 can generate a VPP having a desired level. The VPP generated by the voltage generation circuit 1 is supplied to the power supply selection circuit 2 and also to the cell selection circuit 3.

[0018] The voltage generation circuit 1 changes the VPP according to the environment in which the circuit device 100 is located. Examples of the environment include temperature, humidity, and pressure, and these values ​​are referred to as environmental values ​​E. Environmental values ​​E are obtained from sensors not shown, such as a temperature sensor, humidity sensor, pressure sensor, etc. Unless otherwise specified, the environmental value E will be assumed to be the temperature value.

[0019] By generating a VPP corresponding to the environmental value E, it is possible to provide a power supply voltage level suitable for the operating environment under that environmental value E, for example, the operation of each transistor. However, since the VPP changes depending on the environmental value E, the relative magnitudes of VDDH and VPP may also change. This will be explained with reference to Figure 2.

[0020] Figure 2 shows examples of VDDH and VPP. The horizontal axis of the graph represents the environmental value E. The vertical axis of the graph represents voltage. The solid line graph represents the power supply VDDH. The dashed line graph represents VPP.

[0021] VDDH is constant regardless of the environmental value E. VPP changes with the environmental value E. In this example, VPP changes linearly as the environmental value E changes.

[0022] The environmental value E at which VDDH and VPP are equal is called environmental value E1. The relative magnitudes of VDDH and VPP are reversed at environmental value E1. In this example, when environmental value E is less than environmental value E1 (E < E1), VPP is greater than VDDH (VPP > VDDH). When environmental value E is greater than environmental value E1 (E1 < E), VDDH is greater than VPP (VDDH > VPP).

[0023] Returning to Figure 1, the power supply selection circuit 2 receives VDDH and VPP from the voltage generation circuit 1 as inputs. The power supply selection circuit 2 selectively outputs either VDDH or VPP depending on the relative magnitudes of VDDH and VPP. The voltage output by the power supply selection circuit 2 is referred to as VDDRDDC and is shown in the figure. VDDRDDC is the voltage used in the row selection circuit 4, as will be described later, and can be called the VDD Row Decoder. VDDRDDC may be reinterpreted as, for example, the third voltage. The voltage level of VDDRDDC is the same as the voltage level of VDDH or the voltage level of VPP (VDDRDDC = VDDH, or VDDRDDC = VPP). It can also be said that a voltage that is not lower than either VDDH or VPP is output as VDDRDDC (VDDRDDC ≥ VDDH, and VDDRDDC ≥ VPP). The power supply selection circuit 2 selects the larger of the two voltages, VDDH and VPP, and outputs it as VDDDC. Please refer to Figure 3 for further explanation.

[0024] Figure 3 shows examples of VDDH, VPP, and VDDRDDC. The solid line graph represents the VDDH power supply. The dashed line graph represents VPP. The thick line graph represents VDDDC.

[0025] When VPP is greater than VDDH, VPP is output as VDDRDDC (VDDRDDC = VPP). When VDDH is greater than VPP, VDDH is output as VDDRDDC (VDDRDDC = VDDH).

[0026] Returning to Figure 1, for convenience, the cell array circuit 6 will be described first. The cell array circuit 6 includes a plurality of cells 60 arranged in a two-dimensional array (matrix). The cell array circuit 6 can also be called the cell array section, etc. In the exemplary embodiment, the cells 60 are memory cells and are configured to include memory elements for storing bit information. An example of a memory element is a magnetic memory element. An example of a magnetic memory element is an MTJ (Magnetic Tunnel Junction) element. The cell array circuit 6 can also be called a memory cell array circuit or memory cell array section, etc. Various known configurations may be adopted.

[0027] The cell selection circuit 3 selects any cell 60 from among the multiple cells 60 included in the cell array circuit 6. Specifically, the cell selection circuit 3 includes a row selection circuit 4 and a column selection circuit 5.

[0028] The row selection circuit 4 is connected to each cell 60 in the cell array circuit 6 via signal lines extending in the direction of the array rows. The signal lines extending from the row selection circuit 4 into the cell array circuit 6 are referred to as word lines WL and are shown in the diagram. There may be at least the same number of word lines WL as the number of rows in the array. The row selection circuit 4 is supplied with address information (ADDRESS) that specifies the array row to be selected by the row selection circuit 4.

[0029] If the number of rows in the array of multiple cells 60 included in the cell array circuit 6 is N (where N is an integer of 2 or more), then for example, there are N word lines WL corresponding to N rows. The word line WL for the first row is referred to as word line WL-0 and is shown in the diagram. The word line WL for the second row is referred to as word line WL-1 and is shown in the diagram. The word line WL for the Nth row is referred to as word line WL-N-1 and is shown in the diagram. When no particular distinction is made between them, they are simply called word lines WL. Further details of the row selection circuit 4 will be described later.

[0030] The column selection circuit 5 is connected to each cell 60 of the cell array circuit 6 via signal lines (not shown) that extend in the direction of the array columns. These signal lines extending from the column selection circuit 5 into the cell array circuit 6 are also called bit lines, etc. There may be at least the same number of bit lines as the number of columns in the array. The column selection circuit 5 is supplied with address information that specifies the array column to be selected.

[0031] Note that the cell selection circuit 3 may be understood to mean at least one of the row selection circuit 4 and the column selection circuit 5. The row selection circuit 4 will be further explained with reference to Figure 4.

[0032] Figure 4 shows an example of the schematic configuration of row selection circuit 4. Row selection circuit 4 includes a drive circuit 41 and a logic circuit 42. Unless otherwise specified, transistors are assumed to be MOSFETs. The drain and / or source of the transistor are referred to as current terminals.

[0033] The drive circuit 41 is connected to the word line WL and drives the word line WL. Driving the word line WL includes controlling the voltage of the word line WL.

[0034] There are multiple drive circuits 41 corresponding to multiple word lines WL. The drive circuit 41 to which word line WL-0 is connected is referred to as drive circuit 41-0 and is shown in the figure. The drive circuit 41 to which word line WL-1 is connected is referred to as drive circuit 41-1 and is shown in the figure. The drive circuit 41 to which word line WL-N-1 is connected is referred to as drive circuit 41-N-1 and is shown in the figure. Unless otherwise specified, these are simply called drive circuits 41.

[0035] The drive circuit 41 drives the word line WL using VPP and VNN. More specifically, the drive circuit 41 controls the voltage of the word line WL so that the word line WL has either VPP or VNN. VNN is a lower voltage than VPP.

[0036] The drive circuit 41 in this example is an inverter circuit and includes a cascode-connected P-type transistor 411 and an N-type transistor 412. The body voltages of transistor 411 and transistor 412 are different from each other. In this example, the body voltage of transistor 411 is VDDDC. The body voltage of transistor 412 is VNN.

[0037] The gates of transistors 411 and 412 are connected to each other. This connection point is referred to as node N411 and is shown in the diagram. Node N411 is connected to logic circuit 42. Node N411 may correspond to an input terminal of drive circuit 41.

[0038] The cascode connection point of transistors 411 and 412 is referred to as node N412 and is shown in the diagram. Node N412 is connected to the word line WL. Node N412 may correspond to the output terminal of the drive circuit 41.

[0039] The current terminal of transistor 411 opposite to node N412 is connected to VPP. The current terminal of transistor 412 opposite to node N412 is connected to VNN.

[0040] Node N411 is supplied with VDDDC or VNN from logic circuit 42, and the on and off states (conductive and non-conductive states) of transistors 411 and 412 are controlled mutually.

[0041] When transistor 411 is on and transistor 412 is off, node N412 has a VPP, and the word line WL connected to node N412 also has a VPP. When transistor 411 is off and transistor 412 is on, node N412 has a VNN, and the word line WL connected to node N412 also has a VNN.

[0042] The logic circuit 42 controls the drive circuit 41 using VDDRDDC and VNN. VDDRDDC and VNN may correspond to high-level voltage and low-level voltage in a logic operation. The logic circuit 42 performs a logic operation to select the array row specified by the given address information. The logic circuit 42 supplies VDDRDDC or VNN to each node N411 of the multiple drive circuits 41. Accordingly, as described above, each drive circuit 41 drives the corresponding word line WL.

[0043] In the circuit device 100 having the configuration described above, the power supply selection circuit 2 selectively outputs VDDH or VPP as VDDRDDC. The logic circuit 42 of the row selection circuit 4 operates using VDDRDDC from the power supply selection circuit 2. When the power supply selection circuit 2 selects VDDH and outputs it as VDDRDDC (VDDRDDC = VDDH), the logic circuit 42 operates using VDDH instead of VPP. This suppresses the decrease in power efficiency associated with the generation of VPP by the voltage generation circuit 1 and reduces the increase in power consumption compared to when the logic circuit 42 operates using VPP.

[0044] The leakage current in the drive circuit 41 is also suppressed. Specifically, one current terminal of the P-type transistor 411 included in the drive circuit 41 is connected to VPP, and VDDRC from the logic circuit 42 is supplied to the gate of the transistor 411. If VDDRC is lower than VPP, a leakage current flowing from VPP to VNN may occur. In this embodiment, since VDDRC does not fall below VPP, the leakage current can be suppressed.

[0045] An example of a specific circuit configuration for realizing the functions of the power supply selection circuit 2 described so far will be described with reference to FIG. 5.

[0046] FIG. 5 is a diagram showing an example of the schematic configuration of the power supply selection circuit 2. The power supply selection circuit 2 includes an input circuit 7, a comparison circuit 8, and an output circuit 9. In the following description, when a certain transistor is connected between two elements, it may be understood to mean that one current terminal of the transistor is connected to one element and the other current terminal is connected to the other element.

[0047] VDDH and VPP are input to the input circuit 7. The input circuit 7 includes a resistance element R71, an N-type transistor TN71, a resistance element R72, and an N-type transistor TN72.

[0048] The resistance element R71 and the transistor TN71 are connected in series between VDDH and VSS. VSS is a voltage lower than VDDH and VPP. One end of the resistance element R71 is connected to VDDH. The other end of the resistance element R71 is connected to one current terminal of the transistor TN71. The other current terminal of the transistor TN71 is connected to VSS.

[0049] The connection point of the resistance element R71 and the transistor TN71 is referred to as a node N71 and illustrated. A current flows through the resistance element R71 according to the voltage difference between VDDH and the node N71. This current is referred to as a current I71 and illustrated.

[0050] A voltage called VCMN is connected to the gate of transistor TN71. VCMN is the voltage that causes transistor TN71 (and other transistors) to operate as a constant current source. The constant current flowing through transistor TN71 is referred to as current Ic71 and is shown in the diagram.

[0051] The resistor R72 and the transistor TN72 are connected in series between VPP and VSS. One end of the resistor R72 is connected to VPP. The other end of the resistor R72 is connected to one current terminal of transistor TN72. The other current terminal of transistor TN72 is connected to VSS.

[0052] The connection point between the resistor R72 and the transistor TN72 is referred to as node N72 and is shown in the diagram. Current flows through the resistor R72 according to the voltage difference between VPP and node N72. This current is referred to as current I72 and is shown in the diagram.

[0053] A VCMN is connected to the gate of transistor TN72. The constant current flowing through transistor TN72 is referred to as current Ic72 and is shown in the diagram.

[0054] In the input circuit 7 described above, one end of resistor element R71 and one end of resistor element R72 may correspond to the input terminals of the input circuit 7. Nodes N71 and N72 may correspond to the output terminals of the input circuit 7.

[0055] The comparison circuit 8 is located after the input circuit 7 and compares VDDH and VPP. The comparison circuit 8 operates using the VDDDC output by the power supply selection circuit 2.

[0056] The comparison circuit 8 includes a current mirror circuit 810 and a constant current source circuit 820 connected to the current mirror circuit 810. The current mirror circuit 810 includes a P-type transistor TP81, a P-type transistor TP82, a P-type transistor TP83, a P-type transistor TP84, an N-type transistor TN803, and an N-type transistor TN804. The constant current source circuit 820 includes an N-type transistor TN81, an N-type transistor TN82, an N-type transistor TN83, an N-type transistor TN803, and an N-type transistor TN804.

[0057] Transistors TP83, TN803, and TN83 are connected in series between VDDDC and VSS. One current terminal of transistor TP83 is connected to VDDDC. The other current terminal of transistor TP83 is connected to one current terminal of transistor TN803. The other current terminal of transistor TN803 is connected to one current terminal of transistor TN83. The other current terminal of transistor TN83 is connected to VSS.

[0058] The connection point between transistors TP83 and TN803 is referred to as node N83 and is shown in the diagram. The gate of transistor TP83 is also connected to node N83.

[0059] The gate of transistor TN803 is connected to node N71 of input circuit 7. Current flows through transistor TN803 and transistor TP83 according to the gate voltage of transistor TN803. This current is referred to as current I83 and is shown in the diagram.

[0060] Transistors TP84, TN804, and TN83 are connected in series between VDDDC and VSS. One current terminal of transistor TP84 is connected to VDDDC. The other current terminal of transistor TP84 is connected to one current terminal of transistor TN804. The other current terminal of transistor TN804 is connected to one current terminal of transistor TN83.

[0061] The connection point between transistors TP84 and TN804 is referred to as node N84 and is shown in the diagram. The gate of transistor TP84 is also connected to node N84.

[0062] The gate of transistor TN804 is connected to node N72 of input circuit 7. Current flows through transistor TN804 and transistor TP84 according to the gate voltage of transistor TN804. This current is referred to as current I84 and is shown in the diagram.

[0063] The gate of transistor TN83 is connected to VCMN. The constant current flowing through transistor TN83 is referred to as current Ic83 and is shown in the diagram.

[0064] The sum of currents I83 and I84 corresponds to current Ic83. When one of currents I83 or I84 increases, the other decreases. The gate of transistor TN803, through which current I83 flows, is connected to VDDH via node N71 and resistor R71 of the input circuit 7. The gate of transistor TN804, through which current I84 flows, is connected to VPP via node N72 and resistor R72 of the input circuit 7. The greater VDDH is than VPP, the greater current I83 is than current I84. Conversely, the greater VPP is than VDDH, the greater current I84 is than current I83.

[0065] Transistors TP81 and TN81 are connected in series between VDDDC and VSS. One current terminal of transistor TP81 is connected to VDDDC. The other current terminal of transistor TP81 is connected to one current terminal of transistor TN81. The other current terminal of transistor TN81 is connected to VSS. The connection point between transistors TP81 and TN81 is referred to as node N81 and is shown in the diagram.

[0066] The gate of transistor TP81 is connected to the gate of transistor TP83. Transistor TP81 is a mirror transistor (first mirror transistor) of transistor TP83.

[0067] The gate of transistor TN81 is connected to VCMN. The constant current flowing through transistor TN81 is referred to as current Ic81 and is shown in the diagram.

[0068] Transistors TP82 and TN82 are connected in series between VDDDC and VSS. One current terminal of transistor TP82 is connected to VDDDC. The other current terminal of transistor TP82 is connected to one current terminal of transistor TN82. The other current terminal of transistor TN82 is connected to VSS. The connection point between transistors TP82 and TN82 is referred to as node N82 and is shown in the diagram.

[0069] The gate of transistor TP82 is connected to the gate of transistor TP84. Transistor TP82 is a mirror transistor (second mirror transistor) of transistor TP84.

[0070] The gate of transistor TN82 is connected to VCMN. The constant current flowing through transistor TN82 is referred to as current Ic82 and is shown in the diagram.

[0071] In the comparison circuit 8 described above, the gates of transistor TN803 and transistor TN804 may correspond to the input terminals of the comparison circuit 8. Nodes N81 and N82 may correspond to the output terminals of the comparison circuit 8.

[0072] The voltages at node N81 and node N82 indicate the comparison result of the magnitude relationship between VDDH and VPP. If VDDH is greater than VPP, currents I83 and I81 become greater than currents I84 and I82, and the voltage at node N81 becomes greater than the voltage at node N82. In other words, the voltage at node N82 becomes less than the voltage at node N81. Conversely, if VPP is greater than VDDH, currents I84 and I82 become greater than currents I83 and I81, and the voltage at node N82 becomes greater than the voltage at node N81. In other words, the voltage at node N81 becomes less than the voltage at node N82. Such nodes N81 and N82 can also be called the first and second comparison nodes, having voltages corresponding to the comparison result of the comparison circuit 8.

[0073] As mentioned earlier, the comparator circuit 8 operates using VDDDC. Specifically, node N82 is connected to VDDDC via transistor TP82. When transistor TP92 of the output circuit 9 is turned off, VDDDC from node N82 is supplied to the gate of transistor TP92. The other current terminal of transistor TP92 may be connected to VPP via transistor TP91, but since the VDDDC supplied to the gate does not fall below VPP, current leakage in transistor TP92 can be suppressed.

[0074] The output circuit 9 is located downstream of the comparator circuit 8. The output circuit 9 outputs VDDH or VPP as VDDDC according to the comparison result of the comparator circuit 8, more specifically, the voltages at node N81 and node N82.

[0075] The output circuit 9 includes two P-type transistors (output transistors) connected to a node for outputting VDDDC. The node is referred to as node N9 and is shown in the figure. The first output transistor is referred to as transistor TP91 and is shown in the figure. The second output transistor is referred to as transistor TP92 and is shown in the figure.

[0076] Transistor TP91 is connected between VPP and node N9. One current terminal of transistor TP91 is connected to VPP. The other current terminal of transistor TP91 is connected to node N9. The gate of transistor TP91 is connected to node N81 of comparator circuit 8.

[0077] Transistor TP92 is connected between VDDH and node N9. One current terminal of transistor TP92 is connected to VDDH. The other current terminal of transistor TP92 is connected to node N9.

[0078] When transistor TP91 is ON, node N9 may have VPP. When transistor TP92 is ON, node N9 may have VDDH. For example, when VPP is greater than VDDH, the voltage at node N81 decreases, and transistor TP91 turns ON. Node N9 has VPP. When VDDH is greater than VPP, the voltage at node N82 decreases, and transistor TP92 turns ON. Node N9 has VDDH.

[0079] The VDDH or VPP of node N9 is output as VDDRDDC. The output VDDRDDC is supplied to the row selection circuit 4 (Figures 1 and 4), and is also supplied (returned) to the comparator circuit 8 so that it can be used by the comparator circuit 8 as well.

[0080] Transistors TP91 and TP92 can basically be turned on or off mutually, but when the magnitudes of VDDH and VPP are similar, both can be turned on simultaneously. See also Figure 6 for further explanation.

[0081] Figure 6 shows an example of simultaneous on-up of transistors TP91 and TP92. The VDDH, VPP, voltage at node N81, and voltage at node N82 in response to changes in the ambient value E are schematically shown.

[0082] When VDDH is somewhat greater than VPP, in this example when the ambient value E is somewhat greater than the ambient value E1, the voltage at node N82 is low, and transistor TP92 is turned on. VHHD is output as VDDDC.

[0083] When VPP is somewhat greater than VDDH, and in this example the ambient value E is somewhat less than ambient value E1, the voltage at node N81 is low and transistor TP91 is turned on. VPP is output as VDDDC.

[0084] When the magnitudes of VDDH and VPP are close (including being the same), the voltages of both nodes N81 and N82 are small, and both transistors TP91 and TP92 are turned on simultaneously. This range is referred to as the simultaneous-on region R1 and is shown in the diagram. The simultaneous-on region R1 may be a region where the difference between VDDH and VPP is within a predetermined range.

[0085] Without the simultaneous ON region R1, both transistors TP91 and TP92 may turn OFF, potentially preventing either VDDH or VPP from being output as VDDRDDC. By setting the simultaneous ON region R1, situations where both transistors TP91 and TP92 turn OFF simultaneously can be reliably avoided. This contributes to stabilizing the output of VDDRDDC, among other things.

[0086] As shown in Figure 6, when transistor TP91 is on and transistor TP92 is off, the voltage at node N82 increases as VPP increases. As explained earlier with reference to Figure 5, current leakage at transistor TP92 is suppressed.

[0087] Returning to Figure 5, the comparator circuit 8 is configured such that the simultaneous ON region R1 described above exists. Specifically, the ON and OFF states of transistors TP91 and TP92 of the output circuit 9 are controlled by nodes N81 and N82 of the comparator circuit 8. Therefore, when the difference between VDDH and VPP is greater than a predetermined range, nodes N81 and N82 turn transistors TP91 and TP92 on or off exclusively from each other. When the difference between VDDH and VPP is within a predetermined range, nodes N81 and N82 turn on both transistors TP91 and TP92. For convenience, this control of transistors TP91 and TP92 by nodes N81 and N82 is also called selective control by the comparator circuit 8.

[0088] The comparator circuit 8 may be configured to perform the selection control described above. The comparator circuit 8 is designed so that a desired simultaneous ON region R1 is obtained. An example of the design is the design of the capabilities of the transistors in the comparator circuit 8, more specifically, the transistors included in the current mirror circuit 810 and the transistors included in the constant current source circuit 820.

[0089] One example of transistor design is the design of its size. Another example of transistor size is the channel width. In the following explanation, we will use the design of the channel width as an example. The channel width will be referred to as channel width W. The example values ​​of channel width W are in arbitrary units.

[0090] By adjusting the channel width W, the range of the simultaneous ON region R1 can be changed, for example, by changing the size of that range or shifting it. Specifically, this will be explained using transistors TP81, TP82, TP83, TP84, TN81, TN82, and TN83 as examples.

[0091] Figure 7 shows an example of the relationship between channel width W and simultaneous ON region R1. Figure 7(A) schematically shows the simultaneous ON region R1 when the channel width W of transistors TP81 and TP82 is 8 (W=8). Figure 7(B) schematically shows the simultaneous ON region R1 when the channel width W of transistors TP81 and TP82 is 6 (W=6). The channel widths W of the other transistors are as follows: Channel width W of transistor TP83 = 8 Channel width W of transistor TP84 = 8 Channel width W of transistor TN81 = 2 Channel width W of transistor TN82 = 2 Channel width W of transistor TN83 = 3

[0092] As can be seen from Figures 7(A) and (B), in this example, the range of the simultaneous ON region R1 can be widened by reducing the channel width W of transistors TP81 and TP82. Conversely, the range of the simultaneous ON region R1 can be narrowed by increasing the channel width W of transistors TP81 and TP82.

[0093] The channel width W values ​​shown above are merely examples. By designing the channel width W of each transistor TP81, TP82, TP83, TP84, TN81, TN82, and TN83 in various ways, the desired simultaneous ON region R1 can be obtained.

[0094] The voltage at node N81 may be changed so that transistor TP91 turns on only when VPP becomes somewhat larger than VDDH. This reduces the opportunities for VPP to be output as VDDDC (the opportunities for VPP to be selected), thereby further enhancing the effect of suppressing the increase in power consumption. One specific design technique for this is to increase the channel width W of transistor TP81 connected to the gate of transistor TP91. For example, the channel width W of transistor TP81 may be larger than the channel width W of transistor TP82. This will be explained with reference to Figure 8.

[0095] Figure 8 shows an example of the relationship between channel width W and simultaneous ON region R1. Figure 8(A) schematically shows the simultaneous ON region R1 when the channel width W of transistor TP81 is 6 (W=6). Figure 8(B) schematically shows the simultaneous ON region R1 when the channel width W of transistor TP81 is 8 (W=8). The channel widths W of the other transistors are as follows: Channel width W of transistor TP82 = 6 Channel width W of transistor TP83 = 6 Channel width W of transistor TP84 = 6 Channel width W of transistor TN81 = 2 Channel width W of transistor TN82 = 2 Channel width W of transistor TN83 = 3

[0096] Referring to Figures 8(A) and (B) in comparison with the relative magnitudes of VDDH and VPP in Figure 6 explained earlier, the greater the channel width W of transistor TP81 is compared with the channel width W of transistor TP82, the more delayed the voltage change at node N81 appears in response to the increase in VPP. It can also be said that the timing at which node N81 decreases shifts in the direction of increasing VPP.

[0097] For example, by designing the channel width W of each transistor, particularly the channel width W of transistors TP81 and TP82, as described above, the desired simultaneous ON region R1 can be obtained.

[0098] 2. Modified Examples The technologies disclosed are not limited to the embodiments described above. Several modifications are described below.

[0099] <Modified Power Supply Selection Circuit> In one embodiment, the power supply selection circuit 2 may be configured to forcibly output VDDH or VPP as VDDRDDC. This will be explained with reference to Figure 9.

[0100] Figure 9 shows an example of the schematic configuration of the power supply selection circuit 2. The power supply selection circuit 2 shown in Figure 9 differs from the configuration in Figure 5 described earlier in that it further includes an additional circuit 10.

[0101] The additional circuit 10 disables the comparison of VDDH and VPP by the comparison circuit 8 and forcibly sets the comparison result. The additional circuit 10 includes a P-type transistor TPA1, a P-type transistor TPA2, an N-type transistor TNB1, a P-type transistor TPC1, an N-type transistor TND1, a P-type transistor TPC2, an N-type transistor TND2, and a P-type transistor TPE1.

[0102] Transistors TPA1, TPA2, and TNB1 are used to disable the comparison by the comparator circuit 8. These transistors are connected between the current mirror circuit 810 and the constant current source circuit 820 and their power supply voltages (VDDDC, VSS).

[0103] Specifically, transistor TPA1 is connected between VDDDC and node N83. One current terminal of transistor TPA1 is connected to VDDDC. The other current terminal of transistor TPA1 is connected to node N83. Transistor TPA2 is connected between VDDDC and node N84. One current terminal of transistor TPA2 is connected to VDDDC. The other current terminal of transistor TPA2 is connected to node N84. Transistor TNB1 is connected between the other current terminals of transistors TN81, TN82, and TN83 and VSS.

[0104] The gate voltages of transistors TPA1, TPA2, and TNB1 are controlled, for example, by a control signal (not shown). By turning off transistors TPA1, TPA2, and TNB1, the current mirror circuit 810 is deactivated, and therefore the control of the voltages at nodes N81 and N82 by the current mirror circuit 810 is disabled.

[0105] Transistors TPC1, TND1, TPC2, and TND2 are used to forcibly set the comparison results of the comparator circuit 8, more specifically, the voltages of nodes N81 and N82. Transistors TPC1 and TND1 are connected between node N81 and the power supply voltage (VDDDC or VSS). Transistors TPC2 and TND2 are connected between node N82 and the power supply voltage (VDDDC or VSS).

[0106] More specifically, transistor TPC1 is connected between VDDDC and node N81. Transistor TND1 is connected between node N81 and VSS. Transistor TPC2 is connected between VDDDC and node N82. Transistor TND2 is connected between node N82 and VSS.

[0107] The gate voltages of transistors TPC1, TND1, TPC2, and TND2 are controlled, for example, by control signals (not shown). By controlling the gate voltage of each transistor, the voltages at node N81 and node N82 can be forcibly set to VDDDC or VSS.

[0108] Transistor TPE1 is connected between VDDH and transistor TP92. One current terminal of transistor TPE1 is connected to VDDH. The other current terminal of transistor TPE1 is connected to one current terminal of transistor TP92. The gate of transistor TPE1 is connected to node N82.

[0109] The body voltages of transistor TPE1 and transistor TP92 are different. In this example, the body voltage of transistor TPE1 is VDDH, and the body voltage of transistor TP92 is VDDDC. By connecting transistors TPE1 and TP92 in series between VDDH and node N9, even if node N82 is VDDDC, VDDH and node N9 can be reliably electrically isolated, preventing VDDH from being output as VDDDC. It can also be said that the off function of transistor TP92 is enhanced by transistor TPE1.

[0110] For example, by providing the additional circuit 10 described above, VDDH or VPP can be forcibly output as VDDRDDC. This type of operation can be used, for example, as a test mode.

[0111] <Examples of other devices> In the above embodiment, a memory device 200 was used as an example. However, the disclosed technology may be applied to devices other than the memory device 200. An example of another device is a light detection device. Examples of light detection devices include imaging devices, distance measuring devices, etc. An imaging device includes, for example, a pixel array circuit (pixel array section) including a plurality of pixels arranged in two dimensions, and a drive circuit (vertical drive circuit, horizontal drive circuit) for selecting and driving any pixel among the plurality of pixels. The pixel array circuit and pixels correspond to the cell array circuit 6 and cells 60 described above. The drive circuits (vertical drive circuit, horizontal drive circuit) correspond to the cell selection circuit 3 (row selection circuit 4, column selection circuit 5) described above.

[0112] 3. Summary The technology described above can be identified, for example, as follows: One of the disclosed technologies is a circuit device 100. As described with reference to Figures 1 to 9, the circuit device 100 includes a power supply selection circuit 2 that outputs VDDH or VPP as VDDRDDC (for example, the larger of the two voltages VDDH and VPP) depending on the relative magnitudes of two types of power supply voltages, VDDH and VPP, and a cell selection circuit 3 that selects any cell 60 from a plurality of cells 60 arranged in a two-dimensional array. The cell selection circuit 3 includes a drive circuit 41 that drives signal lines (word lines WL) connected to the plurality of cells 60 using VPP, and a logic circuit 42 that controls the drive circuit 41 using VDDRDDC. The drive circuit 41 includes a P-type transistor 411. The P-type transistor 411 of the drive circuit 41 includes a current terminal connected to VPP, a current terminal connected to the signal line (word line WL), and a gate to which VDDRDDC from the logic circuit 42 is supplied. VDDDC may be the larger of the voltages VDDH and VPP.

[0113] According to the above-described circuit device 100, when the power supply selection circuit 2 selects VDDH and outputs it as VDDDC, the logic circuit 42 operates using VDDH instead of VPP. Compared to when the logic circuit 42 operates using VPP, the decrease in power efficiency associated with the generation of VPP by the voltage generation circuit 1 can be suppressed, and the increase in power consumption can be suppressed. In addition, VDDDC from the logic circuit 42 is supplied to the gate of the transistor 411 of the drive circuit 41. VDDDC may be the larger of the voltages of VDDH and VPP, and in that case, VDDDC will not be lower than VPP. Therefore, leakage current that may occur in transistor 411 can also be suppressed.

[0114] As explained with reference to Figures 5 to 9, the power supply selection circuit 2 may include an input circuit 7 into which VDDH and VPP are input, a comparison circuit 8 located downstream of the input circuit 7 for comparing VDDH and VPP, and an output circuit 9 located downstream of the comparison circuit 8 for outputting VDDH or VPP as VDDRDDC according to the comparison result of the comparison circuit 8. For example, a power supply selection circuit 2 with such a configuration can selectively output VDDH or VPP as VDDRDDC.

[0115] As explained with reference to Figures 5 to 9, the comparator circuit 8 may operate using VDDDC. For example, the comparator circuit 8 may include nodes N81 and N82 (first and second comparator nodes) having voltages corresponding to the comparison results of VDDH and VPP, and the output circuit 9 may include node N9 (output node), a P-type transistor TP91 (first P-type output transistor) with one current terminal connected to VPP, the other current terminal connected to node N9, and its gate connected to node N81, and a P-type transistor TP92 (second P-type output transistor) with one current terminal connected to VDDH, the other current terminal connected to node N9, and its gate connected to node N82. When transistor TP91 is on, node N9 may have VPP, and when transistor TP92 is on, node N9 may have VDDH. In such a configuration, for example, in order to turn off transistor TP92 when transistor TP91 is ON, VDDDC is supplied to the gate of transistor TP92, and in this case, node N9 connected to the other current terminal of transistor TP91 may have VPP. Even in this case, since VDDDC does not fall below VPP, current leakage in transistor TP92 can be suppressed.

[0116] As explained with reference to Figures 5 to 9, the comparison circuit 8 may be configured to perform selective control such that when the difference between VDDH and VPP is greater than a predetermined range, nodes N81 and N82 exclusively turn transistors TP91 and TP92 on or off, and when the difference between VDDH and VPP is within a predetermined range, nodes N81 and N82 turn on both transistors TP91 and TP92. For example, the comparison circuit 8 includes a current mirror circuit 810 including nodes N81 and N82, and a constant current source circuit 820 connected to the current mirror circuit 810, and the size of the transistors included in the current mirror circuit 810 (e.g., channel width W) and the size of the transistors included in the constant current source circuit 820 (e.g., channel width W) may be designed so that the comparison circuit 8 can perform the above-mentioned selective control. By setting a range (simultaneous on region R1) in which both transistors TP91 and TP92 are turned on in this way, it is possible to reliably avoid situations in which both transistors TP91 and TP92 are turned off at the same time. This can contribute to stabilizing the output of VDDDC, etc.

[0117] As explained with reference to Figures 5, 6, and 8, the current mirror circuit 810 of the comparison circuit 8 includes a P-type transistor TP81 (a first P-type mirror transistor) with one current terminal connected to VDDDC and the other current terminal connected to node N81, and a P-type node N82 (a second P-type mirror transistor) with one current terminal connected to VDDDC and the other current terminal connected to the second comparison node. The size of transistor TP81 may be larger than the size of TP82. This allows the voltage at node N81 to be changed so that transistor TP91 turns on only when VPP becomes somewhat larger than VDDH. This reduces the opportunities for VPP to be output as VDDDC, and thereby further enhances the effect of suppressing the increase in power consumption.

[0118] As explained with reference to Figure 9, the power supply selection circuit 2 may include an additional circuit 10 that disables the comparison by the comparison circuit 8 and forcibly sets the comparison result. For example, the additional circuit 10 may include transistors (transistor TPA1, transistor TPA2, transistor TNB1) connected between the current mirror circuit 810 and the constant current source circuit 820 and their power supply voltages (VDDDC or VSS), transistors (transistor TPC1, transistor TND1) connected between node N81 and the power supply voltage (VDDDC or VSS), and transistors (transistor TPC2, transistor TND2) connected between node N82 and the power supply voltage (VDDDC or VSS). For example, by providing such an additional circuit 10, VDDH or VPP can be forcibly output as VDDDC. It can be used as a test mode, etc.

[0119] As explained with reference to Figures 1 and 2, the relative magnitudes of VDDH and VPP may change depending on the environmental value E (e.g., temperature). A power supply voltage level suitable for the operating environment under the environmental value E is provided. For example, the circuit device 100 may include a voltage generation circuit 1 (e.g., a charge pump circuit) that generates VPP.

[0120] As explained with reference to Figure 1, the cell selection circuit 3 may include a row selection circuit 4. The cell 60 may be a memory cell including, for example, a magnetoresistive memory element. In such a circuit device 100, for example, an increase in power consumption can be suppressed.

[0121] The memory device 200, described with reference to Figures 1 to 9, is also one of the disclosed technologies. The memory device 200 comprises the voltage generation circuit 1 described above, a plurality of cells 60 (cell array circuit 6), and a cell selection circuit 3. Even in such a memory device 200, as described above, the increase in power consumption can be suppressed.

[0122] The effects described in this disclosure are merely illustrative and not limited to those disclosed. Other effects may also occur.

[0123] While embodiments of this disclosure have been described above, the technical scope of this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of this disclosure. Furthermore, components from different embodiments and modifications may be combined as appropriate.

[0124] Furthermore, this technology can also take the following configurations: (1) A circuit device comprising: a power supply selection circuit that outputs VDDH or VPP as VDDRDDC according to the relative magnitudes of two types of power supply voltages, VDDH and VPP; and a cell selection circuit that selects any cell from a plurality of cells arranged in a two-dimensional array, wherein the cell selection circuit includes: a drive circuit that drives signal lines connected to the plurality of cells using VPP; and a logic circuit that controls the drive circuit using VDDRDDC, wherein the drive circuit includes a P-type transistor, and the P-type transistor of the drive circuit includes a current terminal connected to VPP, a current terminal connected to the signal line, and a gate to which VDDRDDC from the logic circuit is supplied. (2) The circuit device according to (1), wherein VDDRDDC is the larger of the voltages of VDDH and VPP. (3) The power supply selection circuit includes an input circuit into which the VDDH and VPP are input; a comparison circuit provided downstream of the input circuit for comparing the VDDH and VPP; and an output circuit provided downstream of the comparison circuit for outputting the VDDH or VPP as the VDDRDDC according to the comparison result of the comparison circuit, as described in (1) or (2). (4) The comparison circuit operates using the VDDRDDC, as described in (3). (5) The circuit device according to (3) or (4), wherein the comparison circuit includes a first comparison node and a second comparison node having voltages corresponding to the comparison result of VDDH and VPP, and the output circuit includes an output node, a first P-type output transistor having one current terminal connected to VPP and the other current terminal connected to the output node and its gate connected to the first comparison node, and a second P-type output transistor having one current terminal connected to VDDH and the other current terminal connected to the output node and its gate connected to the second comparison node. (6) The circuit device according to (5), wherein when the first output transistor is on, the output node has VPP, and when the second output transistor is on, the output node has VDDH.(7) The circuit device according to (6), wherein the comparison circuit is configured to perform selection control such that when the difference between VDDH and VPP is greater than a predetermined range, the first comparison node and the second comparison node exclusively turn on or off the first output transistor and the second output transistor, and when the difference between VDDH and VPP is within a predetermined range, the first comparison node and the second comparison node turn on both the first output transistor and the second output transistor. (8) The circuit device according to (7), wherein the comparison circuit includes a current mirror circuit including the first comparison node and the second comparison node, and a constant current source circuit connected to the current mirror circuit, and the sizes of the transistors included in the current mirror circuit and the transistors included in the constant current source circuit are designed so that the comparison circuit can perform the selection control. (9) The circuit device according to (8), wherein the size includes the channel width. (10) The current mirror circuit of the comparison circuit includes: a first P-type mirror transistor with one current terminal connected to the VDDDC and the other current terminal connected to the first comparison node; and a second P-type mirror transistor with one current terminal connected to the VDDDC and the other current terminal connected to the second comparison node, wherein the size of the first mirror transistor is larger than the size of the second mirror transistor, as described in (8) or (9). (11) The circuit device according to any one of (3) to (10), further including an additional circuit that invalidates the comparison by the comparison circuit and forcibly sets the comparison result.(12) The circuit device according to (11), wherein the comparison circuit includes a current mirror circuit including a first comparison node and a second comparison node having voltages corresponding to the comparison result of VDDH and VPP, and a constant current source circuit connected to the current mirror circuit, and the additional circuit includes a transistor connected between the current mirror circuit and the constant current source circuit and their power supply voltages, a transistor connected between the first comparison node and the power supply voltage, and a transistor connected between the second comparison node and the power supply voltage. (13) The circuit device according to any one of (1) to (12), wherein the relative magnitudes of VDDH and VPP change with respect to environmental values. (14) The circuit device according to (13), wherein the environmental values ​​include temperature values. (15) The circuit device according to any one of (1) to (14), further comprising a voltage generation circuit that generates VPP. (16) The circuit device according to (15), wherein the voltage generation circuit includes a charge pump circuit. (17) The circuit device according to any one of (1) to (16), wherein the cell selection circuit includes a row selection circuit. (18) The circuit device according to any one of (1) to (17), wherein the cell is a memory cell. (19) The circuit device according to (18), wherein the memory cell includes a magnetoresistive memory element. (20) A memory device comprising: a power supply selection circuit that outputs VDDH or VPP as VDDRDDC according to the relative magnitudes of two types of power supply voltages, VDDH and VPP; a plurality of cells arranged in a two-dimensional array; and a cell selection circuit that selects any cell from the plurality of cells, wherein the cell selection circuit includes a drive circuit that drives signal lines connected to the plurality of cells using VPP, and a logic circuit that controls the drive circuit using VDDRDDC, the drive circuit includes a P-type transistor, and the P-type transistor of the drive circuit includes a current terminal connected to VPP, a current terminal connected to the signal line, and a gate to which VDDRDDC from the logic circuit is supplied.

[0125] 200 Memory device 100 Circuit device 1 Voltage generation circuit 2 Power supply selection circuit 3 Cell selection circuit 4 Row selection circuit 41 Drive circuit 411 Transistor 412 Transistor 42 Logic circuit 5 Column selection circuit 6 Cell array circuit 60 Cell 7 Input circuit 8 Comparison circuit 810 Current mirror circuit 820 Constant current source circuit 9 Output circuit 10 Additional circuit I71 Current I72 Current I81 Current I82 Current I83 Current I84 Current Ic71 Current Ic72 Current Ic81 Current Ic82 Current Ic83 Current N411 Node N412 Node N71 Node N72 Node N81 Node N82 Node N83 Node N84 Node N9 Node R1 Simultaneous ON region R71 Resistor element R72 Resistor element TN71 Transistor TN72 Transistor TN803 Transistor TN804 Transistor TN81 Transistor TN82 Transistor TN83 Transistor TNB1 Transistor TND1 Transistor TND2 Transistor TP81 Transistor TP82 Transistor TP83 Transistor TP84 Transistor TP91 Transistor TP92 Transistor TPA1 Transistor TPA2 Transistor TPC1 Transistor TPC2 Transistor TPE1 Transistor WL Word line

Claims

1. A circuit device comprising: a power supply selection circuit that outputs VDDH or VPP as VDDRDDC according to the relative magnitudes of two types of power supply voltages, VDDH and VPP; and a cell selection circuit that selects any cell from a plurality of cells arranged in a two-dimensional array, wherein the cell selection circuit includes a drive circuit that drives signal lines connected to the plurality of cells using VPP, and a logic circuit that controls the drive circuit using VDDRDDC, the drive circuit includes a P-type transistor, and the P-type transistor of the drive circuit includes a current terminal connected to VPP, a current terminal connected to the signal line, and a gate to which VDDRDDC from the logic circuit is supplied.

2. The circuit device according to claim 1, wherein VDDDC is the larger of the voltages VDDH and VPP.

3. The circuit device according to claim 1, wherein the power supply selection circuit includes: an input circuit into which the VDDH and VPP are input; a comparison circuit provided downstream of the input circuit for comparing the VDDH and VPP; and an output circuit provided downstream of the comparison circuit for outputting the VDDH or VPP as the VDDRDDC according to the comparison result of the comparison circuit.

4. The circuit device according to claim 3, wherein the comparison circuit operates using the VDDDC.

5. The circuit device according to claim 3, wherein the comparison circuit includes a first comparison node and a second comparison node having voltages corresponding to the comparison result of VDDH and VPP, and the output circuit includes an output node, a first P-type output transistor having one current terminal connected to VPP and the other current terminal connected to the output node and its gate connected to the first comparison node, and a second P-type output transistor having one current terminal connected to VDDH and the other current terminal connected to the output node and its gate connected to the second comparison node.

6. The circuit device according to claim 5, wherein when the first output transistor is ON, the output node has VPP, and when the second output transistor is ON, the output node has VDDH.

7. The circuit device according to claim 6, wherein the comparison circuit is configured to perform selection control such that when the difference between VDDH and VPP is greater than a predetermined range, the first comparison node and the second comparison node exclusively turn on or off the first output transistor and the second output transistor, and when the difference between VDDH and VPP is within a predetermined range, the first comparison node and the second comparison node turn on both the first output transistor and the second output transistor.

8. The circuit device according to claim 7, wherein the comparison circuit includes a current mirror circuit including a first comparison node and a second comparison node, and a constant current source circuit connected to the current mirror circuit, and the sizes of the transistors included in the current mirror circuit and the transistors included in the constant current source circuit are designed so that the comparison circuit can perform the selection control.

9. The circuit device according to claim 8, wherein the size includes the channel width.

10. The current mirror circuit of the comparison circuit includes: a first P-type mirror transistor with one current terminal connected to the VDDDC and the other current terminal connected to the first comparison node; and a second P-type mirror transistor with one current terminal connected to the VDDDC and the other current terminal connected to the second comparison node, wherein the size of the first mirror transistor is larger than the size of the second mirror transistor, the circuit device according to claim 8.

11. The circuit device according to claim 3, further comprising an additional circuit that invalidates the comparison by the comparison circuit and forcibly sets the comparison result.

12. The circuit device according to claim 11, wherein the comparison circuit includes a current mirror circuit including a first comparison node and a second comparison node having voltages corresponding to the comparison results of VDDH and VPP, and a constant current source circuit connected to the current mirror circuit, and the additional circuit includes a transistor connected between the current mirror circuit and the constant current source circuit and their power supply voltages, a transistor connected between the first comparison node and the power supply voltage, and a transistor connected between the second comparison node and the power supply voltage.

13. The relationship between the magnitudes of VDDH and VPP changes depending on environmental values, as described in claim 1.

14. The circuit device according to claim 13, wherein the environmental value includes a temperature value.

15. The circuit device according to claim 1, comprising a voltage generation circuit that generates the VPP.

16. The circuit device according to claim 15, wherein the voltage generation circuit includes a charge pump circuit.

17. The circuit device according to claim 1, wherein the cell selection circuit includes a row selection circuit.

18. The circuit device according to claim 1, wherein the cell is a memory cell.

19. The circuit device according to claim 18, wherein the memory cell includes a magnetoresistive memory element.

20. A memory device comprising: a power supply selection circuit that outputs VDDH or VPP as VDDRDDC according to the relative magnitudes of two types of power supply voltages, VDDH and VPP; a plurality of cells arranged in a two-dimensional array; and a cell selection circuit that selects any cell from the plurality of cells, wherein the cell selection circuit includes a drive circuit that drives signal lines connected to the plurality of cells using VPP, and a logic circuit that controls the drive circuit using VDDRDDC, the drive circuit includes a P-type transistor, and the P-type transistor of the drive circuit includes a current terminal connected to VPP, a current terminal connected to the signal line, and a gate to which VDDRDDC from the logic circuit is supplied.

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