Data processing method and apparatus

Abstract

Provided in the present application is a data processing method. A first apparatus may distribute a first data stream in units of first data blocks to obtain N second data streams, wherein the N second data streams correspond to A physical channels corresponding to the first apparatus, A is an integer greater than or equal to 1, N is greater than or equal to A, and one physical channel corresponds to at least one second data stream. After the first data stream is distributed at the granularity of a first data block to obtain the N second data streams, for any second data stream, the first apparatus can insert an AMG into the second data stream to obtain a third data stream. In this way, energy saving processing at a rate level corresponding to the second data stream can be realized. Since N is greater than or equal to A, energy saving granularity in the present solution can reach the granularity of an individual physical channel, or even be finer than that of the individual physical channel, thereby achieving better energy saving performance.

Description

A data processing method and apparatus

[0001] This application claims priority to Chinese Patent Application No. 2025100377044, filed with the State Intellectual Property Office of China on January 9, 2025, entitled "A Data Processing Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and in particular to a data processing method and apparatus. Background Technology

[0003] In digital communication networks, especially campus networks, traffic exhibits typical tidal characteristics; for example, traffic during late-night hours is generally much lower than the network's bandwidth. Currently, even when there is no traffic on the network, Ethernet interface devices need to remain operational. For instance, the physical layer (PHY), serializer / deserializer (SerDes), and optical modules of Ethernet interface devices remain active, resulting in significant power consumption waste.

[0004] Currently, to reduce the power consumption of Ethernet interface devices, some channels of the Ethernet interface device can be shut down during low traffic periods, and then the shut-down channels can be activated when traffic increases, thereby achieving energy saving. However, even so, the energy saving effect is still limited.

[0005] Therefore, a solution is urgently needed to address the above problems. Summary of the Invention

[0006] This application provides a data processing method that can improve the energy efficiency of Ethernet interface devices.

[0007] Firstly, this application provides a data processing method applied to a first device. The first device can distribute a first data stream in units of first data blocks to obtain N second data streams. The N second data streams correspond to A physical channels of the first device, where A is an integer greater than or equal to 1. Wherein, N is greater than or equal to A, and one physical channel corresponds to at least one second data stream. After distributing the first data stream in units of first data blocks to obtain N second data streams, for any given second data stream, the first device can insert an alignment marker group (AMG) into the second data stream to obtain a third data stream. Therefore, in this application, the AMG insertion operation is performed separately for each second data stream, rather than inserting AMG into the first data stream. This allows for energy-saving processing at the rate level corresponding to the second data stream. Since N is greater than or equal to A, the energy-saving granularity of this solution can reach the granularity of a single physical channel, or even finer than a single physical channel, thereby achieving better energy-saving effects.

[0008] In one possible implementation, the first device can distribute the first data stream to N processing modules at the granularity of first data blocks, and each processing module can receive one second data stream. In other words, the N processing modules correspond one-to-one with the N second data streams. In this scenario, the energy-saving granularity of this solution can reach the granularity of a single processing module. Since N is greater than or equal to A, the energy-saving granularity of this solution can reach the granularity of a single physical channel, or even finer than a single physical channel, thereby achieving better energy-saving effects.

[0009] In one possible implementation, the first device scrambles the second data stream before inserting AMG into it. Correspondingly, inserting AMG into the second data stream can be done by inserting AMG into the scrambled second data stream. This approach ensures DC balance of the physical channel when the processed second data stream after AMG insertion is transmitted over the physical channel.

[0010] In one possible implementation, N equals A, and the N second data streams correspond one-to-one with the A physical channels. Because the N second data streams correspond one-to-one with the A physical channels, in this scenario, the energy-saving granularity of this solution can reach the level of a single physical channel, thereby effectively ensuring the energy-saving effect of the first device.

[0011] In one possible implementation, the A physical channels correspond to B virtual channels, where B is greater than or equal to A, N is equal to B, and the N second data streams correspond one-to-one with the B virtual channels. Because the N second data streams correspond one-to-one with the B virtual channels, in this scenario, the energy-saving granularity of this solution can reach the level of a single virtual channel, thereby effectively ensuring the energy-saving effect of the first device.

[0012] In one possible implementation, N can be greater than A and less than B. In this scenario, one physical channel can correspond to multiple second data streams, and one second data stream can correspond to multiple virtual channels. In this scenario, the energy-saving granularity of this solution lies between that of a single virtual channel and a single physical channel.

[0013] In one possible implementation, a second data stream can correspond to at least one virtual channel, wherein the sum of the rates of the virtual channels corresponding to the second data stream is equal to the rate of the second data stream. In this application, the second data stream with inserted AMG (i.e., the third data stream) is not distributed to all virtual channels in the working state, but is distributed to at least one virtual channel corresponding to the second data stream. Since the number of virtual channels corresponding to the second data stream is fixed, the distribution mechanism of the third data stream is not affected regardless of the number of physical channels in the working state of the first device. Regardless of the number of physical channels in the working state of the first device, after the third data stream is distributed to at least one virtual channel corresponding to the second data stream, the data length between adjacent AMs in each virtual channel of that at least one virtual channel will not change.

[0014] In one possible implementation, after the first device receives the third data stream, it can further distribute the third data stream to M FEC encoders corresponding to the second data stream, whereby the M FEC encoders perform FEC encoding on the data they receive. Further, the FEC codewords encoded by the M FEC encoders are distributed to the virtual channels corresponding to the second data stream. In this application, since the number of virtual channels corresponding to the second data stream is fixed, when distributing the FEC codewords obtained based on the third data stream, the FEC codewords are distributed to the virtual channels corresponding to the second data stream. Therefore, regardless of the number of physical channels in operation of the first device, the distribution mechanism of the second data stream will not be affected. Regardless of the number of physical channels in operation of the first device, after the third data stream is distributed to at least one virtual channel corresponding to the second data stream, the data length between adjacent AMs in each virtual channel will not change.

[0015] In one possible implementation, the first physical channel among the N physical channels corresponds to at least one of the second data streams. After the first device has completed the operation of "distributing the FEC codeword obtained based on the third data stream to the virtual channel corresponding to the second data stream" for each second data stream corresponding to the first physical channel, it can also perform a multiplexing operation on the data carried by the virtual channel corresponding to the first physical channel to map the data carried by the virtual channel corresponding to the first physical channel onto the first physical channel for transmission, thereby realizing the transmission of data to the second device through the first physical channel. The virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to the second data stream.

[0016] In one possible implementation, each first data block comprises 257 bits. That is, the first device can distribute the first data stream in granular units of 257-bit first data blocks to obtain N second data streams. In this scenario, the first data stream can be a data stream obtained by sequentially performing 64B / 66B encoding and 256B / 257B transcoding on a data stream from a MAC or RS.

[0017] In one possible implementation, the first device can insert AMGs into the second data stream according to a rule that the interval between adjacent AMGs is a preset number of second data blocks. In this application, the first device inserts AMGs into the second data stream according to this rule to obtain a third data stream. Regardless of the number of physical channels in the first device's working state, after the third data stream is distributed to at least one virtual channel corresponding to the second data stream, the data length between adjacent AMGs on each virtual channel in that at least one virtual channel will not change.

[0018] In one possible implementation, a second data block can correspond to one FEC codeword. Specifically, after a second data block is FEC encoded, an FEC codeword is obtained. In this case, after the third data stream is distributed to at least one virtual channel corresponding to the second data stream, the data length between adjacent AMs on each virtual channel can correspond to an integer number of FEC codewords.

[0019] In one possible implementation, the first device inserts an alignment flag group (AMG) into the second data stream to obtain a third data stream. Specifically, the second data stream can be distributed at the granularity of the first data block to obtain a fourth and a fifth data stream, and AMGs can be inserted into the fourth and fifth data streams respectively to obtain a third data stream corresponding to the fourth data stream and a third data stream corresponding to the fifth data stream. Using this method, the second data stream can be distributed to obtain the fourth and fifth data streams, and the AMG insertion operation can be performed on the fourth and fifth data streams in parallel, improving the efficiency of inserting AMGs into the second data stream.

[0020] In one possible implementation, in the scenario where the second data stream is distributed to obtain the fourth and fifth data streams, the third data stream is distributed to M FEC encoders corresponding to the second data stream. The M FEC encoders perform FEC encoding on the data they receive. Specifically, this can include: distributing the third data stream corresponding to the fourth data stream to M1 FEC encoders, where the M1 FEC encoders perform FEC encoding on the data they receive; and distributing the third data stream corresponding to the fifth data stream to M2 FEC encoders, where the M2 FEC encoders perform FEC encoding on the data they receive. The M FEC encoders include the M1 encoder and the M2 encoder. That is, in this scenario, the fourth data stream has M1 FEC encoders, and the fifth data stream corresponds to M2 FEC encoders. The M1 and M2 FEC encoders perform FEC encoding in parallel to ensure parallel processing of the fourth and fifth data streams, thus guaranteeing the processing efficiency of the second data stream.

[0021] Secondly, this application provides a data processing method applied to a second device. The second device can remove AMG from a third data stream to obtain a second data stream. Specifically, the second device can remove AMG from each of N third data streams to obtain N second data streams. Further, the second device can merge the N second data streams at a first data block granularity to obtain a first data stream. The second device corresponds to A physical channels, which correspond to the N second data streams, where N is greater than or equal to A, one physical channel corresponds to at least one second data stream, and A is an integer greater than or equal to 1. In this application, the AMG removal operation is performed on the third data streams to obtain the second data streams. This allows for energy-saving processing at the rate level corresponding to the second data stream. Since N is greater than or equal to A, the energy-saving granularity of this solution can reach the granularity of a single physical channel, or even finer than a single physical channel, thereby achieving better energy-saving effects.

[0022] In one possible implementation, removing the alignment flag group (AMG) from the third data stream to obtain the second data stream includes: removing the AMG from the third data stream and descrambling the data stream obtained by removing the AMG to obtain the second data stream.

[0023] In one possible implementation, N equals A, and the N second data streams correspond one-to-one with the A physical channels.

[0024] In one possible implementation, the A physical channels correspond to B virtual channels, where B is greater than or equal to A, N is equal to B, and the N second data streams correspond one-to-one with the B virtual channels.

[0025] In one possible implementation, before removing AMG from the third data stream, the method further includes: sending the data carried on the virtual channel corresponding to the second data stream to M FEC decoders corresponding to the second data stream, and having the M FEC decoders perform FEC decoding on the data they receive to obtain the third data stream.

[0026] In one possible implementation, before sending the data carried on the virtual channel corresponding to the second data stream to the M FEC decoders corresponding to the second data stream, the method further includes: receiving data sent by the first device through the first physical channel, demultiplexing the received data, and sending the demultiplexed data to the virtual channel corresponding to the first physical channel; the virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to the second data stream, the N physical channels include the first physical channel, and the first physical channel corresponds to at least the second data stream.

[0027] In one possible implementation, the first data block comprises 257 bits.

[0028] In one possible implementation, removing the alignment flag group AMG from the third data stream includes: removing the AMG from the third data stream according to a rule that the interval between adjacent AMGs is a preset number of second data blocks.

[0029] In one possible implementation, the second data block corresponds to a forward error correction (FEC) codeword.

[0030] In one possible implementation, data carried on the virtual channel corresponding to the second data stream is sent to M FEC decoders, and the M FEC decoders perform FEC decoding on the data they receive to obtain a third data stream. This includes: sending data carried on at least one first virtual channel corresponding to the second data stream to M1 FEC decoders, and the M1 FEC decoders perform FEC decoding on the data they receive to obtain a third data stream corresponding to a fourth data stream; sending data carried on at least one second virtual channel corresponding to the second data stream to M2 FEC decoders, and the M2 FEC decoders perform FEC decoding on the data they receive to obtain a third data stream corresponding to a fifth data stream; wherein the M FEC decoders include the M1 decoder and the M2 decoder, and the third data stream includes: the third data stream corresponding to the fourth data stream and the third data stream corresponding to the fifth data stream.

[0031] In one possible implementation, removing the alignment flag group AMG from the third data stream to obtain the second data stream includes: removing the AMG from the third data stream corresponding to the fourth data stream and the AMG from the third data stream corresponding to the fifth data stream, respectively, to obtain the fourth data stream and the fifth data stream, wherein the second data stream includes the fourth data stream and the fifth data stream.

[0032] Thirdly, the claimed embodiment provides a data processing apparatus applied to a first device, the apparatus comprising: a sending unit, configured to distribute a first data stream at the granularity of a first data block to obtain N second data streams, the N second data streams corresponding to A physical channels of the first device, wherein N is greater than or equal to A, one physical channel corresponds to at least one second data stream, and A is an integer greater than or equal to 1; and a processing unit, configured to insert an alignment flag group AMG into the second data streams to obtain a third data stream.

[0033] In one possible implementation, the processing unit is configured to scramble the second data stream before inserting AMG into the second data stream; and to insert AMG into the second data stream after scrambling.

[0034] In one possible implementation, N equals A, and the N second data streams correspond one-to-one with the A physical channels.

[0035] In one possible implementation, the A physical channels correspond to B virtual channels, where B is greater than or equal to A, N is equal to B, and the N second data streams correspond one-to-one with the B virtual channels.

[0036] In one possible implementation, the sending unit is further configured to: distribute the third data stream to M FEC encoders corresponding to the second data stream, wherein the M FEC encoders perform FEC encoding on the data they receive; and distribute the FEC codewords encoded by the M FEC encoders to the virtual channel corresponding to the second data stream.

[0037] In one possible implementation, the first physical channel among the N physical channels corresponds to at least the second data stream, and the processing unit is further configured to: perform a multiplexing operation on the data carried by the virtual channel corresponding to the first physical channel to map the data carried by the virtual channel corresponding to the first physical channel onto the first physical channel for transmission, wherein the virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to the second data stream.

[0038] In one possible implementation, the first data block comprises 257 bits.

[0039] In one possible implementation, the processing unit is configured to: insert AMGs into the second data stream according to a rule that the interval between adjacent AMGs is a preset number of second data blocks.

[0040] In one possible implementation, the second data block corresponds to a forward error correction (FEC) codeword.

[0041] In one possible implementation, the processing unit is configured to: distribute the second data stream at the granularity of the first data block to obtain a fourth data stream and a fifth data stream; and insert AMG into the fourth data stream and the fifth data stream respectively to obtain a third data stream corresponding to the fourth data stream and a third data stream corresponding to the fifth data stream.

[0042] In one possible implementation, distributing the third data stream to M FEC encoders corresponding to the second data stream, and having the M FEC encoders perform FEC encoding on the data they receive, includes: distributing the third data stream corresponding to the fourth data stream to M1 FEC encoders, and having the M1 FEC encoders perform FEC encoding on the data they receive; distributing the third data stream corresponding to the fifth data stream to M2 FEC encoders, and having the M2 FEC encoders perform FEC encoding on the data they receive; wherein the M FEC encoders include the M1 encoder and the M2 encoder.

[0043] Fourthly, this application provides a data processing apparatus applied to a second device, the apparatus comprising: a processing unit, the processing unit being configured to: remove alignment flag group (AMG) from a third data stream to obtain a second data stream; merge N second data streams at a first data block granularity to obtain a first data stream, wherein the second device corresponds to A physical channels, the A physical channels correspond to the N second data streams, N is greater than or equal to A, one physical channel corresponds to at least one second data stream, and A is an integer greater than or equal to 1.

[0044] In one possible implementation, the processing unit is configured to: remove AMG from the third data stream and descramble the data stream obtained after removing AMG to obtain the second data stream.

[0045] In one possible implementation, N equals A, and the N second data streams correspond one-to-one with the A physical channels.

[0046] In one possible implementation, the A physical channels correspond to B virtual channels, where B is greater than or equal to A, N is equal to B, and the N second data streams correspond one-to-one with the B virtual channels.

[0047] In one possible implementation, the apparatus further includes: a sending unit, configured to send data carried on the virtual channel corresponding to the second data stream to M FEC decoders corresponding to the second data stream before removing AMG from the third data stream, wherein the M FEC decoders perform FEC decoding on the data they receive to obtain the third data stream.

[0048] In one possible implementation, the apparatus further includes: a receiving unit, configured to receive data transmitted by the first apparatus through a first physical channel before transmitting data carried on a virtual channel corresponding to the second data stream to M FEC decoders corresponding to the second data stream; the processing unit is further configured to demultiplex the received data; the transmitting unit is further configured to transmit the demultiplexed data to a virtual channel corresponding to the first physical channel; the virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to the second data stream, the N physical channels include the first physical channel, and the first physical channel corresponds to at least the second data stream.

[0049] In one possible implementation, the first data block comprises 257 bits.

[0050] In one possible implementation, the processing unit is configured to: remove AMGs from the third data stream according to a rule that the interval between adjacent AMGs is a preset number of second data blocks.

[0051] In one possible implementation, the second data block corresponds to a forward error correction (FEC) codeword.

[0052] In one possible implementation, the sending unit is configured to: send data carried on at least one first virtual channel corresponding to the second data stream to M1 FEC decoders, whereby the M1 FEC decoders perform FEC decoding on the data they receive to obtain a third data stream corresponding to the fourth data stream; send data carried on at least one second virtual channel corresponding to the second data stream to M2 FEC decoders, whereby the M2 FEC decoders perform FEC decoding on the data they receive to obtain a third data stream corresponding to the fifth data stream; wherein the M1 FEC decoders include the M1 decoder and the M2 decoder, and the third data stream includes: the third data stream corresponding to the fourth data stream and the third data stream corresponding to the fifth data stream.

[0053] In one possible implementation, the processing unit is configured to: remove AMG from the third data stream corresponding to the fourth data stream and the third data stream corresponding to the fifth data stream, respectively, to obtain the fourth data stream and the fifth data stream, wherein the second data stream includes the fourth data stream and the fifth data stream.

[0054] Fifthly, this application provides an apparatus comprising a processor, the processor being configured to perform data processing operations as described in the first aspect above and any one of the methods described in the first aspect above; or, the processor being configured to perform data processing operations as described in the second aspect above and any one of the methods described in the second aspect above.

[0055] Optionally, the device further includes a communication interface for performing data transmission and reception operations as described in the first aspect and any one of the first aspects above; or, the communication interface is used to perform data transmission and reception operations as described in the second aspect and any one of the second aspects above.

[0056] In one possible implementation, the device further includes a memory for storing instructions or computer programs, and the processor for executing the instructions or computer programs in the memory to trigger the method described in the first aspect above and any one of the first aspects above; or, the processor is configured to execute the instructions or computer programs in the memory to perform the method described in the second aspect above and any one of the second aspects above.

[0057] In a sixth aspect, this application provides a communication device, the communication device including a processing circuit, the processing circuit being configured to perform data processing operations in the methods described in the first aspect and any one of the first aspects above; or, the processing circuit being configured to perform data processing operations in the methods described in the second aspect and any one of the second aspects above.

[0058] Optionally, the communication device further includes an interface circuit, which is used to perform data transmission and reception operations in the method described in the first aspect and any one of the first aspects above; or, the interface circuit is used to perform data transmission and reception operations in the method described in the second aspect and any one of the second aspects above.

[0059] In one example, the communication device is a network device, a chip, or an optical module, and the chip may be, for example, a PHY chip.

[0060] In a seventh aspect, this application provides a computer-readable storage medium, including instructions or a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any one of the first aspects above, or, when run on a computer, causes the computer to perform the methods described in the second aspect and any one of the second aspects above.

[0061] Eighthly, this application provides a computer program product comprising instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the first aspect and any one of the first aspects above, or causes the computer to perform the methods described in the second aspect and any one of the second aspects above.

[0062] Ninthly, this application provides a communication system, including a first device for performing the method described in the first aspect and any one of the first aspects above, and a second device for performing the method described in the second aspect and any one of the second aspects above.

[0063] In a tenth aspect, embodiments of this application provide a chip system for performing the methods described in the first aspect and any one of the first aspects above, or for performing the methods described in the second aspect and any one of the second aspects above. Attached Figure Description

[0064] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0065] Figure 1a shows a schematic diagram of a transmitting end device and a receiving end device;

[0066] Figure 1b illustrates the data processing method of a 100GE Ethernet interface;

[0067] Figure 1c illustrates the data processing methods for 200GE Ethernet interfaces and 400GE Ethernet interfaces;

[0068] Figure 1d illustrates the data processing method of an 800GE Ethernet interface;

[0069] Figure 1e illustrates the data processing method of the 1.6TE Ethernet interface;

[0070] Figure 1f shows a schematic diagram of a scenario using EEE technology;

[0071] Figure 1g shows a schematic diagram of a channel-level energy-saving scheme;

[0072] Figure 2a illustrates an exemplary application scenario of an embodiment of this application;

[0073] Figure 2b illustrates another exemplary application scenario of this application embodiment;

[0074] Figure 2c illustrates another exemplary application scenario of this application embodiment;

[0075] Figure 2d illustrates another exemplary application scenario of this application embodiment;

[0076] Figure 2e illustrates another exemplary application scenario of this application embodiment;

[0077] Figure 2f illustrates another exemplary application scenario of this application embodiment;

[0078] Figure 2g illustrates another exemplary application scenario of this application embodiment;

[0079] Figure 2h illustrates another exemplary application scenario of this application embodiment;

[0080] Figure 3 is a flowchart illustrating a data processing method provided in an embodiment of this application;

[0081] Figure 4 is a flowchart illustrating another data processing method provided in an embodiment of this application;

[0082] Figure 5 is a flowchart illustrating another data processing method provided in an embodiment of this application;

[0083] Figure 6a shows a schematic diagram of the interaction between two 1.6TE Ethernet interfaces;

[0084] Figure 6b illustrates the data processing framework for the first and second devices;

[0085] Figure 6c shows a schematic diagram of a method executed by a processing module;

[0086] Figure 7a shows a schematic diagram of the interaction between two 400GE Ethernet interfaces;

[0087] Figure 7b illustrates the data processing framework for the first and second devices;

[0088] Figure 7c shows a schematic diagram of a method executed by a processing module;

[0089] Figure 8a shows a schematic diagram of the interaction between two 1.6TE Ethernet interfaces;

[0090] Figure 8b illustrates the data processing framework for the first and second devices;

[0091] Figure 8c shows a schematic diagram of a method executed by a processing module;

[0092] Figure 9 is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0093] Figure 10 is a schematic diagram of another data processing device provided in an embodiment of this application;

[0094] Figure 11 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0095] Figure 12 is a schematic diagram of the structure of a device provided in an embodiment of this application. Detailed Implementation

[0096] This application provides a data processing method and apparatus that can improve the precision of energy-saving control and effectively reduce the power consumption of communication devices.

[0097] The communication device mentioned in the embodiments of this application can be an Ethernet interface or a device including an Ethernet interface. A device including an Ethernet interface can be, for example, a network device including an Ethernet interface, or a component (e.g., a chip or board) on a network device including an Ethernet interface. This application embodiment does not specifically limit the scope of the device.

[0098] The Ethernet interface mentioned in this application embodiment includes an Ethernet media access control (MAC) layer device and a physical layer (PHY) device that support data transmission at a certain rate. Refer to Figure 1a for understanding; Figure 1a shows a schematic diagram of a transmitting end device and a receiving end device. Both the transmitting end device and the receiving end device include an Ethernet interface. The transmitting end device refers to the communication device acting as a data sender, and the receiving end device refers to the communication device acting as a data receiver. Considering that data traffic is bidirectional, the roles of the transmitting end device and the receiving end device shown in Figure 1a can be interchanged in some other scenarios.

[0099] As shown in Figure 1a, both the transmitting and receiving devices include a MAC layer (referred to as MAC in Figure 1a) and a physical layer (referred to as PHY in Figure 1a). The physical layer includes a physical coding sublayer (PCS), a physical medium attachment (PMA) sublayer, and a physical medium dependent (PMD) sublayer. PCS, PMA, and PMD are PHY devices. Additionally, a reconciliation sublayer (RS) may be included between the MAC layer and the physical layer. RS and PCS can communicate via a medium independent interface (MII) channel. The MII channel can be a virtual channel or a logical channel.

[0100] In one example, the aforementioned MAC layer device can be a MAC chip, and the physical layer device can be a PHY chip.

[0101] In another example, the aforementioned MAC layer device and physical layer device can be different functional circuits on the same chip.

[0102] When transmitting data, communication devices can process the data according to the seven-layer model of Open Systems Interconnection (OSI). The first layer of the OSI seven-layer model is the Physical Layer, the second layer is the Data Link Layer, and the Data Link Layer includes the MAC layer. The Physical Layer can include the aforementioned PCS, PMA, and PMD.

[0103] The MAC layer of the transmitting device can generate MAC frames. The MAC layer of the transmitting device sends the MAC frames to the physical layer of the transmitting device. In scenarios where an RS is included between the MAC layer and the physical layer, the RS can convert the serial MAC frames into a parallel data stream and pass the data stream to the PCS through the MII channel.

[0104] The PCS can process the data stream received through the MII channel. In a specific example, the PCS can first encode (e.g., 64B / 66B encoding) and rate match the data stream, and then transcode (e.g., 256B / 257B transcoding) the encoded and rate-matched data stream. Further, a scrambling operation is performed on the transcoded data stream. After scrambling, an AMG insertion is performed on the scrambled data stream to add AMG. After adding AMG, forward error correction (FEC) encoding is performed on the AMG-encoded data stream, and then interleaving and distribution are performed on the FEC-encoded data to distribute the interleaved data to m PCS channels (lanes) connected to the PMA, where "PCS channel" can be abbreviated as "PCSL". In one example, FEC encoding can be performed using Reed-Solomon (RS) codes. "FEC encoding using RS codes" can also be called RS-FEC encoding, and the resulting FEC codeword (CW) can be called an RS-FEC codeword. Of course, the order of the aforementioned transcoding and scrambling operations is not limited to transcoding followed by scrambling; in some scenarios, scrambling can be performed first, followed by transcoding. "Scrambling" can also be called "scrambling code," and in this application, the two can be used interchangeably.

[0105] Currently, for 800GE (800 Gigabit Ethernet) and lower Ethernet interfaces, the bandwidth of a single PCSL is 25 gigabits per second (Gbps). For 100GE Ethernet interfaces, there are 4 PCSLs; for 200GE Ethernet interfaces, there are 8 PCSLs; for 400GE Ethernet interfaces, there are 16 PCSLs; and for 800GE Ethernet interfaces, there are 32 PCSLs. For 1600GE (1.6TE) Ethernet interfaces, the bandwidth of a single PCSL is 100 Gbps, and the number of PCSLs is 16. PCSLs are essentially virtual lanes. After the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard supported FEC on 100GE Ethernet interfaces, it referred to PCSLs as FEC lanes (FECL). For consistency with 200GE / 400GE / 800GE / 1.6TE Ethernet interfaces, this article will uniformly refer to FECL and PCSL as PCSL.

[0106] PMA can perform m:n bit multiplexing on data from PCS (i.e., data from m PCSLs), mapping the data transmitted in the m PCSLs to n physical channels, so that the data carried by these n physical channels can be subsequently sent to the receiving device. The n physical channels can be physical channels connecting the transmitting and receiving devices. The n physical channels can also be internal physical channels of the transmitting device, such as attachment unit interfaces (AUIs). When the n physical channels are internal physical channels of the transmitting device, the transmitting device can further map the data on the internal physical channels of the transmitting device to the physical channels connecting the transmitting and receiving devices to send the data to the receiving device. Wherein:

[0107] The AUI can be, for example, a SerDes. The physical channel connecting the transmitting and receiving devices can be a SerDes, an optical channel, or an electrical channel. An optical channel can be, for example, an optical fiber, and an electrical channel can be, for example, a cable.

[0108] The physical layer of the receiving device also includes PMD, PMA, and PCS. The operations performed by the physical layer of the receiving device are the inverse operations performed by the physical layer of the data sending device, which will not be described in detail here.

[0109] In another example, although not shown in Figure 1a, both the transmitting and receiving devices may include two parts or two PMAs. Assuming the transmitting (or receiving) device includes PMA1 and PMA2, ​​PMA1 connects to the PCS and PMA2, ​​and PMA2 connects to PMA1 and PMD. The PMA and PMD can be interconnected via an AUI, which includes, but is not limited to, SerDes. The PMD and PMA2 connected to it can belong to the PHY module or other modules, such as optical modules or other electrical modules; this is not limited here. The electrical modules mentioned here can be, for example, the retimer shown in Figure 2b or Figure 2d, the redriver shown in Figure 2c, or the electrical module shown in Figure 2h.

[0110] Next, referring to Figures 1b to 1e, we will introduce the data processing methods of existing Ethernet interfaces.

[0111] See Figure 1b, which illustrates the data processing method of a 100GE Ethernet interface.

[0112] As shown in Figure 1b, the operations performed by the transmitting device are as follows:

[0113] For data streams from MAC or RS, 64B / 66B encoding is performed first. Then, the 64B / 66B encoded data stream is scrambled. Next, the scrambled data stream is distributed in 66B granularity, and channel synchronization, reordering, and correction are performed based on the distributed 66B values. After reordering and correction, the reordered and corrected data stream is transcoded to 256B / 257B. The transcoded data stream is then FEC encoded, and the FEC codewords are distributed to four PCSLs at the FEC symbol granularity. Further, the data streams carried on the four PCSLs are multiplexed and mapped to physical channels for transmission.

[0114] The operation performed by the receiving device is the inverse operation of the operation performed by the sending device, which will not be described in detail here.

[0115] in:

[0116] Between the 256B / 257B transcoding and FEC encoding, the transmitting device also needs to insert AMG into the data stream after the 256B / 257B transcoding. Correspondingly, after the FEC codewords are distributed to the four PCSLs, a certain number (integer) of FEC codewords are spaced between two adjacent AMs on each PCSL to facilitate AM locking by the receiving device.

[0117] Refer to Figure 1c, which illustrates the data processing methods for 200GE Ethernet interfaces and 400GE Ethernet interfaces.

[0118] As shown in Figure 1c, the data processing methods of the 200GE Ethernet interface and the 400GE Ethernet interface are basically the same. The main difference between the two is that the number of PCSLs is 8 for the 200GE Ethernet interface and 16 for the 400GE Ethernet interface.

[0119] For the transmitting device, the operations performed are as follows:

[0120] For data streams from MAC or RS, 64B / 66B encoding is performed first. Then, 256B / 257B transcoding is performed on the 64B / 66B encoded data stream, followed by scrambling. The scrambled data stream is then distributed (pre-FEC distribution) to two FEC encoders (FEC-A and FEC-B), where FEC encoding is performed in parallel. Further, the FEC codewords output from FEC-A and FEC-B are interleaved and distributed to distribute the interleaved data to the PCSL. Finally, the data stream carried on the PCSL is multiplexed and mapped onto the physical channel for transmission.

[0121] The operation performed by the receiving device is the inverse operation of the operation performed by the sending device, which will not be described in detail here.

[0122] in:

[0123] Between scrambling and pre-FEC distribution, the transmitting device also needs to insert AMG into the scrambled data stream. Correspondingly, after distributing FEC codewords to PCSLs (e.g., 8 or 16 PCSLs), there is a certain number (integer) of FEC codewords between two adjacent AMs on each PCSL, so that the receiving device can perform AM locking.

[0124] See Figure 1d, which illustrates the data processing method of an 800GE Ethernet interface.

[0125] As shown in Figure 1d, the operations performed by the transmitting device are as follows:

[0126] For data streams from MAC or RS, 64B / 66B encoding is performed first. Then, the data streams after 64B / 66B encoding are distributed with 66B granularity to obtain two data streams, corresponding to flow0 and flow1 in Figure 1d, respectively.

[0127] For flow0 and flow1, the following operations are performed: First, 256B / 257B transcoding is performed, and then scrambling is applied to the data stream after 256B / 257B transcoding. Then, the scrambled data stream is distributed to two FEC encoders: FEC-A and FEC-B for flow0, and FEC-C and FEC-D for flow1. FEC encoding is performed in parallel by these four FEC encoders (FEC-A, FEC-B, FEC-C, and FEC-D). Further, the FEC codewords output from FEC-A and FEC-B are interleaved and distributed to distribute the interleaved data to 32 PCSLs. Similarly, the FEC codewords output from FEC-C and FEC-D are interleaved and distributed to distribute the interleaved data to the 32 PCSLs. The data streams carried on the 32 PCSLs are multiplexed and mapped to physical channels for transmission.

[0128] The operation performed by the receiving device is the inverse operation of the operation performed by the sending device, which will not be described in detail here.

[0129] in:

[0130] Between scrambling and pre-FEC distribution, the transmitting device also needs to insert AMG into the scrambled data stream. Correspondingly, after distributing the FEC codewords to 32 PCSLs, there is a certain number (integer) of FEC codewords between two adjacent AMs on each PCSL, so that the receiving device can perform AM locking.

[0131] See Figure 1e, which illustrates the data processing method of a 1.6TE Ethernet interface.

[0132] As shown in Figure 1e, the operations performed by the transmitting device are as follows:

[0133] For data streams from MAC or RS, 64B / 66B encoding is performed first. Then, 256B / 257B transcoding is performed on the data streams after 64B / 66B encoding. The data streams after 256B / 257B transcoding are then distributed in 257B granularity to obtain two data streams, corresponding to flow0 and flow1 in Figure 1e, respectively.

[0134] For flow0 and flow1, the following operations are performed: First, scrambling is performed. Then, the scrambled data streams are distributed to two FEC encoders: FEC-A and FEC-B for flow0, and FEC-C and FEC-D for flow1. FEC encoding is performed in parallel by these four FEC encoders (FEC-A, FEC-B, FEC-C, and FEC-D). Further, the FEC codewords output from FEC-A, FEC-B, FEC-C, and FEC-D are interleaved and distributed (e.g., interleaving and distribution at a 10-bit granularity) to distribute the interleaved data to 16 PCSLs. The data streams carried on the 32 PCSLs are multiplexed and mapped to physical channels for transmission.

[0135] The operation performed by the receiving device is the inverse operation of the operation performed by the sending device, which will not be described in detail here.

[0136] in:

[0137] Between scrambling and pre-FEC distribution, the transmitting device also needs to insert AMG into the scrambled data stream. Correspondingly, after distributing the FEC codewords to the 16 PCSLs, there is a certain number (integer) of FEC codewords between two adjacent AMs on each PCSL, so that the receiving device can perform AM locking.

[0138] In the scenarios corresponding to Figures 1b to 1e above, when the transmitting device performs AMG insertion, it can do so according to the principle of a certain length of data interval between adjacent AMGs. The data interval between adjacent AMGs is related to the speed of the Ethernet interface.

[0139] In the Ethernet protocol defined by the IEEE standard, when traffic is low, Energy-Efficient Ethernet (EEE) technology is used to put the physical layer into a low-power idle (LPI) mode to save power. Specifically, EEE technology specifies that after a task is completed, some power-consuming components of the PHY layer of the Ethernet interface are turned off to save energy, and the turned-off power-consuming components are woken up before the next task arrives.

[0140] Please refer to Figure 1f, which shows a schematic diagram of a scenario for EEE technology.

[0141] As shown in Figure 1f, "active" indicates that the transmitting device is sending data to the receiving device, and "idle" indicates that the transmitting device is not sending data to the receiving device. In Figure 1f, Ts is the time it takes for the energy-consuming element to enter the sleep state from the working state (i.e., sleep time), Tw is the time it takes for the energy-consuming element to switch from the sleep state to the working state (i.e., wake-up time), and Tq is the energy-saving time that the energy-consuming element can achieve when it is actually in the sleep state.

[0142] It's easy to understand that, given a fixed IDLE time, a larger Ts+Tw results in a smaller actual energy-saving time Tq, and consequently, a worse energy-saving effect. Conversely, a smaller Ts+Tw results in a larger actual energy-saving time Tq, and consequently, a better energy-saving effect. When Ts+Tw = 0, the ideal 0 bits and 0 watts can be achieved, meaning energy consumption is directly proportional to link utilization.

[0143] However, due to limitations in device materials and manufacturing processes, it is difficult to achieve Ts+Tw=0. IEEE 802.3 has standardized a series of Ethernet interfaces. For example, the 802.3ae version released in 2002 standardized the EEE of the 10G BASE-T interface, requiring Ts=2.56 microseconds (us) and Tw=4.88us, that is: Ts+Tw=52.56us.

[0144] With Ts+Tw = 52.56µs, when network utilization is 10%, the energy consumption is equivalent to 88% of that when network utilization is 100%, resulting in poor energy saving. When network utilization is 20%, the energy consumption is equivalent to 81% of that when network utilization is 100%, also resulting in poor energy saving. When network utilization is 30%, the energy consumption is the same as that when network utilization is 100%, with almost no energy saving. The energy consumption mentioned here can include the energy consumption of the transmitting device and / or the energy consumption of the receiving device.

[0145] For a BASE-R optical link with a speed of 100Gbps, when Ts+Tw=52.56us, the energy consumption level of a network utilization rate of 30% is equivalent to that of a network utilization rate of 100%, and there is no energy saving effect; even if the network utilization rate is 2%, the energy consumption level is equivalent to 81% of the energy consumption of a network utilization rate of 100%.

[0146] Moreover, the higher the Ethernet interface speed, the smaller the Ts+Tw value needs to be to achieve energy saving. However, due to limitations in device materials and processes, it is difficult to guarantee a smaller Ts+Tw value.

[0147] In conclusion, current EEE technology does not perform well in terms of energy saving.

[0148] To improve the energy efficiency of communication devices, a channel-level energy-saving technology has been further developed based on EEE technology. Specifically, when traffic is low, some channels can be shut down to save energy. Refer to Figure 1g for an understanding; Figure 1g shows a schematic diagram of a channel-level energy-saving scheme.

[0149] Figure 1g illustrates a schematic diagram of the interaction between two 400GE Ethernet interfaces. (Figure 1g is shown below.)

[0150] The 400GE Ethernet interface 1 and optical module 1 are interconnected via four sets of SerDes. These four sets of SerDes include four SerDes for data transmission from the 400GE Ethernet interface 1 to the optical module 1, and four SerDes for data transmission from the optical module 1 to the 400GE Ethernet interface 1. Similarly, the 400GE Ethernet interface 2 and optical module 2 are also interconnected via four sets of SerDes. These four sets of SerDes include four SerDes for data transmission from the 400GE Ethernet interface 2 to the optical module 2, and four SerDes for data transmission from the optical module 2 to the 400GE Ethernet interface 2. Each SerDes has a speed of 100Gbps.

[0151] Optical module 1 and optical module 2 are interconnected via four sets of optical fibers. These four sets of optical fibers include four fibers for transmitting data from optical module 1 to optical module 2, and four fibers for transmitting data from optical module 2 to optical module 1. Each fiber has a data rate of 100Gbps.

[0152] In one example, when the service traffic between 400GE Ethernet interface 1 and 400GE Ethernet interface 2 is low, three 100Gbps transceiver channels can be shut down to reduce power consumption. Specifically, the three SerDes channels between 400GE Ethernet interface 1 and optical module 1, the three SerDes channels between 400GE Ethernet interface 2 and optical module 2, and the three optical fibers between optical module 1 and optical module 2 can be shut down.

[0153] As previously described, the sum of the PCSL rates is related to the sum of the physical link rates. Therefore, closing some physical channels also requires closing some PCSLs accordingly. For example, closing a 25Gbps physical channel requires closing one PCSL. When the Ethernet interface is running at full speed, the transmitting device performs AMG insertion according to the principle of a certain data interval between adjacent AMGs, ensuring that there is an integer number of FEC codewords between two adjacent AMs on each PCSL. However, when physical channels are closed, if the number of remaining working physical channels is not 2^X (where X is an integer greater than or equal to 0), the data interval between two adjacent AMs on each PCSL will no longer be an integer number of FEC codewords, making it more difficult for the receiving device to perform FEC decoding. Refer to Table 1 for further understanding.

[0154] Table 1

[0155] In Table 1:

[0156] AMG insertion interval refers to "data with a certain length between adjacent AMGs", where the data between adjacent AMGs corresponds to several FEC codewords.

[0157] "Number of PCSLs" indicates the number of working PCSLs, and "Adjacent AM Interval" indicates the data length between two adjacent AMs on each PCSL. The interval between two adjacent AMs corresponds to a number of FEC codewords.

[0158] As shown in the first row of Table 1:

[0159] For a 100GE Ethernet interface, the AMG insertion interval corresponds to 4096 FEC codewords. At full speed, the number of running PCSLs is 4, so the adjacent AM interval corresponds to 4096 / 4 = 1024 FEC codewords. If the speed is reduced, the number of running PCSLs is 3 (e.g., closing a physical channel with a rate of 25Gbps), then the adjacent AM interval corresponds to 4096 / 3 = 1365.333333 FEC codewords.

[0160] As shown in the second row of Table 1:

[0161] For a 200GE Ethernet interface, the AMG insertion interval corresponds to 4096 FEC codewords. At full speed, the number of running PCSLs is 8, so the adjacent AM interval corresponds to 4096 / 8 = 512 FEC codewords. If the speed is reduced, the number of running PCSLs is 6 (e.g., closing a 50Gbps physical channel), then the adjacent AM interval corresponds to 4096 / 6 = 682.6666667 FEC codewords.

[0162] As shown in the third row of Figure 1:

[0163] For a 400GE Ethernet interface, the AMG insertion interval corresponds to 8192 FEC codewords. At full speed, the number of running PCSLs is 16, so the adjacent AM interval corresponds to 8192 / 16 = 512 FEC codewords. If the speed is reduced, the number of running PCSLs is 14 (e.g., closing a 50Gbps physical channel), then the adjacent AM interval corresponds to 8192 / 14 = 585.1428571 FEC codewords.

[0164] As shown in row 4 of Figure 1:

[0165] For an 800GE Ethernet interface, the AMG insertion interval corresponds to 16384 FEC codewords. At full speed, with 32 running PCSLs, the adjacent AM interval corresponds to 16384 / 32 = 512 FEC codewords. If operating at reduced speed, with 10 running PCSLs (e.g., closing eleven 50Gbps physical channels), the adjacent AM interval corresponds to 16384 / 10 = 1638.4 FEC codewords.

[0166] As shown in row 5 of Table 1:

[0167] For a 1.6TE Ethernet interface, the AMG insertion interval corresponds to 32768 FEC codewords. At full speed, with 16 running PCSLs, the adjacent AM interval corresponds to 32768 / 16 = 2048 FEC codewords. If operating at reduced speed, with 12 running PCSLs (e.g., closing a 400Gbps physical channel), the adjacent AM interval corresponds to 32768 / 12 = 2730.666667 FEC codewords.

[0168] To avoid the data length between two adjacent AMs on each PCSL no longer being an integer number of FEC codewords, current channel-level energy-saving solutions can only support a maximum of 2^X (where X is an integer greater than or equal to 0) of working physical channels. For example, in an 800GE Ethernet interface with 8 physical channels at 100Gbps, current channel-level energy-saving solutions only ensure that the data length between two adjacent AMs on the PCSL is an integer number of FEC codewords when the number of working physical channels is 8, 4, 2, or 1. Therefore, current energy-saving solutions can only support reducing the number of working physical channels from 8 to 4, 2, or 1; they cannot support reducing from 8 to 7, 6, 5, or 3 channels, resulting in poor energy-saving performance. For example, if 3 working physical channels are sufficient to handle the current traffic, current energy-saving methods can only reduce the number of working physical channels to 4, leading to unnecessary power consumption and poor energy-saving performance.

[0169] Furthermore, even if the number of working physical channels is 2^X (where X is an integer greater than or equal to 0), the spacing between two adjacent AMs on the PCSL varies depending on the number of working channels. For example, when the 800GE Ethernet interface is running at full speed, the spacing between two adjacent AMs on the PCSL corresponds to 512 FEC codewords. When half of the physical channels corresponding to the 800GE Ethernet interface are turned off (e.g., turning off four 100Gbps physical channels), the spacing between two adjacent AMs on the PCSL corresponds to 1024 FEC codewords. This means that the receiving device needs to perform AM locking based on different spacings when the number of working physical channels is different. In other words, the receiving device needs to support AM locking based on multiple spacings, which places higher demands on the receiving device.

[0170] It should be noted that in this application:

[0171] 1. Physical channels include, but are not limited to, AUI or PMD channels. For example, AUI may include SerDes, and PMD channels may be fiber optic cables or cables (e.g., copper cables).

[0172] 2. A channel rate of 100Gbps, as those skilled in the art will understand, is a common industry term and does not mean the channel rate is exactly 100Gbps. Rather, it means the channel rate is approximately equal to 100Gbps. The precise value of the channel rate could be, for example, 106.25Gbps or 103.125Gbps. Similarly, a channel rate (e.g., PCSL) of 25Gbps does not mean the channel rate is exactly 25Gbps, but rather that the channel rate is approximately equal to 25Gbps. The precise value of the channel rate could be, for example, 106.25 / 4Gbps or 103.125 / 4Gbps. Similarly, a channel rate of 50Gbps does not mean the channel rate is exactly 50Gbps, but rather that the channel rate is approximately equal to 50Gbps. The precise value of the channel rate could be, for example, 106.25 / 2Gbps or 103.125 / 2Gbps.

[0173] 3. The term "n*100GE Ethernet interface" is a common industry term, as those skilled in the art will understand. It does not mean that the Ethernet speed is precisely n*100Gbps, but rather that the Ethernet speed is approximately equal to n*100Gbps. The precise value of the Ethernet speed could be, for example, n*106.25Gbps or n*103.125Gbps. The value of n can be, for example, 1, 2, 4, or 8.

[0174] In view of this, this application provides a data processing method and apparatus that can improve the granularity of energy saving, thereby effectively improving energy-saving performance. Moreover, this solution does not require the receiving device to support AM locking based on multiple intervals, thus placing lower requirements on the receiving device.

[0175] Before introducing the solutions provided in the embodiments of this application, we will first introduce the possible application scenarios of this application.

[0176] Referring to Figures 2a to 2h, which illustrate eight exemplary application scenarios of embodiments of this application.

[0177] As shown in Figure 2a, the transmitting and receiving devices are interconnected via SERDES. Both the transmitting and receiving devices include a MAC layer module, a PCS module, and a PMA module. The interconnection method shown in Figure 2a can be applied to scenarios such as chip interconnection, device interconnection, and board interconnection.

[0178] In the scenario shown in Figure 2a, the PCS of the transmitting device distributes the data to be transmitted on the PCSL. Correspondingly, the PMA of the transmitting device maps the data carried on the PCSL to the serdes between TX1 and RX1 and transmits it to the receiving device.

[0179] Correspondingly, the receiving device receives data through the serdes on TX1 and RX1. The PMA of the receiving device maps the data received through the serdes on TX1 and RX1 onto the PCSL and recovers the MAC frame sent by the transmitting device based on the data on the PCSL.

[0180] The difference between the scenario shown in Figure 2b and that in Figure 2a is that the transmitting device, in addition to the MAC layer module, PCS module, and PMA module, also includes a retimer. This retimer is used to recover the digital signal from the signal received from the PMA module and further perform error correction and signal amplification on the recovered digital signal. As an example, the retimer includes digital signal processing (DSP) and a driver (DRV). The DSP is used to recover the digital signal from the signal received from the PMA module and further perform error correction on the recovered digital signal. The driver is used to amplify the signal obtained after error correction.

[0181] In the scenario shown in Figure 2b, the PCS of the transmitting device distributes the data to be transmitted to be carried on the PCSL. Correspondingly, the PMA of the transmitting device maps the data carried on the PCSL to the serdes between TX1 and RX1 and transmits it to the re-timer. The re-timer maps the data received through the serdes between TX1 and RX1 to the serdes between TX3 and RX3 and transmits it to the receiving device.

[0182] Correspondingly, the receiving device receives data through the serdes on TX3 and RX3. The PMA of the receiving device maps the data received through the serdes on TX3 and RX3 onto the PCSL and recovers the MAC frame sent by the transmitting device based on the data on the PCSL.

[0183] The difference between the scenario shown in Figure 2c and that in Figure 2a is that, in addition to the MAC layer module, PCS module, and PMA module, the transmitting device also includes a secondary driver, which is used to equalize, repair, and amplify the signal received from the PMA module in the analog domain. Furthermore, the transmitting device and the receiving device are interconnected via a cable.

[0184] The scenario shown in Figure 2d differs from that in Figure 2a in that the transmitting device, in addition to the MAC layer module, PCS module, and PMA module, also includes a re-timer. As an example, the re-timer includes a DSP and a driver. Furthermore, the transmitting and receiving devices are interconnected via a cable. For a more detailed description of the re-timer, please refer to the preceding section; it will not be repeated here.

[0185] In the scenarios shown in Figures 2c and 2d, the PCS of the transmitting device distributes the data to be transmitted to be carried on the PCSL. Correspondingly, the PMA of the transmitting device maps the data carried on the PCSL to the serdes between TX1 and RX1 and transmits it to the secondary driver (or re-timer). The secondary driver (or re-timer) maps the data received through the serdes between TX1 and RX1 to the serdes between TX3 and RX3 and transmits it to the receiving device.

[0186] Correspondingly, the receiving device receives data through the serdes on TX3 and RX3. The PMA of the receiving device maps the data received through the serdes on TX3 and RX3 onto the PCSL and recovers the MAC frame sent by the transmitting device based on the data on the PCSL.

[0187] As shown in Figure 2e, the transmitting and receiving devices are interconnected via an optical lane. Both the transmitting and receiving devices include a MAC layer module, a PCS module, a PMA module, and an optical module. In both the transmitting and receiving devices, the PMA module and optical module are interconnected via SERDES. The optical module of the transmitting device includes a DSP, a driver, and a laser diode (LD). The optical module of the receiving device includes a photodiode (PD), a trans-impedance amplifier (TIA), and a DSP. The interconnection method shown in Figure 2e can be applied to short-distance or medium-distance optical interconnects. The DSP in the optical module can, for example, be an optical digital signal processor (oDSP).

[0188] The difference between the scenario shown in Figure 2f and the scenario shown in Figure 2e is that neither the optical module of the transmitting device nor the optical module of the receiving device includes a DSP. The interconnection method shown in Figure 2f can be applied to short-distance optical interconnection.

[0189] The difference between the scenario shown in Figure 2g and the scenario shown in Figure 2e is that the optical module of the receiving device does not include a DSP. The interconnection method shown in Figure 2g can be applied to short-distance optical interconnects.

[0190] In the scenarios shown in Figures 2e to 2g: the PCS of the transmitting device distributes the data to be transmitted to be carried on the PCSL. Correspondingly, the PMA of the transmitting device maps the data carried on the PCSL to the serdes between TX1 and RX1 and transmits it to the optical module. The optical module maps the data received through the serdes between TX1 and RX1 to the optical channel between TX2 and RX2 and transmits it to the receiving device.

[0191] Correspondingly, the receiving device receives data through the optical channels on TX2 and RX2. The optical module of the receiving device maps the data received through the optical channels on TX2 and RX2 onto the SERDES on TX3 and RX3 for transmission. The PMA of the receiving device maps the data received through the SERDES on TX3 and RX3 onto the PCSL and recovers the MAC frame sent by the transmitting device based on the data on the PCSL.

[0192] The difference between the scenario shown in Figure 2h and the scenario shown in Figure 2e is that neither the receiving nor transmitting device includes an optical module, but rather an electrical module. Correspondingly, the transmitting and receiving devices are interconnected via a cable. The electrical module of the transmitting device includes a DSP and a DRV, while the electrical module of the receiving device includes a DSP.

[0193] In the scenario shown in Figure 2h: the PCS of the transmitting device distributes the data to be transmitted to be carried on the PCSL. Correspondingly, the PMA of the transmitting device maps the data carried on the PCSL to the serdes between TX1 and RX1 and transmits it to the electrical module. The electrical module maps the data received through the serdes between TX1 and RX1 to the cable between TX2 and RX2 and transmits it to the receiving device.

[0194] Correspondingly, the receiving device receives data through the cables on TX2 and RX2. The electrical module of the receiving device maps the data received through the cables on TX2 and RX2 onto the serdes on TX3 and RX3 for transmission. The PMA of the receiving device maps the data received through the serdes on TX3 and RX3 onto the PCSL and recovers the MAC frame sent by the transmitting device based on the data on the PCSL.

[0195] Next, referring to Figure 3, the data processing method provided in the embodiments of this application will be described. Figure 3 is a schematic flowchart of a data processing method provided in an embodiment of this application.

[0196] The method shown in Figure 3 can be applied to any of the application scenarios in Figures 2a to 2h. The first device in Figure 3 can correspond to the transmitting device in Figures 2a to 2h. The method shown in Figure 3 includes the following steps S101-S102.

[0197] S101: The first device distributes the first data stream in the form of first data blocks to obtain N second data streams. The N second data streams correspond to A physical channels of the first device. N is greater than or equal to A. One physical channel corresponds to at least one second data stream. A is an integer greater than or equal to 1.

[0198] In this application, the first data stream is a data stream from a MAC or RS, or the first data stream is a data stream obtained by processing a data stream from a MAC or RS.

[0199] In this application, the first data stream may include multiple first data blocks. The first device may distribute the multiple first data blocks included in the first data stream in a round-robin manner to obtain N second data streams. In a specific example, the first device may distribute the first data stream to N processing modules at the granularity of first data blocks, and each processing module may receive one second data stream. In this application, the rate of the second data stream is equal to the rate of the first data stream divided by N, and the rate of the first data stream is the rate of the Ethernet interface corresponding to the first device. Wherein:

[0200] The N processing modules correspond one-to-one with the N second data streams. Therefore, "N second data streams correspond to A physical channels corresponding to the first device" can be understood as "N processing modules correspond to A physical channels corresponding to the first device," and in this application, the two can be used interchangeably. Similarly, "one physical channel corresponds to at least one second data stream" can also be understood as "one physical channel corresponds to at least one processing module." In this application, the two can be used interchangeably. Furthermore, for any processing module, its corresponding rate can be understood as the rate of the second data stream, or in other words, the rate of each processing module is the rate of the first data stream divided by N.

[0201] The processing module in this application can be understood as a module with certain data processing functions, which can be implemented through circuits. That is, one processing module can correspond to one circuit. The processing module may have different names in different scenarios or standards; this application does not impose specific limitations. For example, in one example, the processing module can be called a sub-physical layer (subPHY).

[0202] SubPHY is a concept proposed based on the PHY layer. It involves selecting lower-level resources in the PCS of a standard PHY corresponding to the physical lane (PL) rate to construct resource blocks. When a high-speed PHY supports multiple PLs, the lower-level portion of the PCS of the high-speed PHY consists of these multiple resource blocks. For this high-speed PHY, each resource block is defined as a subPHY, thus dividing the lower-level portion of the PCS of the high-speed PHY into multiple subPHYs. In practical applications, subPHYs can be considered as operational and management entities within the PCS, operating within the PL.

[0203] In this application, each first data block comprises multiple bits. In one example, each first data block comprises 257 bits. That is, the first device can distribute the first data stream to N processing modules in granular units of 257-bit first data blocks. In this scenario, the first data stream can be a data stream obtained by sequentially performing 64B / 66B encoding and 256B / 257B transcoding on a data stream from a MAC or RS. In another example, each first data block comprises 66 bits. That is, the first device can distribute the first data stream to N processing modules in granular units of 66-bit first data blocks. In this scenario, the first data stream can be a data stream obtained by performing 64B / 66B encoding on a data stream from a MAC or RS.

[0204] In this application, the A physical channels corresponding to the first device can be the physical channels in which the first device is currently in operation.

[0205] The physical channel corresponding to the first device can be either the physical channel connecting the first device and the second device, or it can be a physical channel within the first device. This application does not specifically limit this. In one example, when the speed of the physical channel connecting the first device and the second device is different from that of the physical channel within the first device, the A physical channels mentioned here can be the physical channel with the higher speed between the physical channel connecting the first device and the second device and the physical channel within the first device.

[0206] For example, if the first device corresponds to the transmitting device shown in Figure 2a, then the A physical channels can be A serdes between TX1 and RX1.

[0207] For example, if the first device corresponds to the transmitting device shown in Figure 2b, then the A physical channels can be A serdes between TX1 and RX1, or the A physical channels can be A serdes between TX3 and RX3. When the rate of a single serdes channel between TX1 and RX1 is higher than the rate of a single serdes channel between TX3 and RX3, the A physical channels can be A serdes between TX1 and RX1; when the rate of a single serdes channel between TX1 and RX1 is lower than the rate of a single serdes channel between TX3 and RX3, the A physical channels can be A serdes between TX3 and RX3.

[0208] In this application, "serdes channel" can be understood as a channel connected by sending serdes and receiving serdes. For ease of description, in the accompanying drawings and text description, "serdes channel" can also be simply referred to as "serdes".

[0209] In one example, the first device includes multiple processing modules, of which N processing modules are currently in operation, and these N processing modules correspond to A physical channels of the first device that are currently in operation. Wherein, N is greater than or equal to A.

[0210] In one example, N equals A. In other words, the N processing modules correspond to the N physical channels of the first device. In this case, the N processing modules correspond one-to-one with the A physical channels, with one processing module corresponding to one physical channel. That is, the N second data streams correspond one-to-one with the A physical channels. Each of the N processing modules processes the data to be transmitted through its corresponding physical channel. In this scenario, the rate of each processing module can be considered the rate of a single physical channel. In this scenario, assuming one physical channel corresponds to C virtual channels, each processing module also corresponds to C virtual channels. Data transmitted through a physical channel can be carried through the C virtual channels corresponding to that physical channel. The virtual channel corresponding to a processing module can also be understood as the virtual channel corresponding to the second data stream received by that processing module.

[0211] In another example, N is greater than A. Specifically, A physical channels correspond to B virtual channels, where B is greater than or equal to A, and therefore N can be equal to B. In this scenario, the N processing modules correspond one-to-one with the B virtual channels, with one processing module corresponding to one virtual channel. That is, the N second data streams correspond one-to-one with the B virtual channels. For any of the N processing modules, it is used to process the data that will be carried through its corresponding virtual channel. In this scenario, the rate corresponding to each processing module can be considered as the rate corresponding to a single virtual channel. The virtual channel mentioned here can be a PCSL. The one-to-one correspondence between the N processing modules and the B virtual channels means that the N second data streams correspond one-to-one with the B virtual channels.

[0212] In this context, A physical channels correspond to B virtual channels. This can be understood as the sum of the speeds of the A physical channels being equal to the sum of the speeds of the B virtual channels. For example, if the first device corresponds to a 100GE Ethernet interface, a 200GE Ethernet interface, a 400GE Ethernet interface, or an 800GE Ethernet interface, then the speed of the virtual channel is 25Gbps. Assuming the speed of a single physical channel is 50Gbps, A equals 2, and B equals 4. Similarly, one physical channel corresponds to C virtual channels, meaning the speed of one physical channel is equal to the sum of the speeds of the C virtual channels.

[0213] In another example, N can be greater than A and less than B. In this scenario, one physical channel can correspond to multiple processing modules, and one processing module can correspond to multiple virtual channels. In this scenario, each processing module is used to process the data that will be carried through its corresponding virtual channel. In this scenario, the rate corresponding to each processing module is the sum of the rates of the virtual channels corresponding to that processing module. For example:

[0214] The first device corresponds to a 100GE Ethernet interface, a 200GE Ethernet interface, a 400GE Ethernet interface, or an 800GE Ethernet interface. The virtual channel rate is 25Gbps. Assuming the rate of a single physical channel is 100Gbps, A equals 2, then B equals 8. In this scenario, N can equal 4, that is: 2 physical channels correspond to 4 processing modules, and one processing module corresponds to 2 virtual channels. In this scenario, the rate corresponding to each processing module can be 50Gbps (i.e., the sum of the rates of the 2 virtual channels).

[0215] S102: The first device inserts AMG into the second data stream to obtain a third data stream.

[0216] In this application, after obtaining N second data streams, the N second data streams can be processed separately. The operation performed by the first device on each second data stream is the same. Next, the processing of a certain second data stream (for example, the second data stream corresponding to the first processing module among the N processing modules) will be used as an example for explanation.

[0217] In this application, the A physical channels corresponding to the first device include a first physical channel. In one example, the first physical channel corresponds to at least one second data stream, and the first physical channel also corresponds to at least one first processing module.

[0218] The second data stream is a portion of the first data stream that has been distributed to the first processing module. As described in S101, the first data stream is distributed at the granularity of first data blocks. Therefore, the second data stream may include multiple first data blocks.

[0219] In this application, "data block" is defined based on the attribute of data length, without limiting the content of the data block. Multiple first data blocks refer to multiple data blocks of the same length (e.g., all 257 bits or 66 bits). The contents of the multiple first data blocks are not limited in this application embodiment, and the contents of any two first data blocks can be the same or different.

[0220] In this application, an AMG can be inserted into a second data stream to obtain a third data stream. The operation of inserting the AMG into the second data stream can be performed by the first processing module. In other words, in this application, the object of AMG insertion is the data stream obtained after performing a distribution operation on the first data stream; or, in other words, the object of AMG insertion is the second data stream received by the first processing module, rather than inserting the AMG into the complete data stream from the MAC or RS as described in Figures 1b to 1e.

[0221] In one example, considering that the number of 0s and 1s in the second data stream may be unbalanced, and that an unbalanced data stream transmitting over a physical channel can affect the direct-current (DC) balance of the physical channel, in one example, before inserting AMG into the second data stream, the second data stream can be scrambled, for example, using a scrambler. Accordingly, in a specific implementation, S102 can insert AMG into the second data stream after scrambling. The scrambling operation of the second data stream mentioned here can also be performed by the first processing module.

[0222] DC equalization can be understood as a state where the number of 1s and 0s in the data stream transmitted on a physical channel is basically the same, or as a technique to ensure that the number of 1s and 0s in the data stream transmitted on a physical channel is basically the same. DC equalization affecting the physical link refers to making the DC value corresponding to the physical channel non-zero, thereby causing the circuitry related to the physical channel to become unusable or of poor quality. The circuitry related to the physical channel mentioned here can be, for example, the circuitry of the transmitting component and / or the receiving component. The transmitting component mentioned here can be, for example, the transmitting SerDes, and the receiving component mentioned here can be, for example, the receiving SerDes.

[0223] As described above, the first data block may include 257 bits or 66 bits. If the first data block includes 257 bits, the first device can scramble the second data stream and then insert AMG into the scrambled second data stream to obtain a third data stream. If the first data block includes 66 bits, the first device can first perform 256B / 257B transcoding on the second data stream, then scramble the data stream after 256B / 257B transcoding to obtain a scrambled second data stream, and further insert AMG into the scrambled second data stream to obtain a third data stream.

[0224] In one example, in a specific implementation of S102, the second data stream (e.g., the second data stream after scrambling) can be treated as a whole, and AMGs can be inserted into the second data stream. In this case, in a specific implementation of S102, AMGs can be inserted into the second data stream according to a predetermined number of second data blocks between adjacent AMGs. In this application, when the first data block includes 257 bits, the length of each AMG inserted into the second data stream is P times the length of the first data block.

[0225] In one example, the second data block may include a certain number of bits. As a specific example, one second data block can correspond to one FEC codeword. Specifically, after performing FEC encoding on a second data block, an FEC codeword can be obtained. In this scenario, assuming that the FEC encoding uses RS(544, 514) encoding, the second data block may include 5140 bits. After performing RS(544, 514) encoding on the second data block, an RS-FEC codeword can be obtained. An RS-FEC codeword includes 544 RS-FEC symbols, and an RS-FEC symbol includes 10 bits. That is, a 5140-bit second data block, after being encoded by RS(544, 514), yields a 5440-bit RS-FEC codeword. Of course, the length of the second data block will also be different depending on the method of FEC encoding performed by the first device. For example, if the first device uses RS(255, 239) for FEC encoding, the second data block can include 239*8 = 1912 bits. The RS-FEC codeword obtained after encoding the second data block via RS(255, 239) includes 255 RS-FEC symbols. One RS-FEC symbol includes 8 bits. That is, after encoding the 1912-bit second data block via RS(255, 239), a 255*8 = 2040-bit RS-FEC codeword is obtained.

[0226] Regarding the aforementioned P and preset quantity, they are related to the Ethernet interface corresponding to the first device and the rate of the second data stream, which can be understood in conjunction with Table 2 below.

[0227] Table 2

[0228] As shown in Table 2:

[0229] If the rate corresponding to the second data stream is 50Gbps, then the value of P is 1, and the preset quantity is 1024.

[0230] If the rate corresponding to the second data stream is 100Gbps, then the value of P is 2, and the preset quantity is 2048.

[0231] If the rate of the second data stream is 200Gbps and the Ethernet interface of the first device is a 200GE Ethernet interface, a 400GE Ethernet interface, or an 800GE Ethernet interface, then the value of P is 4, and the preset quantity is 4096.

[0232] If the rate of the second data stream is 200Gbps and the Ethernet interface of the first device is a 1600GE Ethernet interface, then the value of P is 1 and the preset quantity is 4096.

[0233] If the rate of the second data stream is 400Gbps and the Ethernet interface of the first device is a 400GE Ethernet interface or an 800GE Ethernet interface, then the value of P is 8 and the preset quantity is 8192.

[0234] If the rate of the second data stream is 400Gbps and the Ethernet interface of the first device is a 1600GE Ethernet interface, then the value of P is 2 and the preset quantity is 8192.

[0235] In another example, S102 can also be implemented by splitting the second data stream and performing AMG insertion on each of the split data streams. As a specific example, when both the Ethernet interface rate of the first device and the rate of the second data stream are high, the second data stream can be split, and AMG insertion can be performed on each of the split data streams. For instance, when the Ethernet interface corresponding to the first device is a 1.6T Ethernet interface, and the rate of the second data stream is 400Gbps, the second data stream can be split, and AMG insertion can be performed on each of the split data streams.

[0236] In this case, S102 may include the following steps A1-A2 in its specific implementation.

[0237] A1: Distribute the second data stream at the granularity of the first data block to obtain the fourth and fifth data streams.

[0238] In one example, the second data stream mentioned here could be the data stream that has not undergone scrambling, that is, the second data stream received by the first processing module.

[0239] Regarding the first data block, please refer to the relevant description above; it will not be repeated here.

[0240] In one example, the second data stream can be distributed in a polling manner at the granularity of the first data block, thus obtaining the fourth and fifth data streams.

[0241] In one example, the rates of the fourth and fifth data streams are the same. For instance, when the Ethernet interface corresponding to the first device is a 1.6T Ethernet interface and the rate of the second data stream is 400Gbps, the rates of the fourth and fifth data streams can both be 200Gbps.

[0242] A2: Insert AMG into the fourth data stream and the fifth data stream respectively to obtain a third data stream corresponding to the fourth data stream and a third data stream corresponding to the fifth data stream.

[0243] In one example, before inserting AMG into the fourth data stream, the fourth data stream can be scrambled, and AMG can be inserted into the scrambled fourth data stream accordingly. Similarly, before inserting AMG into the fifth data stream, the fifth data stream can be scrambled, and AMG can be inserted into the scrambled fifth data stream accordingly.

[0244] As described above, the first data block may include 257 bits or 66 bits.

[0245] If the first data block comprises 257 bits, the first device can scramble the fourth data stream and then insert AMG into the scrambled fourth data stream to obtain the third data stream corresponding to the fourth data stream. If the first data block comprises 66 bits, the first device can first perform 256B / 257B transcoding on the fourth data stream, then scramble the data stream after 256B / 257B transcoding to obtain the scrambled fourth data stream, and further insert AMG into the scrambled fourth data stream to obtain the third data stream corresponding to the fourth data stream.

[0246] Similarly, if the first data block includes 257 bits, the first device can scramble the fifth data stream and then insert AMG into the scrambled fifth data stream to obtain the third data stream corresponding to the fifth data stream. If the first data block includes 66 bits, the first device can first perform 256B / 257B transcoding on the fifth data stream, then scramble the data stream after 256B / 257B transcoding to obtain the scrambled fifth data stream, and further insert AMG into the scrambled fifth data stream to obtain the third data stream corresponding to the fifth data stream.

[0247] The method for inserting AMGs into the fourth data stream can also be to insert them according to the rule of spacing adjacent AMGs by a certain number (e.g., a first number) of second data blocks. Similarly, the method for inserting AMGs into the fifth data stream can also be to insert them according to the rule of spacing adjacent AMGs by a certain number (e.g., a first number) of second data blocks. In this application, when the first data block includes 257 bits, the length of each AMG inserted into the fourth data stream (or the fifth data stream) is P1 times the length of the first data block.

[0248] Regarding P1 and the first quantity, they are related to the rate of the Ethernet interface corresponding to the first device and the rate of the fourth data stream, which can be understood in conjunction with Table 3 below.

[0249] Table 3

[0250] For an explanation of Table 3, please refer to the previous section explaining Table 2; the explanation will not be repeated here.

[0251] As shown in Table 3, when the Ethernet interface corresponding to the first device is a 1.6T Ethernet interface and the rate of the second data stream is 400Gbps, the first processing module can split the second data stream into two data streams with a rate of 200Gbps (i.e., the third data stream and the fourth data stream), and process the third data stream and the fourth data stream in parallel, thereby improving the processing efficiency of the second data stream. In this scenario, the first device can insert AMGs into the fourth data stream and the fifth data stream according to the rule of 4096 second data blocks between adjacent AMGs, and the length of the inserted AMG is one first data block.

[0252] In one example, after obtaining the third data stream, the first device can also execute S103-S105 as shown in FIG4, thereby sending data to the second device. S103-S104 can be executed by the first processing module. FIG4 is a flowchart illustrating another data processing method provided in an embodiment of this application.

[0253] S103: The first device distributes the third data stream to M FEC encoders corresponding to the second data stream, and the M FEC encoders perform FEC encoding on the data they receive.

[0254] In one example, if the third data stream is obtained by performing an AMG insertion operation on the second data stream as a whole, a round-robin distribution method can be used to distribute the third data stream to the M FEC encoders. For example, the third data stream can be distributed to the M FEC encoders at a granularity of RS-FEC symbols (e.g., 10 bits). In this case:

[0255] The number of M can be related to the rate corresponding to the second data stream. For details, please refer to Table 4 below.

[0256] Table 4

[0257] As shown in Table 4, when the rate of the second data stream is 50Gbps, then M is 1;

[0258] If the rate of the second data stream is 100Gbps or 200Gbps, then M is 2;

[0259] If the rate of the second data stream is 400Gbps, then M is 4.

[0260] In another example, if the third data stream is obtained by processing the fourth and fifth data streams distributed from the second data stream, then the third data stream may include the third data stream corresponding to the aforementioned fourth data stream and the third data stream corresponding to the aforementioned fifth data stream. In this case, in a specific implementation of S103, the third data stream corresponding to the fourth data stream can be distributed to M1 FEC encoders, and the M1 FEC encoders can perform FEC encoding on the data they receive. Similarly, the third data stream corresponding to the fifth data stream can be distributed to M2 FEC encoders, and the M2 FEC encoders can perform FEC encoding on the data they receive. In this case, the M FEC encoders include the M1 encoder and the M2 encoder, i.e., M equals M1 + M2. As described above, the rate of the fourth data stream and the rate of the fifth data stream are the same. In this case, the values ​​of M1 and M2 are also the same. The value of M1 can be determined based on the rate of the fourth data stream. For a concrete example, refer to Table 5.

[0261] Table 5

[0262] As shown in Table 5, if the rate corresponding to the fourth data stream is 50Gbps, then M1 is 1;

[0263] If the rate corresponding to the fourth data stream is 100Gbps or 200Gbps, then M1 is 2;

[0264] If the rate corresponding to the fourth data stream is 400Gbps, then M1 is 4.

[0265] In this application, any FEC encoder can perform FEC encoding on the data stream it receives, for example, RS(544, 514) encoding.

[0266] S104: The first device distributes the FEC codewords encoded by the M FEC encoders to the virtual channel corresponding to the second data stream.

[0267] The virtual channel corresponding to the second data stream is also the virtual channel corresponding to the first processing module, and the two can be used alternately.

[0268] After each of the M FEC encoders performs FEC encoding on the data it receives, the FEC codewords encoded by the M FEC encoders can be distributed to the virtual channel corresponding to the first processing module. For example, the FEC codewords encoded by the M encoders can be interleaved (or multiplexed) at the granularity of RS-FEC symbols, and then distributed to the virtual channel corresponding to the second data stream at the granularity of RS-FEC symbols. The virtual channel corresponding to the second data stream can also be understood as the virtual channel corresponding to the first processing module.

[0269] S105: The first device performs a multiplexing operation on the data carried by the virtual channel corresponding to the first physical channel, so as to map the data carried by the virtual channel corresponding to the first physical channel onto the first physical channel for transmission, wherein the virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to the second data stream.

[0270] As described above, the first physical channel can correspond to C virtual channels, where C is greater than or equal to the virtual channel corresponding to the first processing module. Specifically, if the N processing modules correspond one-to-one with the A physical channels, then the first processing module also corresponds to C virtual channels. In this scenario, the C virtual channels corresponding to the first physical channel are the C virtual channels corresponding to the first processing module. If the first physical channel corresponds to multiple processing modules, then the virtual channels corresponding to the first physical channel include not only the virtual channels corresponding to the first processing module but also the virtual channels corresponding to the other processing modules corresponding to the first physical channel.

[0271] In this application, after executing S102-S104 for each second data stream corresponding to the first physical channel, a multiplexing operation can be performed on the data carried by the virtual channel corresponding to the first physical channel to map the data carried by the virtual channel corresponding to the first physical channel onto the first physical channel for transmission. Specifically, a multiplexing operation can be performed on the data carried on all virtual channels corresponding to the first physical channel to map the data carried by the virtual channels corresponding to the first physical channel onto the first physical channel for transmission.

[0272] In one example, assuming that each of the C virtual channels corresponding to the first physical channel carries data, the data carried on the C virtual channels can be multiplexed using C:1 to map the data carried on the C virtual channels to the first physical channel for transmission.

[0273] In another example, in a scenario where the first physical channel corresponds to multiple processing modules, assuming the first physical module corresponds to two processing modules, one of which is in a working state and the other is in a non-working state, then among the C virtual channels corresponding to the first physical channel, only C / 2 virtual channels carry data. Therefore, the data carried on the C / 2 virtual channels can be multiplexed by C / 2:1 to map the data carried on the C / 2 virtual channels to the first physical channel for transmission.

[0274] This application also provides a data processing method applied to a second device. Referring to Figure 5, this figure is a flowchart illustrating another data processing method provided in this application.

[0275] The method shown in Figure 5 can be applied to any of the application scenarios in Figures 2a to 2h. The second device in Figure 5 corresponds to the receiving device in Figures 2a to 2h. It should be noted that the operation performed by the second device is the inverse operation of the operation performed by the first device.

[0276] The method shown in Figure 5 includes the following steps S201-S202.

[0277] S201: The second device removes AMG from the third data stream to obtain the second data stream.

[0278] S201 is the inverse operation of S102.

[0279] As described above, S102 can be implemented in two ways; therefore, S201 can also be implemented in two ways.

[0280] In one example, if S102 is specifically implemented as inserting AMGs into the second data stream according to the rule of a preset number of second data blocks between adjacent AMGs, then S201 can be specifically implemented as removing AMGs from the third data stream according to the rule of a preset number of second data blocks between adjacent AMGs.

[0281] For information on the preset quantity, the second data block, and the length of the removed AMG, please refer to the relevant descriptions of the methods in Figures 3 and 4 above; these will not be repeated here.

[0282] In another example, if S102 is implemented through the aforementioned steps A1-A2, then S201 can be implemented as follows: Remove the AMGs from the third data stream corresponding to the fourth data stream and the AMGs from the third data stream corresponding to the fifth data stream, respectively, to obtain the fourth data stream and the fifth data stream. The second data stream includes the fourth data stream and the fifth data stream. As a specific example, the AMGs in the fourth data stream and the fifth data stream can be removed according to the rule of a first number of second data blocks between adjacent AMGs. The length of the removed AMG is P1 times the length of the first data block. Regarding the first number and P1, please refer to the relevant description above; it will not be repeated here.

[0283] As described above regarding the steps performed by the first device, before inserting AMG into the second data stream, the first device can also scramble the second data stream. In this scenario, after removing AMG from the third data stream, the second device can descramble the data stream obtained after removing AMG to obtain the second data stream. Accordingly, S202 can be executed for the descrambled second data stream.

[0284] S202: The second device merges N second data streams at the first data block granularity to obtain a first data stream, wherein the second device corresponds to A physical channels, the A physical channels correspond to the N second data streams, N is greater than or equal to A, one physical channel corresponds to at least one second data stream, and A is an integer greater than or equal to 1.

[0285] In one example, the second device also includes N processing modules, which correspond one-to-one with the N second data streams mentioned in S202.

[0286] Regarding the N processing modules of the second device, the A physical channels corresponding to the second device, and the correspondence between the A physical channels of the second device and the N processing modules of the second device, please refer to the previous description of the N processing modules of the first device, the A physical channels of the first device, and the correspondence between the A physical channels of the first device and the N processing modules of the first device. It will not be repeated here.

[0287] S202 is the inverse operation of S101, which will not be explained in detail here.

[0288] In one example, the second device may acquire a third data stream before executing S201. Acquiring the third data stream is the reverse operation of the aforementioned S103-S104.

[0289] In one example, the "acquiring the third data stream" can be implemented by sending the data carried on the virtual channel corresponding to the second data stream to M FEC decoders corresponding to the second data stream. The M FEC decoders can then perform FEC decoding on the data they receive to obtain the third data stream.

[0290] In one example, before sending the data carried on the virtual channel corresponding to the second data stream to the M FEC decoders corresponding to the second data stream, the second device may also perform step B1:

[0291] The system receives data transmitted by the first device through a first physical channel, demultiplexes the received data, and sends the demultiplexed data to a virtual channel corresponding to the first physical channel. The virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to a second data stream, or in other words, the virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to the first processing module. The N physical channels include the first physical channel, and the first physical channel corresponds at least to the first processing module. Step B1 is the reverse operation of step S105, and will not be described in detail here.

[0292] In another example, if S102 is implemented through the aforementioned steps A1-A2, then "obtaining the third data stream" can include the following steps C1-C2 in its implementation:

[0293] Step C1: Send the data carried on at least one first virtual channel corresponding to the second data stream to M1 FEC decoders, and have the M1 FEC decoders perform FEC decoding on the data they receive to obtain the third data stream corresponding to the fourth data stream.

[0294] Step C2: Send the data carried on at least one second virtual channel corresponding to the second data stream to M2 FEC decoders, and have the M2 FEC decoders perform FEC decoding on the data they receive to obtain the third data stream corresponding to the fifth data stream; wherein, the M FEC decoders include the M1 decoder and the M2 decoders, and the third data stream includes: the third data stream corresponding to the fourth data stream and the third data stream corresponding to the fifth data stream.

[0295] Steps C1 and C2 are the inverse operations performed by the first device on the third data stream, and will not be repeated here.

[0296] As described above, using the scheme of this application embodiment, for the first device as the transmitting end, it performs AMG insertion operation on the second data stream (i.e., the data stream received by each processing module) obtained by distributing the first data stream, rather than inserting AMG into the first data stream. Correspondingly, for the second device as the receiving end, it performs AMG removal operation on the third data stream corresponding to each processing module. Because AMG is inserted on the second data stream received by the processing module, any number of processing modules can be shut down during speed reduction and energy saving. For other processing modules that are in operation, since the number of virtual channels corresponding to each processing module is fixed, the data processed by each processing module is only distributed to the virtual channel corresponding to itself. Therefore, when inserting AMG on a processing module, even if some processing modules are shut down, the data length between two adjacent AMs on the PCSL will not correspond to a non-integer multiple of FEC codewords. Accordingly, when the receiving device performs AM locking, it can perform AM locking at a fixed interval, which reduces the requirements on the receiving device. In other words, this solution can achieve energy-saving processing at the rate level corresponding to the processing module. For example, it can support shutting down any number (less than N) of processing modules, since N is greater than or equal to A. Therefore, when N equals A, the energy-saving granularity of this solution can reach the granularity of a single physical channel. When N is greater than A, the energy-saving granularity of this solution can be finer than that of a single physical channel, thus achieving better energy-saving effects.

[0297] The solutions provided by the embodiments of this application have been described above. Next, the solutions provided by the embodiments of this application will be described in conjunction with specific scenarios.

[0298] Referring to Figure 6a, this figure is a schematic diagram of an exemplary application scenario provided by an embodiment of this application.

[0299] Figure 6a shows a schematic diagram of the interaction between two 1.6TE Ethernet interfaces. (Figure 6a:)

[0300] The 1.6TE Ethernet interface 1 and optical module 1 are interconnected via eight sets of SerDes. These eight sets of SerDes include eight SerDes for transmitting data from the 1.6TE Ethernet interface 1 to the optical module 1, and eight SerDes for transmitting data from the optical module 1 to the 1.6TE Ethernet interface 1. Similarly, the 1.6TE Ethernet interface 2 and optical module 2 are also interconnected via eight sets of SerDes. These eight sets of SerDes include eight SerDes for transmitting data from the 1.6TE Ethernet interface 2 to the optical module 2, and eight SerDes for transmitting data from the optical module 2 to the 1.6TE Ethernet interface 2. Each SerDes has a speed of 100Gbps.

[0301] Optical module 1 and optical module 2 are interconnected via eight sets of optical fibers. These four sets of optical fibers include: eight optical fibers from optical module 1 to optical module 2 for transmitting data, and eight optical fibers from optical module 2 to optical module 1 for transmitting data. Each optical fiber has a speed of 100 Gbps. In one example, the optical fiber between optical module 1 and optical module 2 can be multimode fiber (MMF).

[0302] In this scenario, the data processing framework for the first and second devices can be as shown in Figure 6b. Figure 6b illustrates the data processing framework for the first and second devices.

[0303] As shown in Figure 6b, the first device first performs 64B / 66B encoding and 256B / 257B transcoding sequentially on the data stream (rate of 1600Gbps, abbreviated as 1.6T) from the MAC or RS to obtain the first data stream. Then, the first data stream is distributed to eight processing modules at a granularity of 257 bits. These eight processing modules correspond one-to-one with the eight physical channels through which optical module 1 transmits data to optical module 2. Each processing module processes the second data stream it receives to distribute the processed data stream to its corresponding PCSL. One processing module corresponds to two PCSLs, and each PCSL has a rate of 100Gbps. Furthermore, for a given processing module, the data carried on its corresponding PCSL is multiplexed 2:1 to map the data carried on the PCSL corresponding to that processing module to the physical channel corresponding to that processing module for transmission.

[0304] The second device also includes eight processing modules, which correspond one-to-one with the eight physical channels through which optical module 1 sends data to optical module 2. The operations performed by the second device are the inverse operations of the operations performed by the first device, and will not be repeated here.

[0305] The operations performed by any processing module of the first device and any processing module of the second device shown in Figure 6b can be understood with reference to Figure 6c. Figure 6c shows a schematic diagram of a method performed by a processing module. As shown in Figure 6c:

[0306] For the first device: it first scrambles the received second data stream, and then, according to the principle that the data length between adjacent AMGs corresponds to 4096 FEC codewords, inserts AMGs into the scrambled second data stream to obtain the third data stream. The inserted AMG consists of 257 bits, of which 240 bits are AM and the remaining 17 bits are padding data. In Figure 6c, ddd represents the data included in the second data stream. Further, the third data stream is distributed to FEC encoders A and B in 10-bit granularities, and FEC encoders A and B respectively perform FEC encoding on the data they receive. Specifically, the data received by FEC encoder A is message A (msg A), which is encoded into codeword A; the data received by FEC encoder B is message B (msg B), which is encoded into codeword B. Finally, codewords A and B are interleaved at a granularity of 10 bits and distributed to the two PCSLs corresponding to themselves (i.e., the processing modules).

[0307] The operation performed by the processing module of the second device is the inverse operation of the operation performed by the processing module of the first device. For details, please refer to Figure 6c. This will not be repeated here.

[0308] The first and second devices employ the data processing methods shown in Figures 6b and 6c. The first device can shut down any number of physical channels based on actual business traffic. Correspondingly, it controls the processing modules corresponding to the shut-down physical channels to be in a non-working state, while maintaining the data processing method of the processing modules corresponding to the working physical channels. That is, the energy-saving level reaches the channel level. For example, when the service traffic is less than 200Gbps, 7 physical channels (i.e., the 7 optical fibers through which optical module 1 transmits data to optical module 2) can be shut down; when the service traffic is between 200Gbps and 400Gbps, 6 physical channels can be shut down; when the service traffic is between 400Gbps and 600Gbps, 5 physical channels can be shut down; when the service traffic is between 600Gbps and 800Gbps, 4 physical channels can be shut down; when the service traffic is between 800Gbps and 1000Gbps, 3 physical channels can be shut down; when the service traffic is between 1000Gbps and 1200Gbps, 2 physical channels can be shut down; and when the service traffic is between 1200Gbps and 1400Gbps, 1 physical channel can be shut down. The first and second devices can determine the number of physical channels to be shut down based on a rate-reduction command. The rate-reduction command will not be described in detail here.

[0309] Referring to Figure 7a, this figure is a schematic diagram of an exemplary application scenario provided by an embodiment of this application.

[0310] Figure 7a shows a schematic diagram of the interaction between two 400GE Ethernet interfaces. (Figure 7a:)

[0311] The 400GE Ethernet interface 1 and optical module 1 are interconnected via four sets of SerDes. These four sets of SerDes include four SerDes for data transmission from the 400GE Ethernet interface 1 to the optical module 1, and four SerDes for data transmission from the optical module 1 to the 400GE Ethernet interface 1. Similarly, the 400GE Ethernet interface 2 and optical module 2 are also interconnected via four sets of SerDes. These four sets of SerDes include four SerDes for data transmission from the 400GE Ethernet interface 2 to the optical module 2, and four SerDes for data transmission from the optical module 2 to the 400GE Ethernet interface 2. Each SerDes has a speed of 100Gbps.

[0312] Optical module 1 and optical module 2 are interconnected via four sets of optical fibers. These four sets of optical fibers include four fibers for transmitting data from optical module 1 to optical module 2, and four fibers for transmitting data from optical module 2 to optical module 1. Each fiber has a data rate of 100 Gbps. In one example, the optical fibers between optical module 1 and optical module 2 can be single-mode fiber (SMF).

[0313] In this scenario, the data processing framework for the first and second devices can be as shown in Figure 7b. Figure 7b illustrates the data processing framework for the first and second devices.

[0314] As shown in Figure 7b, the first device first performs 64B / 66B encoding and 256B / 257B transcoding sequentially on the data stream (at a rate of 400Gbps) from the MAC or RS to obtain the first data stream. Then, the first data stream is distributed in 257-bit granularity to four processing modules. These four processing modules correspond one-to-one with the four physical channels through which optical module 1 transmits data to optical module 2. Each processing module processes the second data stream it receives to distribute the processed data stream to its corresponding PCSL. One processing module corresponds to four PCSLs, and each PCSL has a rate of 25Gbps. Furthermore, for a given processing module, the data carried on its corresponding PCSL is multiplexed 4:1 to map the data carried on the PCSL corresponding to that processing module to the physical channel corresponding to that processing module for transmission.

[0315] The second device also includes four processing modules, which correspond one-to-one with the four physical channels through which optical module 1 sends data to optical module 2. The operations performed by the second device are the inverse operations performed by the first device, and will not be repeated here.

[0316] The operations performed by any processing module of the first device and any processing module of the second device shown in Figure 7b can be understood with reference to Figure 7c. Figure 7c shows a schematic diagram of a method performed by a processing module. As shown in Figure 7c:

[0317] For the first device: it first scrambles the received second data stream. Then, according to the principle that the data length between adjacent AMGs corresponds to 2048 FEC codewords, it inserts AMGs into the scrambled second data stream to obtain a third data stream. The inserted AMG consists of 514 bits, of which 480 bits are AM and the remaining 34 bits are pads. In Figure 7c, ddd represents the data included in the second data stream. Further, the third data stream is distributed to FEC encoders A and B in 10-bit granularity polling. FEC encoders A and B respectively perform FEC encoding on their received data. Specifically, FEC encoder A receives message A, which is encoded into codeword A; FEC encoder B receives message B, which is encoded into codeword B. Finally, codewords A and B are interleaved in 10-bit granularity and distributed to the four PCSLs corresponding to themselves (i.e., the processing module).

[0318] The operation performed by the processing module of the second device is the inverse operation of the operation performed by the processing module of the first device. For details, please refer to Figure 7c. This will not be repeated here.

[0319] The first and second devices employ the data processing methods shown in Figures 7b and 7c. The first device can shut down any number of physical channels based on actual traffic volume. Correspondingly, it controls the processing modules corresponding to the shut-down physical channels to be in a non-working state, while maintaining the data processing method of the processing modules corresponding to the working physical channels. That is, the energy-saving level reaches the channel level. For example, when the traffic volume is less than 100Gbps, three physical channels can be shut down; when the traffic volume is between 100Gbps and 200Gbps, two physical channels can be shut down; and when the traffic volume is between 200Gbps and 300Gbps, one physical channel can be shut down. The first and second devices can determine the number of physical channels to be shut down based on a rate-reduction command. The rate-reduction command will not be described in detail here.

[0320] Referring to Figure 8a, this figure is a schematic diagram of an exemplary application scenario provided by an embodiment of this application.

[0321] Figure 8a shows a schematic diagram of the interaction between two 1.6TE Ethernet interfaces. (Figure 8a:)

[0322] The 1.6TE Ethernet interface 1 and the 1.6TE Ethernet interface 2 are interconnected via four physical channels. These four physical channels include four physical channels for Ethernet interface 1 to send data to Ethernet interface 2, and four physical channels for Ethernet interface 2 to send data to Ethernet interface 1. The four physical channels shown in Figure 8a can be electrical channels (e.g., cables). Each physical channel has a speed of 400 Gbps.

[0323] In this scenario, the data processing framework for the first and second devices can be as shown in Figure 8b. Figure 8b illustrates the data processing framework for the first and second devices.

[0324] As shown in Figure 8b, the first device first performs 64B / 66B encoding and 256B / 257B transcoding sequentially on the data stream (at a rate of 1.6T) from the MAC or RS to obtain the first data stream. Then, the first data stream is distributed in 257-bit granularity to four processing modules. These four processing modules correspond one-to-one with the four physical channels through which Ethernet interface 1 transmits data to Ethernet interface 2. Each processing module processes the second data stream it receives to distribute the processed data stream to its corresponding PCSL. One processing module corresponds to four PCSLs, and each PCSL has a rate of 100Gbps. Furthermore, for a given processing module, the data carried on its corresponding PCSL is multiplexed 4:1 to map the data carried on the PCSL corresponding to that processing module to the physical channel corresponding to that processing module for transmission.

[0325] The second device also includes four processing modules, which correspond one-to-one with the four physical channels through which Ethernet interface 1 sends data to Ethernet interface 2. The operations performed by the second device are the inverse operations of the operations performed by the first device, and will not be repeated here.

[0326] The operations performed by any processing module of the first device and any processing module of the second device shown in Figure 8b can be understood with reference to Figure 8c. Figure 8c shows a schematic diagram of a method performed by a processing module. As shown in Figure 8c:

[0327] For the first device: it first distributes the received second data stream in 257-bit granularity to obtain a fourth and fifth data stream. Then, it processes the fourth and fifth data streams separately. The rate of both the fourth and fifth data streams is 200Gbps. The processing method for the fourth and fifth data streams is the same as the processing method for the second data stream in Figure 6b; please refer to the description of Figure 6b above for details, which will not be repeated here. The difference between the operation performed by the first device in Figure 8b and that in Figure 6b is that in Figure 6b, the FEC codewords encoded by two FEC encoders are interleaved and distributed to two PCSLs. In Figure 8b, the FEC codewords encoded by four FEC encoders are interleaved and distributed to four PCSLs.

[0328] The operation performed by the processing module of the second device is the inverse operation of the operation performed by the processing module of the first device. For details, please refer to Figure 8c. This will not be repeated here.

[0329] The first and second devices employ the data processing methods shown in Figures 8b and 8c. The first device can shut down any number of physical channels based on actual business traffic. Correspondingly, it controls the processing modules corresponding to the shut-down physical channels to be in a non-working state, while maintaining the data processing method of the processing modules corresponding to the working physical channels. The first and second devices can determine the number of physical channels to shut down based on a rate-reduction command; however, the rate-reduction command will not be described in detail here.

[0330] Furthermore, the first and second devices, using the data processing methods shown in Figures 8b and 8c, can interface with chips of different specifications. For example, the chip corresponding to the first device supports 200Gbps, while the chip corresponding to the second device supports 400Gbps. In this case, the first device does not support the data processing methods shown in Figures 6b and 6c, but the first and second devices can use the data processing flow shown in Figures 8b and 8c to achieve energy savings at a 400Gbps level.

[0331] Based on the data processing method provided in the above embodiments, this application also provides a corresponding data processing apparatus. Next, the data processing apparatus provided in this application will be described in conjunction with the accompanying drawings.

[0332] Referring to Figure 9, this figure is a schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application. The data processing apparatus shown in Figure 9 can be applied to a first apparatus to perform the steps performed by the first apparatus provided in the above embodiments.

[0333] As shown in Figure 9, the data processing device 900 includes a sending unit 901 and a processing unit 902.

[0334] The sending unit 901 is used to distribute the first data stream in the form of a first data block to obtain N second data streams. The N second data streams correspond to A physical channels of the first device. N is greater than or equal to A, and one physical channel corresponds to at least one second data stream. A is an integer greater than or equal to 1.

[0335] The processing unit 902 is used to insert an alignment flag group AMG into the second data stream to obtain a third data stream.

[0336] In one possible implementation, the processing unit 902 is configured to scramble the second data stream before inserting AMG into the second data stream; and to insert AMG into the second data stream after scrambling.

[0337] In one possible implementation, N equals A, and the N second data streams correspond one-to-one with the A physical channels.

[0338] In one possible implementation, the A physical channels correspond to B virtual channels, where B is greater than or equal to A, N is equal to B, and the N second data streams correspond one-to-one with the B virtual channels.

[0339] In one possible implementation, the sending unit 901 is further configured to: distribute the third data stream to M FEC encoders corresponding to the second data stream, wherein the M FEC encoders perform FEC encoding on the data they receive; and distribute the FEC codewords encoded by the M FEC encoders to the virtual channel corresponding to the second data stream.

[0340] In one possible implementation, the first physical channel among the N physical channels corresponds to at least the second data stream, and the processing unit 902 is further configured to: perform a multiplexing operation on the data carried by the virtual channel corresponding to the first physical channel to map the data carried by the virtual channel corresponding to the first physical channel onto the first physical channel for transmission, wherein the virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to the second data stream.

[0341] In one possible implementation, the first data block comprises 257 bits.

[0342] In one possible implementation, the processing unit 902 is configured to: insert AMGs into the second data stream according to a rule that the interval between adjacent AMGs is a preset number of second data blocks.

[0343] In one possible implementation, the second data block corresponds to a forward error correction (FEC) codeword.

[0344] In one possible implementation, the processing unit 902 is configured to: distribute the second data stream at the granularity of the first data block to obtain a fourth data stream and a fifth data stream; and insert AMG into the fourth data stream and the fifth data stream respectively to obtain a third data stream corresponding to the fourth data stream and a third data stream corresponding to the fifth data stream.

[0345] In one possible implementation, distributing the third data stream to M FEC encoders corresponding to the second data stream, and having the M FEC encoders perform FEC encoding on the data they receive, includes: distributing the third data stream corresponding to the fourth data stream to M1 FEC encoders, and having the M1 FEC encoders perform FEC encoding on the data they receive; distributing the third data stream corresponding to the fifth data stream to M2 FEC encoders, and having the M2 FEC encoders perform FEC encoding on the data they receive; wherein the M FEC encoders include the M1 encoder and the M2 encoder.

[0346] Referring to Figure 10, this figure is a schematic diagram of another data processing apparatus provided in an embodiment of this application. The data processing apparatus shown in Figure 10 can be applied to a second apparatus to perform the steps performed by the second apparatus provided in the above embodiments.

[0347] As shown in Figure 10, the data processing device 1000 includes a receiving unit 1001, a processing unit 1002, and a transmitting unit 1003. The receiving unit 1001 and the transmitting unit 1003 are optional.

[0348] The processing unit 1002 is used to: remove the alignment flag group AMG from the third data stream to obtain a second data stream; merge the N second data streams at the first data block granularity to obtain a first data stream, wherein the second device corresponds to A physical channels, the A physical channels correspond to the N second data streams, N is greater than or equal to A, one physical channel corresponds to at least one second data stream, and A is an integer greater than or equal to 1.

[0349] In one possible implementation, the processing unit 1002 is configured to: remove AMG from the third data stream and descramble the data stream obtained after removing AMG to obtain the second data stream.

[0350] In one possible implementation, N equals A, and the N second data streams correspond one-to-one with the A physical channels.

[0351] In one possible implementation, the A physical channels correspond to B virtual channels, where B is greater than or equal to A, N is equal to B, and the N second data streams correspond one-to-one with the B virtual channels.

[0352] In one possible implementation, the sending unit 1003 is used to send the data carried on the virtual channel corresponding to the second data stream to M FEC decoders corresponding to the second data stream before removing the AMG from the third data stream. The M FEC decoders then perform FEC decoding on the data they receive to obtain the third data stream.

[0353] In one possible implementation, the receiving unit 1001 is configured to receive data transmitted by the first device through the first physical channel before transmitting the data carried on the virtual channel corresponding to the second data stream to the M FEC decoders corresponding to the second data stream. The processing unit 1002 is further configured to demultiplex the received data. The transmitting unit 1003 is further configured to transmit the demultiplexed data to the virtual channel corresponding to the first physical channel; the virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to the second data stream, and the N physical channels include the first physical channel, wherein the first physical channel corresponds at least to the second data stream.

[0354] In one possible implementation, the first data block comprises 257 bits.

[0355] In one possible implementation, the processing unit 1002 is configured to: remove AMGs from the third data stream according to a rule that the interval between adjacent AMGs is a preset number of second data blocks.

[0356] In one possible implementation, the second data block corresponds to a forward error correction (FEC) codeword.

[0357] In one possible implementation, the sending unit 1003 is configured to: send data carried on at least one first virtual channel corresponding to the second data stream to M1 FEC decoders, whereby the M1 FEC decoders perform FEC decoding on the data they receive to obtain a third data stream corresponding to the fourth data stream; send data carried on at least one second virtual channel corresponding to the second data stream to M2 FEC decoders, whereby the M2 FEC decoders perform FEC decoding on the data they receive to obtain a third data stream corresponding to the fifth data stream; wherein the M1 FEC decoders include the M1 decoders and the M2 decoders, and the third data stream includes: the third data stream corresponding to the fourth data stream and the third data stream corresponding to the fifth data stream.

[0358] In one possible implementation, the processing unit 1002 is configured to: remove AMG from the third data stream corresponding to the fourth data stream and the third data stream corresponding to the fifth data stream, respectively, to obtain the fourth data stream and the fifth data stream, wherein the second data stream includes the fourth data stream and the fifth data stream.

[0359] For details regarding the specific implementation of each unit of the device 900 and each unit of the device 1000, please refer to the preceding descriptions of the steps performed by the first device and the steps performed by the second device; the steps are described again here.

[0360] Referring to Figure 11, this figure is a schematic diagram of the structure of a communication device provided in an embodiment of this application. The communication device 1100 shown in Figure 11 includes an interface circuit 1101 and a processing circuit 1102. The interface circuit 1101 is used to receive and / or transmit data, and the processing circuit 1102 is used to perform data processing. The interface circuit 1101 is optional.

[0361] In a specific example, the communication device 1100 is used to perform the steps performed by the first device as provided in the above embodiments. In this case:

[0362] The interface circuit 1101 is used to distribute the first data stream in the form of a first data block to obtain N second data streams. The N second data streams correspond to A physical channels of the first device. N is greater than or equal to A, and one physical channel corresponds to at least one second data stream. A is an integer greater than or equal to 1.

[0363] The processing circuit 1102 is used to insert an alignment flag group AMG into the second data stream to obtain a third data stream.

[0364] In yet another specific example, the communication device 1100 is used to perform the steps provided in the above embodiments by the second device. In this case:

[0365] The processing circuit 1102 is used to remove the alignment flag group AMG in the third data stream to obtain the second data stream; and to merge the N second data streams at the first data block granularity to obtain the first data stream. The second device corresponds to A physical channels, and the A physical channels correspond to the N second data streams. N is greater than or equal to A, and one physical channel corresponds to at least one second data stream. A is an integer greater than or equal to 1.

[0366] Optionally, the interface circuit 1101 is used to receive data sent by the first device through the first physical channel.

[0367] In one example, the device shown in Figure 11 may be a network device or a chip, wherein the chip may be, for example, a PHY chip.

[0368] In another example, the device shown in Figure 11 could be an optical module.

[0369] Referring to Figure 12, this figure is a schematic diagram of the structure of a device provided in an embodiment of this application.

[0370] In one example, the device 1200 shown in FIG12 can be used to perform the communication method provided in the above method embodiments.

[0371] Please refer to Figure 12. The device 1200 includes a processor 1210 and a communication interface 1220. The communication interface 1220 is optional.

[0372] The device 1200 may contain one or more processors 1210; Figure 12 shows an example with one processor. The processor 1210 is used to perform data processing operations.

[0373] Processor 1210 may be a central processing unit (CPU), an NP, or a combination of CPU and NP. Processor 1210 may further include hardware chips. These hardware chips may be ASICs, programmable logic devices (PLDs), or combinations thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0374] The communication interface 1220 is used to receive and / or send data.

[0375] In a specific example, the device 1200 is used to perform the steps performed by the first device as provided in the above embodiments. In this case:

[0376] The communication interface 1220 is used to distribute the first data stream in the form of a first data block to obtain N second data streams. The N second data streams correspond to A physical channels of the first device. N is greater than or equal to A, and one physical channel corresponds to at least one second data stream. A is an integer greater than or equal to 1.

[0377] The processor 1210 is used to insert an alignment flag group AMG into the second data stream to obtain a third data stream.

[0378] In yet another specific example, the device 1200 is used to perform the steps provided in the above embodiments by the second device. In this case:

[0379] The processor 1210 is used to remove the alignment flag group AMG in the third data stream to obtain a second data stream; and to merge the N second data streams at the first data block granularity to obtain a first data stream. The second device corresponds to A physical channels, and the A physical channels correspond to the N second data streams. N is greater than or equal to A, and one physical channel corresponds to at least one second data stream. A is an integer greater than or equal to 1.

[0380] Optionally, the communication interface 1220 is used to receive data sent by the first device through the first physical channel.

[0381] In one example, the device 1200 further includes a memory 1230. The memory 1230 may include volatile memory, such as random-access memory (RAM); the memory 1230 may also include non-volatile memory, such as flash memory, hard disk drive (HDD), or solid-state drive (SSD); the memory 1230 may also include combinations of the above types of memory.

[0382] Optionally, the memory 1230 stores an operating system and programs, executable modules, or data structures, or subsets thereof, or extended sets thereof. The programs may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and handling hardware-based tasks. The processor 1210 can read the programs in the memory 1230 to implement the methods provided in the embodiments of this application.

[0383] In one example, processor 1210, communication interface 1220 and memory 1230 can be connected via a bus system or other means, wherein Figure 12 shows an example of connection via bus system 1240.

[0384] Bus system 1240 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. Bus system 1240 can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in Figure 12, but this does not mean that there is only one bus or one type of bus.

[0385] This application provides a computer-readable storage medium, including instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the above method embodiments.

[0386] This application provides a computer program product containing instructions or computer programs, which, when run on a computer, causes the computer to perform the methods described in the above method embodiments.

[0387] This application also provides a communication system, which includes the first device and the second device mentioned in the above embodiments, for executing the method provided in the above embodiments by the first device and the second device.

[0388] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0389] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0390] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical business division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0391] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0392] Furthermore, the various business units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software business unit.

[0393] If the integrated unit is implemented as a software business unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0394] Those skilled in the art will recognize that, in one or more of the examples above, the services described in this application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these services can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of computer programs from one place to another. Storage media can be any available medium accessible to general-purpose or special-purpose computers.

[0395] The above specific embodiments further illustrate the purpose, technical solution and beneficial effects of this application. It should be understood that the above are only specific embodiments of this application.

[0396] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data processing method, characterized in that, Applied to a first device, the method includes: The first data stream is distributed in the form of a first data block to obtain N second data streams. The N second data streams correspond to A physical channels of the first device. N is greater than or equal to A. One physical channel corresponds to at least one second data stream. A is an integer greater than or equal to 1. The alignment flag group AMG is inserted into the second data stream to obtain the third data stream.

2. The method according to claim 1, characterized in that, The method further includes: Before inserting AMG into the second data stream, the second data stream is scrambled; The insertion of the alignment flag group AMG into the second data stream includes: AMG is inserted into the second data stream after scrambling.

3. The method according to claim 1 or 2, characterized in that, The N is equal to A, and the N second data streams correspond one-to-one with the A physical channels.

4. The method according to claim 1 or 2, characterized in that, The A physical channels correspond to B virtual channels, where B is greater than or equal to A, N is equal to B, and the N second data streams correspond one-to-one with the B virtual channels.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: The third data stream is distributed to M FEC encoders corresponding to the second data stream, and the M FEC encoders perform FEC encoding on the data they receive. The FEC codewords encoded by the M FEC encoders are distributed to the virtual channel corresponding to the second data stream.

6. The method according to claim 5, characterized in that, The first physical channel among the N physical channels corresponds at least to the second data stream, and the method further includes: The data carried by the virtual channel corresponding to the first physical channel is multiplexed to map the data carried by the virtual channel corresponding to the first physical channel onto the first physical channel for transmission. The virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to the second data stream.

7. The method according to any one of claims 1-6, characterized in that, The first data block consists of 257 bits.

8. The method according to any one of claims 1-7, characterized in that, The insertion of the alignment flag group AMG into the second data stream includes: According to the rule of a preset number of second data blocks between adjacent AMGs, AMGs are inserted into the second data stream.

9. The method according to claim 8, characterized in that, The second data block corresponds to a forward error correction (FEC) codeword.

10. The method according to claim 5 or 6, characterized in that, The step of inserting the alignment flag group AMG into the second data stream to obtain the third data stream includes: The second data stream is distributed at the granularity of the first data block to obtain the fourth data stream and the fifth data stream; AMG is inserted into the fourth data stream and the fifth data stream respectively to obtain a third data stream corresponding to the fourth data stream and a third data stream corresponding to the fifth data stream.

11. The method according to claim 10, characterized in that, The step of distributing the third data stream to M FEC encoders corresponding to the second data stream, and having the M FEC encoders perform FEC encoding on the data they receive, includes: The third data stream corresponding to the fourth data stream is distributed to M1 FEC encoders, and the M1 FEC encoders perform FEC encoding on the data they receive. The third data stream corresponding to the fifth data stream is distributed to M2 FEC encoders, and the M2 FEC encoders perform FEC encoding on the data they receive; wherein, the M FEC encoders include the M1 encoder and the M2 encoders.

12. A data processing method, characterized in that, Applied to a second device, the method includes: Remove the alignment flag group AMG from the third data stream to obtain the second data stream; The N second data streams are merged at the granularity of the first data block to obtain the first data stream. The second device corresponds to A physical channels, and the A physical channels correspond to the N second data streams. N is greater than or equal to A, and one physical channel corresponds to at least one second data stream. A is an integer greater than or equal to 1.

13. The method according to claim 12, characterized in that, The step of removing the alignment flag group AMG from the third data stream to obtain the second data stream includes: Remove AMG from the third data stream and descramble the data stream obtained after removing AMG to obtain the second data stream.

14. The method according to claim 12 or 13, characterized in that, The N is equal to A, and the N second data streams correspond one-to-one with the A physical channels.

15. The method according to claim 12 or 13, characterized in that, The A physical channels correspond to B virtual channels, where B is greater than or equal to A, N is equal to B, and the N second data streams correspond one-to-one with the B virtual channels.

16. The method according to any one of claims 12-15, characterized in that, Before removing AMG from the third data stream, the method further includes: The data carried on the virtual channel corresponding to the second data stream is sent to M FEC decoders corresponding to the second data stream. The M FEC decoders perform FEC decoding on the data they receive to obtain the third data stream.

17. The method according to claim 16, characterized in that, Before sending the data carried on the virtual channel corresponding to the second data stream to the M FEC decoders corresponding to the second data stream, the method further includes: The system receives data sent by the first device through the first physical channel, demultiplexes the received data, and sends the demultiplexed data to the virtual channel corresponding to the first physical channel. The virtual channel corresponding to the first physical channel includes at least one virtual channel corresponding to the second data stream. The N physical channels include the first physical channel, and the first physical channel corresponds to at least the second data stream.

18. The method according to any one of claims 12-17, characterized in that, The first data block consists of 257 bits.

19. The method according to any one of claims 12-18, characterized in that, The removal of the alignment flag group AMG from the third data stream includes: According to the rule of a preset number of second data blocks between adjacent AMGs, the AMGs in the third data stream are removed.

20. The method according to claim 19, characterized in that, The second data block corresponds to a forward error correction (FEC) codeword.

21. The method according to claim 16 or 17, characterized in that, The data carried on the virtual channel corresponding to the second data stream is sent to M FEC decoders. The M FEC decoders perform FEC decoding on the data they receive to obtain the third data stream, which includes: The data carried on at least one first virtual channel corresponding to the second data stream is sent to M1 FEC decoders, and the M1 FEC decoders perform FEC decoding on the data they receive to obtain the third data stream corresponding to the fourth data stream; The data carried on at least one second virtual channel corresponding to the second data stream is sent to M2 FEC decoders, and the M2 FEC decoders perform FEC decoding on the data they receive to obtain the third data stream corresponding to the fifth data stream; wherein, the M FEC decoders include the M1 decoder and the M2 decoders, and the third data stream includes: the third data stream corresponding to the fourth data stream and the third data stream corresponding to the fifth data stream.

22. The method according to claim 21, characterized in that, The step of removing the alignment flag group AMG from the third data stream to obtain the second data stream includes: The AMG streams in the third data stream corresponding to the fourth data stream and the third data stream corresponding to the fifth data stream are removed respectively to obtain the fourth data stream and the fifth data stream. The second data stream includes the fourth data stream and the fifth data stream.

23. A communication device, characterized in that, Includes a processor for performing any of the operations in claims 1-22 other than the receiving and transmitting operations.

24. The communication device according to claim 23, characterized in that, The communication device further includes a communication interface, which is used to perform the receiving operation or sending operation in any one of claims 1-22.

25. A chip, characterized in that, The chip includes a processing circuit for performing other operations as described in any one of claims 1-22, excluding the receiving and transmitting operations.

26. The chip according to claim 25, characterized in that, The chip further includes an interface circuit, which is used to perform the receiving operation or transmitting operation in any one of claims 1-22.

27. A communication system, characterized in that, The system includes: A first apparatus for performing the method according to any one of claims 1-11, and a second apparatus for performing the method according to any one of claims 12-22.

28. A computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1-22.

29. A computer program product, characterized in that, The computer program product includes instructions or a computer program that, when run on a computer, causes the computer to perform the method described in any one of claims 1-22.

Images