Communication device, control method, and program

Abstract

In a communication device according to an embodiment of the present invention, a signal reception unit receives an OFDM signal and converts the signal into a time-axis waveform signal of a baseband. A time waveform arithmetic unit extracts a part of the time-axis waveform signal output from the signal reception unit and calculates a correlation value between the extracted signal and a known signal. In a series of arithmetic stages for performing a Fourier transform, a FFT unit repeatedly uses a single arithmetic circuit and a data storage circuit through time multiplexing and performs FFT on the time-axis waveform signal output from the signal reception unit. A frequency waveform arithmetic unit extracts a part of a frequency-axis waveform signal through the FFT and calculates a degree of similarity between the extracted signal and a known signal. A switching timing estimation unit estimates a switching timing between uplink communication and downlink communication in a host device on the basis of the calculation result for the degree of similarity.

Description

Communication device, control method, and program

[0001] Embodiments of the present invention relate to a communication device, a control method, and a program.

[0002] As one form of a wireless communication system, a distributed antenna system (DAS: Distributed Antenna Systems) is known. In a distributed antenna system, downlink communication (DL: Down Link) transmitted from a base station to a terminal and uplink communication (UL: Up Link) transmitted from the terminal to the base station are communicated by a time division multiplexing method (TDD: Time Division Duplex) that switches every predetermined period. Such a distributed antenna system needs to detect the DL period and UL period of a radio signal and appropriately switch them.

[0003] Conventionally, a communication device detects and decodes a synchronization signal block (SSB: SS / PBCH Block) composed of a primary synchronization signal (PSS: Primary Synchronization Signal), a secondary synchronization signal (SSS: Secondary Synchronization Signal), and a physical broadcast channel (PBCH: Physical Broadcast Channel) to grasp the position of the received SSB within a radio frame. Then, by referring to the position of the received SSB and a preset TDD DL / UL pattern, the switching timing between downlink communication and uplink communication is estimated.

[0004] Japanese Patent Application Laid-Open No. 2024-007110, Japanese Patent Application Laid-Open No. 2024-108794

[0005] Mobile phone carriers have introduced individual DASs for each mobile communication generation, especially in indoor environments, for their existing infrastructure. Therefore, since many individual DASs have already been installed, it is difficult to secure space for additional installation of communication equipment for 5G (5th Generation). Also, in the mobile communication industry, efforts toward carbon neutrality, such as reducing power consumption in infrastructure equipment such as base stations, have become essential.

[0006] Infrastructure-sharing DAS is attracting attention as a solution to the problem of difficulty in securing installation locations and challenges such as reducing power consumption. Infrastructure-sharing DAS is a DAS that can be jointly used by multiple mobile phone operators simultaneously. If each mobile phone operator installs their own DAS, the overall circuitry will be redundant, but by sharing infrastructure-sharing DAS, it becomes possible to eliminate the duplication of functions and reduce both installation space and power consumption.

[0007] In this infrastructure-sharing DAS, it is necessary to detect the TDD timing for each mobile phone operator, and in order to simplify the device configuration, there is a need to miniaturize the TDD timing detection circuit.

[0008] Therefore, the present invention has been made in view of the above circumstances, and aims to provide a communication device, control method, and program that can detect the switching timing between DL communication and UL communication with a small circuit size in a TDD system that switches between DL communication and UL communication at predetermined intervals.

[0009] The communication device of the embodiment is a communication device that functions as either the master station or the slave station and receives an OFDM (Orthogonal Frequency Division Multiplexing) signal transmitted using a time division multiplexing scheme in a distributed antenna system comprising a master station connected to a base station and one or more slave stations that relay signals between terminal stations communicating with the base station and the master station. The communication device comprises a signal receiving unit, a time waveform calculation unit, an FFT unit, a frequency waveform calculation unit, and a switching timing estimation unit. The signal receiving unit receives the OFDM signal and converts it into a baseband time-axis waveform signal. The time waveform calculation unit extracts a portion of the time-axis waveform signal, which is the output of the signal receiving unit, and calculates a correlation value between the extracted signal and a known signal. The FFT unit performs an FFT (Fast Fourier Transform) on the time-axis waveform signal, which is the output of the signal receiving unit. The frequency waveform calculation unit extracts a portion of the frequency-axis waveform signal, which is the output of the FFT unit, and calculates the degree of similarity between the extracted signal and a known signal. The switching timing estimation unit estimates the switching timing between uplink and downlink communication in its own device based on the calculation results of the frequency waveform calculation unit. The FFT unit repeatedly uses a single calculation circuit and a data storage circuit by time multiplexing in a series of calculation stages that perform Fourier transforms.

[0010] Figure 1 shows a schematic example of a distributed antenna system according to the first embodiment. Figure 2 shows an example of the data structure of a wireless frame. Figure 3 shows an example of the SSB arrangement pattern in a wireless frame. Figure 4 shows an example of a DL / UL configuration and SSB arrangement in the TDD method. Figure 5 shows an example of the functional configuration of the master station device in the first embodiment. Figure 6 shows an example of the functional configuration of the control unit in the first embodiment. Figure 7 shows an example of the functional configuration of the switching timing generation unit in the first embodiment. Figure 8 shows an example of the functional configuration of the FFT unit according to the first embodiment. Figure 9 shows an example of switching of the functional blocks of the FFT unit according to the first embodiment. Figure 10 shows an example of the functional configuration of the FFT control unit according to the first embodiment. Figure 11 shows an example of the timing chart of the input counter of the FFT control unit according to the first embodiment. Figure 12 shows an example of the timing chart of the clock counter and stage counter of the FFT control unit according to the first embodiment. Figure 13 shows an example of the timing chart of the output counter of the FFT control unit according to the first embodiment. Figure 14 is a flowchart showing an example of TDD timing detection processing according to the first embodiment. Figure 15 is a flowchart showing an example of time waveform processing according to the first embodiment. Figure 16 is a flowchart showing an example of FFT processing according to the first embodiment. Figure 17 is a flowchart showing an example of FFT input processing according to the first embodiment. Figure 18 is a flowchart showing an example of FFT calculation processing according to the first embodiment. Figure 19 is a flowchart showing an example of butterfly calculation processing according to the first embodiment. Figure 20 is a flowchart showing an example of FFT output processing according to the first embodiment. Figure 21 is a flowchart showing an example of frequency waveform processing according to the first embodiment. Figure 22 is a flowchart showing an example of SSS detection processing according to the first embodiment. Figure 23 is a flowchart showing an example of DMRS detection processing according to the first embodiment. Figure 24 is a flowchart showing an example of switching timing estimation processing according to the first embodiment. Figure 25 is a diagram showing an example of the functional configuration of the FFT unit according to Comparative Example 1.Figure 26 is a diagram showing an example of switching of the functional blocks of the FFT section according to the second embodiment. Figure 27 is a flowchart showing an example of FFT processing according to the second embodiment.

[0011] The communication device, control method, and program will be described in detail below with reference to the attached drawings. In the following descriptions of each embodiment and modification, parts denoted by the same reference numerals have substantially the same function, and the description of overlapping parts will be omitted as appropriate.

[0012] (First Embodiment) Figure 1 shows a schematic example of a distributed antenna system 1 according to the first embodiment. The distributed antenna system 1 comprises a master unit 10 (MU), a relay unit 20 (HU), a slave unit 30 (RU), and a transmission line 40 connecting them. More specifically, the distributed antenna system 1 comprises a master unit 10 connected to a base station 50, and one or more slave units 30 that relay signals between a terminal unit 60 communicating with the base station 50 and the master unit 10.

[0013] The master station 10 is connected to multiple slave stations 30 within the distributed antenna system 1. As shown in Figure 1, the master station 10 may be connected to multiple slave stations 30 via relay devices 20, or it may be connected to multiple slave stations 30 directly. Also, as shown in Figure 1, the master station 10 may have relay devices 20 connected in cascaded order.

[0014] The master station 10 is connected to the base station 50 by a coaxial cable and transmits and receives radio signals with the base station 50. Here, the radio signal is a signal in the radio communication band that is transmitted to the terminal device 60. The master station 10 relays the radio signal received from the base station 50 to the relay device 20 or the slave station 30. The master station 10 also relays the radio signal received from the relay device 20 or the slave station 30 back to the base station 50.

[0015] The slave unit 30 is connected to the terminal unit 60 by a wired cable and an antenna 70 for wireless communication, and transmits and receives wireless signals to and from the terminal unit 60 via this antenna 70. The slave unit 30 relays the wireless signals received from the terminal unit 60 to the master unit 10 or relay unit 20. The slave unit 30 also relays the wireless signals received from the master unit 10 or relay unit 20 to the terminal unit 60.

[0016] With a distributed antenna system 1 having such a configuration, it becomes possible to connect wireless terminals that cannot be directly reached by radio waves to the base station 50, thereby expanding the communication range of the mobile communication network covered by the base station 50. For example, the distributed antenna system 1 is applicable to mobile communication networks such as 5G.

[0017] On the other hand, conventional mobile communications use the TDD (Time Division Duplex) method, in which uplink and downlink communications are switched at predetermined intervals. Therefore, when applying the distributed antenna system 1 to a mobile communication network, the distributed antenna system 1 needs to detect this switching and appropriately switch between DL processing and UL processing.

[0018] Furthermore, in communication equipment that shares a single DAS (Data Transfer System) with multiple mobile phone carriers, interference occurs if the switching timings between downlink and uplink communications of the multiple carriers are out of sync. Therefore, it is necessary to detect the leading symbol of the downlink wireless frame to detect and correct the discrepancy in the switching timing between downlink and uplink communications between carriers. In this case as well, accurate detection of the switching between downlink and uplink communications is required.

[0019] In a distributed antenna system 1 comprising a master station device 10 connected to a base station 50, and one or more slave station devices 30 that relay signals between a terminal device 60 communicating with the base station 50 and the master station device 10, the master station device 10 functions as either the master station device 10 or a slave station device 30, and is a communication device that receives orthogonal frequency division multiplexing (OFDM) signals transmitted using a time division multiplexing scheme. Furthermore, in a distributed antenna system 1 using a TDD scheme in which DL communication and UL communication are switched at predetermined intervals, the master station device 10 receives radio frames including a synchronization signal block (SSB: SS / PBCH Block). The SSB has a primary synchronization signal (PSS), a secondary synchronization signal (SSS), and a physical broadcast channel (PBCH). The master station device 10 then detects and decodes the SSB from the received wireless frame to determine the position of the received SSB within the wireless frame.

[0020] The master station 10 then estimates the DL / UL switching timing based on the position of the SSB within the wireless frame and the DL / UL pattern of the TDD method. This allows the master station 10 to estimate the DL / UL switching timing even when there is no power (signal) in the leading symbol of a wireless frame, such as a 5G wireless signal.

[0021] Figure 2 shows an example of the data structure of a wireless frame. Figure 2 shows an example of a 5G wireless frame. One frame is transmitted in 10ms. One frame consists of 10 subframes, each transmitted in 1ms. In 5G, multiple subcarrier frequency intervals are supported, and these differences result in differences in the length of one symbol. Therefore, the concept of slots is introduced into the wireless frame, and the number of symbols per subframe is divided into multiple slots, absorbing the difference in symbol length due to differences in subcarrier frequency intervals by the number of slots per subframe. One slot has 14 symbols, regardless of the subcarrier frequency interval. Figure 2 shows the case where the subcarrier frequency interval is 30kHz, and one subframe consists of two slots and 28 symbols. As shown in Figure 2, SSB is placed at a specific position in the wireless frame, and an SSB index is assigned to each SSB position.

[0022] Figure 3 shows an example of an SSB placement pattern in a wireless frame. An SSB consists of four symbols. An SSB also has two synchronization signals, PSS and SSS, and a PBCH signal. The PBCH signal has a DMRS (DeModulation of Reference Signal) for PBCH, which is a reference signal for decoding the PBCH signal. Each SSB position in the wireless frame is assigned an SSB index number. For example, in Japanese operations, values ​​from 0 to 7 are assigned as shown in Figure 3. The placement of SSBs depends on the operator, so after detecting an SSB, it is necessary to identify its location.

[0023] Figure 4 shows an example of a DL / UL configuration and SSB arrangement in the TDD system. The SSB shown in Figure 4 represents a case where the subcarrier frequency interval is 30 kHz, the SSB period is 20 ms, and the transmission period is 5 ms. Within the transmission period, there are 10 slots, with DL assigned to the first 6 slots and UL assigned to the last 3 slots, and buffer slots assigned between the DL slots and UL slots. In this way, the number of consecutive DL slots and consecutive UL slots within the transmission period are predetermined. The buffer slots are also assigned consecutive DL symbols, consecutive UL symbols, and blank symbols that function as guards between them. Note that the SSB shown in Figure 4 shows a configuration in which 3 symbols each are assigned to DL symbols and UP symbols, and 8 symbols are assigned as guards.

[0024] From the above, if the master station 10 can detect the index number of the SSB placed at a specific position in the wireless frame, it can estimate the position of that SSB within the transmission cycle. Furthermore, if the master station 10 has known the DL / UL configuration information of the TDD system, it can estimate the DL / UL switching timing within the transmission cycle based on the relative relationship from the placement position of the SSB.

[0025] In the following, the direction of communication from base station 50 to terminal device 60 will be referred to as the downlink, and the opposite direction as the uplink. Correspondingly, signals transmitted in the downlink direction will be called "DL signals," and signals transmitted in the uplink direction will be called "UL signals."

[0026] Furthermore, downlink signals transmitted in frame form are called "downlink frames," and uplink signals transmitted in frame form are called "uplink frames." Also, with respect to a certain device, the uplink side is sometimes called the "upper" side, and the downlink side is sometimes called the "lower" side. Correspondingly, a device connected to the upper side of a certain device is sometimes called the "upper device," and a device connected to the lower side is sometimes called the "lower device."

[0027] For example, the master station 10 is a higher-level device than the relay device 20 and the slave station 30, and the relay device 20 is a higher-level device than the slave station 30. Conversely, the relay device 20 and the slave station 30 are lower-level devices than the master station 10, and the slave station 30 is lower-level devices than the master station 10 and the relay device 20.

[0028] Figure 5 shows an example of the functional configuration of the master station device 10 in the first embodiment. The master station device 10 includes a CPU (Central Processing Unit), memory, and auxiliary storage devices connected by a bus, and executes programs. The master station device 10 includes an upper-side input / output unit 11, a lower-side input / output unit 12, a downlink processing unit 13, an uplink processing unit 14, and a control unit 15 through program execution. Note that all or part of the functions of the master station device 10 may be implemented using hardware such as an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array). The program may be recorded on a computer-readable recording medium. Computer-readable recording media include, for example, portable media such as flexible disks, magneto-optical disks, ROMs, and CD-ROMs, and storage devices such as hard disks built into computer systems. The program may be transmitted via a telecommunications line.

[0029] The higher-level input / output unit 11 is a communication interface that inputs and outputs wireless signals to and from the higher-level device of the master station device 10. Specifically, the higher-level input / output unit 11 is a communication interface that inputs and outputs wireless signals to and from the base station 50 via a coaxial cable. The higher-level input / output unit 11 outputs the DL signal received from the base station 50 to the downlink processing unit 13 and outputs the UL signal input from the uplink processing unit 14 to the base station 50.

[0030] The lower-side input / output unit 12 is a communication interface that inputs and outputs wireless signals to and from lower-side devices of the master station device 10. Specifically, the lower-side input / output unit 12 is a communication interface that inputs and outputs wireless signals to and from the slave station device 30. The lower-side input / output unit 12 outputs the UL signal received from the slave station device 30 to the uplink processing unit 14 and outputs the DL signal input from the downlink processing unit 13 to the slave station device 30.

[0031] The downlink processing unit 13 performs the process of outputting the DL signal received by the master station 10 from the higher-level device to the lower-level device (hereinafter referred to as "DL processing"). Specifically, the DL processing of the master station 10 includes the AD (Analog to Digital) conversion process for the DL signal received from the base station 50, and the mapping process that associates the digital signal with a frame. The downlink processing unit 13 outputs the downlink frame to which the DL signal has been associated in the DL processing to the lower-side input / output unit 12.

[0032] The uplink processing unit 14 performs the process of outputting the UL signal received by the master station 10 from the lower-level device to the upper-level device (hereinafter referred to as "UL processing"). Specifically, the UL processing of the master station 10 includes demapping processing to acquire the UL signal from the uplink frame received from the relay device 20 or the slave station 30, and DA (Digital to Analog) conversion processing for the UL signal acquired by the demapping processing. The uplink processing unit 14 outputs the UL signal converted to an analog signal in the UL processing to the upper-level input / output unit 11.

[0033] The control unit 15 has a function to switch between uplink and downlink communication in the master station device 10. Specifically, the control unit 15 has a function to detect the switch between uplink and downlink communication, and switches between DL processing and UL processing (transmission operation) at the timing when the switch between uplink and downlink communication is detected.

[0034] Figure 6 shows an example of the functional configuration of the control unit 15 in the first embodiment. The control unit 15 includes a switching timing generation unit 153 and a switching unit 154.

[0035] The switching timing generation unit 153 estimates the UL period or DL ​​period and notifies the switching timing between the UL process and the DL process. Specifically, the switching timing generation unit 153 notifies the start timing of the estimated UL period or DL ​​period. The start timing may be notified as the start time of the UL period or DL ​​period, or as the elapsed time from the current time. Furthermore, the notification of the start timing may simply be a notification of the arrival of the start timing.

[0036] The switching unit 154 switches between UL processing and DL processing at the switching timing notified by the switching timing generation unit 153.

[0037] Figure 7 shows an example of the functional configuration of the switching timing generation unit 153 in the first embodiment. The switching timing generation unit 153 includes a signal receiving unit 1001, a time waveform calculation unit 1002, an FFT (Fourier Transform) unit 1004, a frequency waveform calculation unit 1005, and a switching timing estimation unit 1006.

[0038] The signal receiving unit 1001 includes an ADC unit 1010, a carrier frequency conversion unit 1011, and a sampling rate conversion unit 1012. The signal receiving unit 1001 receives an OFDM signal and converts it into a baseband time-domain waveform signal. More specifically, the signal receiving unit 1001 receives wireless frames including SSB. That is, the signal receiving unit 1001 receives PSS, SSS, and SSB having a PBCH including DMRS.

[0039] The ADC unit 1010 converts the input analog signal into a digital signal and outputs it to the carrier frequency conversion unit 1011.

[0040] The carrier frequency conversion unit 1011 converts the input digital signal to a baseband signal by down-converting its frequency and outputs it to the sampling rate conversion unit 1012.

[0041] The sampling rate conversion unit 1012 generates a baseband time-axis waveform signal, which is a baseband time-axis waveform signal, by converting the sampling rate of the input baseband signal. Then, the sampling rate conversion unit 1012 outputs the baseband time-axis waveform signal to the time waveform calculation unit 1002 and the FFT unit 1004.

[0042] The time waveform calculation unit 1002 includes a PSS detection unit 1013. The time waveform calculation unit 1002 extracts a part of the baseband time-axis waveform signal that is the output of the signal reception unit 1001, and calculates the degree of similarity (for example, the correlation value) between the extracted signal and a known signal.

[0043] The PSS detection unit 1013 detects the PSS signal included in the baseband time-axis waveform signal. More specifically, the PSS detection unit 1013 detects the PSS signal arranged at the head of the SSB from the baseband signal after sampling rate conversion, and outputs the detected timing to the FFT unit 1004 as the SSB timing. In addition, the PSS detection unit 1013 determines which of the plurality of PSS code sequences the detected PSS signal corresponds to, and outputs it to the frequency waveform calculation unit 1005 as NID2, which is the cell identifier of the physical layer.

[0044] The FFT unit 1004 performs an FFT on the baseband time-axis waveform signal that is the output of the sampling rate conversion unit 1012 of the signal reception unit 1001. More specifically, the FFT unit 1004 cuts out the SSB from the baseband time-axis waveform signal after sampling rate conversion based on the input SSB timing and performs a Fourier transform. Then, the FFT unit 1004 outputs the frequency-axis waveform signal of the SSB obtained by the Fourier transform to the frequency waveform calculation unit 1005. The configuration of the FFT unit 1004 will be described in detail later.

[0045] The frequency waveform calculation unit 1005 includes an SSS detection unit 1016 and a DMRS detection unit 1017.

[0046] The SSS detection unit 1016 detects the SSS signal included in the frequency-axis waveform signal of the SSB, which is the output of the FFT unit 1004. Further, the SSS detection unit 1016 determines which of the plurality of SSS sequences the detected SSS signal corresponds to. Then, the SSS detection unit 1016 outputs to the DMRS detection unit 1017 as NID1 indicating the group of cell identifiers of the determined physical layer.

[0047] The DMRS detection unit 1017 detects the DMRS signal included in the frequency-axis waveform signal of the SSB, which is the output of the FFT unit 1004. Further, the DMRS detection unit 1017 determines which of the plurality of DMRS sequences the detected DMRS signal corresponds to. Then, the DMRS detection unit 1017 outputs the ibar_SSB corresponding to the DMRS sequence to the switching timing estimation unit 1006.

[0048] The switching timing estimation unit 1006 estimates the switching timing between downlink communication and uplink communication in the own device based on the calculation result of the frequency waveform calculation unit 1005. More specifically, the switching timing estimation unit 1006 estimates at which position in the transmission period the SSB is arranged from the input ibar_SSB. The switching timing estimation unit 1006 estimates the switching timing between downlink communication and uplink communication in the transmission period from the arrangement position of the SSB to be estimated and the DL / UL configuration information in the known TDD mode.

[0049] FIG. 8 is a diagram showing an example of the functional configuration of the FFT unit 1004 according to the first embodiment. The FFT unit 1004 cuts out the SSB from the baseband time-axis waveform signal after sampling rate conversion based on the input SSB timing, executes FFT, and outputs the baseband frequency-axis waveform signal of the SSB.

[0050] The FFT unit 1004 includes an input buffer unit 1041, an FFT control unit 1042, an input data selection unit 1043, a butterfly calculation unit 1049, an output data selection unit 1047, a memory unit 1044, and an output buffer unit 1048. Each of the functional blocks of the input buffer unit 1041, the memory unit 1044, and the output buffer unit 1048 is equipped with RAM for holding data. However, the RAM for holding data is not dedicated to each functional block; the RAM switches between functional blocks that operate according to SSB timing. The switching of these functional blocks will be explained in detail later.

[0051] The input buffer unit 1041 extracts the SSB from the baseband time-domain waveform signal after sampling rate conversion and stores it internally.

[0052] The FFT control unit 1042 controls each functional block provided in the FFT unit 1004 based on the input SSB timing. The FFT control unit 1042 is an example of a control unit. The FFT control unit 1042 may, for example, be configured to operate at a higher operating frequency than the input buffer unit 1041. The configuration of the FFT control unit 1042 will be described in detail later.

[0053] The input data selection unit 1043 selects data input from the memory unit 1044 and outputs it to the butterfly calculation unit 1049.

[0054] The butterfly calculation unit 1049 performs a butterfly calculation on the data input from the input data selection unit 1043 and outputs the calculation result to the output data selection unit 1047. The butterfly calculation is a core calculation method of the FFT algorithm and is used to efficiently process input data and significantly reduce the amount of computation. The butterfly calculation unit 1049 includes a coefficient data generation unit 1046 and a data calculation unit 1045. The butterfly calculation unit 1049 may, for example, be configured to operate at a higher operating frequency than the input buffer unit 1041.

[0055] The coefficient data generation unit 1046 generates coefficients called rotation factors, which are necessary for data synthesis and decomposition during the FFT calculation stage, and outputs them to the data calculation unit 1045.

[0056] The data calculation unit 1045 performs a butterfly operation, which combines data addition and subtraction and multiplication of the rotation factor, on the data input from the input data selection unit 1043 and the rotation factor coefficients input from the coefficient data generation unit 1046, and outputs the calculation result to the output data selection unit 1047.

[0057] The output data selection unit 1047 selects the data input from the butterfly calculation unit 1049 and outputs it to the memory unit 1044.

[0058] The memory unit 1044 holds the data input from the output data selection unit 1047 based on control from the FFT control unit 1042, and outputs the held data to the input data selection unit 1043. The memory unit 1044 may, for example, be configured to operate at a higher operating frequency than the input buffer unit 1041.

[0059] The output buffer unit 1048 outputs the baseband frequency axis waveform signal that it holds internally. The output buffer unit 1048 may operate at a higher operating frequency than, for example, the input buffer unit 1041.

[0060] Figure 9 shows an example of switching the functional blocks of the FFT unit 1004 according to the first embodiment. The FFT unit 1004 has three blocks that have the function of holding data: an input buffer unit 1041, a memory unit 1044, and an output buffer unit 1048. Each functional block is equipped with RAM for holding data. However, the RAM for holding data is not dedicated to each functional block; the RAM provided in the FFT unit 1004 is divided into three parts, RAM1, RAM2, and RAM3, and the functional block operating is switched according to SSB timing.

[0061] The upper part of Figure 9 shows an example sequence illustrating the switching control of functional blocks assigned to RAM1, RAM2, and RAM3 according to the SSB timing. The FFT control unit 1042 controls the functional blocks to be assigned to RAM1, RAM2, and RAM3 according to the SSB timing, in accordance with this sequence.

[0062] In other words, as shown in the upper part of Figure 9, during the first SSB timing, RAM1 functions as an input buffer unit 1041, and RAM2 and RAM3 wait for operation. During the second SSB timing, RAM1 functions as a memory unit 1044, RAM2 functions as an input buffer unit 1041, and RAM3 waits for operation. Then, during the third SSB timing, RAM1 functions as an output buffer unit 1048, RAM2 functions as a memory unit 1044, and RAM3 functions as an input buffer unit 1041.

[0063] Furthermore, during the fourth SSB timing, RAM1 functions again as the input buffer 1041, RAM2 as the output buffer 1048, and RAM3 as the memory 1044. Thereafter, RAM1, RAM2, and RAM3 switch cyclically in a fixed order, functioning as the input buffer 1041, memory 1044, and output buffer 1048, respectively.

[0064] The lower part of Figure 9 is a diagram illustrating the correspondence between the sequence shown in the upper part of Figure 9 and the functional blocks assigned to RAM1, RAM2, and RAM3 according to the SSB timing. In the lower part of Figure 9, the function of the input buffer unit 1041 is shown as hatching in A, the function of the memory unit 1044 is shown as hatching in B, and the function of the output buffer unit 1048 is shown as hatching in C, thus distinguishing them from each other.

[0065] As can be seen from the correspondence between the upper and lower sections of Figure 9, the FFT control unit 1042 cyclically switches and assigns the input buffer section 1041, memory section 1044, and output buffer section 1048 to RAM1, RAM2, and RAM3 respectively in response to the arrival of SSB timing, and operates them continuously as a loop. Therefore, with a small circuit size, it is possible to hold continuously arriving baseband time-axis waveform signals without losing any, perform FFT calculations, and output baseband frequency-axis waveform signals.

[0066] Figure 10 shows an example of the functional configuration of the FFT control unit 1042 according to the first embodiment. The FFT control unit 1042 measures the elapsed time of the clock period based on the input SSB timing and controls other functional blocks constituting the FFT unit 1004 according to the elapsed time. The FFT control unit 1042 includes an input counter control unit 1421, an input buffer control unit 1422, a clock counter control unit 1423, a stage counter control unit 1424, an input data selection control unit 1425, an output data selection control unit 1426, a memory control unit 1427, a coefficient data generation control unit 1428, an output counter control unit 1429, and an output buffer control unit 142a.

[0067] The input counter control unit 1421 controls an input counter that receives SSB timing and measures the elapsed time of the clock period. The input counter is initialized with SSB timing, and the input counter value is updated each time a clock is applied. When it reaches a predetermined value, the counting operation stops.

[0068] The input buffer control unit 1422 receives an input counter value from the input counter control unit 1421 and controls the input buffer unit 1041 according to the input counter value.

[0069] The clock counter control unit 1423 receives SSB timing and stage counter values ​​from the stage counter control unit 1424 and controls a clock counter that measures the elapsed time of the clock period.

[0070] The stage counter control unit 1424 receives SSB timing and clock counter values ​​from the clock counter control unit 1423, and controls a stage counter that measures the progress of stages in which butterfly operations are repeatedly applied during FFT calculations.

[0071] The input data selection control unit 1425 receives clock counter values ​​from the clock counter control unit 1423 and stage counter values ​​from the stage counter control unit 1424, and controls the input data selection unit 1043 according to the clock counter values ​​and stage counter values.

[0072] The output data selection control unit 1426 receives a clock counter value from the clock counter control unit 1423 and a stage counter value from the stage counter control unit 1424, and controls the output data selection unit 1047 according to the clock counter value and the stage counter value.

[0073] The memory control unit 1427 receives a clock counter value from the clock counter control unit 1423 and a stage counter value from the stage counter control unit 1424, and controls the memory unit 1044 according to the clock counter value and the stage counter value.

[0074] The coefficient data generation control unit 1428 receives clock counter values ​​from the clock counter control unit 1423 and stage counter values ​​from the stage counter control unit 1424, and controls the coefficient data generation unit 1046 according to the clock counter values ​​and stage counter values.

[0075] The output counter control unit 1429 receives SSB timing input and controls an output counter that measures the elapsed time of the clock period. The output counter is initialized with SSB timing, and the output counter value is updated each time a clock is applied. When a predetermined value is reached, the counting operation stops.

[0076] The output buffer control unit 142a receives an output counter value from the output counter control unit 1429 and controls the output buffer unit 1048 according to the output counter value.

[0077] Figure 11 shows an example of a timing chart for the input counter of the FFT control unit 1042 according to the first embodiment.

[0078] In the input counter control unit 1421, the input counter is initialized with the input SSB timing, and the clock counter value is updated each time a clock is applied. When the input counter reaches a predetermined value, the counting operation is stopped.

[0079] The input buffer control unit 1422 controls the RAM provided in the input buffer unit 1041 according to the input counter value, and holds the baseband time-domain waveform signal in a predetermined area of ​​the RAM. When the input counter reaches a predetermined value, all of the baseband time-domain waveform signal that is Fourier transformed by the FFT unit 1004 is held in the RAM provided in the input buffer unit 1041.

[0080] Figure 12 shows an example of a timing chart for the clock counter and stage counter of the FFT control unit 1042 according to the first embodiment.

[0081] In the clock counter control unit 1423, the clock counter is initialized with the input SSB timing, and the clock counter value is updated each time a clock signal is applied. When a predetermined value is reached, the clock counter value is initialized, and the counting operation is repeated. Furthermore, when the input stage counter value reaches a predetermined value, the counting operation of the clock counter is stopped.

[0082] In the stage counter control unit 1424, the stage counter is initialized at the input SSB timing, and the stage counter value is updated each time the clock counter value reaches a predetermined value and is initialized. When the stage counter value reaches the predetermined value, the counting operation is stopped.

[0083] The input data selection control unit 1425, the output data selection control unit 1426, the memory control unit 1427, and the coefficient data generation control unit 1428 execute control according to the clock counter value and the stage counter value to sequentially read data from the memory unit 1044, apply the butterfly calculation in the butterfly calculation unit 1049 via the input data selection unit 1043, and write the butterfly calculation result to the memory unit 1044 via the output data selection unit 1047.

[0084] This series of operations—data reading, butterfly calculation, and data writing—is performed once for all the data held in the RAM of the memory unit 1044, completing one calculation stage. Repeating this calculation stage a predetermined number of times completes the Fourier transform from the time-axis waveform signal to the frequency-axis waveform signal.

[0085] Figure 13 shows an example of a timing chart for the output counter control unit 1429 according to the first embodiment.

[0086] In the output counter control unit 1429, the output counter is initialized with the input SSB timing, and the clock counter value is updated each time a clock is applied. When the output counter reaches a predetermined value, the counting operation is stopped.

[0087] The output buffer control unit 142a controls the RAM provided in the output buffer unit 1048 according to the output counter value and reads the baseband frequency axis waveform signal from a predetermined area of ​​the RAM. When the output counter reaches a predetermined value, the reading of the baseband frequency axis waveform signal is completed.

[0088] Next, we will describe the various processes performed by the master station device 10 according to the first embodiment.

[0089] Figure 14 is a flowchart showing an example of the TDD detection process according to the first embodiment.

[0090] Here, it is assumed that the distributed antenna system 1 is receiving either a DL signal or an UL signal, both analog radio signals. Furthermore, it is assumed that the distributed antenna system 1 can refer to identification information indicating whether the TDD detection processing period is enabled or disabled, as well as the DL / UL configuration information of the TDD.

[0091] The signal receiving unit 1001 performs AD conversion, frequency down conversion, and sampling rate conversion on the input analog signal to acquire a baseband time-domain waveform signal as the received signal (step S1).

[0092] Next, the time waveform calculation unit 1002 performs time waveform processing (step S2). Specifically, the time waveform calculation unit 1002 detects the PSS signal placed at the beginning of the SSB from the baseband signal and outputs the detected timing as the SSB timing to the FFT unit 1004. It also determines which of the multiple PSS code sequences the detected PSS signal corresponds to and notifies the SSS detection unit 1016 of the frequency waveform calculation unit 1005 of this as the NID2, which is the cell identifier of the physical layer.

[0093] Next, the FFT unit 1004 extracts the SSB from the baseband signal based on the notified SSB timing, performs a Fourier transform, and notifies the frequency waveform calculation unit 1005 of the completion of the FFT processing (step S3).

[0094] Next, the frequency waveform calculation unit 1005 detects the SSB index, which indicates whether or not the SSB is positioned within the transmission cycle (step S4).

[0095] The signal receiving unit 1001, the time waveform calculation unit 1002, the FFT unit 1004, and the frequency waveform calculation unit 1005 repeatedly execute steps S1 to S4 as long as the TDD detection process is valid (step S5; Yes).

[0096] When the TDD detection processing period ends (step S5; No), the switching timing estimation unit 1006 estimates where the SSB is located within the transmission cycle, and estimates the switching timing between downlink and uplink communication within the transmission cycle from this SSB location and known TDD DL / UL configuration information (step S6).

[0097] Figure 15 is a flowchart showing an example of time waveform processing according to the first embodiment. That is, the flowchart shown in Figure 15 is the time waveform processing of step S2 shown in Figure 14.

[0098] The time waveform calculation unit 1002 determines whether the TDD detection processing period is valid or not (step S21). If the TDD detection processing period is invalid (step S21; No), the time waveform calculation unit 1002 terminates the time waveform processing. On the other hand, if the TDD detection processing period is valid (step S21; Yes), the time waveform calculation unit 1002 executes subsequent processing.

[0099] Next, the time waveform calculation unit 1002 calculates a correlation value by performing a correlation calculation between the baseband time-axis waveform signal and a plurality of PSS code sequences (step S22).

[0100] Next, the time waveform calculation unit 1002 determines whether a significant correlation value exists among the multiple correlation calculations (step S23). A significant correlation value here may be one that exceeds a predetermined threshold or one that is the largest since the start of time waveform processing. If no significant correlation value exists, the process returns to step S21 (step S23; No), and if one exists, the subsequent processing is executed (step S23; Yes).

[0101] Next, the time waveform calculation unit 1002 stores the PSS code sequence number corresponding to the significant correlation value as NID2 (step S24).

[0102] Next, the time waveform calculation unit 1002 stores the system time for which a significant correlation value was calculated as the PSS correlation detection time (step S25).

[0103] Next, the time waveform calculation unit 1002 notifies the FFT process shown in step S3 of the system time for which a significant correlation value has been calculated as the SSB timing (step S26).

[0104] Figure 16 is a flowchart showing an example of the FFT process according to the first embodiment. That is, the flowchart shown in Figure 16 is the FFT process of step S3 shown in Figure 14.

[0105] The FFT unit 1004 determines whether or not SSB timing has been notified (step S31). If no notification has been received (step S31; No), the FFT unit 1004 terminates the FFT process. On the other hand, if a notification has been received (step S31; Yes), the FFT unit 1004 executes subsequent processing.

[0106] Next, the FFT unit 1004 switches the three RAMs, which operate as functional blocks of the input buffer unit 1041, the memory unit 1044, and the output buffer unit 1048, in a predetermined order (step S32).

[0107] Next, the FFT unit 1004 starts parallel processing of FFT input processing (step S33), FFT calculation processing (step S34), and FFT output processing (step S35).

[0108] Next, when the FFT unit 1004 has completed all of the FFT input processing (step S33), FFT calculation processing (step S34), and FFT output processing (step S35), it notifies the frequency waveform processing unit shown in step S4 of the completion of the FFT processing (step S36).

[0109] Figure 17 is a flowchart showing an example of the FFT input processing according to the first embodiment. That is, the flowchart shown in Figure 17 is the FFT input processing of step S33 shown in Figure 16.

[0110] The FFT unit 1004 initializes the input counter value of the input counter control unit 1421 of the FFT control unit 1042 to 0 (step S331).

[0111] Next, the FFT unit 1004 determines whether the input counter value of the input counter control unit 1421 of the FFT control unit 1042 has reached a predetermined value (step S332). If it has reached the predetermined value (step S332; Yes), the FFT unit 1004 terminates the FFT input processing. On the other hand, if it has not reached the predetermined value (step S332; No), the FFT unit 1004 executes subsequent processing.

[0112] Next, the FFT unit 1004 calculates the write address of the RAM that operates as the input buffer unit 1041 (step S333).

[0113] Next, the FFT unit 1004 writes the time-axis waveform signal to the RAM, which operates as the input buffer unit 1041 (step S334).

[0114] Next, the FFT unit 1004 updates the input counter value of the input counter control unit 1421 of the FFT control unit 1042 by adding 1, and returns to step S332 (step S335).

[0115] Figure 18 is a flowchart showing an example of the FFT calculation process according to the first embodiment. That is, the flowchart shown in Figure 18 is the FFT calculation process of step S34 shown in Figure 16.

[0116] The FFT unit 1004 initializes the stage counter value of the stage counter control unit 1424 of the FFT control unit 1042 to 0 (step S341).

[0117] Next, the FFT unit 1004 determines whether the stage counter value of the stage counter control unit 1424 of the FFT control unit 1042 has reached a predetermined value (step S342). If it has reached the predetermined value (step S342; Yes), the FFT unit 1004 terminates the FFT calculation process. On the other hand, if it has not reached the predetermined value (step S342; No), the FFT unit 1004 executes subsequent processing.

[0118] Next, the FFT unit 1004 initializes the clock counter value of the clock counter control unit 1423 of the FFT control unit 1042 to 0 (step S343).

[0119] Next, the FFT unit 1004 determines whether the clock counter value of the clock counter control unit 1423 of the FFT control unit 1042 has reached a predetermined value (step S344). If it has reached the predetermined value (step S344; Yes), the FFT unit 1004 updates the stage counter value of the stage counter control unit 1424 of the FFT control unit 1042 by adding 1, and returns to step S342 (step S347). On the other hand, if it has not reached the predetermined value (step S344; No), the FFT unit 1004 executes the subsequent processing.

[0120] Next, the FFT unit 1004 performs butterfly processing (step S345).

[0121] Next, the FFT unit 1004 updates the clock counter value of the clock counter control unit 1423 of the FFT control unit 1042 by adding 1, and returns to step S344 (step S346).

[0122] Figure 19 is a flowchart showing an example of the butterfly arithmetic process according to the first embodiment. That is, the flowchart shown in Figure 19 is the butterfly arithmetic process of step S345 shown in Figure 18.

[0123] The FFT unit 1004 calculates the read address of the RAM, which operates as the memory unit 1044 (step S3451).

[0124] Next, the FFT unit 1004 reads the data stored in the RAM, which operates as the memory unit 1044 (step S3452).

[0125] Next, the FFT unit 1004 selects data to input to the data calculation unit 1045 from the read data (step S3453).

[0126] Next, the FFT unit 1004 calculates coefficient data to be input to the data calculation unit 1045 (step S3454).

[0127] Next, the FFT unit 1004 performs a butterfly operation on the data and coefficient data input to the data calculation unit 1045 (step S3455).

[0128] Next, the FFT unit 1004 selects data to write to the memory unit 1044 from the data after the butterfly operation. (Step S3456).

[0129] Next, the FFT unit 1004 calculates the write address of the RAM, which operates as the memory unit 1044 (step S3457).

[0130] Next, the FFT unit 1004 writes the data after the butterfly operation to the RAM, which operates as the memory unit 1044. (Step S3458).

[0131] Figure 20 is a flowchart showing an example of the FFT output processing according to the first embodiment. That is, the flowchart shown in Figure 20 is the FFT output processing of step S35 shown in Figure 16.

[0132] The FFT unit 1004 initializes the output counter value of the output counter control unit 1429 of the FFT control unit 1042 to 0 (step S351).

[0133] Next, the FFT unit 1004 determines whether the output counter value of the output counter control unit 1429 of the FFT control unit 1042 has reached a predetermined value (step S352). If it has reached the predetermined value (step S352; Yes), the FFT unit 1004 terminates the FFT output process. On the other hand, if it has not reached the predetermined value (step S352; No), the FFT unit 1004 executes subsequent processing.

[0134] Next, the FFT unit 1004 calculates the read address of the RAM that operates as the output buffer unit 1048 (step S353).

[0135] Next, the FFT unit 1004 reads the frequency axis waveform signal from the RAM, which operates as the output buffer unit 1048 (step S354).

[0136] Next, the FFT unit 1004 updates the output counter value of the output counter control unit 1429 of the FFT control unit 1042 by adding 1, and returns to step S352 (step S355).

[0137] Figure 21 is a flowchart showing an example of frequency waveform processing according to the first embodiment. That is, the flowchart shown in Figure 21 is the frequency waveform processing of step S4 shown in Figure 14.

[0138] The frequency waveform calculation unit 1005 determines whether or not a notification of completion of FFT processing has been received (step S41). If no notification is received (step S41; No), the frequency waveform calculation unit 1005 terminates the frequency waveform processing.

[0139] On the other hand, if there is a notification (step S41; Yes), the frequency waveform calculation unit 1005 executes the subsequent processing.

[0140] Next, the SSS detection unit 1016 executes the SSS detection process (step S42).

[0141] Next, the frequency waveform calculation unit 1005 determines whether or not a significant SSS has been detected (step S43). Here, significance is determined when the similarity with the SSS sequence calculated in the SSS detection process exceeds a predetermined threshold and is the maximum. If no significant SSS exists (step S43; No), the frequency waveform calculation unit 1005 terminates the frequency waveform processing. On the other hand, if one exists (step S43; Yes), the frequency waveform calculation unit 1005 executes the subsequent processing.

[0142] Next, the DMRS detection unit 1017 performs DMRS detection processing (step S44).

[0143] Next, the frequency waveform calculation unit 1005 determines whether or not a significant DMRS has been detected (step S45). Here, significance is determined when the similarity with the DMRS sequence calculated in the DMRS detection process exceeds a predetermined threshold and is the maximum. If no significant DMRS exists (step S45; No), the frequency waveform calculation unit 1005 terminates the frequency waveform processing. On the other hand, if one exists (step S45; Yes), the frequency waveform calculation unit 1005 executes the subsequent processing.

[0144] Next, the frequency waveform calculation unit 1005 notifies the switching timing estimation process shown in step S6 of the completion of frequency waveform processing (step S46).

[0145] Figure 22 is a flowchart showing an example of the SSS detection process according to the first embodiment. That is, the flowchart shown in Figure 22 is the SSS detection process of step S42 shown in Figure 21.

[0146] The SSS detection unit 1016 extracts the frequency components in which the SSS signal is located from the frequency axis waveform signal (step S421).

[0147] Next, the SSS detection unit 1016 reads out the NID2 stored in step S24 (step S422).

[0148] Next, the SSS detection unit 1016 generates a plurality of SSS sequences and an SSS index for identifying the SSS sequences based on the NID2 (step S423).

[0149] Next, the SSS detection unit 1016 detects the SSS sequence that is most similar to the extracted SSS signal (step S424).

[0150] Next, the SSS detection unit 1016 stores the SSS index corresponding to the SSS sequence with the highest similarity as NID1 (step S425).

[0151] Figure 23 is a flowchart showing an example of the DMRS detection process according to the first embodiment. That is, the flowchart shown in Figure 23 is the DMRS detection process of step S44 shown in Figure 21.

[0152] The DMRS detection unit 1017 extracts the frequency components in which the DMRS signal is located from the frequency axis waveform signal (step S441).

[0153] Next, the DMRS detection unit 1017 reads out the NID1 stored in step S425 (step S442).

[0154] Next, the DMRS detection unit 1017 generates a plurality of DMRS sequences and an ibar_SSB index for identifying the DMRS sequences based on the NID1 (step S443).

[0155] Next, the DMRS detection unit 1017 detects the DMRS sequence that is most similar to the extracted DMRS signal (step S444).

[0156] Next, the DMRS detection unit 1017 stores the ibar_SSB index corresponding to the DMRS sequence with the highest similarity as ibar_SSB (step S445).

[0157] Figure 24 is a flowchart showing an example of the switching timing estimation process according to the first embodiment. That is, the flowchart shown in Figure 24 is the switching timing estimation process of step S6 shown in Figure 14.

[0158] The switching timing estimation unit 1006 determines whether or not a notification has been received that the frequency waveform processing is complete (step S61). If no notification is received (step S61; No), the switching timing estimation unit 1006 terminates the switching timing estimation process. On the other hand, if a notification is received (step S61; Yes), the switching timing estimation unit 1006 executes subsequent processing.

[0159] Next, the switching timing estimation unit 1006 reads out the PSS correlation detection time stored in step S25 (step S62).

[0160] Next, the switching timing estimation unit 1006 reads out the ibar_SSB stored in step S445 (step S63).

[0161] Next, the switching timing estimation unit 1006 estimates the position of the frame in which the detected SSB was located, based on known SSB placement patterns and the ibar_SSB read in step S63 (step S64).

[0162] Next, the switching timing estimation unit 1006 estimates the timing at which the next TDD switching will occur based on the known TDD DL / UL configuration information, the PSS correlation detection time read in step S62, and the SSB frame position estimated in step S64 (step S65).

[0163] As described above, in the communication device according to the first embodiment, the signal receiving unit 1001 receives an OFDM signal and converts it into a baseband time-axis waveform signal. The time-axis waveform calculation unit 1002 extracts a portion of the time-axis waveform signal output from the signal receiving unit 1001 and calculates a correlation value between the extracted signal and a known signal. The FFT unit 1004 performs an FFT on the time-axis waveform signal output from the signal receiving unit 1001. The frequency-axis waveform calculation unit 1005 extracts a portion of the frequency-axis waveform signal output from the FFT unit 1004 and calculates the degree of similarity between the extracted signal and a known signal. The switching timing estimation unit 1006 estimates the switching timing between uplink and downlink communication in its own device based on the calculation results of the frequency-axis waveform calculation unit 1005. In the series of calculation stages in which the FFT is performed, the FFT unit 1004 repeatedly uses a single calculation circuit and a data storage circuit by time multiplexing.

[0164] In other words, the FFT unit 1004 cyclically switches and assigns the input buffer unit 1041, memory unit 1044, and output buffer unit 1048 to RAM1, RAM2, and RAM3 respectively in response to the arrival of SSB timing, and operates them continuously as a loop. Therefore, with a small circuit size, it is possible to hold continuously arriving baseband time-axis waveform signals without losing any, perform FFT calculations, and output baseband frequency-axis waveform signals. As a result, in a TDD system that switches between DL communication and UL communication at predetermined intervals, it is possible to realize a communication device that can detect the switching timing between UL and DL with a small circuit size.

[0165] The effects of the communication device according to the first embodiment will be described in more detail with reference to the FFT unit 1004a of Comparative Example 1.

[0166] Figure 25 shows an example of the functional configuration of the FFT unit 1004a according to Comparative Example 1. The FFT unit 1004a includes an input buffer unit 1041, an FFT control unit 1042, a butterfly calculation unit 1049, a memory unit 1044, and an output buffer unit 1048. The butterfly calculation unit 1049 includes a coefficient data generation unit 1046 and a data calculation unit 1045.

[0167] Comparing Figure 25 with Figure 8, Figure 25 lacks the input data selection unit 1043 and output data selection unit 1047 shown in Figure 8. On the other hand, Figure 25 has a pipeline-type structure in which multiple butterfly calculation units 1049 and memory units 1044 are connected in series. This is a circuit configuration in which each of the FFT calculation stages shown in Figure 12 is equipped with a dedicated butterfly calculation unit and memory unit.

[0168] As shown in Figure 25, if each FFT calculation stage is equipped with a dedicated butterfly calculation unit and memory unit, then circuits such as multipliers and adders for realizing butterfly calculations, circuits for generating coefficients called rotation factors, and RAM for holding the results of the calculation stages are required for each FFT calculation stage. As a result, the circuit size of the FFT unit 1004a increases, and consequently, the circuit size of the switching timing generation unit 153 that generates the switching timing between UL and DL of TDD also increases.

[0169] In contrast, the FFT section 1004 of the communication device according to this embodiment has a loop-type structure that repeatedly uses a single butterfly calculation unit 1049 and a memory unit 1044. Therefore, the circuit size of the FFT section 1004 is kept small, and as a result, the circuit size of the switching timing generation unit 153 can be reduced.

[0170] (Second Embodiment) In the first embodiment, as shown in Figure 8, the FFT unit 1004 has three blocks that have the function of holding data: an input buffer unit 1041, a memory unit 1044, and an output buffer unit 1048. Three RAM systems are allocated to these three functional blocks, as shown in Figure 9, and the operating functional block is switched sequentially. This makes it possible to hold continuously arriving baseband time-axis waveform signals without losing any data, perform FFT calculations, and output baseband frequency-axis waveform signals.

[0171] The period during which the input buffer unit 1041 functions cannot be shortened because it is necessary to hold the baseband time-domain waveform signal for the period specified by the transmission method. On the other hand, the periods during which the memory unit 1044 and output buffer unit 1048 function depend on the circuit implementation that realizes the function of the FFT unit 1004, and can be shortened. Therefore, there is room to reduce the number of RAM systems by shortening the periods during which the memory unit 1044 and output buffer unit 1048 function.

[0172] In the following description, the butterfly arithmetic unit 1049, the memory unit 1044, the FFT control unit 1042, and the output buffer unit 1048 are assumed to operate at a higher operating frequency than the input buffer unit 1041.

[0173] Figure 26 shows an example of switching of functional blocks in the FFT unit 1004 according to the second embodiment. As shown in the upper part of Figure 26, the RAM provided in the FFT unit 1004 is divided into two parts, RAM1 and RAM2, and the functional blocks that operate according to SSB timing are switched.

[0174] In other words, during the first SSB timing, RAM1 functions as an input buffer 1041, and RAM2 waits for operation. During the second SSB timing, RAM1 initially functions as a memory 1044, and once its operation as a memory 1044 is complete, it functions as an output buffer 1048. Meanwhile, RAM2 functions as an input buffer 1041. Then, during the third SSB timing, RAM1 again functions as an input buffer 1041, and RAM2 initially functions as a memory 1044, and once its operation as a memory 1044 is complete, it functions as an output buffer 1048.

[0175] As shown in the lower part of Figure 26, in response to the arrival of the SSB timing, the two RAM systems switch between the functions of the input buffer unit 1041, the memory unit 1044, and the output buffer unit 1048. The timing chart when functioning as the input buffer unit 1041 is the same as the timing chart shown in Figure 11. On the other hand, the timing charts when functioning as the memory unit 1044 and the output buffer unit 1048 show that the operating period is halved compared to Figures 12 and 13. This reduction in operating period is achieved by increasing the operating frequency of the related circuits. Then, as soon as the operation as the memory unit 1044 is completed, the operation as the output buffer unit 1048 begins immediately, and the operation as the output buffer unit 1048 is completed before the next SSB timing arrives.

[0176] Figure 27 is a flowchart showing an example of the FFT process according to the second embodiment. That is, the flowchart shown in Figure 27 is a different example from Figure 16, which corresponds to the FFT process in step S3 shown in Figure 14.

[0177] The FFT unit 1004 determines whether or not SSB timing has been notified (step S31a). If no notification has been received (step S31a; No), the FFT unit 1004 terminates the FFT process. On the other hand, if a notification has been received (step S31a; Yes), the FFT unit 1004 executes subsequent processing.

[0178] Next, the FFT unit 1004 switches between the functional block of the input buffer unit 1041 and the two RAMs that operate as the functional blocks of the memory unit 1044 and the output buffer unit 1048 (step S32a).

[0179] Next, the FFT unit 1004 starts parallel processing of the FFT input processing (step S33a) and the FFT calculation processing (step S34a). The content of the FFT input processing (step S33a) is the same as the FFT input processing shown in Figure 17. Also, the content of the FFT calculation processing (step S34a) is the same as the FFT calculation processing shown in Figure 18.

[0180] Next, once the FFT calculation process (step S34a) is completed, the FFT unit 1004 executes the FFT output process (step S35a). The content of the FFT output process (step S35a) is the same as the FFT output process shown in Figure 20.

[0181] Next, when the FFT unit 1004 has completed all of the FFT input processing (step S33a), FFT calculation processing (step S34a), and FFT output processing (step S35a), it notifies the frequency waveform processing unit shown in step S4 of the completion of the FFT processing (step S36a).

[0182] As described above, in the communication device according to the second embodiment, the FFT unit 1004 holds continuously arriving baseband time-axis waveform signals without missing any, performs FFT calculations, and outputs baseband frequency-axis waveform signals. The FFT unit 1004 according to the second embodiment has a loop-type structure that repeatedly uses a single butterfly calculation unit 1049 and a memory unit 1044.

[0183] Furthermore, the combined period during which the data storage circuit in the memory unit 1044 operates as a memory unit and the period during which the data storage circuit in the output buffer unit 1048 operates as an output buffer unit does not exceed the period during which the data storage circuit in the input buffer unit 1041 operates as an input buffer unit. Moreover, one data storage circuit serves both as a data storage circuit in the memory unit 1044 and as a data storage circuit in the output buffer unit 1048.

[0184] In other words, in the FFT unit 1004 of the second embodiment, the three functional blocks that hold the data described in the first embodiment are configured with two RAM systems. As a result, the circuit size of the FFT unit 1004 is kept smaller than that of the FFT unit 1004 of the first embodiment, and consequently, the circuit size of the switching timing generation unit 153 can also be made smaller. As a result, in a TDD system that switches between DL communication and UL communication at predetermined intervals, a communication device can be realized that can detect the switching timing between UL and DL with a small circuit size.

[0185] Furthermore, the program executed by the master station device 10 of this embodiment is provided as an installable or executable file, recorded on a computer-readable recording medium such as a DVD (Digital Versatile Disk), USB (Universal Serial Bus) memory, or SSD (Solid State Drive).

[0186] Furthermore, the program may be configured to be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Alternatively, the program may be configured to be provided or distributed via a network such as the Internet.

[0187] Alternatively, the program may be configured to be pre-installed in ROM or similar media before being provided.

[0188] (Note) The following technologies are disclosed in accordance with the description of the embodiments below. (1) A distributed antenna system comprising a master station device connected to a base station, and one or more slave station devices that relay signals between a terminal device communicating with the base station and the master station device, wherein the communication device functions as the master station device or the slave station device and receives an OFDM (Orthogonal Frequency Division Multiplexing) signal transmitted in a time division multiplexing scheme, comprising: a signal receiving unit that receives the OFDM signal and converts it into a baseband time-axis waveform signal; a time waveform calculation unit that extracts a portion of the time-axis waveform signal which is the output of the signal receiving unit and calculates a correlation value between the extracted signal and a known signal; an FFT (Fast Fourier Transform) unit that performs an FFT on the time-axis waveform signal which is the output of the signal receiving unit; a frequency waveform calculation unit that extracts a portion of the frequency-axis waveform signal which is the output of the FFT unit and calculates the degree of similarity between the extracted signal and a known signal; and a switching timing estimation unit that estimates the switching timing between uplink and downlink communication in the device based on the calculation result of the frequency waveform calculation unit, (1) The FFT unit is a communication device that repeatedly uses a single arithmetic circuit and a data storage circuit by time multiplexing in a series of arithmetic stages that perform a Fourier transform. (2) The signal receiving unit is the communication device according to (1) that receives a PSS (Primary Synchronization Signal), an SSS (Secondary Synchronization Signal), and an SSB (SS / PBCH Block) having a PBCH (Physical Broadcast Channel) including a DMRS (DeModulation of Reference Signal). (3) The FFT unit is the communication device according to (2) that comprises an input buffer unit that holds the SSB included in the time-axis waveform signal, a butterfly arithmetic unit that performs a butterfly arithmetic used to significantly reduce the computational amount of the Fourier transform, a memory unit that holds intermediate data during the Fourier transform, an output buffer unit that holds the frequency-axis waveform signal after the Fourier transform, and a control unit that controls each functional block.(4) The communication device according to (3), wherein the butterfly arithmetic unit and the memory unit are repeatedly used by time multiplexing in a series of arithmetic stages that perform a Fourier transform. (5) The communication device according to (4), wherein the input buffer unit is equipped with a data storage circuit for holding the SSB, the memory unit is equipped with a data storage circuit for holding the intermediate data during the Fourier transform, and the output buffer unit is equipped with a data storage circuit for holding the frequency axis waveform signal after the Fourier transform. (6) The communication device according to (5), wherein the data storage circuit in the input buffer unit functions as a data storage circuit in the memory unit after the operation as the input buffer unit is completed, the data storage circuit in the memory unit functions as a data storage circuit in the output buffer unit after the operation as the memory unit is completed, and the data storage circuit in the output buffer unit functions as a data storage circuit in the input buffer unit after the operation as the output buffer unit is completed. (7) The communication device according to claim (6), wherein the butterfly arithmetic unit operates at a higher operating frequency than the input buffer unit, the memory unit operates at a higher operating frequency than the input buffer unit, the output buffer unit operates at a higher operating frequency than the input buffer unit, the control unit operates at a higher operating frequency than the input buffer unit, and the combined period of the period during which the data storage circuit in the memory unit operates as the memory unit and the period during which the data storage circuit in the output buffer unit operates as the output buffer unit does not exceed the period during which the data storage circuit in the input buffer unit operates as the input buffer unit. (8) The communication device according to claim 7, wherein in the memory unit operating at a higher operating frequency than the input buffer unit and the output buffer unit operating at a higher operating frequency than the input buffer unit, one data storage circuit serves both as a data storage circuit in the memory unit and as a data storage circuit in the output buffer unit.(9) A control method for a communication device that functions as the master station device or the slave station device and receives an OFDM (Orthogonal Frequency Division Multiplexing) signal transmitted in a time division multiplexing scheme, in a distributed antenna system comprising: a master station device connected to a base station; one or more slave station devices that relay signals between a terminal device communicating with the base station and the master station device, the control method comprising: receiving the OFDM signal and converting it into a baseband time-axis waveform signal; extracting a portion of the time-axis waveform signal; calculating a correlation value between the extracted signal and a known signal; performing an FFT (Fast Fourier Transform) on the time-axis waveform signal; extracting a portion of the frequency-axis waveform signal obtained by the FFT; calculating the degree of similarity between the extracted signal and a known signal; and estimating the switching timing between uplink and downlink communication based on the calculation result of the degree of similarity, wherein in the FFT, a single arithmetic circuit and a data storage circuit are repeatedly used by time multiplexing in a series of arithmetic stages that perform the Fourier transform.(10) A control program for a distributed antenna system comprising a master station device connected to a base station, and one or more slave station devices that relay signals between a terminal device communicating with the base station and the master station device, wherein a communication device that functions as the master station device or the slave station device and receives an OFDM (Orthogonal Frequency Division Multiplexing) signal transmitted in a time division multiplexing scheme is configured to function as: a signal receiving unit that receives the OFDM signal and converts it into a baseband time-axis waveform signal; a time waveform calculation unit that extracts a portion of the time-axis waveform signal which is the output of the signal receiving unit and calculates a correlation value between the extracted signal and a known signal; an FFT (Fast Fourier Transform) unit that performs an FFT on the time-axis waveform signal which is the output of the signal receiving unit; a frequency waveform calculation unit that extracts a portion of the frequency-axis waveform signal which is the output of the FFT unit and calculates the degree of similarity between the extracted signal and a known signal; and a switching timing estimation unit that estimates the switching timing between uplink and downlink communication in the device based on the calculation result of the frequency waveform calculation unit. A program that causes the FFT section to function by repeatedly using a single arithmetic circuit and a data storage circuit through time multiplexing in a series of arithmetic stages that perform Fourier transforms.

[0189] 1...Distributed antenna system, 10...Master unit (MU), 11...Higher-side input / output unit, 12...Lower-side input / output unit, 13...Downlink processing unit, 14...Uplink processing unit, 15...Control unit, 20...Relay unit (HU), 30...Slave unit (RU), 40...Transmission line, 50...Base station, 60...Terminal unit, 70...Antenna, 153...Switching timing generation unit, 154...Switching unit, 1001...Signal receiving unit, 1002...Time waveform calculation unit, 1004...FFT (Fourier transform) Transform section, 1005...Frequency waveform calculation section, 1006...Switching timing estimation section, 1010...ADC section, 1011...Carrier frequency conversion section, 1012...Sampling rate conversion section, 1041...Input buffer section, 1042...FFT control section, 1043...Input data selection section, 1044...Memory section, 1045...Data calculation section, 1046...Coefficient data generation section, 1047...Output data selection section, 1048...Output buffer section, 1049...Butterfly calculation section, 1421...Input counter control section, 1422...Input buffer control section, 1423...Clock counter control section, 1424...Stage counter control section, 1425...Input data selection control section, 1426...Output data selection control section, 1427...Memory control section, 1428...Coefficient data generation control section, 1429...Output counter control section, 142a...Output buffer control section

Claims

1. A distributed antenna system comprising a master station device connected to a base station, and one or more slave station devices that relay signals between a terminal device communicating with the base station and the master station device, wherein the communication device functions as the master station device or the slave station device and receives an OFDM (Orthogonal Frequency Division Multiplexing) signal transmitted in a time division multiplexing scheme, comprising: a signal receiving unit that receives the OFDM signal and converts it into a baseband time-axis waveform signal; a time waveform calculation unit that extracts a portion of the time-axis waveform signal which is the output of the signal receiving unit and calculates a correlation value between the extracted signal and a known signal; an FFT (Fast Fourier Transform) unit that performs an FFT on the time-axis waveform signal which is the output of the signal receiving unit; a frequency waveform calculation unit that extracts a portion of the frequency-axis waveform signal which is the output of the FFT unit and calculates the degree of similarity between the extracted signal and a known signal; and a switching timing estimation unit that estimates the switching timing between uplink and downlink communication in the device based on the calculation result of the frequency waveform calculation unit, The FFT section is a communication device that repeatedly uses a single arithmetic circuit and a data storage circuit through time multiplexing in a series of arithmetic stages that perform a Fourier transform.

2. The communication device according to claim 1, wherein the signal receiving unit receives a PSS (Primary Synchronization Signal), an SSS (Secondary Synchronization Signal), and an SSB (SS / PBCH Block) having a PBCH (Physical Broadcast Channel) including a DMRS (DeModulation of Reference Signal).

3. The communication device according to claim 2, wherein the FFT unit comprises an input buffer unit that holds the SSB included in the time-axis waveform signal, a butterfly operation unit that performs a butterfly operation used to significantly reduce the computational complexity of the Fourier transform, a memory unit that holds intermediate data during the Fourier transform, an output buffer unit that holds the frequency-axis waveform signal after the Fourier transform, and a control unit that controls each functional block.

4. The communication device according to claim 3, wherein the butterfly arithmetic unit and the memory unit are repeatedly used by time multiplexing in a series of arithmetic stages that perform a Fourier transform.

5. The communication device according to claim 4, wherein the input buffer section comprises a data storage circuit for holding the SSB, the memory section comprises a data storage circuit for holding the intermediate data during the Fourier transform, and the output buffer section comprises a data storage circuit for holding the frequency axis waveform signal after the Fourier transform.

6. The communication device according to claim 5, wherein the data storage circuit provided in the input buffer section functions as a data storage circuit provided in the memory section after the operation as the input buffer section is completed, the data storage circuit provided in the memory section functions as a data storage circuit provided in the output buffer section after the operation as the memory section is completed, and the data storage circuit provided in the output buffer section functions as a data storage circuit provided in the input buffer section after the operation as the output buffer section is completed.

7. The communication device according to claim 6, wherein the butterfly arithmetic unit operates at a higher operating frequency than the input buffer unit, the memory unit operates at a higher operating frequency than the input buffer unit, the output buffer unit operates at a higher operating frequency than the input buffer unit, the control unit operates at a higher operating frequency than the input buffer unit, and the combined period of the period during which the data storage circuit in the memory unit operates as the memory unit and the period during which the data storage circuit in the output buffer unit operates as the output buffer unit does not exceed the period during which the data storage circuit in the input buffer unit operates as the input buffer unit.

8. The communication device according to claim 7, wherein the memory unit operates at a higher operating frequency than the input buffer unit, and the output buffer unit operates at a higher operating frequency than the input buffer unit, and a single data storage circuit serves both as a data storage circuit in the memory unit and as a data storage circuit in the output buffer unit.

9. A control method for a communication device that functions as either the master station or the slave station and receives an OFDM (Orthogonal Frequency Division Multiplexing) signal transmitted in a time-division multiplexing scheme, in a distributed antenna system comprising: a master station connected to a base station; one or more slave stations that relay signals between a terminal device communicating with the base station and the master station, the control method comprising: receiving the OFDM signal and converting it into a baseband time-axis waveform signal; extracting a portion of the time-axis waveform signal; calculating a correlation value between the extracted signal and a known signal; performing an FFT (Fast Fourier Transform) on the time-axis waveform signal; extracting a portion of the frequency-axis waveform signal obtained by the FFT; calculating the degree of similarity between the extracted signal and a known signal; and estimating the switching timing between uplink and downlink communication based on the calculation result of the degree of similarity, wherein in the FFT, a single arithmetic circuit and a data storage circuit are repeatedly used by time-multiplexing in a series of arithmetic stages that perform the Fourier transform.

10. A control program for a distributed antenna system comprising a master station device connected to a base station, and one or more slave station devices that relay signals between a terminal device communicating with the base station and the master station device, wherein a communication device that functions as the master station device or the slave station device and receives an OFDM (Orthogonal Frequency Division Multiplexing) signal transmitted in a time division multiplexing scheme is configured to function as: a signal receiving unit that receives the OFDM signal and converts it into a baseband time-axis waveform signal; a time waveform calculation unit that extracts a portion of the time-axis waveform signal which is the output of the signal receiving unit and calculates a correlation value between the extracted signal and a known signal; an FFT (Fast Fourier Transform) unit that performs an FFT on the time-axis waveform signal which is the output of the signal receiving unit; a frequency waveform calculation unit that extracts a portion of the frequency-axis waveform signal which is the output of the FFT unit and calculates the degree of similarity between the extracted signal and a known signal; and a switching timing estimation unit that estimates the switching timing between uplink and downlink communication in the device based on the calculation result of the frequency waveform calculation unit. A program that causes the FFT section to function by repeatedly using a single arithmetic circuit and a data storage circuit through time multiplexing in a series of arithmetic stages that perform Fourier transforms.

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