A low power multi-core shared floating point unit structure

Abstract

This invention discloses a low-power multi-core shared floating-point unit structure, relating to the field of digital signal processing technology. It addresses the technical problem that existing floating-point units occupy a large silicon wafer area, leading to increased manufacturing costs and reduced yields after configuring one floating-point unit for each core. The low-power multi-core shared floating-point unit structure of this invention includes a processor core, shared floating-point units, and a multi-level logarithmic interconnect network. The processor core and the shared floating-point units communicate via an auxiliary processing unit interface designed for tightly coupled accelerators. The processor core executes application streams and dispatches floating-point calculation instructions to the shared floating-point unit cluster. The shared floating-point units perform floating-point operations as a shared computing resource time-division multiplexed by multiple processor cores. The multi-level logarithmic interconnect network dynamically and scalably connects all processor cores and shared floating-point units to form a communication path.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and more specifically, to a low-power multi-core shared floating-point unit structure. Background Technology

[0002] In recent years, the development of artificial intelligence algorithms or digital signal processing tasks on sensors has placed higher demands on the computational power requirements of algorithms and the power consumption of devices. To enhance computing power, existing technologies equip each core in multi-core chips with an independent Floating Point Unit (FPU). Multiple cores can simultaneously execute different floating-point intensive tasks or collaboratively process different parts of the same large task. Each core does not need to wait for shared floating-point unit resources, thus greatly improving overall throughput. From a microarchitectural perspective, designing the floating-point unit as a standard functional unit of the core is much simpler than designing a shared floating-point unit that requires complex arbitration and scheduling logic. The core can directly send floating-point instructions to its own dedicated floating-point unit.

[0003] However, floating-point units, especially those supporting high precision (such as double precision) and complex operations (such as fused multiply-add, FMA), occupy a considerable amount of silicon area. Configuring a floating-point unit for each core would significantly increase the number of transistors and the physical size of the entire chip. A larger chip area would reduce the number of chips that can be produced per wafer, thus increasing manufacturing costs. At the same time, the yield would also decrease due to the increased chip area. Summary of the Invention

[0004] The purpose of this invention is to provide a low-power multi-core shared floating-point unit structure to solve the technical problem that existing floating-point units occupy a large silicon wafer area, leading to increased manufacturing costs and reduced yields after configuring one floating-point unit for each core. In view of this, this invention achieves this through the following solution.

[0005] This invention provides a low-power multi-core shared floating-point unit architecture, including a processor core, a shared floating-point unit, and a multi-level logarithmic interconnect network; wherein: A cluster architecture is formed by connecting multiple processor cores and multiple shared floating-point units through the multi-level logarithmic interconnect network; the processor cores and the shared floating-point units communicate through an auxiliary processing unit interface designed for tightly coupled accelerators; The processor core is used to execute application streams and dispatch floating-point calculation instructions to the shared floating-point unit cluster. The shared floating-point unit is used as a common computing resource that is time-division multiplexed by multiple processor cores to perform floating-point operations. The multi-level logarithmic interconnect network is used to dynamically and scalably connect all processor cores and shared floating-point units to form a communication path.

[0006] Compared with existing technologies, the low-power multi-core shared floating-point unit structure of the present invention can be composed of processor cores, shared floating-point units, and a multi-level logarithmic interconnect network. This multi-core shared floating-point unit structure can form a cluster architecture by connecting multiple processor cores and multiple shared floating-point units through the multi-level logarithmic interconnect network. The processor cores and shared floating-point units communicate through an auxiliary processing unit (APU) interface designed for tightly coupled accelerators. Furthermore, in this multi-core shared floating-point unit structure, the processor cores can be used to execute application streams and dispatch floating-point calculation instructions to the shared floating-point unit cluster. The shared floating-point units can be used as common computing resources time-division multiplexed by multiple processor cores to perform floating-point operations. The multi-level logarithmic interconnect network can be used to dynamically and scalably connect all processor cores and shared floating-point units to form a communication path. Based on the above-described technical solution of this invention, the number of shared floating-point units can be significantly reduced, thereby significantly saving die area and reducing manufacturing costs. Furthermore, the saved die area can be used to add more processor cores, increase cache size, and reduce costs and power consumption. Specifically, within the same die area, more integer processor cores or dedicated accelerators (such as AI accelerators) can be integrated, thereby improving overall throughput. The saved area can be used to expand the capacity of the Last Level Cache (LLC), improving the memory access performance of all processor cores, which is highly beneficial for data-intensive applications. Furthermore, a smaller die area means that more chips can be cut from a single wafer, directly reducing unit cost. At the same time, smaller chips typically also mean lower static power consumption and higher yield. Furthermore, in workloads with unbalanced floating-point loads (e.g., some threads are integer-intensive, and a few are floating-point-intensive), the shared architecture of this invention (i.e., multi-core shared floating-point unit structure) ensures that scarce floating-point unit resources are fully utilized, with almost no idle time, and the fewer transistors in the chip directly result in lower power consumption. In summary, the technical solution of the present invention solves the technical problem that existing floating-point units occupy a large silicon wafer area, and that configuring one floating-point unit for each core leads to increased manufacturing costs and reduced yield.

[0007] Furthermore, the low-power multi-core shared floating-point unit structure of the present invention also includes an arbitrator; The arbitrator is configured at the input of the shared floating-point unit; The arbitrator is used to grant access requests from multiple processor cores to the same shared floating-point unit.

[0008] Furthermore, in the low-power multi-core shared floating-point unit structure of the present invention, the arbitrator dynamically grants the processor core access rights to the shared floating-point unit based on the current request status and scheduling policy.

[0009] Furthermore, in the low-power multi-core shared floating-point unit structure of the present invention, the scheduling strategy includes a fair round-robin scheduling strategy and a weighted round-robin strategy with configurable priority.

[0010] Furthermore, in the low-power multi-core shared floating-point unit structure of the present invention, the auxiliary processing unit interface includes a valid signal, a ready signal, and a tag signal; wherein: The valid signal is driven by the processor core, indicating that the request information is valid; The ready signal is driven by the shared floating-point unit, indicating that it is ready to receive new requests or return calculation results; The tag signal serves as an instruction marker, uniquely identifying the correspondence between requests and responses, and supports out-of-order return mechanisms.

[0011] Furthermore, in the low-power multi-core shared floating-point unit structure of the present invention, the request information includes address, opcode, and operand.

[0012] Furthermore, in the low-power multi-core shared floating-point unit structure of the present invention, the auxiliary processing unit interface adopts a two-way handshake mechanism to transmit data.

[0013] Furthermore, in the low-power multi-core shared floating-point unit structure of the present invention, the multi-core shared floating-point unit structure has 8 processor cores and 4 shared floating-point units; wherein: Each pair of processor cores is connected to a shared floating-point unit via a multi-level logarithmic interconnect network; Each of the shared floating-point units is equipped with an arbitrator at its input.

[0014] Furthermore, in the low-power multi-core shared floating-point unit structure of the present invention, the workflow of the multi-core shared floating-point unit structure includes: In the first stage, the processor core reads floating-point instructions, decodes them, pulls up the valid signal and sends the opcode; this process takes one cycle. In the second stage, the shared floating-point unit performs floating-point operations; In the third stage, the shared floating-point unit returns the result and the flag bit, and at the same time pulls the ready signal high.

[0015] Furthermore, in the low-power multi-core shared floating-point unit structure of the present invention, the floating-point operations include floating-point addition and floating-point multiplication. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of a low-power multi-core shared floating-point unit structure according to the present invention. Detailed Implementation

[0017] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0018] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0019] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0020] Floating-point units, especially those supporting high precision (such as double precision) and complex operations (such as fused multiply-add, FMA), occupy a considerable amount of silicon area. Configuring a floating-point unit for each core will significantly increase the number of transistors and the physical size of the entire chip. A larger chip area will reduce the number of chips that can be produced per wafer, thus increasing manufacturing costs. At the same time, the yield will also decrease due to the increase in chip area.

[0021] To address the aforementioned technical problems, this invention provides a low-power multi-core shared floating-point unit architecture, comprising a processor core, a shared floating-point unit, and a multi-level logarithmic interconnect network; wherein: A cluster architecture is formed by connecting multiple processor cores and multiple shared floating-point units through the multi-level logarithmic interconnect network; the processor cores and the shared floating-point units communicate through an auxiliary processing unit interface designed for tightly coupled accelerators; The processor core is used to execute application streams and dispatch floating-point calculation instructions to the shared floating-point unit cluster; the shared floating-point unit is used to perform floating-point operations as a common computing resource that is time-division multiplexed by multiple processor cores; the multi-level logarithmic interconnect network is used to dynamically and scalably connect all processor cores and shared floating-point units to form a communication path.

[0022] With the above technical solution, the low-power multi-core shared floating-point unit structure of the present invention can be composed of a processor core, a shared floating-point unit, and a multi-level logarithmic interconnect network. This multi-core shared floating-point unit structure can form a cluster architecture by connecting multiple processor cores and multiple shared floating-point units through the multi-level logarithmic interconnect network. The processor core and the shared floating-point unit communicate through an auxiliary processing unit (APU) interface designed for tightly coupled accelerators. Furthermore, in this multi-core shared floating-point unit structure, the processor core can be used to execute application streams and dispatch floating-point calculation instructions to the shared floating-point unit cluster. The shared floating-point unit can be used as a shared computing resource time-division multiplexed by multiple processor cores to perform floating-point operations. The multi-level logarithmic interconnect network can be used to dynamically and scalably connect all processor cores and shared floating-point units to form a communication path. Based on the above-described technical solution of this invention, the number of shared floating-point units can be significantly reduced, thereby significantly saving die area and reducing manufacturing costs. Furthermore, the saved die area can be used to add more processor cores, increase cache size, and reduce costs and power consumption. Specifically, within the same die area, more integer processor cores or dedicated accelerators (such as AI accelerators) can be integrated, thereby improving overall throughput. The saved area can be used to expand the capacity of the Last Level Cache (LLC), improving the memory access performance of all processor cores, which is highly beneficial for data-intensive applications. Furthermore, a smaller die area means that more chips can be cut from a single wafer, directly reducing unit cost. At the same time, smaller chips typically also mean lower static power consumption and higher yield. Furthermore, in workloads with unbalanced floating-point loads (e.g., some threads are integer-intensive, and a few are floating-point-intensive), the shared architecture of this invention (i.e., multi-core shared floating-point unit structure) ensures that scarce floating-point unit resources are fully utilized, with almost no idle time, and the fewer transistors in the chip directly result in lower power consumption. In summary, the technical solution of the present invention solves the technical problem that existing floating-point units occupy a large silicon wafer area, and that configuring one floating-point unit for each core leads to increased manufacturing costs and reduced yield.

[0023] To better understand the present invention, the following specific embodiments further illustrate the content of the present invention, but the content of the present invention is not limited to the following embodiments.

[0024] Example 1 This embodiment provides a low-power multi-core shared floating-point unit architecture, including a processor core, a shared floating-point unit, and a multi-level logarithmic interconnect network; wherein: A cluster architecture is formed by connecting multiple processor cores and multiple shared floating-point units through a multi-level logarithmic interconnect network; the processor cores and shared floating-point units communicate through an APU interface designed for tightly coupled accelerators; Furthermore, in this embodiment, the APU interface uses a bidirectional handshake mechanism to transmit data. The APU interface includes a valid signal, a ready signal, and a tag signal; wherein: The valid signal is driven by the processor core, indicating that the request information is valid; the request information includes the address, opcode, and operands. The ready signal is driven by the shared floating-point unit, indicating that it is ready to receive new requests or return calculation results; The tag signal serves as a command marker, uniquely identifying the correspondence between requests and responses, and supports out-of-order return mechanisms.

[0025] Furthermore, in this embodiment, the processor core is used to execute application streams and dispatch floating-point calculation instructions to the shared floating-point unit cluster; Furthermore, in this embodiment, the shared floating-point unit is used as a common computing resource that is time-division multiplexed by multiple processor cores to perform floating-point operations; Furthermore, in this embodiment, a multi-level logarithmic interconnect network is used to dynamically and scalably connect all processor cores and shared floating-point units to form a communication path.

[0026] Example 2 This embodiment provides a low-power multi-core shared floating-point unit architecture, including a processor core, a shared floating-point unit, a multi-level logarithmic interconnect network, and an arbitrator; wherein: A cluster architecture is formed by connecting multiple processor cores and multiple shared floating-point units through a multi-level logarithmic interconnect network; the processor cores and shared floating-point units communicate through an APU interface designed for tightly coupled accelerators; Furthermore, in this embodiment, the APU interface uses a bidirectional handshake mechanism to transmit data. The APU interface includes a valid signal, a ready signal, and a tag signal; wherein: The valid signal is driven by the processor core, indicating that the request information is valid; the request information includes the address, opcode, and operands. The ready signal is driven by the shared floating-point unit, indicating that it is ready to receive new requests or return calculation results; The tag signal serves as a command marker, uniquely identifying the correspondence between requests and responses, and supports out-of-order return mechanisms.

[0027] Furthermore, in this embodiment, the processor core is used to execute application streams and dispatch floating-point calculation instructions to the shared floating-point unit cluster; Furthermore, in this embodiment, the shared floating-point unit is used as a common computing resource that is time-division multiplexed by multiple processor cores to perform floating-point operations; Furthermore, in this embodiment, a multi-level logarithmic interconnect network is used to dynamically and scalably connect all processor cores and shared floating-point units to form a communication path.

[0028] Furthermore, in this embodiment, the arbitrator is configured at the input of the shared floating-point unit; the arbitrator is used to grant access requests from multiple processor cores to the same shared floating-point unit; the arbitrator dynamically grants access permissions to the shared floating-point unit to the processor cores based on the current request status and scheduling policy, the scheduling policy including a fair round-robin scheduling policy and a weighted round-robin policy with configurable priority.

[0029] Example 3 Please see Figure 1 This embodiment provides a low-power multi-core shared floating-point unit architecture, which includes a processor core (i.e., Figure 1 Core in the middle), shared floating-point unit (i.e. Figure 1 The FPU), multi-level logarithmic interconnection network and arbitrator (i.e. Figure 1 The arbitration unit in the cluster connects multiple processor cores and multiple shared floating-point units through a multi-level logarithmic interconnect network to form a cluster architecture; the processor cores and shared floating-point units communicate through the APU interface designed for tightly coupled accelerators. In the above cluster architecture, n processor cores share m floating-point units (FPUs) and are connected through a multi-level logarithmic interconnect network (such as Omega or Butterfly network) to form an interconnect structure. The complexity of this interconnect structure in this embodiment only increases by O(log N), meaning that the complexity of the interconnect structure (such as latency, area, and wiring resources) increases proportionally to log₂N as the number of cores N increases. This offers significant advantages in physical layout and timing. For example, in an 8-processor core (Core 0 to Core 7) and 4 shared floating-point units (FPU 0 to FPU 3) structure, the multi-level logarithmic interconnect network can achieve flexible mapping relationships: Core 0 and Core 4 can share FPU 0, Core 1 and Core 5 can share FPU 1, and so on. This multi-level logarithmic interconnect network consists of multiple levels of 2×2 switching units, enabling dynamic routing of request and response data packets to achieve non-blocking or low-blocking communication.

[0030] Furthermore, in this embodiment, the processor core and the shared floating-point unit communicate via a lightweight APU interface designed specifically for tightly coupled accelerators. This APU interface primarily includes the following signals: valid: Driven by the processor core, it indicates that the request information such as address, opcode, and operands is valid; ready: Driven by a shared floating-point unit, it indicates that the system is ready to receive new requests or return calculation results; tag: Instruction identifier, used to uniquely identify the correspondence between requests and responses, and supports out-of-order completion mechanism; In addition, it includes data / control signals such as opcode, write data (wdata), and read data (rdata).

[0031] Furthermore, the aforementioned APU interface uses a simple two-way handshake mechanism (valid / ready handshake) to transmit data. Compared to the general AXI protocol, its state machine is simpler, the number of channels is fewer, the transmission latency is lower, and the area required for hardware implementation is significantly reduced, making it very suitable for high-frequency, low-latency communication between the processor core and dedicated functional units.

[0032] Furthermore, in this embodiment, when multiple processor cores contend for the same FPU through the interconnect network, scheduling is performed by an arbitrator (i.e., arbitration unit) located at the FPU input. Specifically, a fair round-robin scheduling or a configurable priority weighted round-robin strategy can be adopted to avoid starvation of low-priority cores and meet the needs of real-time, high-requirement cores while ensuring fairness. The arbitrator dynamically grants access permissions based on the current request status and scheduling strategy, thereby achieving efficient time-division multiplexing of FPU resources. The multi-core shared floating-point unit structure of this embodiment significantly reduces chip area and power consumption through resource reuse, while efficient interconnect and lightweight protocols ensure computing performance with minimal overhead.

[0033] Furthermore, in Figure 1 In this design, multiple processor cores access the same floating-point unit (FPU) through a multi-level logarithmic interconnect network, with adjacent cores mapped to different FPUs. This design employs a partially interconnected, statically mapped FPU to the core, ensuring that one core (or a group of cores) always accesses the same physical FPU. This is achieved by using a fair polling strategy and propagating the ready signal only to one processor core, thus preventing other competing processor cores from accessing the FPU concurrently. An arbitration unit arbitrates simultaneous access to the FPU. The interconnect between the processor core and the FPU uses the APU interface. The following is the specific workflow of the multi-core shared floating-point unit structure in this embodiment: Phase 1: The processor core reads the floating-point (FP) instruction, decodes it, pulls up the valid signal and sends the opcode. This process takes one cycle. The second stage: floating-point units perform floating-point operations, such as floating-point addition or floating-point multiplication; In the third stage, the floating-point unit returns the result and the flag bit, and at the same time pulls ready=1 high.

[0034] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0035] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-power multi-core shared floating-point unit structure, characterized in that, It includes a processor core, a shared floating-point unit, and a multi-level logarithmic interconnect network; among which: A cluster architecture is formed by connecting multiple processor cores and multiple shared floating-point units through the multi-level logarithmic interconnect network; the processor cores and the shared floating-point units communicate through an auxiliary processing unit interface designed for tightly coupled accelerators; The processor core is used to execute application streams and dispatch floating-point calculation instructions to the shared floating-point unit cluster. The shared floating-point unit is used as a common computing resource that is time-division multiplexed by multiple processor cores to perform floating-point operations. The multi-level logarithmic interconnect network is used to dynamically and scalably connect all processor cores and shared floating-point units to form a communication path.

2. The low-power multi-core shared floating-point unit structure according to claim 1, characterized in that, The multi-core shared floating-point unit structure also includes an arbitrator; The arbitrator is configured at the input of the shared floating-point unit; The arbitrator is used to grant access requests from multiple processor cores to the same shared floating-point unit.

3. The low-power multi-core shared floating-point unit structure according to claim 2, characterized in that, The arbitrator dynamically grants the processor core access to the shared floating-point unit based on the current request status and scheduling policy.

4. The low-power multi-core shared floating-point unit structure according to claim 3, characterized in that, The scheduling strategies include a fair round-robin scheduling strategy and a weighted round-robin strategy with configurable priorities.

5. The low-power multi-core shared floating-point unit structure according to claim 1, characterized in that, The auxiliary processing unit interface includes valid, ready, and tag signals; wherein: The valid signal is driven by the processor core, indicating that the request information is valid; The ready signal is driven by the shared floating-point unit, indicating that it is ready to receive new requests or return calculation results; The tag signal serves as an instruction marker, uniquely identifying the correspondence between requests and responses, and supports out-of-order return mechanisms.

6. The low-power multi-core shared floating-point unit structure according to claim 5, characterized in that, The request information includes the address, opcode, and operands.

7. The low-power multi-core shared floating-point unit structure according to claim 1 or 5, characterized in that, The auxiliary processing unit interface uses a two-way handshake mechanism to transmit data.

8. The low-power multi-core shared floating-point unit structure according to claim 7, characterized in that, The multi-core shared floating-point unit architecture has 8 processor cores and 4 shared floating-point units; wherein: Each pair of processor cores is connected to a shared floating-point unit via a multi-level logarithmic interconnect network; Each of the shared floating-point units is equipped with an arbitrator at its input.

9. The low-power multi-core shared floating-point unit structure according to claim 8, characterized in that, The workflow of the multi-core shared floating-point unit structure includes: In the first stage, the processor core reads floating-point instructions, decodes them, pulls up the valid signal and sends the opcode; this process takes one cycle. In the second stage, the shared floating-point unit performs floating-point operations; In the third stage, the shared floating-point unit returns the result and the flag bit, and at the same time pulls the ready signal high.

10. The low-power multi-core shared floating-point unit structure according to claim 9, characterized in that, The floating-point operations include floating-point addition and floating-point multiplication.

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