An adaptive load optimization method for a resonant gate drive circuit
By employing a combination of digital signal processing chip and low-dropout regulator chip in the resonant gate drive circuit, the switching loss, conduction loss, and gate drive loss are optimized, solving the problems of high conduction loss and drive circuit loss in the prior art, and achieving more efficient load optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOUTHEAST UNIV
- Filing Date
- 2023-04-10
- Publication Date
- 2026-07-03
AI Technical Summary
Existing adaptive load optimization schemes have failed to effectively reduce the conduction losses of power MOSFETs and the losses of drive circuits, especially under different load current conditions, they suffer from large drive losses and circuit complexity.
An adaptive load optimization method suitable for resonant gate drive circuits is adopted. By combining a digital signal processing chip and a low-dropout regulator chip with a four-channel driver and a resonant gate driver, the switching loss, conduction loss and gate drive loss are optimized. The gate drive circuit voltage and precharge time are adjusted by using data tables and lookup algorithms of DSP chips.
It achieves loss optimization under different load conditions, reduces switching losses, conduction losses and gate drive losses, simplifies the drive circuit structure, and reduces additional power consumption and complexity.
Smart Images
Figure CN116388577B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to switching power supplies, and more particularly to an adaptive load optimization method suitable for resonant gate drive circuits, belonging to the technical field of power generation, transformation or distribution. Background Technology
[0002] With the continuous development of portable devices, miniaturization and high efficiency have become the goals that the field of switching power supplies constantly pursues and develops. Increasing the switching frequency can reduce the size and weight of switching power supplies, but at the same time, it is accompanied by a sharp increase in switching losses, such as gate drive losses, switching losses, and conduction losses.
[0003] To reduce gate drive losses, resonant gate drive technology has been proposed. Resonant gate drivers recover energy from the gate capacitance through LC resonance, resulting in lower gate drive losses and significant advantages in high-frequency applications.
[0004] For high-frequency, low-voltage, and high-current applications, current-source resonant drivers (CSDs) have been proposed. The most significant advantage of CSD technology is its ability to significantly reduce switching losses in power MOSFETs at switching frequencies up to MHz. CSDs establish a current source to charge and discharge the gate capacitance of the power MOSFET, thus significantly reducing the propagation effect of the common-source inductance on the switching process, thereby significantly reducing switching time and switching losses (Zhiliang Zhang, et al. "Optimal Design of Resonant Gate Driver for Buck Converter Based on a New Analytical Loss Model." IEEE Transactions on Power Electronics, vol. 23, no. 2, Mar. 2008, pp. 653–66.).
[0005] For CSD technology, high drive current typically results in lower switching losses. When the power MOSFET carries higher current, a stronger drive current is desirable to further reduce switching losses. However, higher drive current also leads to higher drive cycle losses, and the power MOSFET's conduction losses increase with higher load current. This results in a trade-off between switching losses, gate drive losses, and conduction losses.
[0006] To address this, an adaptive current source driver (CSD) scheme has been proposed to improve CSD performance and achieve optimized design by reducing switching losses and gate drive losses under different load currents (Zhiliang Zhang, et al. "Adaptive Current Source Drivers for Efficiency Optimization of High Frequency Synchronous Buck Converters." 2011 IEEE Energy Conversion Congress and Exposition, Energy Conversion Congress and Exposition (ECCE), 2011 IEEE, Sept. 2011, pp. 1181–87. EBSCOhost, https: / / doi.org / 10.1109 / ECCE.2011.6063910.). In CSD, the drive current increases linearly with the increase of drive voltage; therefore, an adaptive drive voltage will also generate an adaptive drive current. This paper proposes a simple method to achieve adaptive drive current based on adaptive voltage, implemented by simulating a linear regulator. Its advantages are simplicity and fast response. However, the turn-on and turn-off drive currents in the scheme must be the same, which is not applicable to different turn-on and turn-off conditions. In addition, linear regulators lead to additional losses and high complexity in the drive circuitry.
[0007] A further proposed digital adaptive current source driver (CSD) with discontinuous current source (CS) inductor current was developed (Zhiliang Zhang, et al. "A Digital Adaptive Discontinuous Current Source Driver for High-Frequency Interleaved Boost PFC Converters." IEEE Transactions on Power Electronics, Power Electronics, IEEE Transactions on Power Electronics, vol. 29, no. 3, Mar. 2014, pp. 1298–310. EBSCOhost, https: / / doi.org / 10.1109 / TPEL.2013.2260175.). In the proposed CSD, the turn-on and turn-off drive currents are independent of the duty cycle and switching frequency. The drive current is adjusted by the pre-charging time of the current source inductor. For different load currents during turn-on and turn-off, the power curves of switching losses and drive losses are calculated to select the point of minimum loss, thereby designing the magnitude of the turn-on and turn-off drive currents separately. This scheme uses a digital signal processing chip to achieve adaptive adjustment, reducing the losses caused by the analog regulator and lowering the complexity of the drive circuit. It can also provide more flexible control algorithms to construct different on- and off-drive currents. However, this scheme does not consider the impact of conduction losses and uses a fixed drive voltage, resulting in relatively large drive losses. Summary of the Invention
[0008] Technical Problem: The purpose of this invention is to address the shortcomings in the above-mentioned background technology by providing an adaptive load optimization method suitable for resonant gate drive circuits, thus solving the technical problems of neglecting the conduction loss of power MOSFETs and excessive drive circuit losses in existing adaptive load optimization schemes.
[0009] Technical Solution: This invention is an adaptive load optimization method for resonant gate drive circuits. The method's modular structure includes a main power topology, a resonant gate driver, a four-channel driver, a low-dropout regulator chip, a digital signal processing chip, and resistors. The main power topology outputs a load current I to the digital signal processing chip, which outputs six signals. Specifically, four PWM channels of the digital signal processing chip (PPWM waveform 1, PPWM waveform 2, PPWM waveform 3, and PPWM waveform 4) output four signals to the four-channel driver. The four-channel driver outputs the gate voltage signals of Q1, Q2, Q3, and Q4 to the resonant gate driver; the general-purpose input / output terminals of the digital signal processing chip are connected to the enable terminal of the low-dropout regulator chip; the digital-to-analog converter terminal of the digital signal processing chip is connected to the resonant gate driver through a first and second resistor connected in series, the midpoint of the first and second resistors connected in series is connected to the full-bridge pin of the low-dropout regulator chip, the output voltage terminal of the low-dropout regulator chip is connected to the resonant gate driver, and the resonant gate driver outputs the drive power switch signal to the main power topology.
[0010] In the aforementioned main power topology, multiple power metal-oxide-semiconductor field-effect transistors (MOSFETs) are driven by a resonant gate driver, which consists of four MOSFETs and an isolation transformer. The first and second MOSFETs form a half-bridge, with the midpoint of the half-bridge connected to the same-name terminal on the primary side of the isolation transformer, and drive the fourth switch of the main topology through the midpoint of the bridge arm. The third and fourth MOSFETs also form a half-bridge, with the midpoint of the half-bridge connected to the non-same-name terminal on the primary side of the transformer through a port, and drive the second switch of the main topology.
[0011] The transformer secondary side is equipped with coils to achieve floating ground drive and realize multiple isolated drive designs. When two complementary isolated drives are used, two coils are designed on the secondary side. The same-name terminal of the upper coil is connected to the first gate parasitic capacitance of the first switch in the main topology, and the non-same-name terminal is connected to the other end of the first gate parasitic capacitance to float ground. The non-same-name terminal of the lower coil on the secondary side is connected to the third gate parasitic capacitance of the third switch in the main topology, and the same-name terminal is connected to the other end of the third gate parasitic capacitance to float ground.
[0012] The gate input signals of the four MOSFETs are generated by a digital signal processing chip and then by a four-channel driver. The four MOSFETs are designed to conduct in pairs in a complementary manner. The circuit achieves energy recovery of the gate drive of the main topology through the resonance of the gate parasitic capacitance and the transformer inductance.
[0013] The optimization method described above optimizes the switching loss, conduction loss, and gate drive loss under different MOSFET loads. A data table is pre-stored in the digital signal processing chip, which contains the resonant gate driver voltage and pre-charge time corresponding to the lowest overall loss under different load currents in actual tests. In practical applications, after the digital-to-analog converter samples the load current, it takes the load current value closest to the table, enables the digital signal processing chip to perform table lookup, and obtains the optimized gate drive circuit voltage and pre-charge time.
[0014] The pre-charge time is changed by rewriting the parameter value of the PWM register in the digital signal processing chip; in the next cycle, the digital signal processing chip sends the PWM to the four-channel driver through four PWM channels to drive the resonant gate driver; the duty cycle of the gate drive waveform of one of the MOSFETs of the resonant gate driver is changed, because the other waveforms have the same phase or complementary duty cycles, and the duty cycles and phases of the other waveforms are also determined, thereby changing the pre-charge time of the gates of the four switches in the main topology.
[0015] The resonant gate driver voltage is changed by a digital signal processing chip and a low-dropout regulator chip. The fixed voltage output by the low-dropout regulator chip is connected between a first feedback resistor and a second feedback resistor. The other end of the second feedback resistor is connected to the digital-to-analog converter module of the digital signal processing chip, and the other end of the first feedback resistor is connected to the output terminal of the low-dropout regulator chip. By designing the feedback resistor range, the desired output voltage value of the low-dropout regulator chip can be obtained by changing the output value of the digital-to-analog converter module, thereby driving the resonant gate driver.
[0016] The digital signal processing chip employs a DSP optimization algorithm to refresh the values of its PWM and DAC registers before the start of each cycle, thereby adjusting the precharge time and gate drive circuit voltage in the next cycle. This enables adaptive optimization of the main topology load, allowing for the selection of an appropriate time interval for the next optimization.
[0017] Beneficial effects: The present invention, employing the above technical solution, has the following advantages:
[0018] This invention optimizes the switching loss, conduction loss, and gate drive loss of the main topology under different loads. By enabling the DSP chip to perform a lookup table operation, the optimized gate drive circuit voltage and pre-charge time are obtained. This minimizes the computational load of the optimization algorithm and reduces the additional power consumption of the DSP. Attached Figure Description
[0019] Figure 1 This is the overall module block diagram of the present invention.
[0020] Figure 2The structural diagram of the resonant gate driving module of this invention.
[0021] Figure 3 The main waveform diagram of the resonant gate driving module of this invention.
[0022] Figure 4 This is a flowchart of the adaptive algorithm for the DSP chip of this invention.
[0023] Figure 5 This is the main topology diagram of the present invention. Detailed Implementation
[0024] The technical solution of the invention will now be described in detail with reference to the accompanying drawings.
[0025] To achieve the above-mentioned objective, this invention employs a four-switch resonant gate drive circuit suitable for multi-channel driving, as follows:
[0026] In a specific implementation of this invention, it can be applied to drive the four main switching transistors of an LLC-DCX converter. For example... Figure 1 As shown, the DSP's ADC samples the load current I of the main topology, substitutes it into the overall loss function after mathematical modeling, and then calculates the coordinates of the point where the function reaches its minimum value, thus obtaining the optimized gate drive circuit voltage Vc and pre-charge time T for the next cycle. pre The pulse width modulation waveform 1 (PWM1), pulse width modulation waveform 2 (PWM2), pulse width modulation waveform 3 (PWM3), and pulse width modulation waveform 4 (PWM4) channels are input to a four-channel driver, which in turn drives the first MOSFET Q1, second MOSFET Q2, third MOSFET Q3, and fourth MOSFET Q4 of the resonant gate driver, thereby driving the power switches of the main power topology. The enable pin of the low dropout regulator chip (LDO) is connected to the GPIO port of the digital signal processing chip (DSP), with an input voltage of VDD and an output voltage of Vc. FB The fixed voltage value output by the pin means that the voltage at the midpoint between the first feedback resistor R1 and the second feedback resistor R2 is a fixed value. The lower end of the second feedback resistor R2 is connected to the DAC output of the digital signal processing chip (DSP), and the upper end of the first feedback resistor R1 is connected to the output port of the low-dropout regulator chip (LDO). The output voltage of the LDO is Vc, which is then connected to a resonant gate driver to provide the input voltage. The resistances of the first feedback resistor R1 and the second feedback resistor R2 can be designed in a certain ratio, so that the desired output voltage Vc value can be obtained by adjusting the DAC output register value.
[0027] The structure of the resonant gate drive module in this solution is as follows: Figure 2As shown in the diagram, there are four MOSFETs: Q1, Q2, Q3, and Q4. Their gates are connected to the gate voltages Vg1, Vg2, Vg3, and Vg4 of Q1, respectively. MOSFETs Q1 and Q2 form a half-bridge, and Q3 and Q4 form another half-bridge. The source of MOSFET Q1 is connected to port Vgs4 and to the same-name terminal of the primary winding P1 of the transformer. The drain of MOSFET Q4 is connected to port Vgs2 and to the non-same-name terminal of the primary winding P1 of the transformer. The parasitic gate capacitances Cgs1, Cgs2, Cgs3, and Cgs4 of the first, second, and third switching transistors are respectively defined by the following parameters: Vgs1-VHB1, Vgs2, Vgs3-VHB2, and Vgs4. The fourth gate parasitic capacitance Cgs4 of the fourth switching transistor is connected in parallel across the second MOSFET Q2, the second gate parasitic capacitance Cgs2 of the second switching transistor is connected in parallel across the fourth MOSFET Q4, the first gate parasitic capacitance Cgs1 of the first switching transistor is connected in parallel across the first secondary side P2, and the third gate parasitic capacitance Cgs3 of the third switching transistor is connected in parallel across the second secondary side P3. The current value on the primary winding is set to I. L The current flows in from the same-name terminal. The current value on the first secondary side P2 is set to I1, flowing out from the same-name terminal. The current value on the second secondary side P3 is set to I2, flowing in from the same-name terminal. The gates of the second switch S2 and the fourth switch S4 in the main topology are interconnected with the drain connection port Vgs2 of the fourth MOSFET Q4 (the port driven by the resonant gate) and the source connection port Vgs4 of the first MOSFET Q1, respectively. The gate of the first switch S1 in the main topology is connected to the positive terminal of the first gate parasitic capacitance Cgs1, and the first half-bridge of the main topology is connected to the negative terminal of the first gate parasitic capacitance Cgs1. The gate of the third switch in the main topology is connected to the positive terminal of the third gate parasitic capacitance Cgs3, and the second half-bridge of the main topology is connected to the negative terminal of the third gate parasitic capacitance Cgs3.
[0028] exist Figure 2 In this circuit, the four PWM signals generated by the digital signal processing (DSP) chip are input to the gate driver module. The output ports are connected to the gate voltages Vg1 (Q1), Vg2 (Q2), Vg3 (Q3), and Vg4 (Q4) respectively to drive the four MOSFETs of the resonant gate driver. The output voltage Vc of the low-dropout regulator (LDO) chip is connected to the drains of the first MOSFET Q1 and the third MOSFET Q3 to provide the charging voltage. The remaining components are connected to... Figure 1 The descriptions are the same.
[0029] The main waveforms of the resonant gate driving module of this invention are as follows: Figure 3 As shown in the figure. The horizontal axis represents time t, and the vertical axis represents the gate-source voltage values of the first MOSFET (Vg1-VH1), the second MOSFET (Vg2), the third MOSFET (Vg3-VH2), and the fourth MOSFET (Vg4). L I1 is the current flowing into the same terminal of P1, I2 is the current flowing out of the same terminal of the first secondary side P2, and I3 is the current flowing into the same terminal of the second secondary side P3. Vgs2 and Vgs4 are the gate-source voltages of the second and fourth switches in the main topology, respectively, and Vgs1-VHB1 and Vgs3-VHB2 are the gate-source voltages of the first and third switches in the main topology, respectively.
[0030] As can be seen from the waveform diagram, the circuit can be divided into eight different operating modes due to different input signals, and the resonant circuit is in different states in each mode. Specifically, states t0 to t1 are the pre-charge states before the first and fourth switches turn off, and also the pre-charge states before the second and third switches begin to conduct; states t4 to t5 are the pre-charge states before the second and third main switches turn off, and also the pre-charge states before the first and fourth switches begin to conduct. The time for these pre-charge states can be set to the same T. pre Therefore, to change the precharge time, the duty cycle of the gate drive waveform of the first MOSFET Q1 can be changed, that is, the duty cycle register of the PWM1 channel of the digital signal processing chip DSP can be changed. In addition, a certain dead time must be ensured.
[0031] The adaptive algorithm of the digital signal processing chip (DSP) of this invention is as follows: Figure 4 As shown. To reduce computational load and improve algorithm speed, the ADC can sample the main topology load current I every few cycles. A data table is pre-stored in the digital signal processing chip (DSP). The table contains the gate drive circuit voltage and pre-charge time corresponding to the lowest overall loss under different load currents in actual tests. These are empirical values. In practical applications, after the ADC module samples the load current, it takes the load current value closest to the one in the table, enabling the DSP chip to perform a lookup operation to obtain the optimized T. pre And Vc. Finally, update the duty cycle and phase in each PWM register of the digital signal processing chip (DSP) to match the optimized T. pre Update the DAC register value so that the output voltage of the low dropout regulator chip (LDO) matches the optimized Vc.
[0032] The DSP optimization algorithm can refresh the values of the PWM and DAC registers of the DSP before the start of each cycle, thereby adjusting the precharge time and gate drive circuit voltage in the next cycle. This enables adaptive optimization of the main topology load and allows for the selection of an appropriate time interval for the next optimization.
[0033] The LLC-DCX used in the specific embodiment of this invention has the following structural diagram: Figure 5 As shown.
Claims
1. An adaptive load optimization method suitable for resonant gate drive circuits, characterized in that, The module structure of this method includes a main power topology (1), a resonant gate driver (2), a four-channel driver (3), a low-dropout regulator chip (LDO), a digital signal processing chip (DSP), and resistors. The main power topology (1) outputs a load current I to the digital signal processing chip (DSP). The digital signal processing chip (DSP) outputs six signals, of which four PWM channels of the digital signal processing chip (DSP), namely, pulse width modulation waveform 1 (PWM1), pulse width modulation waveform 2 (PWM2), pulse width modulation waveform 3 (PWM3), and pulse width modulation waveform 4 (PWM4), output four signals to the four-channel driver (3). The four-channel driver (3) outputs the gate voltages Q1 (Vg1), Q2 (Vg2), Q3 (Vg3), and Q4 (Vg4) signals to the resonant gate driver (2); the general purpose input / output (GPIO) terminal of the digital signal processing chip (DSP) is connected to the enable terminal (EN) of the low dropout regulator chip (LDO); the digital-to-analog converter (DAC) terminal of the digital signal processing chip (DSP) is connected to the resonant gate driver (2) through a series-connected first resistor (R1) and a second resistor (R2), and the midpoint of the series-connected first resistor (R1) and second resistor (R2) is connected to the full-bridge pin (Vg4) of the low dropout regulator chip (LDO). FB The output voltage terminal (V) of the low dropout voltage regulator chip (LDO) C Connect to the resonant gate driver (2), and the resonant gate driver (2) outputs the driving power switch signal to the main power topology (1).
2. The adaptive load optimization method for resonant gate drive circuits according to claim 1, characterized in that, The main power topology (1) is described in which multiple power metal-oxide-semiconductor field-effect transistors (MOSFETs) are driven by a resonant gate driver. The resonant gate driver consists of four MOSFETs and an isolation transformer. The first MOSFET (Q1) and the second MOSFET (Q2) form a half-bridge, the midpoint of which is connected to the same-name terminal of the primary side of the isolation transformer and drives the fourth switch (S4) of the main topology through the midpoint of the bridge arm. The third MOSFET (Q3) and the fourth MOSFET (Q4) also form a half-bridge, the midpoint of which is connected to the non-same-name terminal of the primary side of the transformer through a port and drives the second switch (S2) of the main topology.
3. The adaptive load optimization method for resonant gate drive circuits according to claim 2, characterized in that, The transformer secondary side is equipped with coils to achieve floating ground drive and realize multiple isolated drive designs. When two complementary isolated drives are used, two coils are designed on the secondary side. The same-name terminal of the upper coil is connected to the first gate parasitic capacitance (Cgs1) of the first switch (S1) of the main topology, and the non-same-name terminal is connected to the other end of the first gate parasitic capacitance (Cgs1) to float ground. The non-same-name terminal of the lower coil on the secondary side is connected to the third gate parasitic capacitance (Cgs3) of the third switch (S3) of the main topology, and the same-name terminal is connected to the other end of the third gate parasitic capacitance (Cgs3) to float ground.
4. The adaptive load optimization method for resonant gate drive circuits according to claim 2, characterized in that, The gate input signals of the four MOSFETs are generated by the digital signal processing chip (DSP) and then by the four-channel driver (3). The four MOSFETs are designed to be paired and complementary, and the circuit realizes the energy recovery of the gate drive of the main topology through the resonance of the gate parasitic capacitance and the transformer inductance.
5. The adaptive load optimization method for resonant gate drive circuits according to claim 1, characterized in that, The optimization method optimizes the switching loss, conduction loss, and gate drive loss under different MOSFET loads. A data table is pre-stored in the digital signal processing chip (DSP), which contains the resonant gate driver voltage and pre-charge time corresponding to the lowest overall loss under different load currents in actual tests. In practical applications, after the digital-to-analog converter (DAC) samples the load current, it takes the load current value closest to the table and enables the DSP to perform table lookup to obtain the optimized gate drive circuit voltage and pre-charge time.
6. The adaptive load optimization method for a resonant gate drive circuit according to claim 5, characterized in that, The precharge time is changed by rewriting the parameter value of the PWM register in the digital signal processing chip (DSP); the digital signal processing chip (DSP) sends the PWM to the four-channel driver (3) through the four PWM channels in the next cycle to drive the resonant gate driver (2); the duty cycle of the gate drive waveform of one of the MOSFETs in the resonant gate driver (2) is changed because the other waveforms have the same phase or complementary duty cycles, and the duty cycles and phases of the other waveforms are also determined, thereby changing the precharge time of the gates of the four switching transistors (S4) of the main topology.
7. The adaptive load optimization method for a resonant gate drive circuit according to claim 5, characterized in that, The resonant gate driver voltage is changed by a digital signal processing chip (DSP) and a low-dropout regulator chip (LDO). The fixed voltage output of the LDO is connected between a first feedback resistor (R1) and a second feedback resistor (R2). The other end of the second feedback resistor (R2) is connected to the digital-to-analog converter (DAC) of the DSP, and the other end of the first feedback resistor (R1) is connected to the output terminal of the LDO. By designing the feedback resistor range, the desired output voltage value of the LDO is obtained by changing the output value of the DAC, thereby driving the resonant gate driver.
8. The adaptive load optimization method for a resonant gate drive circuit according to claim 5, characterized in that, The digital signal processing chip (DSP) employs a DSP optimization algorithm to refresh the values of its PWM and DAC registers before the start of each cycle, thereby adjusting the precharge time and gate drive circuit voltage in the next cycle. This enables adaptive optimization of the main topology load and allows for the selection of an appropriate time interval for the next optimization.