A configurable hardware architecture and bit manipulation method based on Banyan networks

Abstract

This invention provides a configurable hardware architecture and bit manipulation method based on Banyan networks, belonging to the fields of digital logic circuits and high-performance computing technology. The invention aims to solve the problems of high hardware overhead, high power consumption, and long latency caused by the need for separate hardware modules—a Banyan network and a barrel shifter—to achieve combined bit-gathering and cyclic shifting operations in existing technologies. The architecture of this invention includes a Banyan network switching module and a control signal generation module. The control signal generation module generates an offset prefix count by superimposing the cyclic shift amount *r* with the original prefix count based on a bit mask, and uses this count to generate control signals for each stage of the Banyan network via an LROTC circuit. Through innovative modifications to the Banyan network control logic, this invention enables a single network to simultaneously perform both advanced bit operations, bit-gathering and cyclic shifting. This invention offers significant advantages such as hardware resource savings, reduced power consumption, improved performance, flexible design, and easy expansion, and can be widely applied in processor design, cryptographic acceleration, digital signal processing, and other fields.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a configurable hardware architecture and bit manipulation method based on Banyan networks. Background Technology

[0002] In modern processors and digital signal processors, performing complex bit-level operations on data words is key to improving performance. One common operation is "gathering" (also known as parallel extraction), which extracts the discrete, valid bits (those with a mask of "1") from the source data word based on a bitmask and compresses them into the lower-order contiguous region of the resulting word. Another common operation is "rotate," which cyclically shifts all bits in the data word to the left or right by a specified number of bits.

[0003] Traditional hardware implementations typically involve designing separate circuit modules for Gather and Rotate, or using a cascaded approach: first, a Banyan network performs the Gather operation, and then a dedicated barrel shifter performs the Rotate operation. While feasible, this approach incurs significant hardware overhead, requiring two independent sets of control logic and routing networks, thus increasing chip area and power consumption.

[0004] Banyan networks, due to their modularity and recursive structure, are often used to implement Gather operations. Their basic principle is to route data to the correct location by controlling each stage of the switching mechanism based on the statistical characteristics of the bitmask (such as the number of prefix "1"s). However, existing Banyan network designs cannot simultaneously and seamlessly integrate cyclic shift functionality into a single network, limiting their use in applications requiring higher area efficiency and energy efficiency. Summary of the Invention

[0005] Therefore, it is necessary to address the existing technical problems by providing a configurable hardware architecture and bit manipulation method based on Banyan networks. This would enable a single network to simultaneously perform two advanced bit operations: bit collection and cyclic shifting.

[0006] To address the problems in the existing technology, the present invention adopts the following technical solution:

[0007] A configurable hardware architecture based on a Banyan network for simultaneously performing bit-by-bit collection and cyclic shift operations on input data, the architecture comprising:

[0008] A Banyan network switching module has n data input terminals and n data output terminals, and is composed of log2(n) cascaded switching stages, each stage consisting of multiple two-input two-output switching switches;

[0009] A control signal generation module, connected to each stage of the Banyan network switching module, is used to generate control signals for each stage of the switching switch based on a bit mask and a cyclic shift amount.

[0010] The control signal generation module includes:

[0011] An offset prefix calculation unit is used to receive the cyclic shift amount r and superimpose the cyclic shift amount r with an original prefix count based on the bit mask to generate an offset prefix count;

[0012] A level control coding unit is used to generate the final control bit for each switching switch in each level based on the offset prefix count.

[0013] Furthermore, the original prefix count based on the bitmask refers to calculating the number of "1"s to the right of each target bit position in the input data within the bitmask.

[0014] Furthermore, the offset prefix calculation unit is specifically used to: for a given level, add the cyclic shift amount r to the original prefix count corresponding to that level to obtain the offset prefix count value.

[0015] Furthermore, the level control coding unit includes an LROTC circuit that receives an initial control string of all "0"s of length determined by the offset prefix count value, and generates the final control word for that level through a cyclic complement operation.

[0016] A bit manipulation method for the configurable hardware architecture includes the following steps:

[0017] Step 1: Receive an n-bit input data word and an n-bit bitmask, as well as a cyclic shift amount r;

[0018] Step 2: Calculate the basic control information required for each level based on the bitmask, wherein the basic control information includes the original prefix count;

[0019] Step 3: Add the cyclic shift amount r to the original prefix count to generate the offset prefix count;

[0020] Step 4: Based on the offset prefix count, generate the control signal for each level of switching by cyclic complement operation;

[0021] Step 5: Input the input data word into the Banyan network switching module and route it under the control of the control signal to obtain an n-bit result data word from the output end, which has simultaneously completed bit-by-bit collection and cyclic shifting.

[0022] Furthermore, the bit-by-bit collection operation refers to extracting the valid bits marked by the bit mask from the input data word and compressing and arranging them at one end of the result word; the cyclic shift operation refers to treating the compressed valid bits as a whole and cyclically shifting them according to the cyclic shift amount r.

[0023] Furthermore, a formal verification tool is used to verify the correctness of the hardware architecture through assertions. The assertions are used to prove that the following equation holds: the result obtained by first collecting the input data bit by bit according to the bit mask and then cyclically shifting it according to the cyclic shift amount is equal to the result obtained by collecting the input data bit by bit according to the bit mask and then adding the cyclic shift amount to the original prefix count and then performing bit collection.

[0024] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method according to any one of claims 5 to 7.

[0025] A digital signal processor comprising the aforementioned configurable hardware architecture based on the Banyan network.

[0026] The beneficial effects of this invention are as follows:

[0027] 1. Saves hardware resources

[0028] Dual-purpose network: A single Banyan network can perform both "bit-by-bit collection" and "circular shift" operations simultaneously, without the need for a separate barrel shifter.

[0029] Simplified control logic: The added hardware is only the adder in the control path, which greatly reduces the core area of ​​the chip.

[0030] 2. Significantly reduced power consumption

[0031] Single-run routing: Data only needs to be routed through the Banyan network once to output the final result, eliminating redundant node flipping and intermediate buffering in the traditional two-module scheme, effectively reducing dynamic power consumption.

[0032] 3. Performance Improvement

[0033] Critical path shortening: By shifting cyclic shift control from the data path to the preprocessing stage of the control path, the data path latency is reduced to the single Banyan network latency, significantly reducing the time required to complete composite operations.

[0034] Increased throughput: Supports higher clock frequencies or higher instruction throughput at the same frequency.

[0035] 4. Flexible and configurable

[0036] Easy mode switching: By inputting an enable signal or a cyclic shift amount r (r=0 for pure collection, r≠0 for compound operation), it can seamlessly meet the needs of multiple instruction sets.

[0037] Low verification cost: Correctness can be proven through concise mathematical assertions of formal verification tools, shortening the functional verification cycle.

[0038] 5. Universal and easily expandable

[0039] Structure preservation: Improvements are focused on control logic preprocessing, without affecting the core structure of the Banyan network, and can be easily extended to arbitrary bit widths.

[0040] Wide range of applications: Suitable for various scenarios requiring complex bit operations, such as processor SIMD instruction sets, cryptographic accelerators, digital signal processing, and communication baseband processing. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the "gather" operation in the background art of this invention. Figure 2 This is a schematic diagram illustrating the principle of implementing the Gather operation using a Banyan network in the background technology of this invention, showing the generation process of control bits at each level. Figure 3 This is a schematic diagram of the combined "bit-by-bit collection" and "cyclic shift" operation that this invention aims to achieve. Figure 4 This is a schematic diagram of RTL code in one embodiment of the present invention, which calls the Banyan structure and enables the rotation function. Figure 5 This is an RTL code diagram used for comparison and verification, showing how to perform Gather first and then Rotate. Figure 6 This is a schematic diagram illustrating the assertions used in this invention to prove the correctness of the architecture using the JasperGold formal verification tool. Figure 7 This is a waveform example diagram of a successful formal verification in one embodiment of the present invention. Figure 8 This is a schematic diagram comparing the generation of control signals using the Banyan network in this invention, which implements the Gather operation and the composite operation (Gather+Rotate). Detailed Implementation

[0042] To further understand the features, technical means, and specific objectives and functions achieved by the present invention, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0043] Technical Terminology Correspondence Table:

[0044] banyan stage Banyan network level or each level of Banyan network stage control signal Level control signal popcnt+ POPCNT plus Mask control bit bitmask position bit Position

[0045] This invention presents a configurable hardware architecture and bit manipulation method based on Banyan networks, aiming to unify the implementation of two advanced bit operations: "gathering" and "rotate".

[0046] First, implement bitwise collection of "gather" based on the banyan structure:

[0047] "Gather" compresses the required discrete significant bits into consecutive significant bits based on the "mask control bit," such as... Figure 1 As shown, the Banyan structure is an n-bit network consisting of lg(n) stages. Each stage comprises n / 2 two-input switches, each constructed using two 2:1 multiplexers. At each stage, data is routed to the correct "track" based on the control switches.

[0048] Furthermore, to implement "gather" using the banyan structure, the method of implementing "gather" is to use "mask control bit" to implement the control switch of each level. The method is as follows: in each local half (L and R) of each level, the control bit of local L will be rotated according to the total number of "1"s on the right side of the "mask control bit".

[0049] like Figure 2 As shown, control bit "0" indicates that the switch performs an exchange, and control bit "1" indicates that the switch performs a pass-through. The control bit in the first-level LL subnet is initially "0". We first rotate and complement the bit according to the number of "1"s (3) in the bit mask R: 0 → 1 → 0 → 1. Then, we rotate and complement the bit by one position according to the number of "1"s (1) in the bit mask LR: 1 → 0. The final control bit is then "0".

[0050] Therefore, to achieve "gathering" based on the "mask control bit", the control bit of each stage of the Banyan network needs to be obtained through two steps:

[0051] a. POPCNT, which is the total number of "1"s to the right of each "position bit" in the "mask control bit".

[0052] b. LROTC (Loop Complementation Operation) is a loop operation that performs a loop complementation on an initial string consisting of k zeros, where the length k of the string is the length of the local R.

[0053] like Figure 2 In the first stage, k is 1; in the second stage, k is 2; and in the third stage, k is 4. Then, POPCNT is used to perform a cyclical complement operation.

[0054] The formula is:

[0055] Level 1:

[0056] LL:LROTC(0 n / 8 , POPCNT(mask[7n / 8-1:0]))

[0057] LR:LROTC(0 n / 8 , POPCNT(mask[5n / 8-1:0]))

[0058] RL: LROTC(0 n / 8 , POPCNT(mask[3n / 8-1:0]))

[0059] RR: LROTC(0 n / 8 , POPCNT(mask[n / 8-1:0]))

[0060] Level 2:

[0061] L:LROTC(0 n / 4 , POPCNT(mask[3n / 4-1:0]))

[0062] R:LROTC(0) n / 4 , POPCNT(mask[n / 4-1:0]))

[0063] Level 3:

[0064] LROTC(0 n / 2 , POPCNT(mask[n / 2-1:0]))

[0065] like Figure 2 As shown:

[0066] Level 1:

[0067] The control bits for LL are:

[0068] LROTC(01 , POPCNT("0101101")) = LROTC(0 1 , 4) = 0, the control bit of LR is: LROTC(0 1 , POPCNT("01101")) = LROTC(0 1 , 3) = 1, the control bit of RL is: LROTC(0 1 , POPCNT("101")) = LROTC(0 1 , 2) = 0, the control bit of RR is: LROTC(0 1 , POPCNT("1")) = LROTC(0 1 , 1) = 1.

[0069] Level 2:

[0070] The control bit for L is:

[0071] LROTC(0 2 , POPCNT("101101")) = LROTC(0 2 , 4) = 00,

[0072] The control bit for R is:

[0073] LROTC(0 2 , POPCNT("01")) = LROTC(0 2 , 1) = 01.

[0074] Level 3:

[0075] The control bit is: LROTC(0) 4 , POPCNT("1101")) = LROTC(0 4 , 3) = 0111.

[0076] Therefore, banyan can simultaneously achieve "gather" and "rotate":

[0077] like Figure 3 As shown, to achieve "gather" and "rotate", it is equivalent to Figure 1 The data for "gather" is shifted. This is because the core of implementing "gather" using banyan is to modify the control bits of the next level instead of explicitly rotating the data cyclically; that is, the control bits are cyclically complemented. Furthermore, "rotating" the entire string also involves explicitly rotating the data cyclically.

[0078] This invention proposes that performing "gather" and then "rotate" on the data is equivalent to calculating pop_cnt in the control bits of "gather" by adding "rotate number" to POPCNT.

[0079] Assuming the string is "D", the number of strings is n, the string mask is "M", "Gather" is PEX (Parallel Extract), and the POPCN in "gather" is "P" (ROT is a circular right shift, where r is the amount of the circular right shift), verify that ROT(PEX(D, M, P), r) = PEX(D, M, P+r), where P+r represents adding the circular shift amount r to the original prefix count POPCN of each position.

[0080] Proof: ROT(PEX(D, M, P), r) == PEX(D, M, P+r), proved using Jaspergold formalism:

[0081] The `banyan` structure is invoked, where "OFFSET_EN" indicates whether to enable simultaneous "gather" and "rotate". The first `banyan` structure is enabled, as shown below. Figure 4 As shown, the output is "gather_rotate_data". The second banyan structure is not enabled, as shown below. Figure 5 As shown, first `gather` is used to obtain "gather data", then the `rotate` function is called to "rotate" "gather data" to obtain "gather_after_rotate_data". A formal assertion is written stating that, given a `rotate` statement, "gather_rotate_data" is equal to "gather_after_rotate_data". The formal statement verifies that this assertion is successful. Figure 6 As shown. Example as follows. Figure 7As shown, the mask bit is "1100_1010", and the init_data is "87654321", meaning the valid data is "8742". If the left shift of rotate is 2, then gather_rotate_data is "56874213", indicating that the valid data "8742" has been shifted left by 2 bits. If rotate in banyan is not enabled, then gather_data is "13568742", indicating that the valid data "8742" is clustered at position 0. Then, rotate the gather data to get gather_after_rotate_data as "56874213".

[0082] Therefore, the example also proves that gather_rotate_data = gather_after_rotate_data. It is formally proven that the banyan structure can simultaneously achieve "gather" and "rotate", that is, ROT(PEX(D, M, P) , r) = PEX(D,M, P+r).

[0083] like Figure 8 As shown, the difference between the hardware structure of a banyan implementing "gather" and the one that simultaneously implements "gather" and "rotate" lies in the implementation of the stage control signal. A traditional banyan requires two banyan structures to implement both "gather" and "rotate". However, we can implement both advanced bit operations simultaneously using only one banyan structure.

[0084] The core idea of ​​this invention lies in the fact that, through in-depth analysis of the control logic for the Gather operation in traditional Banyan networks, it was discovered that the generation of its control bits is only related to the distribution of "1"s in the bitmask (i.e., the prefix count, POPCNT). Furthermore, the overall cyclic shift of data in a Banyan network can be equivalently interpreted as applying a global offset to the control bits. Based on this, this invention proposes an innovative control signal generation method. By modifying the prefix count in the control bit generation process—that is, by adding an offset related to the cyclic shift amount—the same Banyan network can simultaneously perform both the Gather and Rotate operations during data routing.

[0085] Example 1: Hardware Architecture

[0086] refer to Figure 8This embodiment provides a configurable hardware architecture based on the Banyan network. This architecture mainly consists of two parts: a standard Banyan network switching module (such as...) Figure 2 (as shown) and a control signal generation module coupled thereto.

[0087] 1. Banyan network switching module:

[0088] This module is used to process data with a width of n bits. It consists of log2(n) switching stages; for example, for 8-bit data, it contains 3 stages. Each stage consists of n / 2 two-input, two-output switching switches. Each switching switch can be implemented by two 2:1 multiplexers, and its connection relationship from two inputs to two outputs is determined by a control bit ("0" indicates a switching path, "1" indicates a straight-through path).

[0089] 2. Control signal generation module:

[0090] This module is the innovation of this invention. Its function is to generate the correct control signal for each stage of the Banyan network based on the input n-bit mask M (i.e., the "mask control bit" in the background art) and the cyclic shift amount r. (Reference) Figure 2 The traditional Gather control signal generation method shown has the formula LROTC(0 k , POPCNT(sub_mask)). Here, POPCNT calculates the number of "1"s in a specific submask, while LROTC is a loop that takes a string of length k and all "0"s and performs a loop to extract the complement of the submask based on the value of POPCNT.

[0091] The control signal generation module of this invention has been improved upon, for example... Figure 8 As shown on the right. It includes:

[0092] Offset prefix calculation unit: This unit receives the cyclic shift amount r. For each stage of the Banyan network, it adds the original POPCNT value to r, resulting in a new count value P' = POPCNT(sub_mask) + r. This addition embodies the core idea of ​​integrating the cyclic shift operation into the collection process.

[0093] Level Control Encoding Unit: This unit contains an LROTC circuit. It receives the offset count value P' from the offset prefix calculation unit, and a constant k determined by this level (i.e., the width of the sub-network of this level), and executes LROTC(0... k The operation (P') generates the complete control word for that level. This control word is then loaded onto the respective switching switches of the corresponding level.

[0094] With this structure, when data flows through the Banyan network, not only is the collection operation according to the mask M completed, but also, because the control signal has embedded cyclic shift information, the collected valid bits naturally present the arrangement after cyclic shift at the output.

[0095] Example 2: Bit Manipulation Method

[0096] Based on the above hardware architecture, this embodiment provides a bit manipulation method for performing a Gather operation with a cyclic shift amount r on an input data word D and a bit mask M. This method can be formalized as verifying ROT(PEX(D, M),r) = PEX(D, M, r), that is, collecting D first according to M and then cyclically shifting it by r, which is equivalent to directly using a control signal with an offset r for collection.

[0097] refer to Figure 4 , Figure 5 , Figure 6 and Figure 7 The method includes the following steps:

[0098] 1. Input: Receive an n-bit data word D (e.g., "87654321"), an n-bit bitmask M (e.g., "1100_1010"), and a circular shift amount r (e.g., left shift by 2 bits).

[0099] 2. Calculate basic control information: Based on the bitmask M, according to... Figure 2 The traditional method shown calculates the raw prefix count (POPCNT) required for a simple Gather operation at each stage of the Banyan network. For example, for 8-bit data, the POPCNT of each submask needs to be calculated separately.

[0100] 3. Generate offset control signal: Add the cyclic shift amount r to the original POPCNT of each stage to obtain the offset prefix count P'. Then, using the LROTC circuit, generate the final control signal for each stage based on P'.

[0101] 4. Perform composite operation: Input data word D into the Banyan network switching module. Driven by the control signal generated in step 3, each switch in the Banyan network performs routing. Finally, the result data gather_rotate_data is obtained from the output (e.g., Figure 7 "56874213" shown).

[0102] 5. Result Verification: To verify the correctness of the results, a reference model can be constructed. This model first uses traditional Banyan (without rotation) to perform a Gather operation on D and M, obtaining gather_data (e.g., Figure 7The code "13568742" is shown. Then, a special circular shifter is used to shift "gather_data" by r bits to obtain "gather_after_rotate_data" (as shown). Figure 7 As shown in "56874213"). Assertions are written using formal verification tools (such as JasperGold), such as... Figure 6 As shown, it can be proven that gather_rotate_data and gather_after_rotate_data are equal under any input, thus verifying the correctness of this method.

[0103] This invention achieves the functionality that originally required two separate hardware modules by ingeniously modifying the control signal generation logic of the Banyan network and adding only a simple addition offset. This significantly reduces hardware complexity, chip area, and power consumption, making it particularly suitable for resource-sensitive embedded processors and high-performance computing cores.

[0104] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A configurable hardware architecture based on a Banyan network, characterized in that, The architecture is used to simultaneously perform bitwise collection and cyclic shift operations on input data, and includes: A Banyan network switching module has n data input terminals and n data output terminals, and is composed of log2(n) cascaded switching stages, each stage consisting of multiple two-input two-output switching switches; A control signal generation module, connected to each stage of the Banyan network switching module, is used to generate control signals for each stage of the switching switch based on a bit mask and a cyclic shift amount. The control signal generation module includes: An offset prefix calculation unit is used to receive the cyclic shift amount r and superimpose the cyclic shift amount r with an original prefix count based on the bit mask to generate an offset prefix count; A level control coding unit is used to generate the final control bit for each switching switch in each level based on the offset prefix count.

2. The hardware architecture according to claim 1, characterized in that, The original prefix count based on the bitmask refers to calculating the number of "1"s to the right of each target bit position in the input data within the bitmask.

3. The hardware architecture according to claim 1, characterized in that, The offset prefix calculation unit is specifically used to: for a given level, add the cyclic shift amount r to the original prefix count corresponding to that level to obtain the offset prefix count value.

4. The hardware architecture according to claim 1, characterized in that, The level control coding unit includes an LROTC circuit that receives an initial control string consisting entirely of "0"s of length determined by the offset prefix count value, and generates the final control word for that level through a cyclic complement operation.

5. A bit manipulation method based on the configurable hardware architecture according to any one of claims 1 to 4, characterized in that, Includes the following steps: Step 1: Receive an n-bit input data word and an n-bit bitmask, as well as a cyclic shift amount r; Step 2: Calculate the basic control information required for each level based on the bitmask, wherein the basic control information includes the original prefix count; Step 3: Add the cyclic shift amount r to the original prefix count to generate the offset prefix count; Step 4: Based on the offset prefix count, generate the control signal for each level of switching by cyclic complement operation; Step 5: Input the input data word into the Banyan network switching module and route it under the control of the control signal to obtain an n-bit result data word from the output end, which has simultaneously completed bit-by-bit collection and cyclic shifting.

6. The bit manipulation method according to claim 5, characterized in that, The bit-by-bit collection operation refers to extracting the valid bits marked by the bit mask from the input data word and compressing and arranging them at one end of the result word; the cyclic shift operation refers to treating the compressed valid bits as a whole and cyclically shifting them according to the cyclic shift amount r.

7. The bit manipulation method according to claim 5, characterized in that, Formal verification tools are used to verify the correctness of the hardware architecture through assertions. The assertions are used to prove that the following equation holds: the result obtained by first collecting the input data bit by bit according to the bit mask and then cyclically shifting it according to the cyclic shift amount is equal to the result obtained by collecting the input data bit by bit according to the bit mask and then adding the cyclic shift amount to the original prefix count and then performing bit collection.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the method according to any one of claims 5 to 7.

9. A digital signal processor, characterized in that, It includes the configurable hardware architecture based on the Banyan network as described in any one of claims 1 to 4.

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