Printed circuit board design device, printed circuit board design program, and printed circuit board design method

Abstract

This printed circuit board design device comprises: a grouping processing unit (8) that generates a plurality of circuit diagram groups by dividing a circuit diagram into a plurality of pieces; a component classification unit (10) that classifies components into parent components, child components directly or indirectly connected to the parent components, and other components; a proximity block generation unit (11) that generates a plurality of proximity blocks, each containing parent and child blocks; and an overall layout design unit (15) that arranges the parent components within the plurality of proximity blocks, and arranges the child components within the proximity blocks on the basis of the layout of the parent components.

Description

Printed Circuit Board Design Device, Printed Circuit Board Design Program, and Printed Circuit Board Design Method

[0001] The present disclosure relates to a printed circuit board design device, a printed circuit board design program, and a printed circuit board design method.

[0002] Conventionally, there has been known a design device that can arrange components to be arranged close to each other on a printed circuit board so that the performance or characteristics as an electronic circuit can be sufficiently exhibited. For example, the design device described in Patent Document 1 includes a knowledge pattern storage unit that stores, as knowledge patterns, conditions of components to be arranged close to each other on a printed circuit board, a printed circuit board design information storage unit that stores components to be arranged on the printed circuit board and wiring information between the components, and for each component stored in the printed circuit board design information storage unit, determines whether the knowledge pattern stored in the knowledge pattern storage unit is satisfied based on the wiring information, and group classification means for classifying a collection of components that satisfy the knowledge pattern as one group, and arrangement determination means for determining an arrangement on the printed circuit board by regarding the component group classified into one group as one arrangement element. The arrangement of components other than the group is arranged based on the connection information in the printed circuit board design information storage unit.

[0003] Japanese Patent Laid-Open No. 7-200655

[0004] However, in the printed circuit board design device described in Patent Document 1, when a plurality of groups are generated, there is no description of how to arrange the plurality of groups on the printed circuit board. In order to reduce the circuit area and sufficiently exhibit the performance or characteristics as an electronic circuit, the designer must consider how to arrange the plurality of groups, which increases the work burden on the designer.

[0005] Therefore, an object of the present disclosure is to provide a printed circuit board design device, a printed circuit board design program, and a printed circuit board design method that can arrange components with a small circuit area and a small work burden and can sufficiently exhibit the performance or characteristics as an electronic circuit.

[0006] The printed circuit board design apparatus of this disclosure comprises: a component classification unit that classifies components into parent components, child components directly or indirectly connected to parent components, and other components; a proximity block generation unit that generates a plurality of proximity blocks, each containing parent components and child components; and an overall placement design unit that arranges parent components within the plurality of proximity blocks and arranges child components within the proximity blocks based on the arrangement of parent components.

[0007] According to the printed circuit board design apparatus, printed circuit board design program, and printed circuit board design method of this disclosure, components can be arranged with minimal workload, resulting in a small circuit area and allowing the electronic circuit to perform or exhibit its full potential.

[0008] This is a diagram showing the configuration of the printed circuit board design apparatus 1 of the embodiment. This is a flowchart showing the procedure for designing the placement of components on a printed circuit board by the printed circuit board design apparatus 1 of the embodiment. This is a flowchart showing the detailed processing procedure of S1 in Figure 2. This is a diagram for explaining the relationships between components. This is a flowchart showing the detailed processing procedure of S9 in Figure 2 in the embodiment. (a) is a diagram showing a netlist. (b) is a diagram showing the connection relationships between components. (c) is a diagram showing an example of a power tree. This is a diagram showing examples of position-specified components and semi-position-specified components. (a) is a diagram showing an example of placement with an orientation of 0°. (b) is a diagram showing an example of placement with an orientation of 90°. (c) is a diagram showing an example of placement with an orientation of 180°. (d) is a diagram showing an example of placement with an orientation of 270°. This is a diagram showing an example of a set of two parent components with connections. This is a diagram showing an example of connection pins. This is a diagram showing virtual pins obtained from the connection pins in Figure 17. This is a diagram to illustrate an example of the coordinates of virtual pins in a parent component model. This is a diagram to illustrate another example of the coordinates of virtual pins in a parent component model. (a) is a diagram showing virtual pins between parent component model RB1 and parent component model RB2. (b) is a diagram showing virtual pins between parent component model RB2 and parent component model RB3. (a) and (b) are diagrams to illustrate the ideal orientation relationship between two parent component models. This is a diagram to illustrate the ideal orientation relationship between two parent component models. This is a diagram showing an example of a table representing the ideal orientation relationship between two parent component models. This is a flowchart showing the detailed processing procedure for S505 in Figure 5. This is a diagram to illustrate an example of clustering of placement patterns. This is a diagram showing the results of clustering of placement patterns. (a) is a diagram showing an example of the orientation relationship between two parent component models. (b) is a diagram showing another example of the relationship between the orientations of two parent component models. This is a diagram showing an example of a score based on the relationship between the orientations of two parent component models. This is a diagram showing another example of the relationship between the orientations of two parent component models. (a) is a diagram showing an example with twisted wiring. (b) is a diagram showing an example without twisted wiring. (a) is a diagram showing an example with crossed wiring. (b) is a diagram showing an example without crossed wiring.(a) is a diagram showing an example where a wiring path exists. (b) is a diagram showing an example where a wiring path does not exist. This is a flowchart showing the detailed processing procedure for S604 in Figure 18. This is a diagram showing an example of selecting a representative candidate placement pattern for cluster A. This is a diagram showing an example of a placement pattern generated after the completion of the processing procedure in the flowchart of Figure 18. This is a flowchart showing the detailed processing procedure for S506 in Figure 5. This is a diagram showing an example of acquiring the region of a circuit diagram group model that includes a semi-positioned component. This is a diagram showing an example of acquiring the region of a circuit diagram group model that includes a semi-positioned component. This is a diagram showing an example of a region pattern generated after the completion of the processing procedure in the flowchart of Figure 30. This is a flowchart showing the detailed procedure for S507 in Figure 5. This is a diagram to explain an example of generating an overall placement pattern. This is a flowchart showing the detailed processing procedure for S508 in Figure 5. This is a diagram showing an example of child component placement. This is a diagram to explain the region around the parent component PR1. This is a diagram showing an example of placement of first-generation child components of the same priority. (a) and (b) are diagrams illustrating an example of adjusting the placement of individual components. (a) and (b) are diagrams illustrating another example of adjusting the placement of individual components. This is a diagram showing the hardware configuration of the printed circuit board design apparatus 1.

[0009] The embodiments will be described below with reference to the drawings. Embodiment. Figure 1 is a diagram showing the configuration of the printed circuit board design apparatus 1 according to the embodiment.

[0010] The printed circuit board design apparatus 1 comprises a data input unit 2, a user interface 4, a CAD (Computer Aided Design) unit 3, and a layout design unit 21.

[0011] The functions of the CAD unit 3 and the layout design unit 21 may be realized by the computer executing a printed circuit board design program stored in memory. The printed circuit board design program may be installed into memory from an external source via a network. Alternatively, the printed circuit board design program may be installed into memory via a portable recording medium.

[0012] The data input unit 2 receives data such as circuit diagrams and netlists from an external source. The circuit diagram includes image data and text data.

[0013] User I / F 4 accepts the designer's input and displays the screen. CAD unit 3 creates binary format CAD data using the data input from data input unit 2 according to the designer's input.

[0014] The layout design unit 21 comprises a pre-processing unit 51, a grouping processing unit 8, a component classification unit 10, a proximity block generation unit 11, a component priority setting unit 25, and an overall layout design unit 15. The pre-processing unit 51 comprises a conversion unit 5, a net attribute setting unit 6, and a net point setting unit 7. The overall layout design unit 15 comprises a power tree setting unit 13, a position specification unit 14, a model generation unit 41, a parent component placement pattern design unit 31, a circuit diagram group area pattern design unit 32, an overall layout pattern design unit 33, a child component placement design unit 12, and a component position adjustment unit 34.

[0015] The conversion unit 5 converts the binary format CAD data created based on the circuit diagram into text data and creates a list of component names in text format.

[0016] The net attribute setting unit 6 sets the attributes of nets that connect multiple components included in the circuit diagram. For example, the net attribute setting unit 6 sets the attributes of nets based on the names of nets included in the netlist. Furthermore, if the attribute of the first net connected to one end of the inductor is a power supply attribute, the net attribute setting unit 6 sets the attribute of the second net connected to the other end of the inductor to a power supply attribute, regardless of the name of the second net. If the attribute of the first net connected to one end of the inductor is a ground attribute, the net attribute setting unit 6 sets the attribute of the second net connected to the other end of the inductor to a ground attribute, regardless of the name of the second net.

[0017] The net score setting unit 7 sets a score for each net in response to the designer selecting a net from the net list displayed on the user interface 4 and setting a score for the selected net. This is because nets have different electrical performance importance depending on their function, and therefore an importance level is set for each individual net.

[0018] Figure 2 is a flowchart illustrating the procedure for designing the placement of components on a printed circuit board using the printed circuit board design apparatus 1 of this embodiment.

[0019] In S1, the preprocessing unit 51 performs the acquisition and generation of data necessary for the component placement design.

[0020] Figure 3 is a flowchart showing the detailed processing procedure of S1 in Figure 2. The explanation will refer to Figure 3. In S101, the data input unit 2 inputs data from an external source. The data includes circuit diagrams, outline drawings, netlists, parts lists, and instruction manuals. The circuit diagram includes image data representing the components that make up the circuit and their connections, as well as text data representing component names and net names. For example, the circuit diagram is created as a PDF (Portable Document Format) file containing text.

[0021] In S102, the CAD unit 3 creates CAD data from the input data based on the operation performed by the designer through the user interface 4.

[0022] In S103, the conversion unit 5 converts the binary format CAD data into text data. The text data includes a list of part names, etc.

[0023] In S104, the net attribute setting unit 6 sets the net attributes based on the netlist entered in the data input unit 2. Based on the net name and the components connected to the net, the net attribute setting unit 6 sets the net attribute to one of the following: "power attribute", "ground attribute", and "signal attribute". A net attribute of "power attribute" indicates that the net transmits the power supply voltage. A net attribute of "ground attribute" indicates that the net transmits the ground voltage. A net attribute of "signal attribute" indicates that the net transmits a signal. For example, if the net name contains the string "GND", the net attribute setting unit 6 sets the net attribute to "ground attribute", and if the net name contains the string "VCC" or "3.3V", it sets the net attribute to "power attribute". The net attribute setting unit 6 sets the attribute of the second net connected to the other end of the component "inductor" to "power attribute" when the attribute of the first net connected to one end of the component "inductor" is "power attribute", regardless of the name of the second net. The net attribute setting unit 6 sets the attribute of the second net connected to the other end of the component "inductor" to "ground attribute" when the attribute of the first net connected to one end of the component "inductor" is "ground attribute", regardless of the name of the second net. If the net attributes are set in advance, the process in S104 can be omitted.

[0024] In S105, the net score setting unit 7 sets a score for each net. For example, in response to the designer selecting a net from the net list displayed on the user interface 4 and entering a score for the selected net, the net score setting unit 7 sets a score for the selected net.

[0025] Let us explain again with reference to Figure 2. In S2, the grouping processing unit 8 performs a process to group multiple components placed on the board and generates multiple circuit diagram groups. The grouping processing unit 8 uses the circuit diagram in PDF format containing text and the component name list in text format generated in S103 to generate multiple circuit diagram groups consisting of multiple components. When the designer selects a portion of the circuit diagram in PDF format containing text as a group, the grouping processing unit 8 extracts a string from the text data of the selected portion and identifies the components belonging to the group by comparing the extracted string with the component name list in text format. The identification of components included in the selected portion is determined as follows: If the string included in the selected portion is a component name registered in the component name list in text format, it can be determined that the string represents a component included in the selected portion (i.e., group). If the string included in the selected portion is not a component name registered in the component name list in text format, it can be determined that the string does not represent a component included in the selected portion (i.e., group).

[0026] In S4, the component classification unit 10 classifies the multiple components belonging to all circuit diagram groups into parent components, child components that are electrically connected directly or indirectly to the parent components, and other components. Parent components are, for example, ICs. Child components are, for example, oscillators, bypass capacitors, damping resistors, electrolytic capacitors, and termination resistors.

[0027] The component classification unit 10 sets the generation of the child components. The component classification unit 10 sets child components directly connected to a parent component as first-generation child components. The component classification unit 10 sets child components directly connected to a k-th generation child component as the (k+1)-th generation child component, where k is a natural number greater than or equal to 1. However, the component classification unit 10 excludes connections to ground, prioritizes nets with signal attributes if a child component is connected to multiple nets, and sets that child component as the next generation child component after the youngest generation component if a child component is connected to multiple components. First-generation child components are sometimes called child components in the narrow sense. Second-generation child components are sometimes called grandchild components. Third-generation child components are sometimes called great-grandchild components.

[0028] Figure 4 is a diagram illustrating the relationships between components. The child components CH1 to CH7 are directly connected to the parent component PR1. The grandchild components GC1 to GC4 are directly connected to the child component CH1. The grandchild component GC5 is directly connected to the child component CH6. The great-grandchild component GG1 is directly connected to the grandchild component GC2. The great-grandchild component GG2 is directly connected to the grandchild component GC4. The grandchild components GC1 and GC3 are also directly connected to the parent component PR1, but since they are connected to the ground pin of the parent component PR1, they are not considered child components in the narrow sense.

[0029] In S5, the proximity block generation unit 11 generates a plurality of proximity blocks, each consisting of a parent component and a child component that is directly or indirectly connected to the parent component.

[0030] Let's refer to Figure 2 again for further explanation. In S9, the overall layout design unit 15 executes the overall layout design process multiple times to arrange multiple adjacent blocks included in multiple circuit diagram groups.

[0031] Figure 5 is a flowchart showing the detailed processing steps of S9 in Figure 2 in the embodiment.

[0032] In S501, the power tree setting unit 13 sets up a power tree for all power nets on the circuit diagram, representing the relationship between the neighboring block of the power source and the neighboring block of the power supply destination. The power tree setting unit 13 obtains the relationship between a power net and the neighboring blocks connected to that power net from the connection relationships between the netlist and the neighboring blocks.

[0033] The connection relationships between two adjacent blocks can be determined by understanding the connections between components in one adjacent block and components in the other adjacent block, based on the netlist.

[0034] Next, we will explain the procedure for setting up the power tree. Figure 6(a) is a diagram showing the netlist. Figure 6(b) is a diagram showing the connection relationships between components. Figure 6(c) is a diagram showing an example of a power tree.

[0035] Figure 6(a) shows the netlist. The power tree setting unit 13 refers to the netlist and determines that a 12V power supply is provided through CN1(1), F1(1), and IC1(1). The numbers in parentheses represent pin numbers. The power tree setting unit 13 refers to the netlist and determines that a 5V power supply is provided through IC1(2), FL1(1), and R2(1). The power tree setting unit 13 refers to the netlist and determines that a 3V power supply is provided through IC2(2) and IC5(1).

[0036] Figure 6(b) shows the connections between the components. Neighborhood block NB1 includes CN1, neighborhood block NB2 includes F1 and IC2, neighborhood block NB3 includes IC1, neighborhood block NB4 includes FL1 and IC3, neighborhood block NB5 includes R2 and IC4, and neighborhood block NB6 includes IC5. The first pin of CN1 is connected to the first pin of F1 and the first pin of IC1, the second pin of IC1 is connected to the first pin of FL1 and the first pin of R2, and the second pin of IC2 is connected to the first pin of IC5.

[0037] The designer specifies the 12V power supply source from NB1, NB2, and NB3. The designer specifies the 5V power supply source from NB3, NB4, and NB5. The designer specifies the 3V power supply source from NB2 and NB6.

[0038] Figure 6(c) shows an example of a power tree. This power tree is set up when the designer designates NB1 as the source of the 12V power supply, NB3 as the source of the 5V power supply, and NB2 as the source of the 3V power supply. As shown in Figure 6(c), 12V power is supplied from neighboring block NB1 to neighboring blocks NB2 and NB3, 5V power is supplied from neighboring block NB3 to neighboring blocks NB4 and NB5, and 3V power is supplied from neighboring block NB2 to neighboring block NB6.

[0039] Let us explain again with reference to Figure 5. In S502, the position designation unit 14 sets position designation components whose positions on the substrate are defined, and semi-position designation components whose positions on the substrate are roughly defined. Based on CAD ASCII data, the position designation unit 14 identifies the position designation components and their designated positions. The designated positions include coordinates on the substrate, placement plane, and orientation. Based on the designation by the designer through the user I / F 4, the position designation unit 14 sets the semi-position designation components and their approximate designated positions.

[0040] Figure 7 shows examples of position-specified and semi-position-specified parts. CN2, S1-S8, and D2-D4 are position-specified parts with specified positions.

[0041] IC2, IC3, IC4, IC7, CN1, CN3, CN4, and CN5 are semi-positional components whose approximate positions are specified.

[0042] Let's refer to Figure 5 again for further explanation. In S503, the model generation unit 41 models the circuit diagram group and creates a circuit diagram group model. The circuit diagram group model is used when calculating the area on the board where the circuit diagram group will be placed.

[0043] The circuit diagram group model has the absolute position (hereinafter referred to as position) of the circuit diagram group arranged on the substrate, the size (width and height) of the circuit diagram group arranged on the substrate, and connection information representing the one-to-one connection with other circuit diagram groups to which the circuit diagram group is connected. The position and size change depending on the arrangement.

[0044] The model generation unit 41 models the parent components in the proximity block and creates a parent component model. The parent component model is used when arranging the proximity block on the substrate.

[0045] The parent component model includes the absolute position of the parent component on the substrate, the position and size of the parent component, the orientation of the parent component on the substrate, the connection information with other parent component models directly connected to the parent component one-to-one or via one or more child components, and information representing the placement surface of the parent component. The position, orientation, and placement surface change depending on the arrangement. The orientation is, for example, 0, 90, 180, or 270°, but is not limited thereto. The placement surface is the front or back of the substrate.

[0046] Next, the orientation of the parent component NB on the substrate will be described. Fig. 8(a) is a diagram showing an arrangement example with an orientation of 0°. The horizontal direction of the substrate is set as the X-axis, and the vertical direction of the substrate is set as the Y-axis direction. The upper surface U1 and the lower surface B1 of the substrate parallel to the X-axis direction, and the left surface L1 and the right surface R1 of the substrate parallel to the Y-axis direction are set. When the orientation of the parent component NB is 0°, for example, the direction of the upper surface U2 of the parent component NB is parallel to the direction of the upper surface U1 of the substrate (parallel to the X-axis), and the upper surface U2 of the parent component NB is closest to the upper surface U1 of the substrate.

[0047] Fig. 8(b) is a diagram showing an arrangement example with an orientation of 90°. When the orientation of the parent component NB is 90°, for example, the direction of the upper surface U2 of the parent component NB is rotated 90° clockwise from the direction of the upper surface U1 of the substrate.

[0048] Fig. 8(c) is a diagram showing an arrangement example with an orientation of 180°. When the orientation of the parent component NB is 180°, for example, the direction of the upper surface U2 of the parent component NB is rotated 18° clockwise from the direction of the upper surface U1 of the substrate.

[0049] Figure 8(d) shows an example of an arrangement with an orientation of 270°. When the orientation of the parent component NB is 270°, for example, the direction of the upper surface U2 of the parent component NB is rotated 270° clockwise from the direction of the upper surface U1 of the substrate.

[0050] The model generation unit 41 creates a circuit diagram group connection model that models the connections between two or more circuit diagram group models. The circuit diagram group connection model is used for scoring candidate region patterns of circuit diagram group models. The circuit diagram group connection model includes the total number of net points and virtual pins. The total number of net points is the sum of the number of net points between circuit diagram group models that have connections. The virtual pins are the centers of the circuit diagram group models. The virtual pins are reference points when measuring the distance between circuit diagram group models.

[0051] The model generation unit 41 creates a parent component connection model that models the connections between two or more parent component models. The parent component connection model is used for scoring candidate placement patterns of the parent component models and for scoring candidate overall placement patterns.

[0052] The model generation unit 41 extracts multiple sets of two parent components that have connections from among all the parent components placed on the circuit board. The model generation unit 41 generates a parent component connection model for the multiple extracted sets of parent components.

[0053] The model generation unit 41 determines that the first parent component and the second parent component are connected if the first net connected to the first parent component is a signal attribute, the second net connected to the second parent component is a signal attribute, and the first net of signal attributes and the second net of signal attributes are directly connected, connected via only one child component, or connected via only two or more child components and one or more nets of signal attributes.

[0054] The model generation unit 41 determines that the first parent component and the second parent component are connected if the first net connected to the first parent component is a power supply attribute, the second net connected to the second parent component is a power supply attribute, and the first net of power supply attributes and the second net of power supply attributes are directly connected, connected via only one child component, or connected via only two or more child components and one or more nets of power supply attributes.

[0055] The model generation unit 41 determines that the first parent component and the second parent component are connected if the first net connected to the first parent component is a ground attribute, the second net connected to the second parent component is a ground attribute, and the first net with a ground attribute and the second net with a ground attribute are directly connected, connected via only one child component, or connected via only two or more child components and one or more ground attribute nets.

[0056] The model generation unit 41 determines that the first parent component and the second parent component are connected if the first net connected to the first parent component is a signal attribute, the second net connected to the second parent component is a signal attribute, and the first net of signal attributes and the second net of signal attributes are connected only via two or more child components and one or more power attribute nets, or if they are connected only via two or more child components, one or more power attribute nets, and one or more signal attribute nets.

[0057] The model generation unit 41 determines that the first parent component and the second parent component are connected if the first net connected to the first parent component is a signal attribute, the second net connected to the second parent component is a signal attribute, and the first net with signal attributes and the second net with signal attributes are connected only via two or more child components and one or more ground attribute nets, or if they are connected only via two or more child components, one or more ground attribute nets, and one or more signal attribute nets.

[0058] Figure 9 shows an example of a set of two parent components that have connections. As shown in Figure 9(a), parent component PR1 is connected to signal attribute net SG1, parent component PR2 is connected to signal attribute net SG2, and net SG1 and net SG2 are connected via child component CH1. In this case, the model generation unit 41 determines that parent component PR1 and parent component PR2 are connected.

[0059] As shown in Figure 9(b), parent component PR1 is connected to power attribute net VD1, parent component PR2 is connected to power attribute net VD2, and net VD1 and net VD2 are connected via child component CH1. In this case, the model generation unit 41 determines that parent component PR1 and parent component PR2 are connected.

[0060] As shown in Figure 9(c), parent component PR1 is connected to net GD1 with the ground attribute, parent component PR2 is connected to net GD2 with the ground attribute, and net GD1 and net GD2 are connected via child component CH1. In this case, the model generation unit 41 determines that parent component PR1 and parent component PR2 are connected.

[0061] As shown in Figure 9(d), parent component PR1 is connected to signal attribute net SG1, parent component PR2 is connected to signal attribute net SG2, and net SG1 and net SG2 are connected via child component CH1, signal attribute net SG3, and child component CH2. In this case, the model generation unit 41 determines that parent component PR1 and parent component PR2 are connected.

[0062] As shown in Figure 9(e), parent component PR1 is connected to power attribute net VD1, parent component PR2 is connected to power attribute net VD2, and net VD1 and net VD2 are connected via child component CH1, power attribute net VD3, and child component CH2. In this case, the model generation unit 41 determines that parent component PR1 and parent component PR2 are connected.

[0063] As shown in Figure 9(f), parent component PR1 is connected to the ground attribute net GD1, parent component PR2 is connected to the ground attribute net GD2, and net GD1 and net GD2 are connected via child component CH1, the ground attribute net GD3, and child component CH2. In this case, the model generation unit 41 determines that parent component PR1 and parent component PR2 are connected.

[0064] As shown in Figure 9(g), parent component PR1 is connected to signal attribute net SG1, parent component PR2 is connected to signal attribute net SG2, and net SG1 and net SG2 are connected via child component CH1, power attribute net VD1, and child component CH2. In this case, the model generation unit 41 determines that parent component PR1 and parent component PR2 are connected.

[0065] As shown in Figure 9(h), parent component PR1 is connected to signal attribute net SG1, parent component PR2 is connected to signal attribute net SG2, and net SG1 and net SG2 are connected via child component CH1, ground attribute net GD1, and child component CH2. In this case, the model generation unit 41 determines that parent component PR1 and parent component PR2 are connected.

[0066] The parent component connection model includes the total number of net points, connection pins, and virtual pins. The total number of net points is the sum of the number of net points between parent components that have a connection. If two parent components are connected via multiple nets, the net points are the sum of the net points of the multiple nets. Connection pins are pins that connect two or more parent components. The coordinates of virtual pins are a weighted average of the coordinates of connection pins, weighted by the number of net points. Virtual pins are reference points used when measuring the distance between two parent component models.

[0067] This section explains the relationship between connection pins and virtual pins. Figure 10 shows an example of connection pins.

[0068] Connection pins P1 and P2 of parent component model RB1 are connected to connection pins P6 and P7 of parent component model RB2 via paths L1 and L2. Connection pins P3, P4 and P5 of parent component model RB1 are connected to connection pins P11, P12 and P13 of parent component model RB3 via paths L3, L4 and L5, through connection pins P8, P9 and P10 of parent component model RB2.

[0069] Figure 11 shows the virtual pins obtained from the connection pins in Figure 10. If each of the multiple paths connects only the connection pins between two parent component models, the virtual pins are set from the connection pins of those two parent component models. If each of the multiple paths connects the connection pins of three or more parent component models, the virtual pins are set from the connection pins of those three or more parent component models.

[0070] For paths L1 and L2, virtual pins VP1 of parent component model RB1 and VP2 of parent component model RB2 are defined.

[0071] For paths L3, L4, and L5, virtual pins VP3 of parent component model RB1, VP4 of parent component model RB2, and VP5 of parent component model RB3 are defined.

[0072] Next, we will explain how to calculate the coordinates of the virtual pins. Figure 12 is a diagram illustrating an example of the coordinates of the virtual pins in the parent component model.

[0073] The connection pin P3 (x3, y3) of parent component model RB1 is connected to the connection pin P6 (x6, y6) of parent component model RB2, and the number of points in the net connecting them is 10. The connection pin P1 (x1, y1) of parent component model RB1 is connected to the connection pin P4 (x4, y4) of parent component model RB2, and the number of points in the net connecting them is 10. The connection pin P2 (x2, y2) of parent component model RB1 is connected to the connection pin P5 (x5, y5) of parent component model RB2, and the number of points in the net connecting them is 10.

[0074] The coordinates (XV1, YV1) of the virtual pin VP1 of the parent component model RB1 are calculated using the following formula.

[0075] XV1 = X1 * 10 / 30 + X2 * 10 / 30 + X3 * 10 / 30 ... (B1) YV1 = Y1 * 10 / 30 + Y2 * 10 / 30 + Y3 * 10 / 30 ... (B2) The coordinates (XV2, YV2) of the virtual pin VP2 of the parent component model RB2 are calculated by the following formulas.

[0076] XV2 = X4 * 10 / 30 + X5 * 10 / 30 + X6 * 10 / 30 ... (B3) YV2 = Y4 * 10 / 30 + Y5 * 10 / 30 + Y6 * 10 / 30 ... (B4) Figure 13 is a diagram illustrating another example of the coordinates of the virtual pins in the parent component model.

[0077] The difference between the example in Figure 13 and the example in Figure 12 is that the connection pin P3 (x3, y3) of the parent component model RB1 is connected to the connection pin P6 (x6, y6) of the parent component model RB2, and the number of points on the net connecting them is 100.

[0078] The coordinates (XV1, YV1) of the virtual pin VP1 of the parent component model RB1 are calculated using the following formula.

[0079] XV1 = X1 * 10 / 120 + X2 * 10 / 120 + X3 * 100 / 120 ... (B5) YV1 = Y1 * 10 / 120 + Y2 * 10 / 120 + Y3 * 100 / 120 ... (B6) The coordinates (XV2, YV2) of the virtual pin VP2 of the parent component model RB2 are calculated by the following formulas.

[0080] XV2 = X4 * 10 / 120 + X5 * 10 / 120 + X6 * 100 / 120 ... (B7) YV2 = Y4 * 10 / 120 + Y5 * 10 / 120 + Y6 * 100 / 120 ... (B8) Figure 14(a) shows the virtual pins between parent component model RB1 and parent component model RB2. Figure 14(b) shows the virtual pins between parent component model RB2 and parent component model RB3.

[0081] Virtual pin VP1 of parent component model RB1 is connected to virtual pin VP2 of parent component model RB2. Virtual pin VP3 of parent component model RB1 is connected to virtual pin VP4 of parent component model RB2. Virtual pin VP4 of parent component model RB2 is connected to virtual pin VP5 of parent component model RB3.

[0082] Let us explain again with reference to Figure 5. In S504, the model generation unit 41 sets the ideal orientation relationship between the two parent component models. The model generation unit 41 creates a table that represents the ideal orientation relationship between two parent component models that have connections included in the same circuit diagram group or different circuit diagram groups.

[0083] Figures 15(a) and (b) illustrate the ideal orientation relationship between two parent part models.

[0084] The connection pin P1 on the right side R2 of the parent component model RB1 and the connection pin P5 on the upper side U2 of the parent component model RB2 are connected by wiring WR1. The connection pin P3 on the right side R2 of the parent component model RB1 and the connection pin P4 on the upper side U2 of the parent component model RB2 are connected by wiring WR2. Therefore, the right side R2 of the parent component model RB1 and the upper side U2 of the parent component model RB2 are connected.

[0085] In Figure 15(a), the orientation of the parent component model RB1 is 0 degrees. The orientation of the parent component model RB2 is also 0 degrees. In Figure 15(a), the right side R2 of the parent component model RB1 and the upper side U2 of the parent component model RB2 do not face each other. That is, the distance between the right side R2 of the parent component model RB1 and the upper side U2 of the parent component model RB2 that are to be connected is not the shortest possible distance. Therefore, the distance between the wirings WR1 and WR2 is also not the shortest possible distance.

[0086] In Figure 15(b), as in Figure 15(a), the orientation of the parent component model RB1 is 0 degrees. In Figure 15(b), unlike Figure 15(a), the orientation of the parent component model RB2 is 270 degrees. In Figure 15(b), the right side R2 of the parent component model RB1 and the upper side U2 of the parent component model RB2 face each other at the shortest distance. That is, the orientation of the parent component model RB1 is such that the right side R2 of the parent component model RB1 is at the shortest distance from the parent component model RB2, and the orientation of the parent component model RB2 is such that the upper side U2 of the parent component model RB2 is at the shortest distance from the parent component model RB1. Therefore, the distance between wiring WR1 and WR2 is also the shortest.

[0087] Figure 16 illustrates the ideal orientation relationship between two parent component models. The virtual pin of parent component model RB1 is VP1, and the virtual pin of parent component model RB2 is VP2.

[0088] Of the four sides of the parent component model RB1, the side closest to the virtual pin VP1 is the right side R2. Of the four sides of the parent component model RB2, the side closest to the virtual pin VP2 is the left side L2.

[0089] The right side R2 of parent component model RB1 and the left side L2 of parent component model RB2 face each other at the shortest distance. That is, the orientation of parent component model RB1 is such that its right side R2 is closest to parent component model RB2, and the orientation of parent component model RB2 is such that its left side L2 is closest to parent component model RB1.

[0090] Figure 17 shows an example of a table illustrating the ideal orientation relationship between two parent component models. For example, the right side of parent component model RB1 and the top side of parent component model RB2 face each other at the shortest distance. That is, between parent component model RB1 and parent component model RB2, the ideal orientation of parent component model RB1 relative to parent component model RB2 is when the right side of parent component model RB1 is close to parent component model RB2, and the ideal orientation of parent component model RB2 relative to parent component model RB1 is when the top side of parent component model RB2 is close to parent component model RB1.

[0091] Let's refer to Figure 5 again for further explanation. The process from S505 to S508 is repeated multiple times. The repetition may be terminated after a predetermined number of executions or after a predetermined amount of time has elapsed. Alternatively, the repetition may be terminated when a predetermined condition is met (for example, when the sum of the scores described later falls below a certain value).

[0092] The initial processing will be described below. In S505, the parent component placement pattern design unit 31 generates one or more placement patterns for the multiple parent components included in each circuit diagram group.

[0093] Figure 18 is a flowchart showing the detailed processing procedure for S505 in Figure 5. In S601, the parent component placement pattern design unit 31 creates multiple candidate placement patterns for multiple parent component models included in each circuit diagram group. The size of the parent component model is the size of the rectangular area of ​​the rectangular parent component. The parent component placement pattern design unit 31 generates multiple candidate placement patterns with arbitrarily changed positions and orientations of the parent component models.

[0094] In S602, the parent component placement pattern design unit 31 performs clustering of the generated candidate placement patterns. The parent component placement pattern design unit 31 determines whether the multiple candidate placement patterns belong to the same cluster based on the positions of the two connected parent component models.

[0095] Figure 19 is a diagram illustrating an example of clustering of placement patterns. In Figure 19, the circuit diagram group is assumed to contain only parent component models RB1 and RB2. Placement patterns A and B are determined to belong to the same cluster if the overlapping area of ​​parent component model RB1 in placement pattern A and parent component model RB1 in placement pattern B is greater than or equal to a threshold (for example, 50% or more), and the overlapping area of ​​parent component model RB2 in placement pattern A and parent component model RB2 in placement pattern B is greater than or equal to a predetermined threshold (for example, 50% or more).

[0096] Figure 20 shows the results of clustering the arrangement patterns. By clustering the six arrangement patterns A to F, it was determined that arrangement patterns A and B belong to cluster A, arrangement patterns C, E, and F belong to cluster B, and arrangement pattern D belongs to cluster C.

[0097] Let's refer to Figure 18 again for further explanation. In S603, the parent component placement pattern design unit 31 scores the multiple candidate placement patterns included in each cluster.

[0098] The parent component placement pattern design unit 31 performs scoring between two parent component models (the i-th set) connected by virtual pins as follows. However, the parent component placement pattern design unit 31 refers to the power tree and does not perform scoring between two parent component models if the two parent component models receive power supply voltage from a common parent component model and the two parent component models supply power supply voltage to other parent component models. The score Si is calculated by the following formula.

[0099] Si = (WS1*f(A1) + WS2*f(A2) + WS3*f(A3) + WS4*f(A4) + WS5*f(A5)) * NS ... (C1) The first index A1 represents a score based on the distance between two parent component models. The first index A1 is the Manhattan distance between the virtual pins of the two parent component models. f(A1) is the standard score of A1.

[0100] The second indicator, A2, represents a score based on the orientation relationship between the two parent component models. f(A2) is the standard score of A2.

[0101] Figure 21(a) shows an example of the orientation relationship between two parent component models. The connection pin P1 on the right side R2 of parent component model RB1 is connected to the connection pin P2 on the left side L2 of parent component model RB2.

[0102] Therefore, the right side R2 of the parent component model RB1 and the left side L2 of the parent component model RB2 are connected.

[0103] In the example shown in Figure 21(a), the right side R2 of parent component model RB1 and the left side L2 of parent component model RB2 face each other at the shortest distance. That is, parent component model RB1 is oriented such that its right side R2 is closest to parent component model RB2, and parent component model RB2 is oriented such that its left side L2 is closest to parent component model RB1. Therefore, the distance between the right side R2 of parent component model RB1 and the left side L2 of parent component model RB2 is minimized. Consequently, the distance of the wiring NX is also minimized.

[0104] Figure 21(b) illustrates another example of the orientation relationship between two parent component models. In Figure 21(b), as in Figure 21(a), the connection pin P1 on the right side R2 of parent component model RB1 is connected to the connection pin P3 on the left side L2 of parent component model RB2. However, the orientation of parent component model RB2 is different from that in Figure 21(a).

[0105] In the example in Figure 21(b), the orientation of the parent component model RB1 is such that its right side R2 is closest to that of the parent component model RB2, but the orientation of the parent component model RB2 is such that its right side R2 is closest to that of the parent component model RB1. Therefore, the distance between the right side R2 of the parent component model RB1 and the left side L2 of the parent component model RB2 is not the shortest. As a result, the distance of the wiring NX is also not the shortest.

[0106] Figure 22 shows an example of scoring based on the orientation relationship between two parent component models. In this example, the score for the orientation of the two parent component models is shown when the right side R2 of parent component model RB1 and the upper side U2 of parent component model RB2 are connected.

[0107] In Figure 22, the left column represents the faces of parent component model RB1 that are closest to parent component model RB2. The middle column represents the faces of parent component model RB2 that are closest to parent component model RB1. In other words, in Figure 22, the right column shows the score when the faces in the left column of parent component model RB1 and the faces in the middle column of parent component model RB2 face each other at the shortest distance.

[0108] When the orientation is ideal, the score is the best possible "0". The greater the deviation from the ideal orientation, the higher (or worse) the score becomes.

[0109] Even if the two parent component models are not in a left-right or up-down positional relationship, you can still obtain a score based on the orientation of the two parent component models.

[0110] Figure 23 illustrates another example of the orientation relationship between two parent component models. Assume that the upper side U2 of parent component model RB1 is connected to the right side R2 of parent component model RB2. Parent component model RB2 is positioned to the upper right relative to parent component model RB1. Parent component model RB1 is positioned to the lower right relative to parent component model RB2. The orientation of parent component model RB2 relative to parent component model RB1 is determined based on the positional relationship of the virtual pin of parent component model RB2 to the upper side U2 closest to the virtual pin of parent component model RB1.

[0111] The orientation of the parent component model RB1 relative to the parent component model RB2 is determined based on the positional relationship between the virtual pins of the parent component model RB2 and the right side R2, which is closest to the virtual pins of the parent component model RB2.

[0112] In the example in Figure 23(a), the virtual pins of parent component model RB2 are located above the upper side surface U2 of parent component model RB1, so the orientation of parent component model RB2 relative to parent component model RB1 is "up". The virtual pins of parent component model RB1 are located to the right of the right side surface R2 of parent component model RB2, so the orientation of parent component model RB1 relative to parent component model RB2 is "right".

[0113] In the example in Figure 23(b), the virtual pins of parent component model RB2 are not located above the upper side surface U2 of parent component model RB1, so the orientation of parent component model RB2 relative to parent component model RB1 is "right". The virtual pins of parent component model RB1 are not located to the right of the right side surface R2 of parent component model RB2, so the orientation of parent component model RB1 relative to parent component model RB2 is "down".

[0114] The above is an explanation of the second indicator, A2. The third indicator, A3, represents a score based on whether or not wiring twist occurs between the two parent component models. f(A3) is the standard score of A3. The third indicator, A3, is set to a smaller value when there is no wiring twist than when there is wiring twist. Wiring twist can be calculated from the positional relationship between the two components to which the wiring is connected.

[0115] Figure 24(a) shows an example where the wiring is twisted. Figure 24(b) shows an example where the wiring is not twisted.

[0116] In Figure 24(a), the wiring NX between connection pin P1 of parent component model RB1 and connection pin P4 of parent component model RB2, and the wiring NY between connection pin P3 of parent component model RB1 and connection pin P2 of parent component model RB2 are twisted. In Figure 24(b), the wiring NZ between connection pin P1 of parent component model RB1 and connection pin P2 of parent component model RB2, and the wiring NW between connection pin P3 of parent component model RB1 and connection pin P4 of parent component model RB2 are not twisted.

[0117] The fourth index, A4, represents a score based on whether the wiring between two parent component models intersects with the wiring connected to the other parent component model. f(A4) is the standard score of A4. The fourth index, A4, is set to a smaller value when there is no intersection than when there is an intersection. Wiring intersections are determined using virtual wiring that connects the virtual pins of the parent component models in a straight line.

[0118] Figure 25(a) shows an example where the wiring crosses. Figure 25(b) shows an example where the wiring does not cross.

[0119] In Figure 25(a), the wiring NX between connection pin P1 of parent component model RB1 and connection pin P2 of parent component model RB2 intersects with the wiring NY between the other two parent component models. In Figure 25(b), the wiring NX between connection pin P1 of parent component model RB1 and connection pin P2 of parent component model RB2 does not intersect with any of the other two parent component model wirings.

[0120] The fifth index, A5, represents a score based on whether there are horizontal-only routing paths, vertical-only routing paths, or routing paths consisting of horizontal and vertical directions with one bend that connect the virtual pins of the two parent component models to connect the two parent component models. f(A5) is the standard score of A5. The fifth index, A5, is set to a smaller value when routing paths exist than when routing paths do not exist.

[0121] Figure 26(a) shows an example where a wiring path exists. Figure 26(b) shows an example where a wiring path does not exist.

[0122] In Figure 26(a), there is a wiring path PT1 consisting of horizontal and vertical directions with one bend, connecting the virtual pin VP1 of parent component model RB1 and the virtual pin VP2 of parent component model RB2. Because parent component model RB3 exists, it is determined that the wiring path PT2 cannot connect the two parent component models RB1 and RB2.

[0123] In Figure 26(b), it is determined that the wiring path PT2 cannot connect the two parent component models RB1 and RB2 because the parent component model RB3 exists. Similarly, it is determined that the wiring path PT1 cannot connect the two parent component models RB1 and RB2 because the parent component model RB4 exists.

[0124] NS is the total net points between the two parent component models. WS1 to WS5 are weights. By adjusting the values ​​of WS1 to WS5, the elements that are emphasized can be changed. The more desirable the arrangement pattern, the smaller each index A1 to A5 will be.

[0125] The parent component placement pattern design unit 31 may calculate the score Si based on at least one of the indicators A1 to A5.

[0126] The parent component placement pattern design unit 31, when there are N sets of two parent component models connected by virtual pins in a single circuit diagram group, uses the sum SS (=ΣSi) of the N scores S1 to SN as the score for the candidate placement pattern. The sum SS becomes smaller for more desirable candidate placement patterns.

[0127] Let's refer to Figure 18 again for further explanation. In S604, the parent component placement pattern design unit 31 selects candidate placement patterns for each cluster.

[0128] Figure 27 is a flowchart showing the detailed processing steps of S604 in Figure 18. Figure 28 is a diagram showing an example of selecting candidate placement patterns for cluster A. As shown in Figure 28(a), cluster A includes candidate placement patterns A, B, D, E, and F.

[0129] In S901, the parent component placement pattern design unit 31 sorts the multiple candidate placement patterns of the cluster in order of placement area AS. In the example in Figure 28, the candidate placement patterns are sorted in order from smallest to largest placement area AS as B, F, D, E, and A.

[0130] In S902, the parent component placement pattern design unit 31 selects one or more candidate placement patterns with a small placement area AS (i.e., placement area AS is less than or equal to a predetermined threshold ATH). As shown in Figure 28(b), candidate placement patterns B, D, and F, whose placement area AS is less than or equal to the threshold ATH, are selected. If there are no candidate placement patterns with a placement area AS less than or equal to the predetermined threshold ATH, the candidate placement pattern with the smallest placement area AS may be selected.

[0131] In S903, the parent component placement pattern design unit 31 sorts the candidate placement patterns selected in S902 in order of sum SS. In the example in Figure 28, the candidate placement patterns are sorted in descending order of sum SS as F, D, and B.

[0132] In S904, the parent component placement pattern design unit 31 selects one or more candidate placement patterns with a good sum SS (i.e., the sum SS is less than or equal to a predetermined threshold STH). As shown in Figure 28(c), candidate placement patterns D and F, whose sum SS is less than or equal to the threshold STH, are selected. If there are no candidate placement patterns whose sum SS is less than or equal to the predetermined threshold STH, the candidate placement pattern with the smallest sum SS may be selected.

[0133] Referring again to Figure 18, in S605, the parent component placement pattern design unit 31 sorts the selected candidate placement patterns for all clusters according to the scoring results.

[0134] In S606, the parent component placement pattern design unit 31 retains one or more candidate placement patterns from among the selected candidate placement patterns of all clusters that have a good sum SS (i.e., the sum SS is less than or equal to a predetermined threshold FSTH). If there are no candidate placement patterns whose sum SS is less than or equal to the predetermined threshold FSTH, the candidate placement pattern with the smallest sum SS may be retained.

[0135] In S607, if there is an overlap in the placement positions of multiple parent component models in each of the remaining one or more candidate placement patterns, the parent component design unit 31 removes the overlap by moving at least one of the overlapping parent component models. Such overlaps occur because, when placing one or more parent component models in the area of ​​a circuit diagram group, there is no restriction that all parent component models must fit completely within the area of ​​the circuit diagram group. As a result, one or more placement patterns are generated.

[0136] Figure 29 shows an example of placement patterns generated after the completion of the processing steps in the flowchart of Figure 18. Multiple desirable placement patterns are generated for the multiple parent component models included in each circuit diagram group.

[0137] Let us explain again with reference to Figure 5. In S506, the circuit diagram group area pattern design unit 32 generates one or more area patterns that represent the areas of multiple circuit diagram groups on the substrate.

[0138] Figure 30 is a flowchart showing the detailed processing procedure of S506 in Figure 5. In S701, the circuit diagram group area pattern design unit 32 creates multiple candidate area patterns for one or more circuit diagram group models on the substrate. A circuit diagram group model is a rectangular area having an area greater than or equal to the sum of the areas of all components in that circuit diagram group, and less than or equal to twice the sum of the areas of all components included in that circuit diagram group. The area of ​​the circuit diagram group model is obtained, excluding the areas of circuit diagram group models that include position-specified components and circuit diagram group models that include semi-position-specified components on the substrate. The circuit diagram group area pattern design unit 32 generates multiple candidate area patterns in which the position and size of the circuit diagram group model are arbitrarily changed while satisfying the above conditions. However, if the circuit diagram group model includes position-specified components or semi-position-specified components, the circuit diagram group area pattern design unit 32 obtains the area of ​​the circuit diagram group model so as to include the specified coordinates.

[0139] Figures 31 and 32 illustrate examples of acquiring regions in a schematic group model that include semi-positioned components. Acquiring regions in a schematic group model that include positioned components is done in a similar manner.

[0140] On the circuit board PRB, the region HR of the schematic group model is acquired so as to include the specified coordinates PA of the semi-position-specified component.

[0141] The circuit diagram group area pattern design unit 32 acquires the area of ​​the circuit diagram group model so that the specified coordinates are not included if the other circuit diagram group model includes a position-specified component or a semi-position-specified component.

[0142] In S702, the circuit diagram group area pattern design unit 32 performs clustering of the generated candidate area patterns. Similar to the clustering of the placement patterns of the parent component model, the circuit diagram group area pattern design unit 32 determines whether multiple candidate area patterns belong to the same cluster based on the positions of the two circuit diagram group models.

[0143] In S703, the circuit diagram group area pattern design unit 32 scores multiple candidate area patterns within each cluster.

[0144] Scoring between two circuit diagram group models connected by virtual pins (the i-th set) is performed as follows. The score Ti is given by the following formula.

[0145] Ti = (WT1 * f(B1) + WT2 * f(B2)) * NT ... (C2) The first index B1 is the Manhattan distance between virtual pins VP of two circuit diagram group models connected by virtual pins. f(B1) is the deviation score of B1. The second index B2 represents the crossing of wiring. f(B2) is the deviation score of B2.

[0146] WT1 and WT2 are weights. By adjusting the values ​​of WT1 and WT2, the elements that are emphasized can be changed. The more desirable the domain pattern, the smaller the values ​​of each index B1 and B2 will be.

[0147] NT is the total net score between the two circuit diagram group models. The circuit diagram group area pattern design unit 32 may calculate the score Ti based on one of the indices B1 and B2.

[0148] The circuit diagram group area pattern design unit 32, when there are M sets of two circuit diagram group models connected by virtual pins, uses the sum SS2 (=ΣTi) of the M scores T1 to TM as the score for the candidate area pattern. The sum TT becomes smaller for more desirable area patterns.

[0149] In S704, the circuit diagram group area pattern design unit 32 selects candidate area patterns for each cluster in the same manner as in S901 to S904.

[0150] The circuit diagram group area pattern design unit 32 sorts the multiple candidate area patterns of the cluster in order of their placement area AS2. The circuit diagram group area pattern design unit 32 selects one or more candidate area patterns with a small placement area AS2 (i.e., placement area AS2 is less than or equal to a predetermined threshold ATH2). If there are no candidate area patterns with a placement area AS2 less than or equal to the predetermined threshold ATH2, the candidate area pattern with the smallest placement area AS2 may be selected. The circuit diagram group area pattern design unit 32 sorts the selected candidate area patterns in order of their sum SS2. The circuit diagram group area pattern design unit 32 selects one or more candidate area patterns with a good sum SS2 (i.e., sum SS2 is less than or equal to a predetermined threshold STH2). If there are no candidate area patterns with a sum SS2 less than or equal to the predetermined threshold STH2, the candidate area pattern with the smallest sum SS2 may be selected.

[0151] In S705, the circuit diagram group area pattern design unit 32 sorts the selected candidate area patterns of all clusters according to the scoring results.

[0152] In S706, the circuit diagram group region pattern design unit 32 retains only one or more candidate region patterns from among the selected candidate region patterns of all clusters that have a good sum SS2 (i.e., the sum SS2 is less than or equal to a predetermined threshold FSTH2). If there are no candidate region patterns whose sum SS2 is less than or equal to the predetermined threshold FSTH2, the candidate region pattern with the smallest sum SS2 may be retained.

[0153] In S707, if there is an overlap between the regions of multiple circuit diagram group models in one or more remaining candidate region patterns, the circuit diagram group area pattern design unit 32 removes the overlap by moving at least one of the overlapping circuit diagram group models. This determines one or more region patterns.

[0154] Figure 33 shows an example of a region pattern generated after the completion of the processing steps in the flowchart of Figure 30. In Figure 33, one of several patterns for the regions of circuit diagram group models GRP-G and GRP-H is shown.

[0155] Let us explain again with reference to Figure 5. In S507, the overall layout pattern design unit 33 generates one or more overall layout patterns for each region pattern, in which one or more parent components included in the circuit diagram groups are placed in the regions of multiple circuit diagram groups in the region pattern using layout patterns.

[0156] Figure 34 is a flowchart showing the detailed procedure of S507 in Figure 5. In S801, the overall layout pattern design unit 33 generates multiple candidate overall layout patterns by arranging parent component models in each of the layout patterns of the multiple parent component models included in each circuit diagram group model within each of the area patterns of the multiple circuit diagram group models. The layout is such that the center of the group of parent component models, consisting of one or more parent component models included in the circuit diagram group model, coincides with the center of the area of ​​the circuit diagram group model. As mentioned above, a circuit diagram group model is a rectangular area having an area greater than or equal to the sum of the areas of all components in that circuit diagram group, and less than or equal to twice the sum of the areas of all components included in that circuit diagram group. Therefore, there are cases where not all parent component models included in that circuit diagram group can fit within the area of ​​the circuit diagram group model.

[0157] Figure 35 is a diagram illustrating an example of generating candidate overall placement patterns. In a certain region pattern, parent component models RB3 and RB4 within the circuit diagram group model G are placed in the region of the circuit diagram group model G using placement patterns G1, G2, G3..., and parent component models RB5 and RB6 within the circuit diagram group model H are placed in the region of the circuit diagram group model H using placement patterns H1, H2, H3.... For example, the centers of the parent component model group consisting of parent component models RB3 and RB4 are arranged to coincide with the center of the region of the circuit diagram group model G.

[0158] For example, suppose there are 10 region patterns for the circuit diagram group model, 2 circuit diagram group models G and H, 5 placement patterns for the parent component model of circuit diagram group model G, and 7 placement patterns for the parent component model of circuit diagram group model H. The overall placement pattern design unit 33 places the parent component model in the region of circuit diagram group model G in the i-th region pattern (i=1 to 10) using 5 different placement patterns, and places the parent component model in the region of circuit diagram group model H using 7 different placement patterns. As a result, 10 × 5 × 7 = 350 candidate overall placement patterns are generated.

[0159] In S802, the overall layout pattern design unit 33 performs clustering of the generated candidate overall layout patterns. The overall layout design unit 15 determines whether the multiple candidate overall layout patterns belong to the same cluster based on the positions of two connected parent component models among all parent component models in all circuit diagram group models, similar to the clustering of parent component model placement patterns within a single circuit diagram group model described above.

[0160] In S803, the overall layout pattern design unit 33 scores multiple candidate overall layout patterns within each cluster. The overall layout pattern design unit 33 scores the pair of parent component models connected by virtual pins (the i-th set) within all parent component models of all circuit diagram group models in the same way as the scoring of the pair of parent component models connected by virtual pins within one circuit diagram group model described above. If there are multiple pairs of parent component models connected by virtual pins, the overall layout pattern design unit 33 uses the sum of the scores SS3 as the sum of the overall layout patterns. The more desirable the candidate overall layout pattern, the smaller the sum SS3 will be.

[0161] In S804, the overall arrangement pattern design unit 33 selects a candidate overall arrangement pattern for each cluster, in the same manner as in S901 to S904.

[0162] The overall arrangement pattern design unit 33 sorts multiple candidate overall arrangement patterns of the cluster in order of arrangement area AS3. The overall arrangement pattern design unit 33 selects one or more candidate overall arrangement patterns with small arrangement area AS3 (i.e., arrangement area AS3 is less than or equal to a predetermined threshold ATH3). If there are no candidate overall arrangement patterns with an arrangement area AS3 less than or equal to the predetermined threshold ATH3, the candidate overall arrangement pattern with the smallest arrangement area AS3 may be selected. The overall arrangement pattern design unit 33 sorts the selected candidate overall arrangement patterns in order of sum SS3. The overall arrangement pattern design unit 33 selects one or more candidate overall arrangement patterns with a good sum SS3 (i.e., sum SS3 is less than or equal to a predetermined threshold STH3). If there are no candidate overall arrangement patterns with a sum SS3 less than or equal to the predetermined threshold STH3, the candidate overall arrangement pattern with the smallest sum SS3 may be selected.

[0163] In S805, the overall arrangement pattern design unit 33 sorts the selected candidate overall arrangement patterns for all clusters according to the scoring results.

[0164] In S806, the overall arrangement pattern design unit 33 selects and retains only one or more candidate overall arrangement patterns from among the selected candidate overall arrangement patterns for all clusters that have a good sum SS3 (i.e., the sum SS3 is less than or equal to a predetermined threshold FSTH3). If there are no candidate overall arrangement patterns whose sum SS3 is less than or equal to the predetermined threshold FSTH3, the candidate overall arrangement pattern with the smallest sum SS3 may be retained.

[0165] In S807, if the overall layout pattern design unit 33 finds that there is an overlap in the placement positions of multiple parent component models in the remaining one or more candidate overall layout patterns, it removes the overlap by moving at least one of the overlapping parent component models. This generates one or more overall layout patterns.

[0166] Let us explain again with reference to Figure 5. In step S508, the sub-component placement design unit 12 determines the placement of sub-components within the adjacent block.

[0167] Figure 36 is a flowchart showing the detailed processing procedure for S508 in Figure 5. In S201, the component priority setting unit 25 sets the priority of all child components in adjacent blocks.

[0168] The component priority setting unit 25 sets priorities for first-generation child components (child components directly connected to parent components) and classifies them into first-generation high-priority child components or first-generation low-priority child components. Examples of first-generation high-priority child components include bypass capacitors and oscillators.

[0169] The component classification unit 10 sets priorities for second-generation and later child components according to the attributes of the nets to which those child components are connected. For example, the component classification unit 10 sets the highest priority for child components connected to a signal attribute net and a ground attribute net, an intermediate priority for child components connected to a signal attribute net and a power attribute net, and the lowest priority for child components connected to two signal attribute nets.

[0170] The component priority setting unit 25 sets a first group consisting of a first-generation high-priority sub-component and a plurality of sub-components directly or indirectly connected to this first-generation high-priority sub-component to have a higher priority than a group consisting of a first-generation low-priority sub-component and a plurality of sub-components directly or indirectly connected to this first-generation low-priority sub-component.

[0171] The component priority setting unit 25 sets the priority of the sub-components in the first group or the sub-components in the second group as follows:

[0172] The component priority setting unit 25 sets the priority of the k-th generation child component lower than that of the (k-1)th generation child component, which is directly connected to this component. k is a natural number greater than or equal to 2. In other words, the priority of a certain child component (let's call it the first child component) is higher than the priority of all child components (let's call them the second child components) that are directly connected to the first child component and have one more child component in transit to connect to the parent component than the first child component.

[0173] The component priority setting unit 25 sets priorities for multiple second-generation and later child components that are not directly related, according to the attributes of the nets to which they are connected. That is, when there are multiple second child components, the priority of each second child component is determined based on the attributes of the two nets to which each second child component is connected.

[0174] The component priority setting unit 25 sets the priority of all child components of adjacent blocks in order from first according to the above criteria, and in S202, i is set to 1.

[0175] In S203, the sub-component placement design unit 12 places all i-priority sub-components within adjacent blocks as close as possible to the parent component within the unplaced area.

[0176] In S204, if all sub-components have been placed, the process ends. If there are any sub-components that have not yet been placed, the process proceeds to S205.

[0177] In S205, i is incremented, and the process returns to S203. Figure 37 shows an example of the arrangement of sub-components.

[0178] The first-generation high-priority sub-component CH1 and the first-generation high-priority sub-component CH2 are set to first priority.

[0179] A first group GR1 consisting of a first-generation high-priority sub-component CH1 and second-generation components (grandchild components) GC1 and GC2 directly or indirectly connected to the first-generation high-priority sub-component CH1, and a first group GR2 consisting of a first-generation high-priority sub-component CH2 and second-generation components (grandchild components) GC3 and third-generation components (great-grandchild components) GG1 directly or indirectly connected to the first-generation high-priority sub-component CH2, are given higher priority than a second group GR3 consisting of a first-generation low-priority sub-component CH3 and second-generation components (grandchild components) GC4, GC5 and third-generation components (great-grandchild components) GG2 directly or indirectly connected to the first-generation low-priority sub-component CH3.

[0180] In the first group GR1, the sub-sub-component GC1 is connected to the signal attribute net and the ground attribute net, while the sub-sub-component GC2 is connected to the signal attribute net and the power attribute net. Therefore, the sub-sub-component GC1 is set to second priority, and the sub-sub-component GC2 is set to third priority.

[0181] In the first group GR2, the great-grandchild component GG1 is directly connected to the grandchild component GC3 and is a direct descendant of the grandchild component GC3. Therefore, the grandchild component GC3 is set as the second priority, and the great-grandchild component GG1 is set as the third priority.

[0182] In the second group GR3, the first-generation low-priority sub-component CH3 is set to fourth priority. Sub-sub

[0183] The great-grandchild component GG2 is directly connected to the grandchild component GC4 and is a direct descendant of the grandchild component GC4. Therefore, the great-grandchild component GG2 is set as the sixth priority.

[0184] In Figure 37, the components are arranged in order of priority, starting with the first priority, and are positioned closest to the parent component PR1. Figure 38 is a diagram illustrating the region around the parent component PR1.

[0185] The first side LE1 and the second side LE2 of the parent component are connected at the first crossing line P1, the first side LE1 and the third side LE3 of the parent component are connected at the second crossing line P2, the second side LE2 and the fourth side LE4 of the parent component are connected at the third crossing line P3, and the third side LE3 and the fourth side LE4 of the parent component are connected at the fourth crossing line P4.

[0186] The first boundary surface BR1 is defined as the surface that bisects the space separated by the first extension surface ET1, which is obtained by extending the first side surface LE1 of the parent component toward the first intersection line P1, and the second extension surface ET2, which is obtained by extending the second side surface LE2 of the parent component toward the first intersection line P1.

[0187] The second boundary surface BR2 is defined as the surface that bisects the space separated by the third extension surface ET3, which is obtained by extending the first side surface LE1 of the parent component toward the second intersection line P2, and the fourth extension surface ET4, which is obtained by extending the third side surface LE3 of the parent component toward the second intersection line P2.

[0188] The region demarcated by the first side surface LE1 of the parent component, the first boundary surface BR1, and the second boundary surface BR2 is defined as the first region RE1.

[0189] The third boundary surface BR3 is defined as the surface that bisects the space separated by the fifth extension surface ET5, which is obtained by extending the second side surface LE2 of the parent component toward the third intersection line P3, and the sixth extension surface ET6, which is obtained by extending the fourth side surface LE4 of the parent component toward the third intersection line P3.

[0190] The region demarcated by the second side surface LE2 of the parent component, the first boundary surface BR1, and the third boundary surface BR3 is defined as the second region RE2.

[0191] The fourth boundary surface BR4 is defined as the surface that bisects the space separated by the seventh extension surface ET7, which is obtained by extending the third side surface LE3 of the parent component toward the fourth intersection line P4, and the eighth extension surface ET8, which is obtained by extending the fourth side surface LE4 of the parent component toward the fourth intersection line P4.

[0192] The region demarcated by the third side surface LE3 of the parent component, the second boundary surface BR2, and the fourth boundary surface BR4 is defined as the third region RE3.

[0193] The region demarcated by the fourth side surface LE4 of the parent component, the third boundary surface BR3, and the fourth boundary surface BR4 is defined as the fourth region RE4.

[0194] In the above description, the first side surface LE1 and the first boundary surface BR1 intersect at 135 degrees, and the first side surface LE1 and the second boundary surface BR2 intersect at 135 degrees. However, the description is not limited to this, and the first side surface LE1 and the first boundary surface BR1 may intersect at an angle greater than 90 degrees, and the first side surface LE1 and the second boundary surface BR2 may intersect at an angle greater than 90 degrees.

[0195] The second side surface LE2 and the first interface BR1 intersect at 135 degrees, and the second side surface LE2 and the third interface BR3 intersect at 135 degrees. However, the design is not limited to this; the second side surface LE2 and the first interface BR1 may intersect at an angle greater than 90 degrees, and the second side surface LE2 and the third interface BR3 may intersect at an angle greater than 90 degrees.

[0196] The third side surface LE3 and the second interface BR2 intersect at 135 degrees, and the third side surface LE3 and the fourth interface BR4 intersect at 135 degrees. However, the design is not limited to this; the third side surface LE3 and the second interface BR2 may intersect at an angle greater than 90 degrees, and the third side surface LE3 and the fourth interface BR4 may intersect at an angle greater than 90 degrees.

[0197] The fourth side surface LE4 and the third interface BR3 intersect at 135 degrees, and the fourth side surface LE4 and the fourth interface BR4 intersect at 135 degrees. However, the design is not limited to this; the fourth side surface LE4 and the third interface BR3 may intersect at an angle greater than 90 degrees, and the fourth side surface LE4 and the fourth interface BR4 may intersect at an angle greater than 90 degrees.

[0198] The sub-component placement design unit 12 places sub-components connected to pins of parent components arranged along the first side surface LE1, and sub-components directly or indirectly connected to those sub-components, in the first region RE1. The sub-component placement design unit 12 places sub-components connected to pins of parent components arranged along the second side surface LE2, and sub-components directly or indirectly connected to those sub-components, in the second region RE2. The sub-component placement design unit 12 places sub-components connected to pins of parent components arranged along the third side surface LE3, and sub-components directly or indirectly connected to those sub-components, in the third region RE3. The sub-component placement design unit 12 places sub-components connected to pins of parent components arranged along the fourth side surface LE4, and sub-components directly or indirectly connected to those sub-components, in the fourth region RE4.

[0199] The sub-component placement design unit 12 places sub-components with the same priority on lines that are the same distance from the parent component.

[0200] If the sub-component placement design unit 12 cannot place all sub-components of the same priority on the same line in any of the four regions, it places one or more sub-components of the same priority on the next closest line from the parent component within the same region.

[0201] Figure 39 shows an example of the arrangement of first-generation sub-components of the same priority. Sub-components CH1 to CH5 are all first-generation high-priority sub-components or all first-generation low-priority sub-components and have the same priority. In the first region RE1, sub-components CH2 and CH4 are placed in the first line closest to the parent component PR1, and sub-components CH1, CH3, and CH5 are placed in the second line, the next closest to the parent component PR1. In the second line, sub-component CH1 is placed beyond the second extension plane ET2, and sub-component CH5 is placed beyond the fourth extension plane ET4.

[0202] Furthermore, components within a proximity block can be placed not only on the front surface of the circuit board but also on the back surface. Next, the processing of S505 to S508 from the second time onward will be explained.

[0203] In the detailed step S601 of S505, initially, the parent component placement pattern design unit 31 generated multiple candidate placement patterns for parent component models, in which the position and orientation of the parent component models were arbitrarily changed.

[0204] In subsequent iterations, the parent component placement pattern design unit 31 generates multiple candidate placement patterns for the current multiple parent component models from one or more placement patterns generated based on the scoring results in the previous overall placement design process (i.e., one or more placement patterns generated upon completion of S607). For example, the parent component placement pattern design unit 31 generates multiple candidate placement patterns for the current multiple parent component models by changing the position and orientation of each parent component model in the one or more placement patterns generated in the previous iteration.

[0205] In the detailed step S701 of S506, initially, the circuit diagram group area pattern design unit 32 generated multiple candidate area patterns in which the position and size of the circuit diagram group model were arbitrarily changed.

[0206] In subsequent iterations, the circuit diagram group area pattern design unit 32 generates multiple candidate area patterns for the current iteration from one or more area patterns generated based on the scoring results in the previous overall layout design process (i.e., one or more area patterns generated upon completion of S707). For example, the circuit diagram group area pattern design unit 32 generates multiple candidate area patterns for the current iteration by changing the position and size of each area in the one or more area patterns generated in the previous iteration.

[0207] In the detailed step S801 of S507, initially, the overall layout pattern design unit 33 generated multiple candidate overall layout patterns by arranging the parent component models in each of the layout patterns of the multiple parent component models included in each circuit diagram group model within each of the region patterns of the multiple circuit diagram group models. The overall layout pattern design unit 33 arranged the parent component model group, consisting of one or more parent component models included in the circuit diagram group model, so that its center coincided with the center of the region of the circuit diagram group model.

[0208] In subsequent iterations, the overall layout pattern design unit 33 generates multiple candidate overall layout patterns in the current overall layout design process based on one or more overall layout patterns generated in the previous overall layout design process based on the scoring results (i.e., one or more overall layout patterns generated upon completion of S807). For example, the overall layout pattern design unit 33 generates multiple candidate overall layout patterns by arranging parent component models in each of the arrangement patterns of multiple parent component models included in each circuit diagram group model within each of the region patterns of multiple circuit diagram group models. The overall layout pattern design unit 33 may choose to retain only those of the generated multiple candidate overall layout patterns that are dissimilar to the one or more overall layout patterns generated in the previous iteration. Similarity may mean, for example, that the overlap of the positions of adjacent blocks between patterns is 50% or more.

[0209] The processing in S508 from the second time onward is the same as the processing in the first time described above. In S509, the component position adjustment unit 34 adjusts the arrangement of individual components. If the overall arrangement pattern design unit 33 determines that a first sub-component of a neighboring block belonging to a circuit diagram group is positioned outside the area of ​​the circuit diagram group, and the position of the first sub-component overlaps with the position of a second sub-component of another neighboring block, the component position adjustment unit 34 moves either the first sub-component or the second sub-component so that the positions of the first and second sub-components do not overlap. The component position adjustment unit 34 may also determine which of the first and second sub-components to move based on priority.

[0210] Figures 40(a) and 40(b) illustrate an example of adjusting the placement of components. As shown in Figure 40(a), a first child component (low-priority child component) of a neighboring block A belonging to a certain circuit diagram group is located outside the area of ​​the circuit diagram group, and the position of the first child component overlaps (interferes with) the position of a second child component (high-priority child component) of another neighboring block B.

[0211] As shown in Figure 40(b), the component position adjustment unit 34 moves the position of the first sub-component (low priority component) of the adjacent block A. The component position adjustment unit 34 moves the first sub-component to a position where the connection between the pins is closest and it does not overlap with other components.

[0212] Figures 41(a) and 41(b) illustrate another example of adjusting the placement of components. In Figure 41(a), similar to Figure 40(a), the first child component (low-priority child component) of a neighboring block A belonging to a certain schematic group is located outside the area of ​​the schematic group, and the position of the first child component overlaps (interferes with) the position of a second child component (high-priority child component) of another neighboring block B.

[0213] As shown in Figure 41(b), the component position adjustment unit 34 moves the position of the first sub-component (low-priority component) of the adjacent block A. The component position adjustment unit 34 moves the first sub-component to a position where the connection between the pins is closest and it does not overlap with other components.

[0214] The component position adjustment unit 34 selects one of the low-priority components to be moved if the positions of two low-priority components overlap. The component position adjustment unit 34 selects one of the high-priority components to be moved if the positions of two high-priority components overlap.

[0215] Referring to Figure 5, in S510, the overall layout design unit 15 outputs the layout result. For example, the overall layout design unit 15 may output multiple representative layout patterns obtained through multiple iterations. Alternatively, the overall layout design unit 15 may output the best of the multiple representative layout patterns obtained through multiple iterations.

[0216] Figure 42 is a diagram showing the hardware configuration of the printed circuit board design apparatus 1. The printed circuit board design apparatus 1 can be implemented using a known personal computer or the like. The printed circuit board design apparatus 1 comprises a processor 100, a display device 200 such as a liquid crystal display, an input device 300 such as a keyboard and mouse, an internal storage device 400 such as memory, an external storage device 500 such as a hard disk or a portable recording medium, and a communication device 600.

[0217] The input device 300 receives input from the designer. The communication device 600 can receive printed circuit board design programs and data from external sources such as the internet. The external storage device 500 can store printed circuit board design programs and data. The internal storage device 400 stores printed circuit board design programs and data transferred from the communication device 600 or the external storage device 500. The processor 100 displays the circuit diagram, proximity blocks, netlist, etc., on the display device 200. The processor 100 executes the printed circuit board design program stored in the internal storage device 400. As a result, processing is executed according to the flowchart in Figure 2.

[0218] (Modifications) This disclosure is not limited to the embodiments described above, but also includes, for example, the following modifications:

[0219] (1) In the above embodiment, standard scores were used to calculate the score, but it is not necessary to use standard scores. That is, the following formula (C1A) may be used instead of formula (C1), and the following formula (C2A) may be used instead of formula (C2).

[0220] Si = (WS1*A1 + WS2*A2 + WS3*A3 + WS4*A4 + WS5*A5) * NS ... (C1A) Ti = (WT1*B1 + WT2*B2) * NT ... (C2A) (2) In the above embodiment, as shown in Figure 11, when each of the multiple paths connects the connection pins of three or more parent component models, virtual pins are set from the connection pins of the three or more parent component models of the multiple paths. As a result, as shown in Figure 14, RB1 and RB2 are connected by virtual pins, and RB2 and RB3 are connected by virtual pins. The disclosure is not limited to these. Even when each of the multiple paths connects the connection pins of three or more parent component models, virtual pins may be set from the connection pins of two parent component models included in the multiple paths. In this case, RB1 and RB2 are connected by virtual pins, RB2 and RB3 are connected by virtual pins, and RB1 and RB3 are connected by virtual pins.

[0221] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims and not by the foregoing description, and all modifications within the meaning and scope of the claims are intended to be included.

[0222] 1 Printed circuit board design device, 2 Data input unit, 3 CAD unit, 4 User I / F, 5 Conversion unit, 6 Net attribute setting unit, 7 Net point count setting unit, 8 Grouping processing unit, 10 Component classification unit, 11 Proximity block generation unit, 12 Child component placement design unit, 13 Power tree setting unit, 14 Position specification unit, 15 Overall placement design unit, 21 Placement design unit, 25 Component priority setting unit, 31 Parent component placement pattern design unit, 32 Circuit diagram group area pattern design unit, 33 Overall placement pattern design unit, 34 Component position adjustment unit, 41 Model generation unit, 100 Processor, 200 Display device, 300 Input device, 400 Internal storage device, 500 External storage device, 600 Communication device.

Claims

1. A printed circuit board design apparatus comprising: a component classification unit that classifies components into parent components, child components directly or indirectly connected to the parent components, and other components; a proximity block generation unit that generates a plurality of proximity blocks, each containing a parent component and the child components; and an overall arrangement design unit that arranges the parent components within the plurality of proximity blocks and arranges the child components within the proximity blocks based on the arrangement of the parent components.

2. A printed circuit board design apparatus according to claim 1, further comprising a grouping processing unit that generates multiple circuit diagram groups by dividing a circuit diagram into multiple parts, wherein the overall layout design unit executes an overall layout design process multiple times to arrange multiple adjacent blocks included in the multiple circuit diagram groups, the overall layout design unit includes, for each circuit diagram group, a parent component layout pattern design unit that generates one or more layout patterns within the circuit diagram group for parent components in multiple adjacent blocks included in the circuit diagram group, a circuit diagram group area pattern design unit that generates one or more area patterns representing the areas of the multiple circuit diagram groups on a board, for each area pattern, an overall layout pattern design unit that generates one or more overall layout patterns in which one or more parent components included in the circuit diagram groups are arranged in the area of ​​the multiple circuit diagram groups in the area pattern according to the layout pattern, and a child component layout design unit that arranges child components in the multiple adjacent blocks based on the arrangement of the parent components.

3. The parent component placement pattern design unit generates one or more placement patterns of the parent components within the circuit diagram group based on the connection relationships of the plurality of parent components, and further comprises a model generation unit, the model generation unit determines that the first parent component and the second parent component are connected if the first net connected to the first parent component is a signal attribute, the second net connected to the second parent component is a signal attribute, and the first net and the second net are directly connected, connected via only one child component, or connected via only two or more child components and one or more signal attribute nets, and determines that the first parent component and the second parent component are connected if the first net connected to the first parent component is a power supply attribute, the second net connected to the second parent component is a power supply attribute, and the first net and the second net are directly connected, connected via only one child component, or connected via only two or more child components and one or more power supply attribute nets. If the first net connected to the first parent component is of the ground attribute, and the second net connected to the second parent component is of the ground attribute, and the first net and the second net are directly connected, connected via only one child component, or connected via only two or more child components and one or more nets of the ground attribute, then it is determined that the first parent component and the second parent component are connected. If the first net connected to the first parent component is of the signal attribute, and the second net connected to the second parent component is of the signal attribute, and the first net and the second net are connected via only two or more child components and one or more nets of the power attribute, or connected via only two or more child components, one or more nets of the power attribute, and one or more nets of the signal attribute, then it is determined that the first parent component and the second parent component are connected.The printed circuit board design apparatus according to claim 2, wherein it is determined that the first parent component and the second parent component are connected if the first net connected to the first parent component is a signal attribute, the second net connected to the second parent component is a signal attribute, and the first net and the second net are connected only via two or more child components and one or more ground attribute nets, or only via two or more child components, one or more ground attribute nets, and one or more signal attribute nets.

4. The printed circuit board design apparatus according to claim 3, wherein the parent component placement pattern design unit generates multiple candidate placement patterns for multiple parent components included in the circuit diagram group, scores the multiple candidate placement patterns, and generates one or more placement patterns based on the scoring results.

5. The printed circuit board design apparatus according to claim 4, wherein the parent component placement pattern design unit clusters the plurality of candidate placement patterns based on the placement position of the parent component, scores the plurality of candidate placement patterns belonging to the same cluster, selects one or more candidate placement patterns based on the scoring results and placement area, and generates one or more placement patterns based on the scoring results of the selected candidate placement patterns for the plurality of clusters.

6. The printed circuit board design apparatus according to claim 5, wherein the parent component placement pattern design unit scores the candidate placement pattern based on at least one of a first index representing the distance between two parent components included in the candidate placement pattern, a second index representing the orientation relationship between the two parent components, a third index representing whether or not wiring twist occurs between the two parent components, a fourth index representing whether or not wiring connected to another parent component intersects with the wiring between the two parent components, and a fifth index representing whether or not there is a horizontal wiring path, a vertical wiring path, or a horizontal and vertical wiring path with one bend to connect the two parent components.

7. A printed circuit board design apparatus according to claim 6, further comprising a net score setting unit for setting the net score between two components included in the circuit diagram, wherein the parent component placement pattern design unit calculates the score of the two parent components based on the first index, the second index, the third index, the fourth index, and the fifth index and the sum of the net scores between the two parent components, and scores the candidate placement pattern based on the sum of the scores for all sets of two connected parent components included in the candidate placement pattern and the area of ​​the candidate placement pattern.

8. A printed circuit board design apparatus according to claim 2, comprising a positioning unit for specifying positioning components whose positions on the board are specified, and semi-positioning components whose approximate positions on the board are specified by the designer, wherein the circuit diagram group area pattern design unit generates a plurality of areas of the circuit diagram group in addition to the areas where the unplaced positioning components and semi-positioning components are placed.

9. The printed circuit board design apparatus according to claim 8, wherein the circuit diagram group region pattern design unit generates a plurality of candidate region patterns for a plurality of circuit diagram groups, scores the plurality of candidate region patterns, and generates one or more of the region patterns based on the scoring results.

10. The printed circuit board design apparatus according to claim 9, wherein the circuit diagram group area pattern design unit clusters a plurality of candidate area patterns based on the location of the area of ​​the circuit diagram group, scores a plurality of candidate area patterns belonging to the same cluster, selects one or more candidate area patterns based on the scoring results and placement area, scores the selected plurality of candidate area patterns, and generates a plurality of area patterns based on the scoring results.

11. The printed circuit board design apparatus according to claim 10, wherein the circuit diagram group area pattern design unit scores the candidate area pattern based on at least one of a first index representing the distance between the areas of two circuit diagram groups included in the candidate area pattern, and a second index representing whether or not wiring connected to another circuit diagram group intersects with wiring between the areas of the two circuit diagram groups.

12. A printed circuit board design apparatus according to claim 11, further comprising a net score setting unit for setting the net score between two components included in the circuit diagram, wherein the circuit diagram group area pattern design unit calculates the score for one set of areas of the two circuit diagram groups based on the first index, the second index and the sum of the net scores between the two circuit diagram groups, and scores the candidate area pattern based on the sum of the scores for all sets of areas of the two connected circuit diagram groups included in the candidate area pattern.

13. The printed circuit board design apparatus according to claim 12, wherein the distance between the regions of the two circuit diagram groups is the Manhattan distance between the virtual pins of the two circuit diagram groups, and the virtual pins of the circuit diagram groups are the centers of the circuit diagram groups.

14. The printed circuit board design apparatus according to claim 9, wherein the circuit diagram group area pattern design unit generates a rectangular area having an area greater than or equal to the sum of the areas of all components included in the circuit diagram group, and less than or equal to twice the sum, as a candidate area pattern for the circuit diagram group.

15. The printed circuit board design apparatus according to claim 9, wherein the circuit diagram group region pattern design unit generates a plurality of candidate region patterns in the current overall layout design process from one or more region patterns generated in the previous overall layout design process based on the scoring results.

16. The printed circuit board design apparatus according to claim 2, wherein the overall arrangement pattern design unit generates a plurality of candidate overall arrangement patterns obtained by arranging a plurality of parent components included in a plurality of circuit diagram groups in each of the plurality of arrangement patterns for each of the plurality of arrangement patterns, scores the plurality of candidate overall arrangement patterns, and generates one or more overall arrangement patterns based on the scoring results.

17. The printed circuit board design apparatus according to claim 16, wherein the overall layout pattern design unit clusters a plurality of candidate overall layout patterns based on the placement positions of two parent components in two circuit diagram groups within the same or different circuit diagram groups, scores a plurality of candidate overall layout patterns belonging to the same cluster, selects one or more candidate overall layout patterns based on the scoring results and placement area, and generates one or more overall layout patterns based on the scoring results of the selected candidate overall layout patterns for the plurality of clusters.

18. The printed circuit board design apparatus according to claim 17, wherein the overall arrangement pattern design unit scores the candidate overall arrangement pattern based on at least one of a first index representing the distance between two parent components included in the candidate overall arrangement pattern, a second index representing the orientation relationship between the two parent components, a third index representing whether or not wiring twist occurs between the two parent components, a fourth index representing whether or not wiring connected to another parent component intersects with wiring between the two parent components, and a fifth index representing whether or not there is a horizontal wiring path, a vertical wiring path, or a horizontal and vertical wiring path with one bend to connect the two parent components.

19. A printed circuit board design apparatus according to claim 18, further comprising a net score setting unit for setting the net score between two parent components included in the circuit diagram, wherein the overall arrangement pattern design unit calculates the score of one set of the two parent components based on the sum of the first index, the second index, the third index, the fourth index, and the fifth index and the net score between the two parent components, and scores the candidate overall arrangement pattern based on the sum of the scores for all sets of two connected parent components included in the candidate overall arrangement pattern.

20. The printed circuit board design apparatus according to claim 16, wherein the overall layout pattern design unit generates a plurality of candidate overall layout patterns in the current overall layout design process based on one or more overall layout patterns generated in the previous overall layout design process based on the scoring results.

21. A printed circuit board design apparatus according to claim 7 or 19, wherein one of the two parent components is designated as a first parent component, and the other of the two parent components is designated as a second parent component, the ideal orientation relationship is defined as the time when the first side of the first parent component closest to the virtual pin of the first parent component and the second side of the second parent component closest to the virtual pin of the second parent component face each other and are the shortest distance apart, the second index represents the magnitude of the deviation from the ideal orientation, the coordinates of the virtual pins of the first parent component are the weighted average of the coordinates of one or more pins of the first parent component that connect to the second parent component, according to the number of points in the net connecting to the pins, and the coordinates of the virtual pins of the second parent component are the weighted average of the coordinates of one or more pins of the second parent component that connect to the first parent component, according to the number of points in the net connecting to the pins.

22. The printed circuit board design apparatus according to claim 2, wherein the component classification unit further comprises a component priority setting unit that sets the generation of the sub-components, sets the first generation sub-components as high-priority sub-components and low-priority sub-components, sets the priority of the high-priority sub-components and a first group of sub-components directly or indirectly connected to the high-priority sub-components higher than the low-priority sub-components and a second group of sub-components directly or indirectly connected to the low-priority sub-components, and the sub-component placement design unit places the sub-components of the first group in a position close to the parent component for all adjacent blocks, and then places the sub-components of the second group for all adjacent blocks.

23. The printed circuit board design apparatus according to claim 22, wherein the component priority setting unit sets a priority for a plurality of sub-components belonging to the first group based on the generation or the attributes of the connected net, sets a priority for a plurality of sub-components belonging to the second group based on the generation or the attributes of the connected net, the sub-component placement design unit arranges all adjacent blocks in order from the highest priority sub-components belonging to the first group to the position closest to the parent component, and the sub-component placement design unit arranges all adjacent blocks in order from the highest priority sub-components belonging to the second group to the position closest to the parent component.

24. The first side surface of the parent component and the second side surface of the parent component are connected at a first intersection line, the first side surface of the parent component and the third side surface of the parent component are connected at a second intersection line, the surface dividing the space separated by a first extension surface obtained by extending the first side surface of the parent component toward the first intersection line and a second extension surface obtained by extending the second side surface of the parent component toward the first intersection line is defined as the first boundary surface, the surface dividing the space separated by a third extension surface obtained by extending the first side surface of the parent component toward the second intersection line and a fourth extension surface obtained by extending the third side surface of the parent component toward the second intersection line is defined as the second boundary surface, the region separated by the first side surface of the parent component, the first boundary surface and the second boundary surface is defined as the first region, The printed circuit board design apparatus according to claim 2, wherein the first side surface and the first interface intersect at an angle greater than 90 degrees, the first side surface and the second interface intersect at an angle greater than 90 degrees, and the sub-component placement design unit places sub-components directly connected to first pins arranged along the first side surface of the parent component, and sub-components directly or indirectly connected to the sub-components, in the first region.

25. The printed circuit board design apparatus according to claim 24, wherein the first side surface and the first interface intersect at a 135-degree angle, and the first side surface and the second interface intersect at a 135-degree angle.

26. The printed circuit board design apparatus according to claim 24, wherein, if the sub-component placement design unit cannot place all sub-components having the same priority on lines that are the same distance from the parent component within the first region, it places one or more sub-components having the same priority on lines that are the next closest distance from the parent component within the first region.

27. The printed circuit board design apparatus according to claim 2, wherein the overall layout design unit further comprises a component position adjustment unit that moves the first child component or the second child component so that the positions of the first child component and the second child component do not overlap when the first child component of a parent component belonging to the circuit diagram group is located outside the area of ​​the circuit diagram group and the position of the first child component overlaps with the position of a second child component of another parent component.

28. The printed circuit board design apparatus according to claim 27, wherein the component position adjustment unit determines which sub-component to move based on the priority of the first sub-component and the second sub-component.

29. A printed circuit board design program that causes a computer to perform the following steps: generate multiple circuit diagram groups by dividing a circuit diagram into multiple parts; classify components into parent components, child components directly or indirectly connected to the parent components, and other components; generate multiple proximity blocks, each containing a parent component and the child components; and perform an overall layout design process multiple times to arrange the multiple proximity blocks contained in the multiple circuit diagram groups in the multiple circuit diagram groups, wherein the overall layout design process includes, for each circuit diagram group, generating one or more arrangement patterns of the multiple parent components contained in the circuit diagram group within the circuit diagram group; generating one or more region patterns representing the regions of the multiple circuit diagram groups on a circuit board; for each region pattern, generating one or more overall layout patterns in which one or more proximity blocks contained in the circuit diagram groups are arranged in the arrangement patterns in the regions of the multiple circuit diagram groups in the region pattern; and arranging the child components in the multiple proximity blocks based on the arrangement of the parent components.

30. A printed circuit board design method comprising: generating multiple circuit diagram groups by dividing a circuit diagram into multiple parts; classifying components into parent components, child components directly or indirectly connected to the parent components, and other components; generating multiple proximity blocks, each including a parent component and the child components; and performing an overall layout design process multiple times to arrange the multiple proximity blocks included in the multiple circuit diagram groups, wherein the step of performing the overall layout design process multiple times includes, for each circuit diagram group, generating one or more arrangement patterns of the multiple parent components included in the circuit diagram group within the circuit diagram group; generating one or more region patterns representing the regions of the multiple circuit diagram groups on a board; for each region pattern, generating one or more overall layout patterns in which one or more proximity blocks included in the circuit diagram groups are arranged in the arrangement pattern within the regions of the multiple circuit diagram groups in the region pattern; and arranging the child components within the multiple proximity blocks based on the arrangement of the parent components.

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