Pixel driving circuit, display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display, and provides a pixel driving circuit, a display panel and a display apparatus. The pixel driving circuit comprises: a driving circuit, a first compensation circuit, a second compensation circuit, a voltage stabilizing circuit and a second storage circuit; the driving circuit is connected to a first node, a second node and a third node, and is used for forming a driving current between the second node and the third node on the basis of a signal of the first node; the first compensation circuit is connected to the first node, a fourth node and a first gate driving signal terminal, and the first compensation circuit is configured to connect the first node and the fourth node in response to a signal of the first gate driving signal terminal; the second compensation circuit is connected to the third node, the fourth node and a second enabling signal terminal, and the second compensation circuit is configured to connect the third node and the fourth node in response to a signal of the second enabling signal terminal; the voltage stabilizing circuit is connected to the fourth node, a third initial signal terminal and a third enabling signal terminal, and the voltage stabilizing circuit is configured to transmit a signal of the third initial signal terminal to the fourth node in response to a signal of the third enabling signal terminal; the second storage circuit is connected to the fourth node, and the second storage circuit is configured to store a voltage signal of the fourth node. The display panel can improve the display effect of the display panel. (FIG. 3)

Description

Pixel driving circuit, display panel, display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, and a display device. Background Technology

[0002] In related technologies, pixel driving circuits include driving transistors. During the light-emitting stage of the pixel driving circuit driving the light-emitting unit, leakage current may occur at the gate of the driving transistor, leading to abnormal display on the display panel. Simultaneously, the hysteresis phenomenon of the driving transistor can cause problems such as image retention on the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a pixel driving circuit is provided, wherein the pixel driving circuit includes:

[0005] A driving circuit, connected to a first node, a second node, and a third node, is used to generate a driving current between the second node and the third node based on the signal from the first node.

[0006] A first compensation circuit is connected to the first node, the fourth node, and the first gate drive signal terminal. The first compensation circuit is used to respond to the signal of the first gate drive signal terminal to connect the first node and the fourth node.

[0007] The second compensation circuit is connected to the third node, the fourth node, and the second enable signal terminal. The second compensation circuit is used to respond to the signal of the second enable signal terminal to connect the third node and the fourth node.

[0008] A voltage regulator circuit is connected to the fourth node, the third initial signal terminal, and the third enable signal terminal. The voltage regulator circuit is used to respond to the signal of the third enable signal terminal to transmit the signal of the third initial signal terminal to the fourth node.

[0009] A second storage circuit is connected to the fourth node, and the second storage circuit is used to store the voltage signal of the fourth node.

[0010] In one exemplary embodiment of this disclosure, the driving circuit includes:

[0011] A driving transistor, with its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the first node;

[0012] The first compensation circuit includes:

[0013] The second transistor has its first electrode connected to the first node, its second electrode connected to the fourth node, and its gate connected to the first gate drive signal terminal.

[0014] The second compensation circuit includes:

[0015] The ninth transistor has its first terminal connected to the fourth node, its second terminal connected to the third node, and its gate connected to the second enable signal terminal.

[0016] The voltage regulator circuit includes:

[0017] The eighth transistor has its first terminal connected to the third initial signal terminal, its second terminal connected to the fourth node, and its gate connected to the third enable signal terminal.

[0018] The second storage circuit includes:

[0019] The second capacitor has its first electrode connected to the fourth node.

[0020] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0021] A data writing circuit is connected to a data signal terminal, a second node, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the second node.

[0022] A first reset circuit is connected to a first initial signal terminal, a first node, and a first reset signal terminal. The first reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the first initial signal terminal to the first node.

[0023] A light-emitting control circuit is connected to a first power supply terminal, a second node, a first enable signal terminal, a third node, and a fifth node. The light-emitting control circuit is used to connect the first power supply terminal and the second node in response to a signal from the first enable signal terminal, and to connect the third node and the fifth node in response to a signal from the first enable signal terminal.

[0024] The second reset circuit is connected to the second initial signal terminal, the fifth node, and the third enable signal terminal. The second reset circuit is used to respond to the signal of the third enable signal terminal to transmit the signal of the second initial signal terminal to the fifth node.

[0025] A first storage circuit is connected between the first node and the first power supply terminal.

[0026] In one exemplary embodiment of this disclosure, the data writing circuit includes:

[0027] The fourth transistor has its first terminal connected to the data signal terminal, its second terminal connected to the second node, and its gate connected to the first gate drive signal terminal.

[0028] The first reset circuit includes:

[0029] The first transistor has a first terminal connected to the first initial signal terminal, a second terminal connected to the first node, and a gate connected to the first reset signal terminal.

[0030] The light-emitting control circuit includes:

[0031] The fifth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the second node, and its gate connected to the first enable signal terminal.

[0032] The sixth transistor has its first terminal connected to the third node, its second terminal connected to the fifth transistor, and its gate connected to the first enable signal terminal.

[0033] The second reset circuit includes:

[0034] The seventh transistor has its first terminal connected to the second initial signal terminal, its second terminal connected to the fifth node, and its gate connected to the third enable signal terminal.

[0035] The first storage circuit includes:

[0036] The first capacitor has a first electrode connected to the first node and a second electrode connected to the first power supply terminal.

[0037] In one exemplary embodiment of this disclosure, the pixel driving circuit includes:

[0038] A light-emitting control circuit is connected to a first power supply terminal, a second node, and a first enable signal terminal. The light-emitting control circuit is used to respond to the signal of the first enable signal terminal to connect the first power supply terminal and the second node.

[0039] The second storage circuit includes:

[0040] The second capacitor has its first electrode connected to the fourth node. The second electrode of the second capacitor includes one or more sub-electrodes, and the one or more sub-electrodes are connected in a one-to-one correspondence with one or more of the first enable signal terminal, the second enable signal terminal, and the third node.

[0041] In one exemplary embodiment of this disclosure, the second storage circuit includes:

[0042] The second capacitor has its first electrode connected to the fourth node;

[0043] The pixel driving circuit further includes a first capacitor, a first electrode connected to the first node, and a second electrode connected to the first power supply terminal.

[0044] The ratio of the capacitance of the first capacitor to the capacitance of the second capacitor is 8-12.

[0045] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes the pixel driving circuit described above.

[0046] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0047] Substrate;

[0048] Multiple pixel driving circuits are located on one side of the substrate, and the multiple pixel driving circuits are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect.

[0049] The pixel driving circuit includes a driving transistor, a second transistor, a ninth transistor, an eighth transistor, and a second capacitor. The first electrode of the second transistor is connected to the gate of the driving transistor, the second electrode of the second transistor is connected to the first electrode of the ninth transistor, the second electrode of the ninth transistor is connected to the second electrode of the driving transistor, the first electrode of the eighth transistor is connected to a third initial signal line, the second electrode of the eighth transistor is connected to the second electrode of the second transistor, and the first electrode of the second capacitor is connected to the second electrode of the eighth transistor.

[0050] In one exemplary embodiment of this disclosure, the display panel further includes:

[0051] A first gate layer, comprising a first gate line, a second enable signal line, and a first conductive portion, wherein the orthogonal projections of the first gate line and the second enable signal line on the substrate extend along the first direction, wherein a portion of the structure of the first gate line is used to form the gate of the second transistor, a portion of the structure of the second enable signal line is used to form the gate of the ninth transistor, and the first conductive portion is used to form the gate of the driving transistor.

[0052] In the same pixel driving circuit, the orthographic projection of the second enable signal line on the substrate is located between the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first gate line on the substrate.

[0053] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a fourth transistor, wherein the first terminal of the fourth transistor is connected to a data line, and the second terminal is connected to the first terminal of the driving transistor;

[0054] The display panel also includes:

[0055] An active layer is located on one side of the substrate. The active layer includes a second active portion, a fourth active portion, and a third active portion. The second active portion is used to form the channel region of the second transistor, the fourth active portion is used to form the channel region of the fourth transistor, and the third active portion is used to form the channel region of the driving transistor.

[0056] A first gate layer is located on the side of the active layer opposite to the substrate. The first gate layer includes a first gate line. The orthographic projection of the first gate line on the substrate extends along a first direction. A portion of the structure of the first gate line is used to form the gates of the second transistor and the fourth transistor, respectively.

[0057] In the first direction of the same pixel driving circuit, the orthographic projection of the third active part on the substrate is at least partially located between the orthographic projection of the second active part on the substrate and the orthographic projection of the fourth active part on the substrate.

[0058] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes a fifth transistor and a seventh transistor. The first electrode of the fifth transistor is connected to a first power line, and the second electrode is connected to the first electrode of the driving transistor. The first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit.

[0059] The display panel also includes:

[0060] A first gate layer, comprising a first gate line, a first enable signal line, a first conductive portion, and a third enable signal line, wherein the orthogonal projections of the first gate line, the first enable signal line, and the third enable signal line on the substrate extend along the first direction; a portion of the structure of the first gate line is used to form the gate of the second transistor; a portion of the structure of the first enable signal line is used to form the gate of the fifth transistor; the first conductive portion is used to form the gate of the driving transistor; and a portion of the structure of the third enable signal line is used to form the gates of the seventh transistor and the eighth transistor, respectively.

[0061] In the same pixel driving circuit, the orthographic projection of the first enable signal line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is far from the orthographic projection of the first gate line on the substrate, and the orthographic projection of the third enable signal line on the substrate is located on the side where the orthographic projection of the first enable signal line on the substrate is far from the orthographic projection of the first conductive part on the substrate.

[0062] In one exemplary embodiment of this disclosure, the display panel further includes:

[0063] An active layer is located on one side of the substrate. The active layer includes a third active portion, a seventh active portion, and an eighth active portion. The third active portion is used to form the channel region of the driving transistor, the seventh active portion is used to form the channel region of the seventh transistor, and the eighth active portion is used to form the channel region of the eighth transistor.

[0064] In the first direction of the same pixel driving circuit, the orthographic projection of the third active part on the substrate is at least partially located between the orthographic projection of the seventh active part on the substrate and the orthographic projection of the eighth active part on the substrate.

[0065] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a fifth transistor, wherein the first terminal of the fifth transistor is connected to a first power supply line, and the second terminal is connected to the first terminal of the driving transistor;

[0066] The display panel also includes:

[0067] A first gate layer, the first gate layer including a first enable signal line, the first enable signal line extending along the first direction in its orthogonal projection on the substrate, and a portion of the structure of the first enable signal line being used to form the gate of the fifth transistor;

[0068] The first source / drain layer is located on the side of the first gate layer away from the substrate. The first source / drain layer includes a third bridging portion, which is connected to the second electrode of the eighth transistor and the second electrode of the second transistor through vias.

[0069] Wherein, the orthographic projection of the third bridging portion on the substrate and the orthographic projection of the first enable signal line on the substrate at least partially overlap, the portion of the third bridging portion intersecting with the first enable signal line is used to form at least a portion of the first electrode of the second capacitor, and the portion of the first enable signal line intersecting with the third bridging portion is used to form at least a portion of the second electrode of the second capacitor.

[0070] In one exemplary embodiment of this disclosure, the first enable signal line includes a first extension and a second extension, wherein the size of the orthographic projection of the first extension on the substrate in a direction perpendicular to its extension is greater than the size of the orthographic projection of the second extension on the substrate in a direction perpendicular to its extension.

[0071] The third bridging portion includes a third extension segment and a fourth extension segment. The size of the orthographic projection of the third extension segment on the substrate in the direction perpendicular to its extension is larger than the size of the orthographic projection of the fourth extension segment on the substrate in the direction perpendicular to its extension.

[0072] Wherein, the orthographic projection of the first extension segment on the substrate and the orthographic projection of the third extension segment on the substrate intersect.

[0073] In one exemplary embodiment of this disclosure, the first gate layer further includes:

[0074] The second enable signal line extends along the first direction in its orthogonal projection on the substrate, and a portion of the structure of the second enable signal line is used to form the gate of the ninth transistor.

[0075] Wherein, the orthographic projection of the third bridging portion on the substrate and the orthographic projection of the second enable signal line on the substrate overlap, the portion of the third bridging portion intersecting with the second enable signal line is used to form at least a portion of the first electrode of the second capacitor, and the portion of the second enable signal line intersecting with the third bridging portion is used to form at least a portion of the second electrode of the second capacitor.

[0076] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first capacitor, wherein a first electrode of the first capacitor is connected to the gate of the driving transistor, and a second electrode is connected to a first power supply line;

[0077] The third bridging portion includes a third extension section, a fourth extension section, and a fifth extension section, wherein the fourth extension section connects the third extension section and the fifth extension section;

[0078] The orthographic projections of the third extension segment and the fifth extension segment on the substrate extend along the second direction, and the orthographic projections of the third extension segment and the fifth extension segment on the substrate are spaced apart in the second direction and spaced apart in the first direction;

[0079] Wherein, the extension direction of the fourth extension segment on the substrate intersects both the first direction and the second direction, and the orthogonal projection of the fourth extension segment on the substrate and the orthogonal projection of the second electrode of the first capacitor on the substrate at least partially overlap.

[0080] In one exemplary embodiment of this disclosure, the display panel further includes:

[0081] An active layer is located on one side of the substrate. The active layer includes a second active portion, a ninth active portion, and a fourteenth active portion. The second active portion is used to form the channel region of the second transistor, the ninth active portion is used to form the channel region of the ninth transistor, and the fourteenth active portion is connected between the second active portion and the ninth active portion.

[0082] A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a first bridging portion, which is connected to the gate of the driving transistor and the first electrode of the second transistor through vias.

[0083] The shielding part is connected to the stable voltage terminal;

[0084] Wherein, the orthographic projection of the first bridging portion on the substrate and the orthographic projection of the fourteenth active portion on the substrate overlap, and the overlapping area of ​​the orthographic projection of the first bridging portion on the substrate and the orthographic projection of the fourteenth active portion on the substrate overlaps with the orthographic projection of the shielding portion on the substrate.

[0085] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first capacitor, wherein a first electrode of the first capacitor is connected to the gate of the driving transistor, and a second electrode is connected to a first power supply line;

[0086] The display panel also includes:

[0087] A second gate layer is located between the active layer and the first source / drain layer. The second gate layer includes a second conductive portion, which is used to form the second electrode of the first capacitor.

[0088] The shielding portion is located in the second gate layer and is connected to the second conductive portion.

[0089] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first capacitor, wherein a first electrode of the first capacitor is connected to the gate of the driving transistor, and a second electrode is connected to a first power supply line;

[0090] The display panel also includes:

[0091] An active layer, at least a portion of the structure of which is used to form the channel region of the transistor in the pixel driving circuit;

[0092] A first gate layer is located on the side of the active layer opposite to the substrate, and at least a portion of the structure of the first gate layer is used to form the gate of a transistor in the pixel driving circuit.

[0093] A second gate layer is located on the side of the first gate layer away from the substrate, and at least a portion of the structure of the second gate layer is used to form the second electrode of the first capacitor;

[0094] A first source / drain layer is located on the side of the second gate layer opposite to the substrate, and at least a portion of the structure of the first source / drain layer is bridged between different transistors.

[0095] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0096] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0097] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0098] Figure 1 is a schematic diagram of the pixel driving circuit in the related technology;

[0099] Figure 2 is a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0100] Figure 3 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0101] Figure 4 is a structural layout of the active layer in the display panel shown in Figure 3;

[0102] Figure 5 is a structural layout of the first gate layer in the display panel shown in Figure 3;

[0103] Figure 6 is a structural layout of the second gate layer in the display panel shown in Figure 3;

[0104] Figure 7 is a structural layout of the first source / drain layer in the display panel shown in Figure 3;

[0105] Figure 8 is a structural layout of the second source / drain layer in the display panel shown in Figure 3;

[0106] Figure 9 is a structural layout of the electrode layer in the display panel shown in Figure 3;

[0107] Figure 10 is a structural layout of the active layer and the first gate layer in the display panel shown in Figure 3;

[0108] Figure 11 is a structural layout of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 3.

[0109] Figure 12 is a structural layout of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 3;

[0110] Figure 13 is a structural layout of the active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 3;

[0111] Figure 14 is a structural layout of the electrode layer in the display panel of this disclosure;

[0112] Figure 15 is a partial cross-sectional view of the display panel shown in Figure 3, cut along the dashed line BB.

[0113] Figure 16 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0114] Figure 17 is a structural layout of the second gate layer in the display panel shown in Figure 16. Detailed Implementation

[0115] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0116] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0117] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0118] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0119] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0120] Figure 1 shows a schematic diagram of a pixel driving circuit in the related art. This pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. In this configuration, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to node N; the first electrode of the second transistor T2 is connected to node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to node N, the first electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to node N, and the second electrode is connected to the first power supply terminal VDD; the first electrode of the eighth transistor T8 is connected to the third initial signal line Vinit3, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the second reset signal terminal Re2. The pixel driving circuit can be connected to a light-emitting unit L, which is used to drive the light-emitting unit L to emit light. The light-emitting unit L can be connected between the second terminal of the sixth transistor T6 and the second power supply terminal VSS. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors.

[0121] The pixel driving circuit driving method can include a reset stage, a data writing stage, and a light-emitting stage. In the reset stage, the first reset signal terminal Re1 outputs a low-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs a first initial signal to node N, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. In the data writing stage, the first gate driving signal terminal G1 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and simultaneously the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. In the light-emitting stage: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in capacitor C. In this pixel driving circuit, the output current of the driving transistor is I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth). 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the driving transistor threshold voltage.

[0122] However, during the light-emitting stage, the gate of the driving transistor T3 leaks current through the second transistor T2, which causes changes in the brightness of the light-emitting unit. At the same time, the hysteresis phenomenon of the driving transistor can cause display problems such as image retention on the display panel.

[0123] Based on this, this exemplary embodiment first provides a pixel driving circuit, as shown in FIG2, which is a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure. The pixel driving circuit may include: a driving circuit 1, a first compensation circuit 2, a second compensation circuit 3, a voltage regulator circuit 4, and a second storage circuit 5. A driving circuit 1 is connected to a first node N1, a second node N2, and a third node N3. The driving circuit 1 is used to generate a driving current between the second node N2 and the third node N3 based on the signal from the first node N1. A first compensation circuit 2 is connected to the first node N1, a fourth node N4, and a first gate drive signal terminal G1. The first compensation circuit is used to connect the first node N1 and the fourth node N4 in response to the signal from the first gate drive signal terminal G1. A second compensation circuit 3 is connected to the third node N3, the fourth node N4, and a second enable signal terminal EM2. The second compensation circuit 3 is used to connect the third node N3 and the fourth node N4 in response to the signal from the second enable signal terminal EM2. A voltage regulator circuit 4 is connected to the fourth node N4, a third initial signal terminal Vinit3, and a third enable signal terminal EM3. The voltage regulator circuit 4 is used to transmit the signal from the third initial signal terminal Vinit3 to the fourth node N4 in response to the signal from the third enable signal terminal EM3. A second storage circuit 5 is connected to the fourth node N4 and is used to store the voltage signal of the fourth node N4.

[0124] The driving method of the pixel driving circuit provided in this exemplary embodiment may include a first reset stage, a data writing stage, a second reset stage, and a light emission stage. In the first reset phase, a first initial signal can be input to the first node N1. In the data writing phase, a data signal can be input to the second node N2, and the first compensation circuit 2 and the second compensation circuit 3 are simultaneously turned on to input a compensation voltage Vdata+Vth to the first node N1 through the driving circuit 1, the first compensation circuit 2, and the second compensation circuit 3, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving circuit. In the second reset phase, the second compensation circuit 3 and the voltage regulator circuit 4 are turned on, and the first compensation circuit 2 is turned off. A third initial signal is input to the third node N3 through the voltage regulator circuit 4 and the second compensation circuit 3 to improve the hysteresis problem of the driving circuit. At the same time, this setting can reduce the voltage difference between the first node N1 and the fourth node N4, thereby reducing the leakage current of the first node N1. In the light-emitting phase, the first compensation circuit 2, the second compensation circuit 3, and the voltage regulator circuit 4 are turned off. The voltage signal of the fourth node N4 stored in the second storage circuit 5 can continuously reduce the leakage current from the first node N1 to the fourth node N4. At the same time, the driving circuit provides driving current to the light-emitting unit through the third node N3 to drive the light-emitting unit to emit light.

[0125] The pixel driving circuit provided in this exemplary embodiment can improve the hysteresis problem of the driving circuit and reduce the leakage current of the first node N1.

[0126] In this exemplary embodiment, as shown in FIG2, the driving circuit 1 may include: a driving transistor T3, the first electrode of the driving transistor T3 being connected to the second node N2, the second electrode being connected to the third node N3, and the gate being connected to the first node N1; the first compensation circuit includes: a second transistor T2, the first electrode of the second transistor T2 being connected to the first node N1, the second electrode being connected to the fourth node N4, and the gate being connected to the first gate driving signal terminal G1; the second compensation circuit includes: a ninth transistor T9, the first electrode of the ninth transistor T9 being connected to the fourth node N4, the second electrode being connected to the third node N3, and the gate being connected to the second enable signal terminal EM2; the voltage regulator circuit includes: an eighth transistor T8, the first electrode of the eighth transistor T8 being connected to the third initial signal terminal Vinit3, the second electrode being connected to the fourth node N4, and the gate being connected to the third enable signal terminal EM3; the second storage circuit includes: a second capacitor C2, the first electrode of the second capacitor C2 being connected to the fourth node N4.

[0127] In this exemplary embodiment, as shown in FIG2, the pixel driving circuit may further include: a data writing circuit 6, a first reset circuit 7, a light emission control circuit 8, a second reset circuit 9, and a first storage circuit 10. The data writing circuit 6 is connected to a data signal terminal Da, a second node N2, and a first gate driving signal terminal G1. The data writing circuit 6 is used to transmit the signal of the data signal terminal Da to the second node N2 in response to the signal of the first gate driving signal terminal G1. The first reset circuit 7 is connected to a first initial signal terminal Vinit1, a first node N1, and a first reset signal terminal Re1. The first reset circuit 7 is used to transmit the signal of the first initial signal terminal Vinit1 to the first node N1 in response to the signal of the first reset signal terminal Re1. The light emission control circuit 8 is connected to a first power supply terminal VDD, a second node N2, a first enable signal terminal EM1, and a third node N3. The fifth node N5, the light-emitting control circuit 8 is used to connect the first power supply terminal VDD and the second node N2 in response to the signal of the first enable signal terminal EM1, and to connect the third node N3 and the fifth node N5 in response to the signal of the first enable signal terminal EM1; the second reset circuit 9 is connected to the second initial signal terminal Vinit2, the fifth node N5 and the third enable signal terminal EM3, and the second reset circuit 9 is used to transmit the signal of the second initial signal terminal Vinit2 to the fifth node N5 in response to the signal of the third enable signal terminal EM3; the first storage circuit 10 is connected between the first node N1 and the first power supply terminal VDD.

[0128] In this exemplary embodiment, as shown in FIG2, the data writing circuit includes: a fourth transistor T4, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the second node N2, and the gate is connected to the first gate drive signal terminal G1; the first reset circuit includes: a first transistor T1, the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode is connected to the first node N1, and the gate is connected to the first reset signal terminal Re1; the light emission control circuit includes: a fifth transistor T5 and a sixth transistor T6, the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the second node N2, and the gate is connected to the first enable signal terminal EM1; the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the fifth transistor, and the gate is connected to the first enable signal terminal EM1; the second reset circuit includes: a seventh transistor T7, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the second electrode is connected to the fifth node N5, and the gate is connected to the third enable signal terminal EM3; the first storage circuit includes: a first capacitor C1, the first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode is connected to the first power supply terminal VDD.

[0129] In this exemplary embodiment, as shown in FIG2, the second electrode of the second capacitor C2 can be connected to the first enable signal terminal EM1. It should be understood that in other exemplary embodiments, the second electrode of the second capacitor C2 can also be connected to other signal terminals such as the first enable signal terminal EM1, the second enable signal terminal EM2, and the third node N3. Furthermore, the second electrode of the second capacitor C2 can also include multiple sub-electrodes, and the multiple sub-electrodes can be connected one-to-one with multiple of the first enable signal terminal EM1, the second enable signal terminal EM2, and the third node N3. For example, the second electrode of the second capacitor C2 may include two sub-electrodes, which can be connected one-to-one with any two signal terminals among the first enable signal terminal EM1, the second enable signal terminal EM2, and the third node N3. That is, the two sub-electrodes are respectively connected to any two signal terminals among the first enable signal terminal EM1, the second enable signal terminal EM2, and the third node N3. As another example, the second electrode of the second capacitor C2 may include three sub-electrodes, which can be connected one-to-one with the first enable signal terminal EM1, the second enable signal terminal EM2, and the third node N3. That is, the three sub-electrodes are respectively connected to the first enable signal terminal EM1, the second enable signal terminal EM2, and the third node N3.

[0130] In this exemplary embodiment, as shown in FIG2, the pixel driving circuit can be used to drive the light-emitting unit L to emit light. The first electrode of the light-emitting unit L can be connected to the second electrode of the sixth transistor T6, and the second electrode can be connected to the second power supply terminal VSS.

[0131] In this exemplary embodiment, as shown in FIG2, the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor is 8-12. For example, this ratio can be 8, 9, 10, 11, 12, etc. If the capacitance of the second capacitor is too large, the pixel driving circuit will have difficulty writing the third initial signal to the fourth node during the limited second reset phase, resulting in leakage current in the first node. If the capacitance of the second capacitor is too small, it will have difficulty stabilizing the voltage of the fourth node during the longer light-emitting phase, resulting in leakage current in the first node. This exemplary embodiment sets the capacitance value of the second capacitor to an appropriate size, which can effectively improve the leakage current problem of the first node N1.

[0132] This exemplary embodiment also provides a display panel, which may include a substrate, an active layer, a first gate layer, a second gate layer, a first source / drain layer, a second source / drain layer, and an electrode layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 3-13, Figure 3 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, Figure 4 is a structural layout diagram of the active layer in the display panel shown in Figure 3, Figure 5 is a structural layout diagram of the first gate layer in the display panel shown in Figure 3, Figure 6 is a structural layout diagram of the second gate layer in the display panel shown in Figure 3, Figure 7 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 3, Figure 8 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 3, Figure 9 is a structural layout diagram of the electrode layer in the display panel shown in Figure 3, Figure 10 is a structural layout diagram of the active layer and the first gate layer in the display panel shown in Figure 3, Figure 11 is a structural layout diagram of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 3, Figure 12 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 3, and Figure 14 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 3.

[0133] As shown in Figure 13, the display panel may include multiple pixel driving circuits as shown in Figure 2. As shown in Figure 13, the multiple pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X. The first pixel driving circuit P1 and the second pixel driving circuit P2 may be mirror-symmetrically arranged with a mirror symmetry plane AA. The mirror symmetry plane AA may be perpendicular to the substrate. Furthermore, the orthographic projections of the first pixel driving circuit P1 and the second pixel driving circuit P2 on the substrate may be symmetrically arranged with the intersection of the mirror symmetry plane AA and the substrate as the axis of symmetry. The first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit. The display panel may include multiple repeating units arrayed in the first direction X and the second direction Y, where the first direction X may be a row direction and the second direction Y may be a column direction.

[0134] As shown in Figures 3, 4, and 10, the active layer may include: a first active section 71, a second active section 72, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, an eighteenth active section 718, a nineteenth active section 719, and a twentieth active section 720. The first active portion 71 is used to form the channel region of the first transistor T1; the second active portion 72 is used to form the channel region of the second transistor T2; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 can be used to form the channel region of the ninth transistor T9; the tenth active portion 710 is connected between the first active portion 71 and the second active portion 72; the... Eleventh active part 711 and twelfth active part 712 are connected to both ends of fourth active part 74; thirteenth active part 713 is connected to the side of first active part 71 away from second active part 72; fourteenth active part 714 is connected between second active part 72 and ninth active part 79; fifteenth active part 715 is connected between third active part 73 and fifth active part 75; sixteenth active part 716 is connected between sixth active part 76 and seventh active part 67; seventeenth active part 717 is connected to the end of seventh active part 77 away from sixth active part 76; eighteenth active part 718 is connected to the end of fifth active part 75 away from third active part 73; nineteenth active part 719 and twentieth active part 720 are connected to both ends of eighth active part 78.

[0135] As shown in Figures 3, 4, and 10, the orthographic projection of the third active part 73 on the substrate is at least partially located between the orthographic projection of the second active part 72 on the substrate and the orthographic projection of the fourth active part 74 on the substrate.

[0136] As shown in Figures 3, 4, and 10, in the first direction of the same pixel driving circuit, the orthographic projection of the third active part 73 on the substrate is at least partially located between the orthographic projection of the seventh active part 77 on the substrate and the orthographic projection of the eighth active part 78 on the substrate.

[0137] As shown in Figures 3, 5, and 10, the first gate layer may include: a first conductive portion 11, a first gate line G1, a first reset signal line Re1, a first enable signal line EM1, a second enable signal line EM2, and a third enable signal line EM3. The first gate line G1 can be used to provide the first gate drive signal terminal in Figure 2; the first enable signal line EM1 can be used to provide the first enable signal terminal in Figure 2; the second enable signal line EM2 can be used to provide the second enable signal terminal in Figure 2; the third enable signal line EM3 can be used to provide the third enable signal terminal in Figure 2; and the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 2. The orthogonal projections of the first gate line G1, the first reset signal line Re1, the first enable signal line EM1, the second enable signal line EM2, and the third enable signal line EM3 onto the substrate can all extend along the first direction X. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the first capacitor C1. The orthographic projection of the first gate line G1 on the substrate covers the orthographic projections of the fourth active portion 74 and the second active portion 72 on the substrate. A portion of the structure of the first gate line G1 is used to form the gate of the fourth transistor T4, and a portion of the structure of the first gate line G1 is used to form the gate of the second transistor T2. The orthographic projection of the first enable signal line EM1 on the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 on the substrate. A portion of the structure of the first enable signal line EM1 can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the second enable signal line EM2 on the substrate covers the orthographic projection of the ninth active portion 79 on the substrate. A portion of the structure of the second enable signal line EM2 can be used to form the gate of the ninth transistor T9. The orthographic projection of the third enable signal line EM3 onto the substrate covers the orthographic projections of the seventh active portion 77 and the eighth active portion 78 onto the substrate. A portion of the structure of the third enable signal line EM3 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first reset signal line Re1 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. This display panel can utilize the first gate layer as a mask to perform conductor processing on the active layer; that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductive structure.

[0138] As shown in Figures 3, 5, and 10, in the same pixel driving circuit, the orthographic projection of the second enable signal line EM2 on the substrate is located between the orthographic projection of the first conductive part 11 on the substrate and the orthographic projection of the first gate line G1 on the substrate.

[0139] As shown in Figures 3, 5, and 10, in the same pixel driving circuit, the orthographic projection of the first enable signal line EM1 on the substrate is located on the side where the orthographic projection of the first conductive part 11 on the substrate is far from the orthographic projection of the first gate line G1 on the substrate, and the orthographic projection of the third enable signal line EM3 on the substrate is located on the side where the orthographic projection of the first enable signal line EM1 on the substrate is far from the orthographic projection of the first conductive part 11 on the substrate.

[0140] As shown in Figures 3, 6, and 11, the second gate layer may include: a second conductive portion 22, a first protrusion 23, a second protrusion 24, a first initial signal line Vinit1, and a third initial signal line Vinit3. The orthographic projection of the second conductive portion 22 on the substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 is used to form the second electrode of the first capacitor C1. The orthographic projections of the first initial signal line Vinit1 and the third initial signal line Vinit3 on the substrate extend along the first direction X. The first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 2, and the third initial signal line Vinit3 is used to provide the third initial signal terminal in Figure 2. The first protrusion 23 and the second protrusion 24 are connected to the same side of the first initial signal line Vinit1 in the second direction Y. The orthographic projection of the first protrusion 23 on the substrate is located between the orthographic projections of the tenth active portion 710 and the eleventh active portion 711 on the substrate, and the first protrusion 23 can shield the signal interference between the first node N1 and the data signal terminal. The orthographic projection of the second protrusion 24 on the substrate and the orthographic projection of the tenth active part 710 on the substrate at least partially overlap, and the second protrusion 24 can stabilize the voltage of the first node N1.

[0141] As shown in Figures 3, 7, and 12, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a seventh bridging portion 47, an eighth bridging portion 48, a second initial signal line Vinit2, and a first fan-out line FIPH. The first bridging portion 41 connects to the tenth active portion 710 and the first conductive portion 11 via vias, connecting the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the gate of the driving transistor T3. A through-hole 221 is formed on the second conductive portion 22, and the through-hole connecting the first conductive portion 11 and the first bridging portion 41 can be disposed through the through-hole 221. The second bridging portion 42 can connect to the eleventh active portion 711 via vias, connecting the first electrode of the fourth transistor. The third bridging section 43 can be connected to the fourteenth active section 714 and the twentieth active section 720 via vias, respectively, to connect the second electrode of the eighth transistor T8 and the second electrode of the second transistor T2. The fourth bridging section 44 can be connected to the second conductive section 22 and the eighteenth active section 718 via vias, respectively, to connect the second electrode of the first capacitor C1 and the first electrode of the fifth transistor T5. Two fourth bridging sections 44 located in adjacent repeating units in the first direction X can be interconnected. The fifth bridging section 45 can be connected to the sixteenth active section 716 via vias, respectively, to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The sixth bridging section 46 can be connected to the twelfth active section 712 and the fifteenth active section 715 via vias, respectively, to connect the second electrode of the fourth transistor and the first electrode of the driving transistor T3. The seventh bridging section 47 can connect the first initial signal line Vinit1 and the thirteenth active section 713 via vias to connect the first electrode and the first initial signal terminal of the first transistor T1. Two pixel driving circuits in the same repeating unit can share the same seventh bridging section 47. The eighth bridging section 48 can connect the third initial signal line Vinit3 and the nineteenth active section 719 via vias to connect the first electrode and the third initial signal terminal of the eighth transistor T8. Two pixel driving circuits in the same repeating unit can share the same eighth bridging section 48. The second initial signal line Vinit2 can connect the seventeenth active section 717 via vias to connect the second initial signal terminal and the first electrode of the seventh transistor T7. The orthogonal projection of the first fan-out line FIPH onto the substrate can extend along the first direction X. The first fan-out line FIPH can serve as a row-direction fan-out line connecting data lines in the FIP (Fanout In Pixel).

[0142] As shown in Figures 3, 7, and 12, the orthographic projection of the third bridging portion 43 on the substrate and the orthographic projection of the first enable signal line EM1 on the substrate at least partially overlap. The portion of the third bridging portion 43 intersecting with the first enable signal line EM1 is used to form at least a portion of the first electrode of the second capacitor C2, and the portion of the first enable signal line EM1 intersecting with the third bridging portion 43 is used to form at least a portion of the second electrode of the second capacitor C2.

[0143] As shown in Figures 3, 5, 7, and 12, the first enable signal line EM1 includes a first extension segment EM11 and a second extension segment EM12. The orthographic projection of the first extension segment EM11 onto the substrate in a direction perpendicular to its extension is larger than the orthographic projection of the second extension segment EM12 onto the substrate in the same direction. The third bridging portion 43 includes a third extension segment 433 and a fourth extension segment 434. The orthographic projection of the third extension segment 433 onto the substrate in a direction perpendicular to its extension is larger than the orthographic projection of the fourth extension segment 434 onto the substrate in the same direction. The orthographic projections of the first extension segment EM11 and the third extension segment 433 onto the substrate intersect. This configuration increases the local linewidth of the first enable signal line EM1 and the third bridging portion 43, thereby increasing the capacitance of the second capacitor C2.

[0144] As shown in Figures 3, 7, and 12, the orthographic projection of the third bridging portion 43 on the substrate and the orthographic projection of the second enable signal line EM2 on the substrate overlap. The portion of the third bridging portion 43 intersecting with the second enable signal line EM2 is used to form at least a portion of the first electrode of the second capacitor, and the portion of the second enable signal line EM2 intersecting with the third bridging portion 43 is used to form at least a portion of the second electrode of the second capacitor. This arrangement can further increase the capacitance of the second capacitor.

[0145] As shown in Figures 3, 7, and 12, the third bridging portion 43 includes a third extension segment 433, a fourth extension segment 434, and a fifth extension segment 435. The fourth extension segment 434 connects the third extension segment 433 and the fifth extension segment 435. The orthographic projections of the third extension segment 433 and the fifth extension segment 435 on the substrate extend along the second direction Y. The orthographic projections of the third extension segment 433 and the fifth extension segment 435 on the substrate are spaced apart in the second direction Y and spaced apart in the first direction X. The extension direction of the orthographic projection of the fourth extension segment 434 on the substrate intersects both the first direction X and the second direction Y. The orthographic projection of the fourth extension segment 434 on the substrate and the orthographic projection of the second conductive portion 22 on the substrate at least partially overlap. A portion of the structure of the second conductive portion 22 can be used to form a portion of the second electrode of the second capacitor. This arrangement can further increase the capacitance of the second capacitor.

[0146] As shown in Figures 3, 8, and 13, the second source / drain layer may include a data line Da, a first power line VDD, a second fan-out line FIPV, and a ninth bridge portion 59. The orthographic projections of the data line Da, the first power line VDD, and the second fan-out line FIPV on the substrate all extend along the second direction Y. The data line Da provides the data signal terminal shown in Figure 2. The data line Da can be connected to the second bridge portion 42 via a via to connect the data signal terminal and the first terminal of the fourth transistor T4. The first power line VDD provides the first power terminal shown in Figure 2. The first power line VDD can be connected to the fourth bridge portion 44 via a via to connect the first power terminal and the first terminal of the fifth transistor T5 and the second terminal of the capacitor C. The second fan-out line FIPV can serve as a column-direction fan-out line connecting the data line in the FIP (Fanout In Pixel).

[0147] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in other conductive layers. For example, any one of the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in any one of the active layer, the second gate layer, the first source / drain layer, and the second source / drain layer.

[0148] As shown in Figures 3, 9, and 14, Figure 14 is a structural layout of the electrode layer in the display panel of this disclosure, showing multiple electrode sections. The electrode layer may include multiple electrode sections: the multiple electrode sections include a first electrode section R, a second electrode section B, and a third electrode section G. Each electrode section can be connected to a ninth bridge section 59 through a via to connect to the second electrode of a sixth transistor. Among the multiple electrode sections connected to the same row pixel driving circuit, the first electrode section R, the third electrode section G, the second electrode section B, and the third electrode section G are alternately distributed in the row direction; in two adjacent column pixel driving circuits, multiple first electrode sections R and multiple second electrode sections B are connected to the same column pixel driving circuit, and the first electrode sections R and second electrode sections B connected to the same column pixel driving circuit are alternately distributed in the column direction, and multiple third electrode sections G are connected to another column pixel driving circuit. In this design, the orthographic projection of the first electrode portion R onto the substrate coincides with the orthographic projection of its corresponding opening onto the pixel definition layer. Similarly, the orthographic projection of the third electrode portion G onto the substrate coincides with the orthographic projection of its corresponding opening onto the pixel definition layer. The orthographic projection of the second electrode portion B onto the substrate coincides with the orthographic projection of its corresponding opening onto the pixel definition layer. The third electrode portion G can serve as the first electrode of a green light-emitting unit, the first electrode portion R can serve as the first electrode of a red light-emitting unit, and the second electrode portion B can serve as the first electrode of a blue light-emitting unit. Furthermore, the edges of the third electrode portion G, the first electrode portion R, and the second electrode portion B are all provided with epitaxial portions, which can be redundantly provided to form electrode portions that coincide with the pixel opening.

[0149] Figure 15 shows a partial cross-sectional view of the display panel shown in Figure 3, taken along the dashed line BB. The display panel may further include a buffer layer 101, a first insulating layer 102, a second insulating layer 103, a dielectric layer 104, a passivation layer 105, a first planarization layer 106, and a second planarization layer 107. The substrate 100, buffer layer 101, active layer, first insulating layer 102, first gate layer, second insulating layer 103, second gate layer, dielectric layer 104, first source / drain layer, passivation layer 105, first planarization layer 106, second source / drain layer, second planarization layer 107, and electrode layer are sequentially stacked. The buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 104 can be a silicon nitride layer; the materials of the first planarization layer 106 and the second planarization layer 107 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 105 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer and the second gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of either the first or second source / drain layer can be less than the sheet resistance of either the first or second gate layer.

[0150] As shown in Figures 16 and 17, Figure 16 is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 17 is a structural layout diagram of the second gate layer in the display panel shown in Figure 16. The second gate layer may further include a shielding portion 25, which is connected to a second conductive portion. The overlapping area of ​​the orthographic projection of the first bridging portion 41 on the substrate and the orthographic projection of the fourteenth active portion 714 on the substrate overlaps with the orthographic projection of the shielding portion 25 on the substrate. The shielding portion 25 can shield the fourteenth active portion 714 from interference to the gate of the driving transistor.

[0151] It should be understood that in other exemplary embodiments, the shielding portion 25 may also be located in other conductive layers, and the shielding portion 25 may also be connected to other stable voltage terminals. For example, the shielding portion 25 may be located in the first gate layer or in other conductive layers added between the active layer and the first source / drain layer, and the shielding portion 25 may be connected to other stable voltage terminals such as the first initial signal line, the second initial signal line, and the third initial signal line.

[0152] It should be noted that, as shown in Figure 3-16, the chamfered black squares drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black circles drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black rectangles drawn on the side of the electrode layer away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Vias at different positions can penetrate different insulating layers.

[0153] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0154] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0155] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0156] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A pixel driving circuit, wherein, The pixel driving circuit comprises: a driving circuit connected to the first node, the second node and the third node, for forming a driving current between the second node and the third node according to a signal of the first node; a first compensation circuit connected to the first node, the fourth node and the first gate driving signal terminal, for connecting the first node and the fourth node in response to a signal of the first gate driving signal terminal; a second compensation circuit connected to the third node, the fourth node and the second enable signal terminal, for connecting the third node and the fourth node in response to a signal of the second enable signal terminal; a voltage stabilizing circuit connected to the fourth node, the third initial signal terminal and the third enable signal terminal, for transmitting a signal of the third initial signal terminal to the fourth node in response to a signal of the third enable signal terminal; a second storage circuit connected to the fourth node, for storing a voltage signal of the fourth node.

2. The pixel driving circuit according to claim 1, wherein The driving circuit comprises: a driving transistor with a first electrode connected to the second node, a second electrode connected to the third node and a gate connected to the first node; The first compensation circuit comprises: a second transistor with a first electrode connected to the first node, a second electrode connected to the fourth node and a gate connected to the first gate driving signal terminal; The second compensation circuit comprises: a ninth transistor with a first electrode connected to the fourth node, a second electrode connected to the third node and a gate connected to the second enable signal terminal; The voltage stabilizing circuit comprises: an eighth transistor with a first electrode connected to the third initial signal terminal, a second electrode connected to the fourth node and a gate connected to the third enable signal terminal; The second storage circuit comprises: a second capacitor with a first electrode connected to the fourth node.

3. The pixel driving circuit of claim 1, wherein, The pixel driving circuit further comprises: a data writing circuit connected to the data signal terminal, the second node and the first gate driving signal terminal, for transmitting a signal of the data signal terminal to the second node in response to a signal of the first gate driving signal terminal; a first reset circuit connected to the first initial signal terminal, the first node and the first reset signal terminal, for transmitting a signal of the first initial signal terminal to the first node in response to a signal of the first reset signal terminal; a light emitting control circuit connected to the first power supply terminal, the second node, the first enable signal terminal, the third node and the fifth node, for connecting the first power supply terminal and the second node in response to a signal of the first enable signal terminal, and for connecting the third node and the fifth node in response to a signal of the first enable signal terminal; a second reset circuit connected to the second initial signal terminal, the fifth node and the third enable signal terminal, for transmitting a signal of the second initial signal terminal to the fifth node in response to a signal of the third enable signal terminal; a first storage circuit connected between the first node and the first power supply terminal.

4. The pixel driving circuit of claim 3, wherein, The data writing circuit comprises: A fourth transistor, a first electrode of which is connected to the data signal terminal, a second electrode of which is connected to the second node, and a gate of which is connected to the first gate drive signal terminal; The first reset circuit comprises: A first transistor, a first electrode of which is connected to the first initial signal terminal, a second electrode of which is connected to the first node, and a gate of which is connected to the first reset signal terminal; The light emitting control circuit comprises: A fifth transistor, a first electrode of which is connected to the first power supply terminal, a second electrode of which is connected to the second node, and a gate of which connected to the first enable signal terminal; A sixth transistor, a first electrode of which is connected to the third node, a second electrode of which is connected to the fifth transistor, and a gate of which is connected to the first enable signal terminal; The second reset circuit comprises: A seventh transistor, a first electrode of which is connected to the second initial signal terminal, a second electrode of which is connected to the fifth node, and a gate of which is connected to the third enable signal terminal; The first storage circuit comprises: A first capacitor, a first electrode of which is connected to the first node, and a second electrode of which is connected to the first power supply terminal.

5. The pixel driving circuit of claim 1, wherein, The pixel driving circuit comprises: A light emitting control circuit, which is connected to the first power supply terminal, the second node, and the first enable signal terminal, and is used for connecting the first power supply terminal and the second node in response to a signal of the first enable signal terminal; The second storage circuit comprises: A second capacitor, a first electrode of which is connected to the fourth node, and a second electrode of which comprises one or more sub-electrodes, one or more of the sub-electrodes being connected to one or more of the first enable signal terminal, the second enable signal terminal, and the third node in a one-to-one correspondence.

6. The pixel driving circuit of claim 1, wherein, The second storage circuit comprises: A second capacitor, a first electrode of which is connected to the third node; The pixel driving circuit further comprises a first capacitor, a first electrode of which is connected to the first node, and a second electrode thereof being connected to the first power supply terminal. The ratio of the capacitance of the first capacitor to the capacitance of the second capacitor is 8-12.

7. A display panel, wherein, The display panel comprises the pixel driving circuit of any one of claims 1-6.

8. A display panel, wherein, The display panel comprises: A substrate; A plurality of pixel driving circuits, the plurality of pixel driving circuits being located on one side of the substrate, and the plurality of pixel driving circuits being arrayed along a first direction and a second direction, the first direction and the second direction intersecting; The pixel driving circuit comprises a driving transistor, a second transistor, a ninth transistor, an eighth transistor, and a second capacitor, a first electrode of the second transistor being connected to a gate of the driving transistor, a second electrode of the second transistor being connected to a first electrode of the ninth transistor, a second electrode of the ninth transistor being connected to a second electrode of the driving transistor, a first electrode of the eighth transistor being connected to a third initial signal line, a second electrode of the eighth transistor being connected to the second electrode of the second transistor, and a first electrode of the second capacitor being connected to the second electrode of the eighth transistor.

9. The display panel of claim 8, wherein, The display panel further comprises: The first gate layer includes a first gate line, a second enable signal line, and a first conductive part, a projection of the first gate line and the second enable signal line on the substrate substrate extends along the first direction, part of the structure of the first gate line is used to form a gate of the second transistor, part of the structure of the second enable signal line is used to form a gate of the ninth transistor, and the first conductive part is used to form a gate of the driving transistor. In the same pixel driving circuit, the projection of the second enable signal line on the substrate substrate is located between the projection of the first conductive part on the substrate substrate and the projection of the first gate line on the substrate substrate.

10. The display panel of claim 8, wherein, The pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor. The display panel further includes: An active layer located on one side of the substrate substrate, the active layer includes a second active part, a fourth active part, and a third active part, the second active part is used to form a channel region of the second transistor, the fourth active part is used to form a channel region of the fourth transistor, and the third active part is used to form a channel region of the driving transistor. A first gate layer located on a side of the active layer away from the substrate substrate, the first gate layer includes a first gate line, a projection of the first gate line on the substrate substrate extends along a first direction, and part of the structure of the first gate line is used to form gates of the second transistor and the fourth transistor respectively. In the first direction of the same pixel driving circuit, the projection of the third active part on the substrate substrate is at least partially located between the projection of the second active part on the substrate substrate and the projection of the fourth active part on the substrate substrate.

11. The display panel of claim 8, wherein, The display panel further includes a light emitting unit, the pixel driving circuit is used to drive the light emitting unit to emit light, and the pixel driving circuit further includes a fifth transistor and a seventh transistor, a first electrode of the fifth transistor is connected to a first power supply line, a second electrode of the fifth transistor is connected to the first electrode of the driving transistor, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to a first electrode of the light emitting unit. The display panel further includes: The first gate layer includes a first gate line, a first enable signal line, a first conductive part, and a third enable signal line, a projection of the first gate line, the first enable signal line, and the third enable signal line on the substrate substrate extends along the first direction, part of the structure of the second gate line is used to form a gate of the second transistor, part of the structure of the first enable signal line is used to form a gate of the fifth transistor, the first conductive part is used to form a gate of the driving transistor, and part of the structure of the third enable signal line is used to form gates of the seventh transistor and the eighth transistor respectively. The first enable signal line is located on one side of the first conductive part away from the first gate line in the substrate.

12. The display panel of claim 11, wherein, The display panel further comprises: An active layer located on one side of the substrate, the active layer comprising a third active part, a seventh active part and an eighth active part, the third active part being used for forming a channel region of the driving transistor, the seventh active part being used for forming a channel region of the seventh transistor, and the eighth active part being used for forming a channel region of the eighth transistor. In the first direction of the same pixel driving circuit, the third active part is at least partially located between the seventh active part and the eighth active part on the substrate.

13. The display panel of claim 8, wherein, The pixel driving circuit further comprises a fifth transistor, the first electrode of the fifth transistor being connected to a first power supply line, and the second electrode of the fifth transistor being connected to the first electrode of the driving transistor. The display panel further comprises: A first gate layer comprising a first enable signal line, the orthogonal projection of the first enable signal line on the substrate extending along the first direction, and part of the structure of the first enable signal line being used for forming a gate electrode of the fifth transistor. A first source-drain layer located on the side of the first gate layer away from the substrate, the first source-drain layer comprising a third bridge part, the third bridge part being connected to the second electrode of the eighth transistor and the second electrode of the second transistor through vias respectively. The orthogonal projection of the third bridge part on the substrate and the orthogonal projection of the first enable signal line on the substrate at least partially overlap, the part of the third bridge part intersecting the first enable signal line being used for forming at least part of the first electrode of the second capacitor, and the part of the first enable signal line intersecting the third bridge part being used for forming at least part of the second electrode of the second capacitor.

14. The display panel of claim 13, wherein, The first enable signal line comprises a first extension segment and a second extension segment, the size of the orthogonal projection of the first extension segment on the substrate in the direction perpendicular to the extension direction being greater than the size of the orthogonal projection of the second extension segment on the substrate in the direction perpendicular to the extension direction. The third bridge part comprises a third extension segment and a fourth extension segment, the size of the orthogonal projection of the third extension segment on the substrate in the direction perpendicular to the extension direction being greater than the size of orthogonal projection of the fourth extension segment on the substrate in the direction perpendicular to the extension direction. The orthogonal projection of the first extension segment on the substrate and the orthogonal projection of the third extension segment on the substrate intersect.

15. The display panel of claim 13, wherein, The first gate layer further comprises: A second enable signal line, a projection of the second enable signal line on the substrate extends along the first direction, and a partial structure of the second enable signal line is used to form a gate of the ninth transistor; The third bridge portion is overlapped with a projection of the second enable signal line on the substrate, and a portion where the third bridge portion intersects with the second enable signal line is used to form at least part of a first electrode of the second capacitor, and a portion where the second enable signal line intersects with the third bridge portion is used to form at least part of a second electrode of the second capacitor.

16. The display panel of claim 13, wherein, The pixel driving circuit further comprises a first capacitor, a first electrode of the first capacitor is connected to the gate of the driving transistor, and a second electrode of the first capacitor is connected to a first power supply line; The third bridge portion comprises a third extending segment, a fourth extending segment and a fifth extending segment, and the fourth extending segment is connected between the third extending segment and the fifth extending segment; The third extending segment and the fifth extending segment are overlapped with a projection of the substrate in the second direction, and the third extending segment and the fifth extending segment are spaced apart in the second direction and spaced apart in the first direction; The fourth extending segment is overlapped with a projection of the first capacitor on the substrate in the first direction and the second direction.

17. The display panel of claim 8, wherein, The display panel further comprises: An active layer located on one side of the substrate, the active layer comprises a second active portion, a ninth active portion and a fourteenth active portion, the second active portion is used to form a channel region of the second transistor, the ninth active portion is used to form a channel region of the ninth transistor, and the fourteenth active portion is connected between the second active portion and the ninth active portion; A first source-drain layer located on one side of the substrate, the first source-drain layer comprises a first bridge portion, and the first bridge portion is connected to the gate of the driving transistor and the first electrode of the second transistor through a via hole respectively; A shielding portion connected to a stable voltage terminal; The first bridge portion is overlapped with a projection of the fourteenth active portion on the substrate, and an overlapping area of the first bridge portion and the projection of the fourteenth active portion on the substrate is overlapped with a projection of the shielding portion on the substrate.

18. The display panel of claim 17, wherein, The pixel driving circuit further comprises a first capacitor, a first electrode of the first capacitor isconnected to the gate of the driving transistor, and a second electrode of the first capacitor is connected to the first power supply line. The display panel further comprises: A second gate layer located between the active layer and the first source-drain layer, the second gate layer comprises a second conductive portion, and the second conductive portion is used to form a second electrode of the first capacitor; The shielding portion is located in the second gate layer and connected to the second conductive portion.

19. The display panel of claim 8, wherein, The pixel driving circuit further comprises a first capacitor, a first electrode of the first capacitor is connected to the gate of the driving transistor, and a second electrode of the first capacitor is connected to a first power supply line; The display panel further comprises: an active layer, at least part of the structure of the active layer is used to form a channel region of a transistor in the pixel driving circuit; a first gate layer, located on a side of the active layer away from the substrate, at least part of the structure of the first gate layer is used to form a gate of a transistor in the pixel driving circuit; a second gate layer, located on a side of the first gate layer away from the substrate, at least part of the structure of the second gate layer is used to form a second electrode of the first capacitor; a first source-drain layer, located on a side of the second gate layer away from the substrate, at least part of the structure of the first source-drain layer is bridged between different transistors.

20. A display device comprising: The display device comprises the display panel according to any one of claims 7-19.

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