Capacitor structure and method for forming the same

Abstract

The present application provides a capacitor structure and a method for forming the same, the method comprising: providing a semiconductor substrate; forming a groove in the semiconductor substrate, wherein the groove has a plurality of discrete columnar structures formed by a portion of the semiconductor substrate, wherein the plurality of columnar structures are distributed in an array; forming a first electrode layer on the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the groove, and the sidewall surface and the top surface of the columnar structure; forming a dielectric layer on the surface of the first electrode layer; forming a second electrode layer on the surface of the dielectric layer, wherein the second electrode layer fills the groove around the columnar structure. The method improves the electrostatic capacitance and breakdown voltage resistance of the capacitor structure, and realizes the manufacture of high-density silicon capacitors.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a capacitor structure and a method for forming the same. Background Art

[0002] The positive capacitance temperature coefficient of the commonly used capacitors in integrated circuits is small, and they can be used as bypass or DC isolation in high-stability oscillation circuits. However, in situations where stability and loss requirements are high, the capacitance of commonly used capacitors is small, and the small size has poor machinability, and they are easily broken down by pulse voltage when used in high-pulse circuits. Therefore, the development of silicon-based capacitors can adopt more general semiconductor processing technology to manufacture smaller sizes, larger electrode structure surface areas, and obtain higher capacitance density and charge and discharge speed.

[0003] At present, in order to obtain a larger electrode structure surface area and capacitance density, a trench structure is usually used to deposit a layer of silicon inner electrode, a layer of dielectric layer and a layer of metal layer as an outer electrode in the trench. However, when the trench is extended deeper, this process cannot etch an ideal silicon-based structural profile and sufficient spacing to allow the deposited layer to have good trench film formation to obtain accurate and stable capacitance performance; in addition, the two electrodes in the trench will also occupy more dielectric layer space, making it impossible to obtain more charge storage capacity; if the trench width is widened, the unit trench density will be reduced, and a better deep trench process expansion effect cannot be obtained.

[0004] Therefore, it is necessary to develop a new capacitor structure and a method for forming the same to increase the surface area of ​​the capacitor, thereby improving the electrostatic capacitance per unit area of ​​the substrate, the breakdown voltage resistance, etc. Summary of the invention

[0005] The present application provides a capacitor structure and a method for forming the same to improve the performance of the capacitor structure.

[0006] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate; forming a groove in the semiconductor substrate, wherein the groove has a plurality of discrete columnar structures composed of a portion of the semiconductor substrate, and the plurality of columnar structures are distributed in an array; forming a first electrode layer on the top surface of the semiconductor substrate, the side wall surface and the bottom surface of the groove, and the side wall surface and the top surface of the columnar structure; forming a dielectric layer on the surface of the first electrode layer; and forming a second electrode layer on the surface of the dielectric layer, wherein the second electrode layer fills the groove around the columnar structure.

[0007] Optionally, the shape of the columnar structure includes a cylinder.

[0008] Optionally, among the plurality of columnar structures distributed in an array, columnar structures in two adjacent rows are arranged in a staggered manner.

[0009] Optionally, the first electrode layer is located on the top surface of the semiconductor substrate, in a portion of the semiconductor substrate on the sidewalls and bottom of the trench, and in the sidewall region and top region of the columnar structure; or, the first electrode layer is located on the top surface of the semiconductor substrate, in a portion of the semiconductor substrate on the sidewalls and bottom of the trench, and in the entire region of the columnar structure.

[0010] Optionally, the first electrode layer is formed by a solid source diffusion process.

[0011] Optionally, the method of forming the first electrode layer using a solid source diffusion process includes forming a doping source layer on the surface of the semiconductor substrate, the surface of the trench and the surfaces of the plurality of columnar structures, the doping source layer having diffused ions; forming a covering layer on the surface of the doping source layer; after forming the covering layer, performing a thermal drive treatment to diffuse the diffused ions in the doping source layer to the top surface of the semiconductor substrate, part of the semiconductor substrate at the sidewall and bottom of the trench, and the columnar structure to form a first electrode layer; after performing the thermal drive treatment, removing the covering layer and the doping source layer.

[0012] Optionally, the material of the doping source layer includes phosphorus-doped silicon oxide, and the diffused ions include phosphorus.

[0013] Optionally, the thickness of the doping source layer is 60 nanometers to 100 nanometers; before the thermal driving process is performed, the concentration of diffused ions in the doping source layer is 15% to 25%.

[0014] Optionally, the material of the covering layer includes silicon oxide; and the thickness of the covering layer is 150 nanometers to 250 nanometers.

[0015] Optionally, the method for forming the first electrode layer includes: performing ion implantation on the top surface of the semiconductor substrate, the sidewalls and bottom of the trench, and the sidewall region and top region of the columnar structure; and performing annealing after the ion implantation.

[0016] Optionally, the process of forming the first electrode layer includes a deposition process; and the first electrode layer is located outside the semiconductor substrate and outside the columnar structure.

[0017] Optionally, the method of forming the dielectric layer on the surface of the first electrode includes an atomic layer deposition process.

[0018] Optionally, the dielectric layer is a single-layer structure, and the material of the dielectric layer includes silicon oxide or silicon nitride; or, the dielectric layer is a multi-layer stack structure; the dielectric layer includes a first dielectric sub-layer and a second dielectric sub-layer located on the first dielectric sub-layer; the material of the first dielectric sub-layer includes silicon oxide, and the material of the second dielectric sub-layer includes silicon nitride.

[0019] The present invention also provides a capacitor structure, comprising: a semiconductor substrate, wherein the semiconductor substrate has a groove, wherein the groove has a plurality of discrete columnar structures composed of part of the semiconductor substrate, wherein the plurality of columnar structures are distributed in an array; a first electrode layer, wherein the first electrode layer is located on the top surface of the semiconductor substrate, the side wall surface and the bottom surface of the groove, and the side wall surface and the top surface of the columnar structure; a dielectric layer, located on the surface of the first electrode layer; and a second electrode layer, located on the surface of the dielectric layer, wherein the second electrode fills the groove around the columnar structure.

[0020] Optionally, the plurality of columnar structures are cylinders.

[0021] Optionally, the diameter of each of the columnar structures is 0.2 micrometers to 0.8 micrometers, and the height of the columnar structures is 20 micrometers to 50 micrometers.

[0022] Optionally, among the plurality of columnar structures distributed in an array, columnar structures in two adjacent rows are arranged in a staggered manner.

[0023] Optionally, the first electrode layer is located on the top surface of the semiconductor substrate, in a portion of the semiconductor substrate on the sidewalls and bottom of the trench, and in the sidewall region and top region of the columnar structure; or, the first electrode layer is located on the top surface of the semiconductor substrate, in a portion of the semiconductor substrate on the sidewalls and bottom of the trench, and in the entire region of the columnar structure.

[0024] Optionally, the first electrode layer is located outside the semiconductor substrate and outside the columnar structure.

[0025] Optionally, the dielectric layer is a single-layer structure, and the material of the dielectric layer includes silicon oxide or silicon nitride; or, the dielectric layer is a multi-layer stack structure; the dielectric layer includes a first dielectric sub-layer and a second dielectric sub-layer located on the first dielectric sub-layer; the material of the first dielectric sub-layer includes silicon oxide, and the material of the second dielectric sub-layer includes silicon nitride.

[0026] Beneficial Effects

[0027] In the method for forming a capacitor structure provided by the technical method of the present invention, a groove is formed in the semiconductor substrate, and the groove has a plurality of discrete columnar structures composed of a portion of the semiconductor substrate, and the plurality of columnar structures are distributed in an array, so that the opening rate of the groove is relatively high. Secondly, due to the high opening rate of the groove, it is conducive to forming a deeper groove, so that the sidewall area and the bottom area of ​​the groove are relatively large. The first electrode layer is partially formed along the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the groove, and is also formed along the sidewall surface and the top surface of the columnar structure, so that the effective area of ​​the first electrode layer is increased. A dielectric layer is formed on the surface of the first electrode layer, and the dielectric layer is formed along the surface of the first electrode layer, so that the effective area of ​​the first electrode layer is increased. Correspondingly, the area of ​​the second electrode layer on the side opposite to the dielectric layer is also increased. The second electrode layer, the dielectric layer and the first electrode layer constitute a capacitor structure. As a result, the effective area of ​​the second electrode layer, the dielectric layer and the first electrode layer per unit area of ​​the substrate is increased, thereby improving the electrostatic capacitance and the breakdown voltage resistance of the capacitor structure, and realizing the manufacture of high-density silicon capacitors. In summary, the performance of the capacitor structure is improved.

[0028] Further, the first electrode layer is located on the top surface of the semiconductor substrate, in the part of the semiconductor substrate on the sidewall and bottom of the groove, and in the sidewall region and top region in the columnar structure, or the first electrode layer is located on the top surface of the semiconductor substrate, in the part of the semiconductor substrate on the sidewall and bottom of the groove, and in the entire region of the columnar structure. In other words, the first electrode layer will not occupy the space of the groove, so that the dielectric layer and the second electrode layer have more filling space, which is conducive to increasing the thickness of the dielectric layer. In this way, the breakdown voltage resistance of the capacitor structure is improved. Secondly, since the first electrode layer will not occupy the space of the groove, and the first electrode layer is located in the part of the semiconductor substrate on the sidewall and bottom of the groove, and in the columnar structure, the effective area of ​​the first electrode layer and the dielectric layer in contact is further increased, further improving the electrostatic capacitance and breakdown voltage resistance of the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only used for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0030] Figures 1 to 8 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0032] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0033] refer to Figure 1 ,in, Figure 1 (a) is a top view of the semiconductor substrate; Figure 1 (b) is a cross-sectional view of the semiconductor substrate. A semiconductor substrate 100 is provided; a trench 110 is formed in the semiconductor substrate 100, wherein the trench 110 has a plurality of discrete columnar structures 120 formed by a portion of the semiconductor substrate 100, and the plurality of columnar structures 120 are distributed in an array.

[0034] The material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon on insulator (SOI) or germanium on insulator (GOI), etc. The semiconductor substrate 100 may be one of single crystal silicon, polycrystalline silicon and amorphous silicon. The semiconductor substrate 100 may also be a structure with an epitaxial layer grown thereon.

[0035] In some embodiments of the present application, the semiconductor substrate 100 is a P-type substrate, and in a subsequent process, impurity ions may be doped on the surface of the P-type substrate through an N-type ion diffusion process to form a first electrode layer. In other embodiments of the present application, the semiconductor substrate 100 is an N-type substrate, and in a subsequent process, impurity ions may be doped on the surface of the N-type substrate through a P-type ion diffusion process to form a first electrode layer.

[0036] In some embodiments of the present application, the method for forming the groove 110 includes: forming a patterned mask layer on the semiconductor substrate 100, wherein the patterned mask layer is used to define the position of the groove 110; using the patterned mask layer as a mask, etching the semiconductor substrate 100 using an anisotropic dry etching process to form the groove 110; after etching the semiconductor substrate 100 using the anisotropic dry etching process, removing the patterned mask layer.

[0037] After the semiconductor substrate 100 is etched by an anisotropic dry etching process, before the patterned mask layer is removed, the inner wall of the groove 110 and the surface of the columnar structure 120 may be heat-treated with nitrogen to repair the etching damage. During the heat treatment of the inner wall of the groove 110 and the surface of the columnar structure 120, the temperature of the heat treatment is 800 degrees Celsius to 1200 degrees Celsius, such as 900 degrees Celsius, 1000 degrees Celsius or 1100 degrees Celsius, and the time of the heat treatment is 25 minutes to 40 minutes, such as 25 minutes, 30 minutes, 35 minutes or 40 minutes.

[0038] In some embodiments of the present application, a wet etching process is used to remove the patterned mask layer, and in the process of removing the patterned mask layer, the surface of the groove and the surface of the columnar structure are cleaned.

[0039] In some embodiments of the present application, the plurality of columnar structures 120 are cylinders. Figure 1 (a), when the number of columnar structures 120 is the same, the use of a cylindrical structure can maximize the spacing between adjacent columnar structures 120, accommodate more dielectric layers, and increase capacitance.

[0040] In some embodiments of the present application, the diameter of the plurality of columnar structures 120 is 0.2 micrometers to 0.8 micrometers, for example, 0.2 micrometers, 0.4 micrometers, 0.6 micrometers or 0.8 micrometers, etc. The smaller the diameter of the columnar structure 120, the more columnar structures 120 can be formed in the semiconductor substrate 110, the larger the surface area of ​​the capacitor, and the higher the capacitance, but too small a diameter will, on the one hand, cause the volume of the first electrode in the columnar structure 120 to be too small, affecting the performance of the capacitor; on the other hand, it will cause the ratio of the height to the diameter of the columnar structure 120 to be too large, resulting in an unstable structure and easy damage.

[0041] In some embodiments of the present application, the height of the plurality of columnar structures 120 is 20 microns to 50 microns, such as 20 microns, 30 microns, 40 microns or 50 microns, etc. The higher the height of the columnar structure 120, the larger the surface area of ​​the capacitor and the higher the capacitance, but the requirements for the etching process and the deposition process will be higher.

[0042] In some embodiments of the present application, two adjacent rows of the plurality of columnar structures 120 are arranged in a staggered manner. Figure 1(a), the two adjacent rows of the columnar structures 120 distributed in an array are staggered, not aligned, and this arrangement can form a larger number of the columnar structures 120 on the semiconductor substrate of the same area. It should be noted that only a few of the columnar structures 120 are drawn in the drawings to illustrate the arrangement of the columnar structures 120, and the number of the columnar structures 120 is not limited.

[0043] refer to Figures 2 to 5 The solid source diffusion process is used to form a first electrode layer 150 on the top surface of the semiconductor substrate 100, the sidewall surface and the bottom surface of the trench 110, and the sidewall surface and the top surface of the columnar structure 120. The first electrode layer 150 does not occupy the space of the dielectric layer subsequently formed in the trench 110, and can increase the charge storage capacity. By controlling the process parameters of the solid source diffusion process, the solid source diffusion process can form a first electrode layer 150 with good uniformity, controllable size and resistivity.

[0044] refer to Figure 2 The method for forming the first electrode layer 150 by using a solid source diffusion process includes: forming a doping source layer 130 on the surface of the semiconductor substrate 100, the surface of the groove 110, and the surface of the plurality of columnar structures 120, wherein the doping source layer 130 has diffused ions, and the diffused ions include phosphorus. For example, the material of the doping source layer 130 is PSG, and the PSG is silicon oxide doped with phosphorus. In a subsequent process, the phosphorus in the doping source layer 130 can be diffused to the surface of the semiconductor substrate 100, the groove 110, and the plurality of columnar structures 120 to form the first electrode layer 150.

[0045] In some embodiments of the present application, the method for forming the doping source layer 130 is TEOS and TEPO deposition method. The thickness of the doping source layer 130 is 60 nanometers to 100 nanometers, such as 60 nanometers, 80 nanometers or 100 nanometers, etc.; the concentration of doped phosphorus in the doping source layer 130 is 15% to 25%, such as 15%, 20% or 25%, etc.

[0046] In some embodiments of the present application, the doping ions in the doping source layer 130 may also be other types of doping ions besides phosphorus. The function of the doping source layer 130 is to provide doping ions for diffusing the doping ions on the top surface of the semiconductor substrate 100, the side wall surface and the bottom surface of the trench 110, and the side wall surface and the top surface of the columnar structure 120 to form a first electrode layer 150, as long as the doping ions in the doping source layer 130 can be used to form the first electrode layer.

[0047] refer to Figure 3, the method for forming the first electrode layer 150 by using a solid source diffusion process further includes: forming a capping layer 140 on the surface of the doping source layer 130. In the subsequent process, it is necessary to diffuse the phosphorus in the doping source layer 130 to the surface of the semiconductor substrate 100, the surface of the groove 110, and the surface of the plurality of columnar structures 120 to form the first electrode 150. According to the diffusion principle, a substance will diffuse in a direction with a lower concentration. Therefore, the capping layer 140 is required to allow the phosphorus in the doping source layer 130 to diffuse to the surface of the semiconductor substrate 100, the surface of the groove 110, and the surface of the plurality of columnar structures 120 to form the first electrode 150, rather than being gathered on the side of the doping source layer 130 away from the surface of the semiconductor substrate 100, the surface of the groove 110, and the surface of the plurality of columnar structures 120.

[0048] In some embodiments of the present application, the method for forming the cover layer 140 includes a TEOS deposition method. The thickness of the cover layer 140 is 150 nanometers to 250 nanometers, such as 150 nanometers, 200 nanometers or 250 nanometers.

[0049] In some embodiments of the present application, the material of the cover layer 140 includes silicon oxide, silicon nitride, silicon carbide, etc.

[0050] refer to Figure 4 The method for forming the first electrode layer 150 by using a solid source diffusion process further includes: performing a thermal driving process to diffuse the diffusion ions in the doping source layer 130 to the top surface of the semiconductor substrate 100, the sidewalls and bottom of the trench 110, and the columnar structure 120 to form the first electrode layer 150. The first electrode layer 150 will not occupy the space of the dielectric layer subsequently formed in the trench 110, and can increase the charge storage capacity.

[0051] In some embodiments of the present application, the plurality of columnar structures 120 are fully doped, and the first electrode layer 150 is located on the top surface of the semiconductor substrate 100, in a portion of the semiconductor substrate 100 at the sidewall and bottom of the trench 110, and in the entire region of the columnar structure 120. In other embodiments of the present application, the plurality of columnar structures 120 are only partially doped, and the first electrode layer 150 is located on the top surface of the semiconductor substrate 100, in a portion of the semiconductor substrate 100 at the sidewall and bottom of the trench 110, and in the sidewall region and top region of the columnar structure 120.

[0052] In some embodiments of the present application, the thermal drive treatment is to use nitrogen to perform thermal drive treatment on the semiconductor substrate. The temperature of the thermal drive treatment is 800 degrees Celsius to 1200 degrees Celsius, such as 900 degrees Celsius, 1000 degrees Celsius or 1100 degrees Celsius, etc.; the time of the thermal drive treatment is 100 minutes to 150 minutes, such as 100 minutes, 120 minutes or 150 minutes, etc. By controlling the process parameters of the thermal drive process, the size, resistivity and uniformity of the first electrode layer 150 can be adjusted.

[0053] refer to Figure 5 The method for forming the first electrode layer 150 by using a solid source diffusion process further includes: removing the doping source layer 130 and the covering layer 140. The doping source layer and the covering layer 140 are used to form the first electrode layer 150. After the first electrode layer 150 is formed, the doping source layer 130 and the covering layer 140 need to be removed.

[0054] In some embodiments of the present application, the method of removing the doping source layer 130 and the capping layer 140 includes wet etching.

[0055] In some other embodiments of the present application, the method for forming the first electrode layer 150 includes: performing ion implantation on the top surface of the semiconductor substrate 100, the sidewalls and bottom of the groove 110 in a portion of the semiconductor substrate 100, and the sidewall area and top area in the columnar structure 120; and performing annealing after the ion implantation.

[0056] In some other embodiments of the present application, the process of forming the first electrode layer 150 includes a deposition process; the first electrode layer 150 is located outside the semiconductor substrate 100 and outside the columnar structure 120 .

[0057] refer to Figure 6 , a dielectric layer 160 is formed on the surface of the first electrode layer 150 .

[0058] In some embodiments of the present application, the method of forming the dielectric layer 160 on the surface of the first electrode layer 150 includes an atomic layer deposition method. The atomic layer deposition method can form a film layer with good uniformity and high step coverage.

[0059] In some embodiments of the present application, the dielectric layer 160 is a single-layer structure, and the material of the dielectric layer 160 includes silicon oxide or silicon nitride.

[0060] In some other embodiments of the present application, the dielectric layer 160 is a multi-layer stack structure; the dielectric layer 160 includes a first dielectric sublayer 161 and a second dielectric sublayer 162 located on the first dielectric sublayer 161; the material of the first dielectric sublayer 161 includes silicon oxide, and the material of the second dielectric sublayer 162 includes silicon nitride.

[0061] The method for forming the first dielectric sublayer 161 includes: using H2, O2 and HCD to grow the first dielectric sublayer 161 under high temperature conditions, the high temperature is 500 degrees Celsius to 800 degrees Celsius, for example, 500 degrees Celsius, 600 degrees Celsius, 700 degrees Celsius or 800 degrees Celsius, etc., and the thickness of the first dielectric sublayer 161 is 60 nanometers to 100 nanometers, for example, 60 nanometers, 80 nanometers or 100 nanometers, etc.

[0062] In some embodiments of the present application, after growing the first dielectric sublayer 161, the semiconductor substrate may be heat treated with nitrogen at a high temperature. The high temperature is 700 degrees Celsius to 800 degrees Celsius, such as 700 degrees Celsius, 750 degrees Celsius or 800 degrees Celsius, and the heat treatment time is 100 minutes to 150 minutes, such as 100 minutes, 120 minutes or 150 minutes.

[0063] The method for forming the second dielectric sublayer 162 includes: using SiH2Cl2 to grow the second dielectric sublayer 162 under high temperature conditions, the high temperature is 550 degrees Celsius to 650 degrees Celsius, for example, 550 degrees Celsius, 580 degrees Celsius, 600 degrees Celsius or 650 degrees Celsius, etc., and the thickness of the second dielectric sublayer 162 is 100 nanometers to 150 nanometers, for example, 100 nanometers, 120 nanometers or 150 nanometers, etc.

[0064] In some other embodiments of the present application, the dielectric layer 160 may further include more dielectric sub-layers, such as a first dielectric sub-layer, a second dielectric sub-layer, a third dielectric sub-layer, and a fourth dielectric sub-layer.

[0065] refer to Figure 7 A second electrode layer 170 is formed on the surface of the dielectric layer 160 , and the second electrode layer 170 fills the groove 110 around the columnar structure 120 .

[0066] In some embodiments of the present application, the method for forming the second electrode layer 170 includes: using SiH4 and PH3 to grow the second electrode layer 170 under high temperature conditions. The high temperature is 600 degrees Celsius to 700 degrees Celsius, such as 600 degrees Celsius, 620 degrees Celsius, 650 degrees Celsius or 700 degrees Celsius. The thickness of the second electrode layer 170 is 250 nanometers to 350 nanometers, such as 250 nanometers, 300 nanometers or 350 nanometers.

[0067] In some embodiments of the present application, the second electrode layer 170 is N-type doped polysilicon, and the doping concentration of the N-type doping is 2E20cm -3 .

[0068] In some embodiments of the present application, the resistivity of the second electrode layer 170 is 1.5 mΩ·cm to 2 mΩ·cm, for example, 1.5 mΩ·cm, 1.8 mΩ·cm or 2 mΩ·cm.

[0069] refer to Figure 8 , the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer 180 on the semiconductor substrate 100, and forming a plurality of contact structures 190 in the interlayer dielectric layer 180, which penetrate the interlayer dielectric layer 180 and are electrically connected to the first electrode layer 150 and the second electrode layer 170 respectively. It should be noted that each contact structure 190 can only electrically connect to the first electrode layer 150 or the second electrode layer 170 alone, and cannot electrically connect to the first electrode layer 150 and the second electrode layer 170 at the same time. Therefore, before forming the interlayer dielectric layer 180, a portion of the second electrode layer 170 located on the semiconductor substrate 100 is first etched so that the second electrode layer 170 does not completely cover the first electrode layer 150.

[0070] In some embodiments of the present application, a passivation layer may be formed on the contact surfaces of the contact structure 190 and the first electrode layer 150 and the second electrode layer 170 respectively, and the passivation layer may reduce the resistance of the first electrode layer 150 and the second electrode layer 170 and increase the conductivity.

[0071] In some embodiments of the present application, the material of the passivation layer includes salicide.

[0072] In some embodiments of the present application, the method for forming the semiconductor structure further includes forming an aluminum pad on the surface of the contact structure.

[0073] In the method for forming a capacitor structure provided by the technical method of the present invention, a groove is formed in the semiconductor substrate, and the groove has a plurality of discrete columnar structures composed of a portion of the semiconductor substrate, and the plurality of columnar structures are distributed in an array, so that the opening rate of the groove is relatively high. Secondly, due to the high opening rate of the groove, it is conducive to forming a deeper groove, so that the sidewall area and the bottom area of ​​the groove are relatively large. The first electrode layer is partially formed along the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the groove, and is also formed along the sidewall surface and the top surface of the columnar structure, so that the effective area of ​​the first electrode layer is increased. A dielectric layer is formed on the surface of the first electrode layer, and the dielectric layer is formed along the surface of the first electrode layer, so that the effective area of ​​the first electrode layer is increased. Correspondingly, the area of ​​the second electrode layer on the side opposite to the dielectric layer is also increased. The second electrode layer, the dielectric layer and the first electrode layer constitute a capacitor structure. As a result, the effective area of ​​the second electrode layer, the dielectric layer and the first electrode layer per unit area of ​​the substrate is increased, thereby improving the electrostatic capacitance and the breakdown voltage resistance of the capacitor structure, and realizing the manufacture of high-density silicon capacitors. In summary, the performance of the capacitor structure is improved.

[0074] Further, the first electrode layer is located on the top surface of the semiconductor substrate, in the part of the semiconductor substrate on the sidewall and bottom of the groove, and in the sidewall region and top region in the columnar structure, or the first electrode layer is located on the top surface of the semiconductor substrate, in the part of the semiconductor substrate on the sidewall and bottom of the groove, and in the entire region of the columnar structure. In other words, the first electrode layer will not occupy the space of the groove, so that the dielectric layer and the second electrode layer have more filling space, which is conducive to increasing the thickness of the dielectric layer. In this way, the breakdown voltage resistance of the capacitor structure is improved. Secondly, since the first electrode layer will not occupy the space of the groove, and the first electrode layer is located in the part of the semiconductor substrate on the sidewall and bottom of the groove, and in the columnar structure, the effective area of ​​the first electrode layer and the dielectric layer in contact is further increased, further improving the electrostatic capacitance and breakdown voltage resistance of the capacitor structure.

[0075] The embodiment of the present application also provides a semiconductor structure, referring to Figure 1 and Figure 8The semiconductor structure includes: a semiconductor substrate 100, wherein the semiconductor substrate 100 has a groove 110, wherein the groove 110 has a plurality of discrete columnar structures 120 formed by part of the semiconductor substrate 100, wherein the plurality of columnar structures 120 are distributed in an array; a first electrode layer 150, located on the top surface of the semiconductor substrate 100, the sidewall surface and the bottom surface of the groove 110, and the sidewall surface and the top surface of the columnar structure 120; a dielectric layer 160, located on the surface of the first electrode layer 150; and a second electrode layer 170, located on the surface of the dielectric layer 160, wherein the second electrode layer 170 fills the groove 110 around the columnar structure 120.

[0076] refer to Figure 8 The material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon on insulator (SOI) or germanium on insulator (GOI). The semiconductor substrate 100 may be one of single crystal silicon, polycrystalline silicon and amorphous silicon. The semiconductor substrate 100 may also be a structure with an epitaxial layer grown thereon.

[0077] In some embodiments of the present application, the semiconductor substrate 100 is a P-type substrate, and in a subsequent process, an N-type diffusion process may be used to dope impurity ions on the surface of the P-type substrate to form the first electrode 150. In other embodiments of the present application, the semiconductor substrate 100 is an N-type substrate, and in a subsequent process, an N-type diffusion process may be used to dope impurity ions on the surface of the N-type substrate to form the first electrode 150.

[0078] refer to Figure 1 and Figure 8 The semiconductor substrate 100 has a groove 110, and the groove 110 has a plurality of discrete columnar structures 120 formed by a portion of the semiconductor substrate 100, and the plurality of columnar structures 120 are distributed in an array. The plurality of columnar structures 120 distributed in an array can form a first electrode layer 150 in a subsequent process, and this structure distributed in an array can increase the surface area of ​​the capacitor, thereby increasing the capacitance.

[0079] In some embodiments of the present application, the plurality of columnar structures 120 are cylinders. Figure 1 (a), when the number of columnar structures 120 is the same, the use of a cylindrical structure can maximize the spacing between adjacent columnar structures 120, accommodate more dielectric layers, and increase capacitance.

[0080] In some embodiments of the present application, the diameter of the plurality of columnar structures 120 is 0.2 micrometers to 0.8 micrometers, for example, 0.2 micrometers, 0.4 micrometers, 0.6 micrometers or 0.8 micrometers, etc. The smaller the diameter of the columnar structure 120, the more columnar structures 120 can be formed in the semiconductor substrate 110, the larger the surface area of ​​the capacitor, and the higher the capacitance, but too small a diameter will, on the one hand, cause the volume of the first electrode in the columnar structure 120 to be too small, affecting the performance of the capacitor; on the other hand, it will cause the ratio of the height to the diameter of the columnar structure 120 to be too large, resulting in an unstable structure and easy damage.

[0081] In some embodiments of the present application, the height of the plurality of columnar structures 120 is 20 microns to 50 microns, such as 20 microns, 30 microns, 40 microns or 50 microns, etc. The higher the height of the columnar structure 120, the larger the surface area of ​​the capacitor and the higher the capacitance, but the requirements for the etching process and the deposition process will be higher.

[0082] In some embodiments of the present application, two adjacent rows of the plurality of columnar structures 120 are arranged in a staggered manner. Figure 1 (a), the two adjacent rows of the columnar structures 120 distributed in an array are staggered, not aligned, and this arrangement can form a larger number of the columnar structures 120 on the semiconductor substrate of the same area. It should be noted that only a few of the columnar structures 120 are drawn in the drawings to illustrate the arrangement of the columnar structures 120, and the number of the columnar structures 120 is not limited.

[0083] refer to Figure 2 , the method for forming the first electrode layer 150 includes: forming a doping source layer 130 on the surface of the semiconductor substrate 100, the surface of the groove 110, and the surface of the plurality of columnar structures 120, wherein the doping source layer 130 has diffused ions, and the diffused ions include phosphorus. For example, the material of the doping source layer 130 is PSG, and the PSG is silicon oxide doped with phosphorus. In a subsequent process, the phosphorus in the doping source layer 130 can be diffused to the surface of the semiconductor substrate 100, the groove 110, and the plurality of columnar structures 120 to form the first electrode layer 150. .

[0084] In some embodiments of the present application, the thickness of the doping source layer 130 is 60 nanometers to 100 nanometers, for example, 60 nanometers, 80 nanometers or 100 nanometers, etc.; the concentration of doped phosphorus in the doping source layer 130 is 15% to 25%, for example, 15%, 20% or 25%, etc.

[0085] refer to Figure 3, the method for forming the first electrode layer 150 further includes: forming a capping layer 140 on the surface of the doping source layer 130. In the subsequent process, it is necessary to diffuse the phosphorus in the doping source layer 130 to the surface of the semiconductor substrate 100, the surface of the groove 110, and the surface of the plurality of columnar structures 120 to form the first electrode 150. According to the diffusion principle, a substance will diffuse in the direction of lower concentration. Therefore, the capping layer 140 is required to allow the phosphorus in the doping source layer 130 to diffuse to the surface of the semiconductor substrate 100, the surface of the groove 110, and the surface of the plurality of columnar structures 120 to form the first electrode 150, rather than gathering on the side of the doping source layer 130 away from the surface of the semiconductor substrate 100, the surface of the groove 110, and the surface of the plurality of columnar structures 120. In some embodiments of the present application, the thickness of the capping layer 140 is 150 nanometers to 250 nanometers, for example, 150 nanometers, 200 nanometers, or 250 nanometers.

[0086] In some embodiments of the present application, the material of the cover layer 140 includes silicon oxide, silicon nitride, silicon carbide, etc.

[0087] refer to Figure 4 The method for forming the first electrode layer 150 further includes: performing a thermal driving process to diffuse the diffusion ions in the doping source layer 130 to the top surface of the semiconductor substrate 100, the sidewalls and the bottom of the trench 110, and the columnar structure 120 to form the first electrode layer 150. The first electrode layer 150 will not occupy the space of the dielectric layer subsequently formed in the trench 110, and can increase the charge storage capacity.

[0088] In some embodiments of the present application, the plurality of columnar structures 120 are fully doped, and the first electrode layer 150 is located on the top surface of the semiconductor substrate 100, in a portion of the semiconductor substrate 100 at the sidewall and bottom of the trench 110, and in the entire region of the columnar structure 120. In other embodiments of the present application, the plurality of columnar structures 120 are only partially doped, and the first electrode layer 150 is located on the top surface of the semiconductor substrate 100, in a portion of the semiconductor substrate 100 at the sidewall and bottom of the trench 110, and in the sidewall region and top region of the columnar structure 120.

[0089] In some embodiments of the present application, the thermal drive process is to use nitrogen to perform thermal drive treatment on the semiconductor substrate. The temperature of the thermal drive treatment is 800 degrees Celsius to 1200 degrees Celsius, such as 900 degrees Celsius, 1000 degrees Celsius or 1100 degrees Celsius, etc.; the time of the thermal drive treatment is 100 minutes to 150 minutes, such as 100 minutes, 120 minutes or 150 minutes, etc. By controlling the process parameters of the thermal drive process, the size, resistivity and uniformity of the first electrode 150 can be adjusted.

[0090] refer to Figure 5 , the method for forming the first electrode layer 150 further includes: removing the doping source layer 130 and the covering layer 140. The doping source layer and the covering layer 140 are used to form the first electrode layer 150. After the first electrode layer 150 is formed, the doping source layer 130 and the covering layer 140 need to be removed.

[0091] In some other embodiments of the present application, the method for forming the first electrode layer 150 includes: performing ion implantation on the top surface of the semiconductor substrate 100, the sidewalls and bottom of the groove 110 in a portion of the semiconductor substrate 100, and the sidewall area and top area in the columnar structure 120; and performing annealing after the ion implantation.

[0092] In some other embodiments of the present application, the process of forming the first electrode layer 150 includes a deposition process; the first electrode layer 150 is located outside the semiconductor substrate 100 and outside the columnar structure 120 .

[0093] Continue to refer Figure 8 A dielectric layer 160 is formed on the surface of the first electrode layer 150 .

[0094] In some embodiments of the present application, the dielectric layer 160 is a single-layer structure, and the material of the dielectric layer 160 includes silicon oxide or silicon nitride.

[0095] In some other embodiments of the present application, the dielectric layer 160 is a multi-layer stack structure; the dielectric layer 160 includes a first dielectric sublayer 161 and a second dielectric sublayer 162 located on the first dielectric sublayer 161; the material of the first dielectric sublayer 161 includes silicon oxide, and the material of the second dielectric sublayer 162 includes silicon nitride.

[0096] The thickness of the first dielectric sublayer 161 is 60 nanometers to 100 nanometers, such as 60 nanometers, 80 nanometers or 100 nanometers, etc. The thickness of the second dielectric sublayer 162 is 100 nanometers to 150 nanometers, such as 100 nanometers, 120 nanometers or 150 nanometers, etc.

[0097] In some other embodiments of the present application, the dielectric layer 160 may further include more dielectric sub-layers, such as a first dielectric sub-layer, a second dielectric sub-layer, a third dielectric sub-layer, and a fourth dielectric sub-layer.

[0098] refer to Figure 7 A second electrode layer 170 is formed on the surface of the dielectric layer 160 , and the second electrode layer 170 fills the groove 110 around the columnar structure 120 .

[0099] In some embodiments of the present application, the thickness of the second electrode layer 170 is 250 nanometers to 350 nanometers, for example, 250 nanometers, 300 nanometers or 350 nanometers.

[0100] In some embodiments of the present application, the second electrode layer 170 is N-type doped polysilicon, and the doping concentration of the N-type doping is 2E20cm -3 .

[0101] In some embodiments of the present application, the resistivity of the second electrode layer 170 is 1.5 mΩ·cm to 2 mΩ·cm, for example, 1.5 mΩ·cm, 1.8 mΩ·cm or 2 mΩ·cm.

[0102] Continue to refer Figure 8 , the semiconductor structure further includes an interlayer dielectric layer 180 located on the semiconductor substrate 100, and a plurality of contact structures 190 penetrating the interlayer dielectric layer 180 and electrically connected to the first electrode layer 150 and the second electrode layer 170, respectively. It should be noted that each contact structure 190 can only electrically connect to the first electrode layer 150 or the second electrode layer 170 alone, and cannot electrically connect to the first electrode layer 150 and the second electrode layer 170 at the same time. Therefore, a portion of the second electrode layer 170 located on the semiconductor substrate 100 is etched away, so that the second electrode layer 170 does not completely cover the first electrode layer 150.

[0103] In some embodiments of the present application, a passivation layer may be formed on the contact surfaces of the contact structure 190 and the first electrode layer 150 and the second electrode layer 170 respectively, and the passivation layer may reduce the resistance of the first electrode layer 150 and the second electrode layer 170 and increase the conductivity.

[0104] In some embodiments of the present application, the material of the passivation layer includes salicide.

[0105] In some embodiments of the present application, the semiconductor structure further includes an aluminum pad formed on a surface of the contact structure.

[0106] In the capacitor structure provided by the technical method of the present invention, a groove is formed in the semiconductor substrate, and the groove has a plurality of discrete columnar structures composed of a portion of the semiconductor substrate, and the plurality of columnar structures are distributed in an array, so that the opening rate of the groove is relatively high. Secondly, due to the high opening rate of the groove, it is conducive to forming a deeper groove, so that the sidewall area and the bottom area of ​​the groove are relatively large. The first electrode layer is partially formed along the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the groove, and is also formed along the sidewall surface and the top surface of the columnar structure, so that the effective area of ​​the first electrode layer is increased. A dielectric layer is formed on the surface of the first electrode layer, and the dielectric layer is formed along the surface of the first electrode layer, so the effective area of ​​the first electrode layer is increased. Correspondingly, the area of ​​the second electrode layer on the side opposite to the dielectric layer is also increased. The second electrode layer, the dielectric layer and the first electrode layer constitute a capacitor structure. As a result, the effective area of ​​the second electrode layer, the dielectric layer and the first electrode layer per unit area of ​​the substrate is increased, thereby improving the electrostatic capacitance and the breakdown voltage resistance of the capacitor structure, and realizing the manufacture of high-density silicon capacitors. In summary, the performance of the capacitor structure is improved.

[0107] Further, the first electrode layer is located on the top surface of the semiconductor substrate, in the part of the semiconductor substrate on the sidewall and bottom of the groove, and in the sidewall region and top region in the columnar structure, or the first electrode layer is located on the top surface of the semiconductor substrate, in the part of the semiconductor substrate on the sidewall and bottom of the groove, and in the entire region of the columnar structure. In other words, the first electrode layer will not occupy the space of the groove, so that the dielectric layer and the second electrode layer have more filling space, which is conducive to increasing the thickness of the dielectric layer. In this way, the breakdown voltage resistance of the capacitor structure is improved. Secondly, since the first electrode layer will not occupy the space of the groove, and the first electrode layer is located in the part of the semiconductor substrate on the sidewall and bottom of the groove, and in the columnar structure, the effective area of ​​the first electrode layer and the dielectric layer in contact is further increased, further improving the electrostatic capacitance and breakdown voltage resistance of the capacitor structure.

[0108] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0109] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may also be present.

[0110] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0111] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0112] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a capacitor structure, characterized in that: include: providing a semiconductor substrate; A groove is formed in the semiconductor substrate, wherein the groove has a plurality of discrete columnar structures formed by a portion of the semiconductor substrate, the plurality of discrete columnar structures are distributed in an array, and in the plurality of discrete columnar structures distributed in an array, columnar structures in two adjacent rows are arranged in a staggered manner; forming a first electrode layer on the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the trench, and the sidewall surface and the top surface of the columnar structure, wherein the first electrode layer is formed by doping a portion of the semiconductor substrate and a portion or all of the columnar structure; forming a dielectric layer on a surface of the first electrode layer; A second electrode layer is formed on the surface of the dielectric layer, and the second electrode layer fills the groove around the columnar structure.

2. The method for forming a capacitor structure according to claim 1, wherein: The shape of the columnar structure includes a cylinder.

3. The method for forming a capacitor structure according to claim 1, wherein: The first electrode layer is located on the top surface of the semiconductor substrate, in a portion of the semiconductor substrate on the sidewall and bottom of the trench, and in the sidewall region and top region of the columnar structure; alternatively, the first electrode layer is located on the top surface of the semiconductor substrate, in a portion of the semiconductor substrate on the sidewall and bottom of the trench, and in the entire region of the columnar structure.

4. The method for forming a capacitor structure according to claim 3, wherein: The first electrode layer is formed by a solid source diffusion process.

5. The method for forming a capacitor structure according to claim 4, wherein: The method of forming the first electrode layer by using a solid source diffusion process includes: forming a doping source layer on the surface of the semiconductor substrate, the surface of the groove, and the surfaces of the plurality of discrete columnar structures, wherein the doping source layer has diffused ions; forming a capping layer on the surface of the doping source layer; After forming the capping layer, performing a thermal driving process to diffuse the diffusion ions in the doping source layer to the top surface of the semiconductor substrate, the sidewalls and bottom of the trench, and the columnar structure to form a first electrode layer; After the thermal driving process is performed, the capping layer and the doping source layer are removed.

6. The method for forming a capacitor structure according to claim 5, wherein: The material of the doping source layer includes phosphorus-doped silicon oxide, and the diffused ions include phosphorus.

7. The method for forming a capacitor structure according to claim 5, wherein: The thickness of the doping source layer is 60 nanometers to 100 nanometers; before the thermal driving process is performed, the concentration of diffused ions in the doping source layer is 15% to 25%.

8. The method for forming a capacitor structure according to claim 5, wherein: The material of the covering layer includes silicon oxide; the thickness of the covering layer is 150 nanometers to 250 nanometers.

9. The method for forming a capacitor structure according to claim 3, wherein: The method for forming the first electrode layer includes: performing ion implantation on the top surface of the semiconductor substrate, the sidewalls and bottom of the trench, and the sidewall region and top region of the columnar structure; and performing annealing after the ion implantation.

10. The method for forming a capacitor structure according to claim 1, wherein: The process of forming the first electrode layer includes a deposition process; the first electrode layer is located outside the semiconductor substrate and outside the columnar structure.

11. The method for forming a capacitor structure according to claim 1, wherein: The method of forming a dielectric layer on the surface of the first electrode layer includes an atomic layer deposition process.

12. The method for forming a capacitor structure according to claim 1, wherein: The dielectric layer is a single-layer structure, and the material of the dielectric layer includes silicon oxide or silicon nitride; or, the dielectric layer is a multi-layer stack structure; the dielectric layer includes a first dielectric sub-layer and a second dielectric sub-layer located on the first dielectric sub-layer; the material of the first dielectric sub-layer includes silicon oxide, and the material of the second dielectric sub-layer includes silicon nitride.

13. A capacitor structure, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has a groove, wherein the groove has a plurality of discrete columnar structures formed by a portion of the semiconductor substrate, wherein the plurality of discrete columnar structures are arranged in an array, and wherein two adjacent rows of columnar structures are arranged in a staggered manner; A first electrode layer, the first electrode layer is located on the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the trench, and the sidewall surface and the top surface of the columnar structure, and the first electrode layer is formed by doping a portion of the semiconductor substrate and a portion or all of the columnar structure; A dielectric layer, located on a surface of the first electrode layer; The second electrode layer is located on the surface of the dielectric layer, and the second electrode layer fills the groove around the columnar structure.

14. The capacitor structure according to claim 13, characterized in that: The plurality of discrete columnar structures are cylinders.

15. The capacitor structure according to claim 14, characterized in that: The diameter of each of the columnar structures is 0.2 micrometers to 0.8 micrometers, and the height of the columnar structures is 20 micrometers to 50 micrometers.

16. The capacitor structure according to claim 13, characterized in that: The first electrode layer is located on the top surface of the semiconductor substrate, in a portion of the semiconductor substrate on the sidewall and bottom of the trench, and in the sidewall region and top region of the columnar structure; alternatively, the first electrode layer is located on the top surface of the semiconductor substrate, in a portion of the semiconductor substrate on the sidewall and bottom of the trench, and in the entire region of the columnar structure.

17. The capacitor structure according to claim 13, characterized in that: The first electrode layer is located outside the semiconductor substrate and outside the columnar structure.

18. The capacitor structure according to claim 13, characterized in that: The dielectric layer is a single-layer structure, and the material of the dielectric layer includes silicon oxide or silicon nitride; or, the dielectric layer is a multi-layer stack structure; the dielectric layer includes a first dielectric sub-layer and a second dielectric sub-layer located on the first dielectric sub-layer; the material of the first dielectric sub-layer includes silicon oxide, and the material of the second dielectric sub-layer includes silicon nitride.

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