Current detection circuit, current detection method and converter

Abstract

The present application provides a current detection circuit, comprising a current transformer, a magnetic reset circuit, a chip select circuit, a sampling circuit and a clamp circuit. The primary winding of the current transformer receives the current to be detected and generates a sampling current in the secondary winding. The magnetic reset circuit is used to reset the current transformer. The chip select circuit is electrically connected to the magnetic reset circuit and can be switched between a first mode and a second mode. The first mode is used to detect a current to be detected having a first direction, and the second mode is used to detect a current to be detected having a second direction opposite to the first direction. The sampling circuit is electrically connected to the chip select circuit to sample the sampling current and output a sampling signal to a controller. The clamp circuit is electrically connected between the sampling circuit and the controller and provides a reference potential. The present application also provides a converter having the current detection circuit.

Description

Technical Field

[0001] The present application relates to power electronics technology, and in particular to a current detection circuit based on a current transformer, a current detection method, and a converter having the current detection circuit. Background Art

[0002] Pulse width modulation (PWM) isolated DC / DC converters widely use current transformer (CT)-based detection circuits combined with peak current mode control to avoid magnetic bias or even saturation of the transformer. Generally speaking, current transformer-based detection circuits can achieve the following functions:

[0003] 1. Current reporting: The CT-based detection circuit converts the current signal into a voltage signal and outputs it to the digital signal processor (DSP, MCU, etc.). The digital signal processor obtains the current value of the primary side of the CT through calculation and reports the current value to the host computer.

[0004] 2. Peak current protection: The CT-based current detection circuit can sense the current value in real time and is suitable for peak current protection.

[0005] 3. Peak current mode control: The peak current mode compares the current signal of the inductor or transformer with the output of the error amplifier to generate a PWM signal. Under this control method, loop compensation is easy and the influence of input disturbance can be well suppressed, so it is widely used.

[0006] 4. Magnetic bias control: Detect the primary (or secondary) current of the transformer in adjacent switching cycles, and then correct the duty cycle (or phase shift angle) of the drive signal to achieve transformer current balance. Since the transformer current includes load current and excitation current, and the load current can be considered to be constant in adjacent cycles, bidirectional excitation current balance can be achieved.

[0007] However, in specific applications, such as in a vehicle charger, when a DC / DC converter needs to have a bidirectional energy transmission function, a detection circuit based on a current transformer is required to have a bidirectional current detection capability. Summary of the invention

[0008] The purpose of the present application is to provide a current transformer-based detection circuit with bidirectional current detection capability.

[0009] According to one aspect of the present application, a current detection circuit is provided, comprising a current transformer, a magnetic reset circuit, a chip select circuit, a sampling circuit and a clamp circuit. The primary winding of the current transformer receives the current to be detected, and generates a sampling current in the secondary winding of the current transformer. The two ends of the magnetic reset circuit are respectively electrically connected to the secondary winding of the current transformer to reset the current transformer. The chip select circuit is electrically connected to the magnetic reset circuit, and the chip select circuit is operable to switch between a first mode and a second mode, wherein the first mode is used to detect the current to be detected having a first direction, and the second mode is used to detect the current to be detected having a second direction opposite to the first direction. The sampling circuit is electrically connected to the chip select circuit to sample the sampling current and output a sampling signal to a controller. The clamp circuit is electrically connected between the sampling circuit and the controller, and the clamp circuit is used to provide a reference potential.

[0010] Optionally, in the above-mentioned current detection circuit, the magnetic reset circuit includes a magnetic reset resistor and a voltage stabilizing branch, and the magnetic reset resistor and the voltage stabilizing branch are connected in parallel between two ends of the secondary winding.

[0011] Optionally, in the above current detection circuit, the voltage stabilizing branch includes a first voltage stabilizing diode and a second voltage stabilizing diode, and the first voltage stabilizing diode and the second voltage stabilizing diode are connected in reverse series.

[0012] Optionally, in the above current detection circuit, the chip select circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes a first branch electrically connected between the first input terminal and the first output terminal, and a second branch electrically connected between the second input terminal and the second output terminal. When the chip select circuit is in the first mode, the current flows through the first branch, the sampling circuit, and the second branch in sequence, and when the chip select circuit is in the second mode, the current flows through the second branch, the sampling circuit, and the first branch in sequence.

[0013] Optionally, in the above current detection circuit, the first branch includes a first switch and a first diode connected in parallel, the second branch includes a second switch and a second diode connected in parallel, the anodes of the first diode and the second diode are electrically connected to the first output terminal and the second output terminal respectively, and the cathodes of the first diode and the second diode are electrically connected to the first input terminal and the second input terminal respectively. When the chip select circuit is in the first mode, the first switch and the second diode are turned on, the second switch is turned off and the first diode is turned off, and when the chip select circuit is in the second mode, the second switch and the first diode are turned on, the first switch is turned off and the second diode is turned off.

[0014] Optionally, in the above-mentioned current detection circuit, the first switch and the second switch are N-channel MOSFETs, and the first diode and the second diode are parasitic diodes of the first switch and the second switch respectively; or, the first diode and the second diode are both Schottky diodes.

[0015] Optionally, in the above-mentioned current detection circuit, the sampling circuit has a first sampling terminal electrically connected to the first output terminal of the chip select circuit and a second sampling terminal electrically connected to the second output terminal of the chip select circuit, and includes a sampling resistor and a sampling capacitor connected in parallel between the first sampling terminal and the second sampling terminal.

[0016] Optionally, in the above current detection circuit, the clamping circuit includes a first filter capacitor, a second filter capacitor, a third switch and a fourth switch, the first filter capacitor and the fourth switch are connected in parallel and electrically connected between the first sampling terminal and a clamping node clamped to the reference potential, and the second filter capacitor and the third switch are connected in parallel and electrically connected between the clamping node and the second sampling terminal. When the chip select circuit is in the first mode, the third switch is turned on and the fourth switch is turned off, and when the chip select circuit is in the second mode, the fourth switch is turned on and the third switch is turned off.

[0017] Optionally, in the above current detection circuit, the sampling capacitor is composed of a first sampling capacitor and a second sampling capacitor connected in series, and

[0018] The clamping circuit is used to clamp a midpoint formed by the first sampling capacitor and the second sampling capacitor being connected in series to the reference potential.

[0019] According to another aspect of the present application, a converter is also provided, comprising a DC capacitor and a switching circuit, wherein the converter further comprises a current detection circuit according to any embodiment of the present application, and the primary winding of the current transformer of the current detection circuit receives the current between the DC capacitor and the switching circuit.

[0020] According to another aspect of the present application, a converter is also provided, comprising a transformer, a primary circuit located on the primary side of the transformer, and a secondary circuit located on the secondary side of the transformer, wherein the converter further comprises a current detection circuit according to any embodiment of the present application, and the primary winding of the current transformer of the current detection circuit receives the current on the primary winding of the transformer.

[0021] According to another aspect of the present application, a current detection method is also provided, comprising the following steps: receiving a current to be detected from a primary winding of a current transformer, and generating a sampling current in a secondary winding of the current transformer; allowing the sampling current to flow through a chip selection circuit; and sampling the sampling current using a sampling circuit electrically connected to the chip selection circuit, and outputting a sampling signal to a controller. When the current to be detected flows in a first direction, the chip selection circuit is set to a first mode, and when the current to be detected flows in a second direction opposite to the first direction, the chip selection circuit is set to a second mode, and the sampling circuit is clamped to a reference potential through a clamping circuit.

[0022] Optionally, the method further comprises: utilizing a magnetic reset circuit to reset the current transformer.

[0023] Optionally, in the above method, the magnetic reset circuit includes a magnetic reset resistor and a voltage stabilizing branch, the magnetic reset resistor and the voltage stabilizing branch are connected in parallel between the two ends of the secondary winding of the current transformer, and the voltage stabilizing branch includes a first voltage stabilizing diode and a second voltage stabilizing diode, and the first voltage stabilizing diode and the second voltage stabilizing diode are connected in reverse series.

[0024] Optionally, in the above method, the chip select circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes a first branch electrically connected between the first input terminal and the first output terminal and a second branch electrically connected between the second input terminal and the second output terminal, and the first input terminal and the second input terminal are electrically connected to the two ends of the secondary winding of the current transformer, respectively. When the chip select circuit is in the first mode, the current flows through the first branch, the sampling circuit, and the second branch in sequence, and when the chip select circuit is in the second mode, the current flows through the second branch, the sampling circuit, and the first branch in sequence.

[0025] Optionally, in the above method, the first branch includes a first switch and a first diode connected in parallel, the second branch includes a second switch and a second diode connected in parallel, the anodes of the first diode and the second diode are electrically connected to the first output terminal and the second output terminal respectively, and the cathodes of the first diode and the second diode are electrically connected to the first input terminal and the second input terminal respectively. When the chip select circuit is in the first mode, the first switch and the second diode are turned on, the second switch is turned off and the first diode is turned off, and when the chip select circuit is in the second mode, the second switch and the first diode are turned on, the first switch is turned off and the second diode is turned off.

[0026] Optionally, in the above method, the first switch and the second switch are N-channel MOSFETs, and the first diode and the second diode are parasitic diodes of the first switch and the second switch respectively, or the first diode and the second diode are both Schottky diodes.

[0027] Optionally, in the above method, the sampling circuit has a first sampling terminal electrically connected to the first output terminal of the chip select circuit and a second sampling terminal electrically connected to the second output terminal of the chip select circuit, and includes a sampling resistor and a sampling capacitor connected in parallel between the first sampling terminal and the second sampling terminal.

[0028] Optionally, in the above method, the clamping circuit comprises a first filter capacitor, a second filter capacitor, a third switch and a fourth switch, the first filter capacitor and the fourth switch are connected in parallel and electrically connected between the first sampling terminal and a clamping node clamped to the reference potential, and the second filter capacitor and the third switch are connected in parallel and electrically connected between the clamping node and the second sampling terminal. When the chip select circuit is in the first mode, the third switch is turned on and the fourth switch is turned off, and when the chip select circuit is in the second mode, the fourth switch is turned on and the third switch is turned off.

[0029] Optionally, in the above method, the sampling capacitor is composed of a first sampling capacitor and a second sampling capacitor connected in series, and the clamping circuit is used to clamp a midpoint formed by the first sampling capacitor and the second sampling capacitor connected in series to the reference potential.

[0030] According to the current transformer-based current detection circuit provided by the present application, currents in different directions can be detected by setting the mode of the chip selection circuit to one of the first mode or the second mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A circuit diagram of a converter requiring current sensing is shown.

[0032] Figure 2 A current detection circuit in the prior art is shown.

[0033] Figure 3 and Figure 4 Shows the use of Figure 2 The current sensing circuit is Figure 1 The waveform diagram of the relevant signals when the converter performs current detection.

[0034] Figure 5 Another current detection circuit in the prior art is shown.

[0035] Figure 6Shows the use of Figure 5 The current sensing circuit is Figure 1 The waveform diagram of the relevant signals when the converter performs current detection.

[0036] Figure 7 A structural block diagram of a current detection circuit according to an embodiment of the present application is shown.

[0037] Figure 8 A circuit diagram of a current detection circuit according to an embodiment of the present application is shown.

[0038] Fig. 9 Shows Figure 8 The current detection circuit shown is a current flow path diagram in the first mode.

[0039] Fig.10 Shows Figure 8 The current flow path diagram of the current detection circuit in the second mode is shown.

[0040] Fig.11 Shows the use of Fig. 9 The current detection circuit in the first mode is shown Figure 1 The waveform diagram of the relevant signals when the converter performs current detection at position A.

[0041] Fig.12 Shows the use of Fig.10 The current detection circuit in the second mode is shown Figure 1 The waveform diagram of the relevant signals when the converter performs current detection at position A.

[0042] Fig.13 shows that when the load current is large, Figure 8 The current sensing circuit shown is for Figure 1 The waveform diagram of the relevant signals when the converter performs current detection at position B.

[0043] Fig.14 shows that the load current is small when using Figure 8 The current sensing circuit shown is for Figure 1 The waveform diagram of the relevant signals when the converter performs current detection at position B.

[0044] Fig.15 A circuit diagram of a current detection circuit according to another embodiment of the present application is shown.

[0045] Fig.16 Shows Fig.15 The current detection circuit shown is a current flow path diagram in the first mode.

[0046] Fig.17 Shows Fig.15The current flow path diagram of the current detection circuit in the second mode is shown.

[0047] Fig.18 Shows the use of Fig.16 The current detection circuit in the first mode is shown Figure 1 The waveform diagram of the relevant signals when the converter performs current detection at position A.

[0048] Fig.19 Shows the use of Fig.17 The current detection circuit in the second mode is shown Figure 1 The waveform diagram of the relevant signals when the converter performs current detection at position A.

[0049] Fig. 20 shows that when the load current is large, Fig.15 The current sensing circuit shown is for Figure 1 The waveform diagram of the relevant signals when the converter performs current detection at position B.

[0050] Fig.21 shows that the load current is small when using Fig.15 The current sensing circuit shown is for Figure 1 The waveform diagram of the relevant signals when the converter performs current detection at position B.

[0051] Fig. 22 A current detection method according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0052] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0053] When introducing the elements / components / etc. described and / or illustrated herein, the terms "a", "an", "the", "said", and "at least one" are used to indicate the presence of one or more elements / components / etc. The terms "comprises", "includes", and "have" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc. Relative terms may be used in the embodiments, such as "upper" or "lower" to describe the relative relationship of one component of the icon to another component. It is understood that if the device of the icon is turned over so that it is upside down, the component described on the "upper" side will become the component on the "lower" side. In addition, the terms "first", "second", etc. in the claims are used only as labels and are not numerical limitations on their objects.

[0054] Figure 1 A circuit diagram of a converter 100 is shown for one embodiment where current sensing is required. Figure 1 The converter 100 shown is a widely used DC / DC converter. The converter 100 includes a transformer T1, a primary circuit connected to the primary side of the transformer T1, and a secondary circuit connected to the secondary side of the transformer T1. The primary circuit of the converter 100 receives an input voltage Vin from an input terminal, and converts the input voltage Vin into an output voltage Vout through the primary circuit, the transformer T1, and the secondary circuit, and then outputs it through an output terminal. In addition, the converter 100 also includes an input capacitor C1 (DC capacitor) and an output capacitor C2. The input capacitor C1 is connected in parallel to the input terminal of the converter 100, and the output capacitor C2 is connected in parallel to the output terminal of the converter 100.

[0055] It is understandable that the converter 100 may also be other types of converters, such as a DC / AC converter or an AC / DC converter, and the current detection circuit may also be used to detect the current at other locations of the converter, which is not limited in the present application. Figure 1 Taking the DC / DC converter as an example, energy can be transferred from the primary side of the transformer to the secondary side, or from the secondary side of the transformer to the primary side. Therefore, the input and output ends in this application do not limit the direction of energy flow.

[0056] Transformer T1 has a primary winding Np and two secondary windings Ns1 and Ns2 connected in series. Figure 1The inductor Lm is the excitation inductance equivalent to the primary side of the transformer T1. The primary circuit of the converter 100 is connected between the input terminal and the primary winding Np of the transformer T1, and the primary circuit includes a full-bridge circuit composed of four switch tubes Qp1~Qp4, wherein the four switch tubes Qp1~Qp4 can be but not limited to MOSFET. The secondary winding of the transformer T1 is a center tap structure, and the secondary circuit is connected between the secondary winding and the output terminal, and includes a rectifier circuit composed of two switch tubes (such as synchronous rectifier tubes) SR1 and SR2, wherein the switch tubes SR1 and SR2 can be but not limited to MOSFET.

[0057] A current detection circuit may be connected at position A of the converter 100 to detect the current iHV on the line between the input capacitor C1 and the full-bridge circuit. Alternatively, a current detection circuit may be connected at position B of the converter 100 to detect the current iT1_pri on the primary side of the transformer T1.

[0058] Figure 2 and Figure 5 Two current detection circuits in the prior art are shown respectively.

[0059] like Figure 2 As shown, the current detection circuit 200 has a current transformer CT. In the current detection circuit 200, the rear stage of the current transformer CT is sequentially connected with a magnetic reset resistor Rd, voltage stabilizing diodes Dz1 and Dz2, a rectifier diode Drec, a sampling resistor Rs and a filter capacitor Cs. The sampling voltage signal CS+ on the sampling resistor Rs is provided to the digital signal processor DSP.

[0060] Combined with the following Figure 3 and Figure 4 The operation of the current detection circuit 200 is briefly described.

[0061] When the current detection circuit 200 is connected to Figure 1 When the converter 100 is at position A shown in the figure, the primary side of the current transformer CT receives the current to be detected Ipri (i.e., iHV) from the position A of the converter 100. At this time, a current Ipri_R is induced at the secondary side of the current transformer CT. Assuming that the excitation current flowing through the excitation inductance Lmc of the secondary side of the current transformer CT is Imag, the total current Isense flowing out of the secondary side of the current transformer CT satisfies the following formula (1):

[0062] Isense=Ipri_R–Imag (1)

[0063] When the primary current Ipri of the current transformer CT is 0, the secondary current Ipri_R is also 0. The excitation current Imag of the current transformer CT will continue to flow in the original direction and flow through the magnetic reset resistor Rd, so the energy of the excitation inductance Lmc will be consumed on Rd. When the excitation current Imag of the current transformer CT decreases to 0, the current transformer CT completes the magnetic reset through the magnetic reset resistor Rd.

[0064] However, when the primary current Ipri of the current transformer CT is Figure 2 When the current direction is opposite (i.e., from top to bottom), the Ipri_R induced by the secondary side of the current transformer CT is also Figure 2 The direction is opposite to that shown. Due to the reverse blocking effect of the rectifier diode Drec, the secondary current Ipri_R can only flow through the magnetic reset resistor Rd. The secondary current Ipri_R will generate a negative voltage on the magnetic reset resistor Rd and cause the excitation current Imag to increase from 0 in the same direction as Figure 2 The direction is opposite to that shown, and it also flows through the magnetic reset resistor Rd. At this time, no sampling voltage is generated on the sampling resistor Rs. If the energy accumulation of the excitation inductance of the current transformer CT exceeds a certain value, the current transformer CT will be saturated.

[0065] Figure 2 The current detection circuit 200 shown can only detect unidirectional current, and the current signal must be in the form of a pulse, such as a pulse square wave, a pulse trapezoidal wave, etc. The pulse current must drop to 0 before the current transformer CT is saturated. Then the current transformer CT starts magnetic reset. Only after the magnetic reset is successful can the next pulse signal be detected.

[0066] Figure 3 and Figure 4 The detection circuit 200 is connected to Figure 1 When current detection is performed at position A of the converter 100, the load current iLV of the converter 100 is respectively large and small, the waveforms of the drive signal of the converter 100, the secondary current iL1 of the transformer, the excitation current Im, the primary current iT1_pri and the sampling voltage signal CS+ output by the detection circuit 200 are shown.

[0067] like Figure 3 As shown, when the load current iLV is large, since the current to be detected received by the current transformer CT of the current detection circuit 200 is the input current of the full-bridge switch circuit of the converter 100, the current signal is in the form of a unidirectional pulse, and the voltage sampling signal CS+ output by the detection circuit 200 is also in the form of a unidirectional pulse. Figure 4As shown, when the load current iLV is small, the current to be detected received by the current transformer CT may be a bidirectional signal. Since the current detection circuit 200 can only detect unidirectional current, the sampling voltage signal CS+ output by it can only reflect a part of the current to be detected, that is, it presents a unidirectional pulse triangle wave form.

[0068] therefore, Figure 2 The current sensing circuit 200 shown is only suitable for use when Figure 1 The converter 100 shown is a one-way energy transmission condition in which energy is transferred from the input end to the output end. However, when the converter 100 needs to perform bidirectional energy transmission, this condition is no longer applicable.

[0069] In order to realize bidirectional detection of current, another current detection circuit 300 is applied, such as Figure 5 As shown, the rear stage of the current transformer CT is connected in sequence with a diode rectifier bridge, a sampling resistor Rs and a filter capacitor Cs. The sampled voltage signal CS+ on the sampling resistor is provided to the digital signal processor DSP.

[0070] Figure 5 The current detection circuit 300 shown can be connected to Figure 1 The converter 100 is shown at position B to detect the current iT1_pri on the primary side of the transformer T1.

[0071] When the load current iLV of the converter 100 is large, the sampling voltage signal CS+ output by the current detection circuit 300 is Figure 3 However, when the load current iLV of the converter 100 is small, the sampling voltage signal CS+ output by the current detection circuit 300 is as follows. Figure 6 shown. Figure 6 In the example, the signal CS+ presents two wave heads, and the amplitude first decreases and then increases. Therefore, the converter 100 cannot directly use the detection result of the current detection circuit 300 to achieve peak current control.

[0072] Figure 7 A structural block diagram of a current detection circuit 400 according to an embodiment of the present application is shown.

[0073] like Figure 7 As shown, the current detection circuit 400 includes a current transformer CT, a magnetic reset circuit 410 , a chip selection circuit 420 , a sampling circuit 430 , and a clamping circuit 440 .

[0074] The current transformer CT has a primary winding N1 and a secondary winding N2, and Figure 7The middle inductor Lmc is shown as the excitation inductance of the current transformer CT, wherein when the current detection circuit 400 is connected to the DC / DC converter to perform current detection, the current to be detected from the converter flows into the primary winding N1, and at the same time a secondary current is induced on the secondary winding N2, and at the same time an excitation current is generated in the excitation inductor Lmc, and the sampling current is obtained according to the secondary current and the excitation current.

[0075] The magnetic reset circuit 410 has a first input terminal IN1, a second input terminal IN2, a first output terminal O1 and a second output terminal O2. The first input terminal IN1 and the second input terminal IN2 of the magnetic reset circuit 410 are electrically connected to the two ends of the secondary winding N2 of the current transformer CT respectively. Figure 2 The current detection circuit 200 described, in some embodiments that can be combined with the embodiments of the present application, the magnetic reset circuit 410 may have a magnetic reset resistor Rd and a voltage stabilizing branch. One end of the magnetic reset resistor Rd is electrically connected to the first input terminal IN1 and the first output terminal O1 of the magnetic reset circuit 410, and the other end of the magnetic reset resistor Rd is electrically connected to the second input terminal IN2 and the second output terminal O2 of the magnetic reset circuit 410. In one embodiment, the voltage stabilizing branch can be formed by the reverse series connection of the voltage stabilizing diodes Dz1 and Dz2, and the voltage stabilizing branch is connected in parallel with the magnetic reset resistor Rd. Therefore, the magnetic reset circuit 410 can be used to magnetically reset the current transformer CT, and its operation method is the same as Figure 2 The magnetic resetting method of the current detection circuit 200 is the same as that of the current detection circuit 200, so it will not be repeated here.

[0076] The chip select circuit 420 has a first input terminal IN3, a second input terminal IN4, a first output terminal O3, and a second output terminal O4. The first input terminal IN3 and the second input terminal IN4 of the chip select circuit 420 are respectively connected to the first output terminal O1 and the second output terminal O2 of the magnetic reset circuit 410. The chip select circuit 420 is operable to switch between a first mode and a second mode, which can be used to detect a bidirectional current.

[0077] The sampling circuit 430 has a first input terminal IN5 (i.e., a first sampling terminal), a second input terminal IN6 (i.e., a second sampling terminal), a first output terminal O5, and a second output terminal O6. The first input terminal IN5 and the second input terminal IN6 of the sampling circuit 430 are electrically connected to the first output terminal O3 and the second output terminal O4 of the chip select circuit 420, respectively. In some embodiments that can be combined with the embodiments of the present application, the sampling circuit 430 has a sampling resistor Rs and a sampling capacitor Cs in parallel. One end of the sampling resistor Rs is electrically connected to the first input terminal IN5 and the first output terminal O5 of the sampling circuit 430, and the other end of the sampling resistor Rs is electrically connected to the second input terminal IN6 and the second output terminal O6 of the sampling circuit 430. One end of the sampling capacitor Cs is electrically connected to the first input terminal IN5 and the first output terminal O5 of the sampling circuit 430, and the other end of the sampling capacitor Cs is electrically connected to the second input terminal IN6 and the second output terminal O6 of the sampling circuit 430. The resistance of the sampling resistor Rs can be 10% or less, 5% or less, 2% or less, or even 1% or less of the resistance of the magnetic reset resistor Rd. The capacitance of the sampling capacitor Cs is very small and plays a filtering function. Therefore, when the sampling current of the secondary side of the current transformer CT flows through the sampling resistor Rs, a positive sampling voltage CS+ and a negative sampling voltage CS- can be obtained at both ends of the sampling resistor Rs. The positive sampling voltage CS+ is provided to the first A / D input port P1 of the controller (for example, a digital signal processor DSP), and the negative sampling voltage CS- is provided to the second A / D input port P2 of the digital signal processor DSP. Optionally, a comparator may be included in the digital signal processor DSP to monitor the level of the positive sampling voltage CS+ and / or the negative sampling voltage CS- to play a role in overcurrent protection. Among them, the controller can also be other forms of control chips, such as a single-chip microcomputer, FPGA, etc., which are not limited by this application.

[0078] The clamp circuit 440 has a first input terminal IN7, a second input terminal IN8, a first output terminal O7 and a second output terminal O8. The first input terminal IN7 and the second input terminal IN8 of the clamp circuit 440 are respectively connected to the first output terminal O5 and the second output terminal O6 of the sampling circuit 430. The clamp circuit 440 is used to provide a reference potential so that the voltage difference (i.e., the common mode voltage) between the positive sampling voltage CS+ and the negative sampling voltage CS- relative to the controller ground GND is a determined, non-floating value. The output sampling voltage of the current detection circuit 400 is within the input voltage range of the digital signal processor DSP.

[0079] In some embodiments of the present application, the chip select circuit 420 includes a first branch electrically connected between the first input terminal IN3 and the first output terminal O3 and a second branch electrically connected between the second input terminal IN4 and the second output terminal O4. When the chip select circuit 420 is in the first mode, the current detection circuit 400 can be used to detect a current to be detected having a first direction. For example, the current in the first direction is Figure 7 The chip selection circuit 420 only allows the sampling current generated at the secondary side of the current transformer CT to flow from the first input terminal IN3 through the first branch to the first output terminal O3, and then the sampling current flows to the sampling circuit 430, and only allows the sampling current flowing out of the sampling circuit to flow from the second output terminal O4 through the second branch to the second input terminal IN4. When the chip selection circuit 420 is in the second mode, the current detection circuit 400 can be used to detect a current to be detected having a second direction opposite to the first direction. For example, the current in the second direction is Figure 7 The chip selection circuit 420 only allows the sampling current generated at the secondary side of the current transformer CT to flow from the second input terminal IN4 through the second branch to the second output terminal O4, and then the sampling current flows to the sampling circuit 430, and only allows the sampling current flowing out of the sampling circuit to flow from the first output terminal O3 through the first branch to the first input terminal IN3.

[0080] Specifically, if Figure 7 As shown, the first branch of the chip selection circuit 420 includes a first switch S1 and a first diode D1 connected in parallel, and the second branch includes a second switch S2 and a second diode D2 connected in parallel. In one embodiment, the anodes of the first diode D1 and the second diode D2 are connected to the first output terminal O3 and the second output terminal O4, respectively, and the cathodes of the first diode D1 and the second diode D2 are connected to the first input terminal IN3 and the second input terminal IN4, respectively. When the chip selection circuit 420 is in the first mode, the first switch S1 and the second diode D2 are turned on, the second switch S2 is turned off, and the first diode D1 is turned off. When the chip selection circuit 420 is in the second mode, the second switch S2 and the first diode D1 are turned on, the first switch S1 is turned off, and the second diode D2 is turned off. It can be understood that the connection method of the first diode D1 and the second diode D2 is not limited to the above-described situation, and the anodes of the two diodes can also be connected to the first input terminal IN3 and the second input terminal IN4, respectively, and the cathodes are connected to the first output terminal O3 and the second output terminal O4, respectively.

[0081] In some embodiments of the present application, the first switch S1 and the second switch S2 in the chip selection circuit 420 are N-channel MOSFETs, and the first diode D1 and the second diode D2 can be parasitic diodes (body diodes) of the first switch S1 and the second switch S2, respectively. Alternatively, the first diode D1 and the second diode D2 can also be external diodes, for example, both are Schottky diodes.

[0082] Figure 8 1 shows a current detection circuit 500 according to an embodiment of the present application. The current detection circuit 500 includes a current transformer CT, a magnetic reset circuit 510, a chip select circuit 520, a sampling circuit 530, and a clamp circuit 540. The current transformer CT, the magnetic reset circuit 510, the chip select circuit 520, and the sampling circuit 530 of the current detection circuit 500 are all Figure 7 The description is given in , so I will not repeat it here.

[0083] Figure 8 In the embodiment shown, the specific structure of the clamping circuit 540 is further shown, such as Figure 8 As shown, the clamp circuit 540 includes a first filter capacitor C1, a second filter capacitor C2, a third switch S3 and a fourth switch S4. The first filter capacitor C1 and the fourth switch S4 are connected in parallel and electrically connected between a clamp node (e.g., a grounding point) clamped to a reference potential and a first output terminal of the sampling circuit 530. The second filter capacitor C2 and the third switch S3 are connected in parallel and electrically connected between a clamp node (e.g., a grounding point) and a second output terminal of the sampling circuit 530. When the chip select circuit 520 is in the first mode, the third switch S3 in the clamp circuit 540 is turned on and the fourth switch S4 is turned off. When the chip select circuit 520 is in the second mode, the fourth switch S4 in the clamp circuit 540 is turned on and the third switch S3 is turned off.

[0084] Fig. 9 and Fig.10 It shows respectively when Figure 8 FIG. 5 is a current flow path diagram of the current detection circuit 500 when the current detection circuit 500 is in the first mode and in the second mode. Fig. 9 and Fig.10 In the figures, the electrical components that are disconnected by the current detection circuit 500 when in different modes are shown in grey.

[0085] like Fig. 9As shown, when the current detection circuit 500 is in the first mode, the first switch S1 of the chip selection circuit 520 is turned on, the first diode D1 is reversely cut off, the second switch S2 is turned off, the second diode D2 is turned on, and the third switch S3 in the clamping circuit 540 is turned on, so that the second filter capacitor C2 is short-circuited, and the fourth switch S4 is turned off, so that the sampling current flows through the first filter capacitor C1. The turning on and off of each switch in the current detection circuit 500 can be controlled by a digital signal processor DSP or by a separate control chip.

[0086] like Fig.10 As shown, when the current detection circuit 500 is in the second mode, the first switch S1 of the chip selection circuit 520 is disconnected, the first diode D1 is turned on, the second switch S2 is turned on, the second diode D2 is reversely cut off, and the fourth switch S4 in the clamping circuit 540 is turned on, so that the first filter capacitor C1 is short-circuited, and the third switch is disconnected, so that the sampling current flows through the second filter capacitor C2.

[0087] As described above, when the current detection circuit 500 is in the first mode, the current detection circuit 500 can be used to detect a current to be detected having a first direction, that is, the current in the first direction is Fig. 9 The current Ipri flows from bottom to top through the primary winding N1 of the current transformer CT. At this time, the vector sum of the current Ipri_R induced by the secondary winding N2 of the current transformer CT and the excitation current Imag is the sampling current Isense, as shown in Fig. 9 As shown, the sampling current Isense flows out from one end of the secondary side of the current transformer CT, passes through the first switch S1, the first filter capacitor C1, the third switch S3, the second diode D2, and then returns to the other end of the secondary side of the current transformer CT. When the primary current Ipri is 0, the excitation current Imag of the current transformer CT is magnetically reset by the magnetic reset resistor Rd in the magnetic reset circuit 510. The voltage stabilizing branch is used to prevent the voltage across the magnetic reset resistor Rd from overvoltage. Since S3 is turned on, one end of the secondary winding N2 of the current transformer CT is clamped to the clamping node, which is, for example, grounded or connected to a fixed potential, and the positive sampling voltage CS+ output by the current detection circuit 500 is transmitted to the first A / D input port of the digital signal processor DSP. Similarly, when the current detection circuit 500 is in the second mode, the current detection circuit 500 is used to detect the current to be detected having a direction opposite to the first direction, that is, in Fig.10The current Ipri flows from top to bottom through the primary winding N1 of the current transformer CT. The sampling current Isense flows out from the other end of the secondary side of the current transformer CT through the second switch S2, the second filter capacitor C2, the fourth switch S4, the first diode D1, and then returns to one end of the secondary side of the current transformer CT. Since S4 is turned on, one end of the secondary winding N2 of the current transformer CT is clamped to the clamping node, which is, for example, grounded or connected to a fixed potential. The negative sampling voltage CS- output by the current detection circuit 500 is transmitted to the second A / D input port of the digital signal processor DSP.

[0088] Fig.11 The current detection circuit 500 in the first mode is connected to Figure 1 When current detection is performed at position A of the converter 100, waveforms of the drive signal of the converter 100, the secondary current iL1 of the transformer T1, the excitation current Im, the primary current iT1_pri and the sampling voltage output by the detection circuit 500 are shown.

[0089] like Fig.11 As shown, at this time, the converter 100 is working in the forward direction, and energy is transferred from the primary side of the transformer to the secondary side of the transformer. The switches S1 and S3 of the current detection circuit 500 are always in the on state, and the switches S2 and S4 are always in the off state. At this time, the CS+ signal represents the current waveform on the primary side of the current transformer CT. Since the switch S3 is turned on, CS- is clamped to a fixed level.

[0090] Fig.12 The current detection circuit 500 in the second mode is connected to Figure 1 When current detection is performed at position A of the converter 100, waveforms of the drive signal of the converter 100, the secondary current iL1 of the transformer T1, the excitation current Im, the primary current iT1_pri and the sampling voltage output by the detection circuit 500 are shown.

[0091] like Fig.12 As shown, at this time, the converter 100 works in reverse, and energy is transferred from the secondary side of the transformer T1 to the primary side of the transformer T1. When the switches SR1 and SR2 of the full-bridge circuit are turned on at the same time, the current iL1 of the power inductor L1 (i.e., the secondary current of the transformer T1) increases. At this time, the switches S2 and S4 in the current detection circuit 500 are always in the on state, and the switches S1 and S3 are always in the off state. At this time, the CS- signal represents the current waveform on the primary side of the current transformer CT. Since the switch S4 is turned on, CS+ is clamped to a fixed level.

[0092] Fig.13 The current detection circuit 500 is connected to the load current when the load current is large. Figure 1When current detection is performed at position B of the converter 100, waveforms of the drive signal of the converter 100, the secondary current iL1 of the transformer, the excitation current Im, the primary current iT1_pri, the switch drive signal in the current detection circuit 500, and the output sampling voltage.

[0093] like Fig.13 As shown, at this time, the load current iLV is relatively large, and the driving waveform of the switches S1 to S4 of the current detection circuit 500 is a square wave signal, and the width of the square wave is greater than or equal to the width of the driving signal of the switches Qp1 to Qp4 of the full-bridge circuit of the converter 100. That is, if the driving signals of the switches Qp1 and Qp4 of the converter 100 are at a high level, then the switches S2 and S4 in the current detection circuit 500 are also at a high level. When the primary current iT1_pri of the transformer T1 of the converter 100 flows from the switch Qp1 through the transformer T1 and then to the switch Qp4, since the chip selection circuit 520 and the clamping circuit 540 of the current detection circuit 500 have been enabled, the sampling voltage CS- output by the current detection circuit 500 can well follow the change of the primary current iT1_pri of the transformer T1. Similarly, when the drive signals of the switches Qp2 and Qp3 in the converter 100 are at a high level, the switches S1 and S3 in the current detection circuit 500 are also at a high level. At this time, the sampling voltage CS+ output by the current detection circuit 500 can well follow the change of the primary current iT1_pri of the transformer T1. It can be seen that the sampling voltages CS+ and CS- output by the current detection circuit 500 are both pulse signals reflecting the amplitude of the primary current of the transformer T1.

[0094] Fig.14 The current detection circuit 500 is connected to the load current when the load current is small. Figure 1 When current detection is performed at position B of the converter 100, waveforms of the drive signal of the converter 100, the secondary current iL1 of the transformer, the excitation current Im, the primary current iT1_pri, the switch drive signal in the current detection circuit 500, and the output sampling voltage.

[0095] like Fig.14 As shown, at this time, the load current iLV is small, and the corresponding relationship between the drive signals of the switches S1-S4 of the current detection circuit 500 and the switches Qp1-Qp4 of the full-bridge circuit of the converter 100 is Fig.13At this time, since the current detection circuit 500 can only detect a current in a specific direction when in any mode, the sampling voltages CS+ and CS- output by the current detection circuit 500 are both pulse triangle wave signals, and the phase difference is 180°. Taking the sampling voltage CS- as an example, when the primary side current iT1_pri of the transformer T1 of the converter 100 increases from negative to crossing 0A, the sampling voltage CS- output by the current detection circuit 500 will output a voltage value greater than 0V.

[0096] Fig.15 FIG. 6 shows a current detection circuit 600 according to another embodiment of the present application. The current detection circuit 600 includes a current transformer CT, a magnetic reset circuit 610, a chip select circuit 620, a sampling circuit 630, and a clamp circuit 640. The current transformer CT, the magnetic reset circuit 610, the chip select circuit 620 and the clamp circuit 640 of the current detection circuit 600 are Figure 8 The current transformer CT, magnetic reset circuit 410, and chip select circuit 420 of the current detection circuit 400 shown are the same, so they are not repeated here. The difference between the current detection circuit 600 and the current detection circuit 500 is that the current detection circuit 600 shows another form of sampling circuit 630 and clamping circuit 640. In the current detection circuit 600, the sampling circuit 630 is composed of a sampling resistor Rs, a first sampling capacitor Cs1, and a second sampling capacitor Cs2. One end of the sampling resistor Rs is connected to the first input terminal and the first output terminal of the sampling circuit 630, and the other end of the sampling resistor Rs is connected to the second input terminal and the second output terminal of the sampling circuit 630. The first sampling capacitor Cs1 and the second sampling capacitor Cs2 are connected in series and then connected in parallel with the sampling resistor Rs. The clamping circuit 640 includes a reference voltage source for clamping the midpoint formed by the first sampling capacitor Cs1 and the second sampling capacitor Cs2 in series to a reference voltage Vref.

[0097] Fig.16 A current flow path diagram of the current detection circuit 600 in the first mode is shown. Fig.16 Electrical elements disconnected from the current sensing circuit 600 when in the first mode are shown in grey.

[0098] like Fig.16 As shown, when the current detection circuit 600 is in the first mode, the first switch S1 of the chip selection circuit 620 is turned on, the first diode D1 is turned off, the second switch S2 is turned off, and the sampling current flows through the second diode D2. The on and off states of the switches of the current detection circuit 600 can be controlled by the digital signal processor DSP.

[0099] As described above, when the current detection circuit 600 is in the first mode, the current detection circuit 600 can be used to detect a current to be detected having a first direction, that is, the current in the first direction is Fig. 9 The current Ipri flows from bottom to top through the primary winding N1 of the current transformer CT. At this time, the direction of the sampling current Isense is obtained according to the current Ipri_R induced by the secondary winding N2 of the current transformer CT and the excitation current Imag. Fig.16 As shown by the middle arrow, the current flows out from one end of the secondary side of the current transformer CT through the first switch S1, the sampling resistor Rs, the first sampling capacitor Cs1, the sampling capacitor Cs2, the second diode D2, and then returns to the other end of the secondary side of the current transformer CT. When the primary current Ipri is 0, the excitation current Imag of the current transformer CT is magnetically reset by the magnetic reset resistor Rd in the magnetic reset circuit 610.

[0100] Fig.17 A current flow path diagram of the current detection circuit 600 in the second mode is shown. Fig.17 The electrical components disconnected from the current sensing circuit 600 when in the second mode are shown in grey.

[0101] like Fig.17 As shown, when the current detection circuit 600 is in the second mode, the second switch S2 of the chip selection circuit 620 is turned on, the second diode D2 is turned off, the first switch S1 is turned off, and the sampling current flows through the first diode D1. The on and off states of each switch of the current detection circuit 600 can be controlled by a digital signal processor DSP.

[0102] As described above, when the current detection circuit 600 is in the second mode, the current detection circuit 600 can be used to detect a detection current having a second direction, that is, the current in the second direction is Fig.17 The current Ipri flows from top to bottom through the primary winding N1 of the current transformer CT. At this time, the direction of the sampling current Isense is obtained according to the current Ipri_R induced by the secondary winding N2 of the current transformer CT and the excitation current Imag. Fig.17 As shown by the middle arrow, the current flows out from one end of the secondary side of the current transformer CT through the second switch S2, the sampling resistor Rs, the second sampling capacitor Cs2, the first sampling capacitor Cs1, the first diode D1, and then returns to the other end of the secondary side of the current transformer CT. When the primary current Ipri is 0, the excitation current Imag of the current transformer CT is magnetically reset by the magnetic reset resistor Rd in the magnetic reset circuit 610.

[0103] Fig.18 The current detection circuit 600 in the first mode is connected to Figure 1 When the converter 100 performs current detection at position A, the waveform of the relevant signal of the converter 100 and the sampled voltage output by the current detection circuit 600.

[0104] like Fig.18 As shown, at this time, the converter 100 is working in the forward direction, and energy is transferred from the primary side of the transformer T1 to the secondary side of the transformer T1. The switch S1 of the current detection circuit 600 is always in the on state, and the switch S2 is always in the off state. At this time, the CS+ signal and the CS- signal can both represent the current waveform on the primary side of the current transformer CT. Fig.18 In the example, when the transformer current iT1_pri is 0, the sampling voltages CS+ and CS- are both Vref. When the transformer current iT1_pri is not 0, the sampling voltage CS+ satisfies the following equation (2), and the sampling voltage CS- satisfies the following equation (3):

[0105] V CS+ =Vref+0.5×Isense×Rs (2)

[0106] V CS- =Vref-0.5×Isense×Rs (3)

[0107] Fig.19 The current detection circuit 600 in the second mode is connected to Figure 1 When the converter 100 performs current detection at position A, the waveform of the relevant signal of the converter 100 and the sampled voltage output by the current detection circuit 600.

[0108] like Fig.19 As shown, at this time, the converter 100 works in reverse, and energy is transferred from the secondary side of the transformer T1 to the primary side of the transformer T1. The second switch S2 of the current detection circuit 600 is controlled to be in the on state, and the first switch S1 is controlled to be in the off state. At this time, the sampling voltages CS+ and CS- output by the current detection circuit 600 can both represent the current waveform on the primary side of the current transformer CT. Fig.19 In the example, when the transformer current iT1_pri is 0, the sampling voltages CS+ and CS- are both Vref. When the transformer current iT1_pri is not 0, the sampling voltage CS+ satisfies the following equation (4), and the sampling voltage CS- satisfies the following equation (5):

[0109] V CS+ =Vref-0.5×Isense×Rs (4)

[0110] V CS- =Vref+0.5×Isense×Rs (5)

[0111] Fig. 20 The current detection circuit 600 is connected to the load current when the load current is large. Figure 1When the DC / DC converter 100 performs current detection at position B, waveforms of related signals of the converter 100 and a sampled voltage output by the current detection circuit 600 are shown.

[0112] like Fig. 20 As shown, at this time, the converter 100 works in the forward direction, and energy is transferred from the primary side of the transformer to the secondary side of the transformer. The driving waveform of the switches S1-S2 of the current detection circuit 600 is a square wave signal, and the square wave width is greater than or equal to the driving signal of the switches Qp1-Qp4 of the full-bridge circuit of the converter 100. That is, if the driving signals of the switches Qp1 and Qp4 of the converter 100 are high level, then the switch S2 of the current detection circuit 600 is also high level at this time. When the primary side current iT1_pri of the transformer T1 of the converter 100 flows from the switch Qp1 through the transformer T1 and then to the switch Qp4, since the chip selection circuit 620 of the current detection circuit 600 has been enabled, the sampling voltages CS+ and CS- output by the current detection circuit 600 can well follow the changes of the primary side current iT1_pri of the transformer T1. At this time, the sampling voltage CS+ satisfies the following formula (6), and the sampling voltage CS- satisfies the following formula (7). If the drive signals of the switches Qp3 and Qp2 of the converter 100 are at a high level, then the switch S1 of the current detection circuit 600 is also at a high level. When the primary side current iT1_pri of the transformer T1 of the converter 100 flows from the switch Qp3 through the transformer T1 and then to the switch Qp2, the sampling voltage CS+ satisfies the following equation (8), and the sampling voltage CS- satisfies the following equation (9):

[0113] V CS+ =Vref-0.5×Isense×Rs (6)

[0114] V CS - = Vref + 0.5 × Isense × Rs (7)

[0115] V CS+ =Vref+0.5×Isense×Rs (8)

[0116] V CS- =Vref-0.5×Isense×Rs (9)

[0117] Fig.21 The current detection circuit 600 is connected to the load current when the load current is small. Figure 1 When the converter 100 performs current detection at position B, the waveform of the relevant signal of the converter 100 and the sampled voltage output by the current detection circuit 600.

[0118] like Fig.21As shown, at this time, the converter 100 is working in the forward direction, and energy is transferred from the primary side of the transformer to the secondary side of the transformer. The drive signals of the switches S1-S2 of the current detection circuit 600 and the drive signals of the switches Qp1-Qp4 of the full-bridge circuit of the converter 100 are Fig. 20 The same as shown. During the period when the drive signals of the switches Qp1, Qp4 of the converter 100 and the switch S2 of the current detection circuit 600 are at a high level, after the primary current iT1_pri of the transformer T1 of the converter 100 passes through 0A from the negative minimum value, the sampling voltage CS+ output by the current detection circuit 600 satisfies the formula (10) and the sampling voltage CS- satisfies the formula (11). During the period when the drive signals of the switches Qp2, Qp3 of the DC / DC converter 100 and the switch S1 of the current detection circuit 600 are at a high level, after the primary current iT1_pri of the transformer T1 of the converter 100 passes through 0A from the positive maximum value, the sampling voltage CS+ output by the current detection circuit 600 satisfies the formula (12), and the sampling voltage CS- satisfies the formula (13):

[0119] V CS+ =Vref-0.5×Isense×Rs (10)

[0120] V CS- =Vref+0.5×Isense×Rs (11)

[0121] V CS+ =Vref+0.5×Isense×Rs (12)

[0122] V CS- =Vref-0.5×Isense×Rs (13)

[0123] Fig. 22 A current detection method according to an embodiment of the present application is shown. For example, the method can use a current detection circuit according to any embodiment of the present application to detect a current. Figure 1 Current detection is performed at position A or B of the converter 100.

[0124] like Fig. 22As shown, in step S102, the current to be detected is received from the primary winding of the current transformer, and a sampling current is generated in the secondary winding of the current transformer. The current to be detected received from the primary winding of the current transformer can flow through the primary winding of the current transformer in two flow directions, and the sampling current flowing out of the secondary winding of the current transformer is the vector sum of the secondary current induced by the secondary winding of the current transformer and the excitation current of the current transformer. In step S104, the sampling current flows through the chip selection circuit. The chip selection circuit is operable to switch between a first mode and a second mode. When the current to be detected flows through the primary winding of the current transformer in a first direction, the chip selection circuit can be switched to the first mode, and when the current to be detected flows through the primary winding of the current transformer in a second direction opposite to the first direction, the chip selection circuit can be switched to the second mode. In step S106, the sampling current is sampled by a sampling circuit electrically connected to the chip selection circuit, and a sampling signal is output to a controller, for example, the sampling signal is output to two A / D input ports of a digital signal processor. The sampling circuit includes, for example, a sampling resistor, and when sampling currents in different directions flow through the sampling resistor, two sampling voltages can be obtained at both ends of the sampling resistor.

[0125] Optionally, the method can utilize a clamping circuit to clamp the sampling circuit to a reference potential, so that the two sampling voltages generated at the sampling resistor are respectively determined and non-floating values ​​relative to the voltage difference between the secondary grounds (i.e., the common-mode voltage), and the sampling voltages are within the voltage range of the A / D input port of the digital signal processor.

[0126] Optionally, the current detection method may further include step S108, using a magnetic reset circuit to magnetically reset the current transformer. The magnetic reset circuit may include a magnetic reset resistor, and when the primary current of the current transformer drops to 0, the magnetic reset resistor may be used to consume the energy in the magnetizing inductance of the current transformer to achieve the function of magnetically resetting the current transformer.

[0127] In summary, the present application provides a current detection circuit, which utilizes a controllable chip select circuit to achieve bidirectional current detection capabilities. Compared with the bidirectional current detection circuit in the prior art, when the converter has a bidirectional energy transmission requirement, the detection result obtained using the current detection circuit provided by the present application can still be used for peak current control.

[0128] It should be noted that the above description is only a preferred embodiment proposed for illustrating the present application, and the present application is not limited to the above embodiment, and the protection scope of the present application is determined by the attached claims. Moreover, those skilled in the art may make further modifications to the embodiments of the present application, but these modifications all fall within the protection scope of the attached claims.

Claims

1. A current detection circuit, comprising: A current transformer, wherein the primary winding of the current transformer receives the current to be detected and the secondary winding of the current transformer generates a sampling current; A magnetic reset circuit, wherein two ends of the magnetic reset circuit are respectively electrically connected to the secondary winding of the current transformer to reset the current transformer; a chip selection circuit electrically connected to the magnetic reset circuit, the chip selection circuit being operable to switch between a first mode and a second mode, wherein the first mode is used to detect the current to be detected having a first direction, and the second mode is used to detect the current to be detected having a second direction opposite to the first direction; A sampling circuit having a first sampling terminal and a second sampling terminal electrically connected to the chip selection circuit to sample the sampling current and output a sampling signal to a controller; as well as a clamping circuit, electrically connected between the sampling circuit and the controller, the clamping circuit being used to provide a reference potential, the clamping circuit comprising a first filter capacitor, a second filter capacitor, a third switch and a fourth switch, the first filter capacitor and the fourth switch being electrically connected in parallel between the first sampling terminal and a clamping node clamped to the reference potential, the second filter capacitor and the third switch being electrically connected in parallel between the clamping node and the second sampling terminal, When the chip select circuit is in the first mode, the third switch is turned on, the fourth switch is turned off, and When the chip selection circuit is in the second mode, the fourth switch is turned on and the third switch is turned off.

2. The current detection circuit according to claim 1, wherein: The magnetic reset circuit comprises a magnetic reset resistor and a voltage stabilizing branch. The magnetic reset resistor and the voltage stabilizing branch are connected in parallel between two ends of the secondary winding. 3 . The current detection circuit according to claim 2 , wherein the voltage-stabilizing branch comprises a first voltage-stabilizing diode and a second voltage-stabilizing diode, and the first voltage-stabilizing diode and the second voltage-stabilizing diode are connected in reverse series.

4. The current detection circuit according to claim 1 or 2, wherein The chip select circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes a first branch electrically connected between the first input terminal and the first output terminal and a second branch electrically connected between the second input terminal and the second output terminal. When the chip selection circuit is in the first mode, current flows through the first branch, the sampling circuit and the second branch in sequence, and When the chip selection circuit is in the second mode, current flows through the second branch, the sampling circuit and the first branch in sequence.

5. The current detection circuit according to claim 4, wherein The first branch includes a first switch and a first diode connected in parallel, the second branch includes a second switch and a second diode connected in parallel, anodes of the first diode and the second diode are electrically connected to the first output terminal and the second output terminal respectively, and cathodes of the first diode and the second diode are electrically connected to the first input terminal and the second input terminal respectively, When the chip selection circuit is in the first mode, the first switch and the second diode are turned on, the second switch is turned off and the first diode is turned off, and When the chip selection circuit is in the second mode, the second switch and the first diode are turned on, the first switch is turned off and the second diode is turned off.

6. The current detection circuit according to claim 5, wherein The first switch and the second switch are N-channel MOSFETs, and The first diode and the second diode are parasitic diodes of the first switch and the second switch respectively; or, The first diode and the second diode are both Schottky diodes.

7. The current detection circuit according to claim 4, wherein: The first sampling end of the sampling circuit is electrically connected to the first output end of the chip select circuit, the second sampling end of the sampling circuit is electrically connected to the second output end of the chip select circuit, and the sampling circuit further includes a sampling resistor and a sampling capacitor connected in parallel between the first sampling end and the second sampling end.

8. A converter comprising a DC capacitor and a switching circuit, wherein The converter further comprises a current detection circuit as claimed in any one of claims 1 to 7, wherein a primary winding of a current transformer of the current detection circuit receives a current between the DC capacitor and the switching circuit.

9. A converter comprising a transformer, a primary circuit located on the primary side of the transformer, and a secondary circuit located on the secondary side of the transformer, wherein The converter further comprises a current detection circuit as claimed in any one of claims 1 to 7, wherein a primary winding of a current transformer of the current detection circuit receives the current on the primary winding of the transformer.

10. A current detection method comprising the following steps: Receiving a current to be detected from a primary winding of a current transformer, and generating a sampling current in a secondary winding of the current transformer; allowing the sampling current to flow through a chip selection circuit; and The sampling current is sampled by a sampling circuit electrically connected to the chip selection circuit, and a sampling signal is output to a controller, wherein the sampling circuit has a first sampling terminal and a second sampling terminal electrically connected to the chip selection circuit, wherein When the current to be detected flows in a first direction, the chip select circuit is set to a first mode; when the current to be detected flows in a second direction opposite to the first direction, the chip select circuit is set to a second mode, and The sampling circuit is clamped to a reference potential through a clamping circuit, wherein the clamping circuit comprises a first filter capacitor, a second filter capacitor, a third switch and a fourth switch, wherein the first filter capacitor and the fourth switch are connected in parallel and electrically connected between the first sampling terminal and a clamping node clamped to the reference potential, and the second filter capacitor and the third switch are connected in parallel and electrically connected between the clamping node and the second sampling terminal. When the chip select circuit is in the first mode, the third switch is turned on, the fourth switch is turned off, and When the chip selection circuit is in the second mode, the fourth switch is turned on and the third switch is turned off.

11. The current detection method according to claim 10, further comprising: A magnetic reset circuit is used to reset the current transformer.

12. The current detection method according to claim 11, wherein The magnetic reset circuit comprises a magnetic reset resistor and a voltage stabilizing branch, wherein the magnetic reset resistor and the voltage stabilizing branch are connected in parallel between two ends of the secondary winding of the current transformer, and The voltage stabilizing branch includes a first voltage stabilizing tube and a second voltage stabilizing tube, and the first voltage stabilizing tube and the second voltage stabilizing tube are connected in reverse series.

13. The current detection method according to claim 10, wherein The chip selection circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes a first branch electrically connected between the first input terminal and the first output terminal and a second branch electrically connected between the second input terminal and the second output terminal, the first input terminal and the second input terminal are electrically connected to two ends of the secondary winding of the current transformer, respectively. When the chip selection circuit is in the first mode, current flows through the first branch, the sampling circuit and the second branch in sequence, and When the chip selection circuit is in the second mode, current flows through the second branch, the sampling circuit and the first branch in sequence.

14. The current detection method according to claim 13, wherein The first branch includes a first switch and a first diode connected in parallel, the second branch includes a second switch and a second diode connected in parallel, anodes of the first diode and the second diode are electrically connected to the first output terminal and the second output terminal respectively, and cathodes of the first diode and the second diode are electrically connected to the first input terminal and the second input terminal respectively, When the chip selection circuit is in the first mode, the first switch and the second diode are turned on, the second switch is turned off and the first diode is turned off, and When the chip selection circuit is in the second mode, the second switch and the first diode are turned on, the first switch is turned off and the second diode is turned off.

15. The current detection method according to claim 14, wherein The first switch and the second switch are N-channel MOSFETs, and The first diode and the second diode are parasitic diodes of the first switch and the second switch respectively; or The first diode and the second diode are both Schottky diodes.

16. The current detection method according to claim 13, wherein The first sampling end of the sampling circuit is electrically connected to the first output end of the chip select circuit, the second sampling end of the sampling circuit is electrically connected to the second output end of the chip select circuit, and the sampling circuit further includes a sampling resistor and a sampling capacitor connected in parallel between the first sampling end and the second sampling end.

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