Current Sensor

Abstract

This electric current sensor comprises: first and second input terminals configured so that both ends of a sense resistor can be connected thereto; a square wave generation circuit that is connected to the first and second input terminals and configured so as to be capable of generating a square wave signal having an amplitude proportional to the voltage between the two ends of the sense resistor; and an electric current detection signal output circuit configured so as to be capable of using the square wave signal as a basis to output an electric current detection signal corresponding to the electric current flowing through the sense resistor.

Description

[Technical Field]

[0001] The present disclosure relates to a current sensor. [Background technology]

[0002] There is a current sensor that detects the current flowing through a sense resistor (shunt resistor) and outputs a current detection signal that indicates the detection result. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-173353 Summary of the Invention [Problem to be solved by the invention]

[0004] By providing two input terminals to which both ends of a sense resistor are connected and inputting the voltages at the two input terminals directly into a differential amplifier, a current detection signal can be generated. However, when the sense resistor is provided on the high-potential side of the load, a relatively high voltage is applied to the two input terminals, requiring the components of the differential amplifier to have a high breakdown voltage. The need for a high breakdown voltage leads to larger components and higher costs.

[0005] An object of the present disclosure is to provide a current sensor that contributes to reducing the withstand voltage required for the element. [Means for solving the problem]

[0006] The current sensor according to the present disclosure comprises first and second input terminals configured to be connectable to both ends of a sense resistor, a square wave generating circuit connected to the first and second input terminals and configured to generate a square wave signal having an amplitude proportional to the voltage across the sense resistor, and a current detection signal output circuit configured to output a current detection signal corresponding to the current flowing through the sense resistor based on the square wave signal. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a current sensor that contributes to reducing the withstand voltage required for the element. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic configuration diagram of a current sensor according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a partial configuration diagram of the current sensor of FIG. [Figure 3] FIG. 3 is a timing chart showing the relationship between the two clock signals and the states of the four switches in the configuration of FIG. [Figure 4] FIG. 4 is a diagram showing the states of the switches in the configuration of FIG. [Figure 5] FIG. 5 is a circuit diagram of a portion of the current sensor according to the embodiment of the present disclosure that is involved in generating a square wave signal. [Figure 6] FIG. 6 is a timing chart for explaining the operation of the circuit of FIG. [Figure 7] FIG. 7 is a timing chart for explaining the operation of the circuit of FIG. [Figure 8] FIG. 8 is a timing chart for explaining the operation of the circuit of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and duplicate descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, this specification may use symbols or characters referring to information, signals, physical quantities, elements, or parts, and may omit or abbreviate the names of the information, signals, physical quantities, elements, or parts corresponding to the symbols or characters. For example, the current detection signal output circuit referred to by "13" (see FIG. 1) described below may be referred to as current detection signal output circuit 13 or abbreviated as circuit 13, but these terms all refer to the same thing.

[0010] First, some terms used in describing the embodiments of the present disclosure will be explained. A line refers to a wiring through which an electrical signal is propagated or applied. A ground refers to a reference conductive part having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductive part is formed of a conductor such as metal. A potential of 0V is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0011] A level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a high level of the signal or voltage strictly means that the signal or voltage is at a high level, and a low level of the signal or voltage strictly means that the signal or voltage is at a low level. A level of a signal may be expressed as a signal level, and a level of a voltage may be expressed as a voltage level. For any given signal or voltage, when the signal is at a high level, the inverted signal of the signal is at a low level, and when the signal is at a low level, the inverted signal of the signal is at a high level. For any given signal or voltage, a transition from a low level to a high level is called an up edge (or rising edge), and a transition from a high level to a low level is called a down edge (or falling edge).

[0012] For any transistor configured as a FET (field-effect transistor), including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Additionally, unless otherwise specified, the backgate of any MOSFET can be considered shorted to the source.

[0013] Any switch can be configured with one or more FETs (field effect transistors), and when a switch is in the on state, conduction occurs between both ends of the switch, while when a switch is in the off state, conduction does not occur between both ends of the switch. Hereinafter, the on and off states of any transistor or switch may be simply referred to as on and off. For any transistor or switch, switching from the off state to the on state is referred to as turning on, and switching from the on state to the off state is referred to as turning off.

[0014] Furthermore, for any transistor or switch, the section in which the transistor or switch is in the on state may be referred to as the on section, and the section in which the transistor or switch is in the off state may be referred to as the off section. For any signal that takes a high or low signal level, the section in which the signal level is high will be referred to as the high level section, and the section in which the signal level is low will be referred to as the low level section. The same applies to any voltage that takes a high or low voltage level.

[0015] Unless otherwise specified, the connection between a plurality of parts that form a circuit, such as any circuit element, wiring (line), node, etc., may be understood to refer to an electrical connection.

[0016] 1 shows a schematic configuration diagram of a current sensor 10 according to an embodiment of the present disclosure. The current sensor 10 includes terminals TM1 to TM5, as well as a square wave generating circuit 11, a switch control circuit 12, a current detection signal output circuit 13, an internal power supply circuit 14, terminals 21 and 22, and capacitors 23 and 24. The terminals TM1 to TM5 correspond to external terminals, and the terminals 21 and 22 correspond to internal terminals.

[0017] Current sensor 10 is a semiconductor device (electronic component) that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed from the housing to the outside of current sensor 10. The semiconductor chip is sealed in a housing (package) made of resin to form the semiconductor device. The circuits and circuit elements that make up current sensor 10, including circuits 11 to 14 and capacitors 23 and 24, are included in the semiconductor integrated circuit. While FIG. 1 shows only terminals TM1 to TM5 as external terminals provided on current sensor 10, other external terminals may also be provided on current sensor 10.

[0018] A sense resistor R SNS A sense resistor R SNS One end of the resistor is connected to terminal TM1, and the other end of the resistor R SNS The other end of is connected to terminal TM2. SNS The connection node with the positive voltage V CM is connected to the terminal to which the voltage V is applied, and therefore the voltage V CM is added. Voltage V CM Hereinafter, this may be referred to as the common-mode voltage.

[0019] Terminal TM1 and sense resistor R SNS The connection node between the two is connected to one end of the load LD, and the other end of the load LD is connected to ground. CM From the terminal to which the sense resistor R SNS Current I flows through the load LD LD Then, the sense resistor R SNSA current I flows between both ends of LD A voltage drop occurs based on the sense resistor R SNS The voltage drop at the sense voltage V SNS Terminal TM1 is connected to the common-mode voltage V CM than the sense voltage V SNS The voltage (V CM -V SNS ) is added. In the following, the voltage at terminal TM1 is represented by the symbol "V INM " and the voltage at terminal TM2 is referred to as "V INP " may be referred to.

[0020] The current detection signal S (described later) is output from terminal TM3. OUT is output. A power supply voltage VDD is supplied to terminal TM4. The power supply voltage VDD has a positive DC voltage value within a predetermined voltage range. Terminal TM5 is connected to ground.

[0021] The square wave generating circuit 11 is connected to the terminals TM1 and TM2. The square wave generating circuit 11 includes a plurality of switches and generates a voltage V INP and V INM Based on the sense resistor R SNS The voltage across the terminals (i.e., the sense voltage V SNS ) is generated. The square wave generating circuit 11 uses the above-mentioned multiple switches to output a square wave signal through terminals 21 and 22 (details will be described later). The terminals 21 and 22 correspond to the output terminals of the square wave generating circuit 11. The voltages applied to the terminals 21 and 22 are respectively represented by the symbol "V OUTM ", "V OUTP " for reference.

[0022] The switch control circuit 12 controls the state (on / off state) of each switch in the square wave generating circuit 11.

[0023] The current detection signal output circuit 13 detects the current flowing through the sense resistor R SNS The current I LD Current detection signal S according to OUT and generates the current detection signal SOUT is output from the terminal TM3 to an external circuit (not shown) of the current sensor 10. The external circuit outputs the current detection signal S OUT Based on the current I LD For example, the value of the current detection signal S OUT is the current I LD Alternatively, for example, the current detection signal S OUT is the current I LD A capacitor 23 is inserted between the terminal 21 and the circuit 13, and a capacitor 24 is inserted between the terminal 22 and the circuit 13. Therefore, the voltage V OUTM and V OUTP The AC components are input to the circuit 13.

[0024] The internal power supply circuit 14 generates one or more internal power supply voltages based on the power supply voltage VDD supplied to the terminal TM4. Each circuit in the current sensor 10 can be driven by the internal power supply voltage generated by the internal power supply circuit 14. In FIG. 1, an internal power supply voltage Vreg is shown as an example of the internal power supply voltage generated by the internal power supply circuit 14. The internal power supply voltage Vreg has a predetermined positive DC voltage value.

[0025] 2 shows the internal configuration of the square wave generating circuit 11. The square wave generating circuit 11 includes switches SW1 to SW4. The first and second terminals of the switch SW1 are connected to terminals TM1 and 21, respectively. The first and second terminals of the switch SW2 are connected to terminals TM2 and 22, respectively. The first and second terminals of the switch SW3 are connected to terminals TM1 and 22, respectively. The first and second terminals of the switch SW4 are connected to terminals TM2 and 21, respectively.

[0026] The switch control circuit 12 includes a clock output circuit 30. The clock output circuit 30 generates and outputs clock signals CLK1 and CLK2. The clock signals CLK1 and CLK2 are square wave signals having a predetermined frequency and a predetermined amplitude. The clock signals CLK1 and CLK2 have the same frequency and amplitude. However, the phases of the clock signals CLK1 and CLK2 are 180° different from each other. That is, the clock signal CLK2 corresponds to the inverted signal of the clock signal CLK1 (in other words, the clock signal CLK1 corresponds to the inverted signal of the clock signal CLK2). The clock signals CLK1 and CLK2 are supplied to a square wave generating circuit 11. The states (on / off states) of the switches SW1 to SW4 are individually controlled based on the clock signals CLK1 and CLK2.

[0027] FIG. 3 shows a timing chart illustrating the relationship between the clock signals CLK1 and CLK2 and the states of the switches SW1 to SW4. The clock signals CLK1 and CLK2 alternate between high and low signal levels. However, when the clock signal CLK1 is at high level, the clock signal CLK2 is at low level, and when the clock signal CLK1 is at low level, the clock signal CLK2 is at high level. The duty cycles of the clock signals CLK1 and CLK2 are arbitrary. With regard to the signal levels of the clock signals CLK1 and CLK2, a low level is an example of a first level, and a high level is an example of a second level.

[0028] In each of the clock signals CLK1 and CLK2, the high level has a potential of voltage Vreg, and the low level has a potential of 0 V. The voltage Vreg is, for example, 4 V. The sense voltage V SNS is the current I LD In Figure 3, the sense voltage V SNS In other drawings and the following description, unless otherwise required, the sense voltage V SNS Assume that is constant.

[0029] The low level section of the clock signal CLK1 is referred to as the first section. The low level section of the clock signal CLK1 coincides with the high level section of the clock signal CLK2. The high level section of the clock signal CLK1 is referred to as the second section. The high level section of the clock signal CLK1 coincides with the low level section of the clock signal CLK2. After the supply of the power supply voltage VDD to the current sensor 10 begins and a predetermined startup process is performed, the first section and the second section alternate.

[0030] 4 shows states ST1 and ST2, which are two states that the square wave generating circuit 11 can be in. In the first interval, the state of the square wave generating circuit 11 is state ST1, and in the second interval, the state of the square wave generating circuit 11 is state ST2. In state ST1 (thus in the first interval), the switches SW1 and SW2 are on, and the switches SW3 and SW4 are off. In state ST2 (thus in the second interval), the switches SW1 and SW2 are off, and the switches SW3 and SW4 are on. That is, the switch control circuit 12 outputs clock signals CLK1 and CLK2 to alternately switch the state of the square wave generating circuit 11 (in other words, the states of the switches SW1 to SW4) between states ST1 and ST2.

[0031] In the first state, the voltage at the terminal TM1 is applied to the terminal 21 and the voltage at the terminal TM2 is applied to the terminal 22. Therefore, in the first state, "V OUTP =V INP =V CM " and "V OUTM =V INM =V CM -V SNS In the second state, the voltage at the terminal TM1 is applied to the terminal 22 and the voltage at the terminal TM2 is applied to the terminal 21. Therefore, in the second state, "V OUTP =V INM =V CM -V SNS " and "V OUTM =V INP =V CM "

[0032] Voltage VOUTP and V OUTM are, respectively, "V SNS It becomes a rectangular wave pulsating voltage with an amplitude of 1 / 2”. However, the voltage V OUTP and V OUTM are out of phase with each other by 180°. Therefore, a difference voltage (V OUTP -V OUTM ) is generated. OUTP -V OUTM ) is a square wave signal, SNS The current detection signal output circuit 13 outputs the differential voltage (V OUTP -V OUTM ) based on the square wave signal corresponding to the sense voltage V SNS By extracting the information of the current I LD Current detection signal S according to OUT It is possible to generate a voltage V OUTP and V OUTM Therefore, the current detection signal output circuit 13 outputs a square wave signal OUTP and the square wave signal corresponding to the voltage V OUTM The current detection signal S is generated based on a square wave signal corresponding to OUT It can be thought of as generating

[0033] 5 shows a detailed circuit example of a portion of the current sensor 10. The switches SW1 to SW4 in FIG. 2 are respectively configured by the transistors TR1 to TR4 in FIG. 5. The switch control circuit 12 in FIG. 2 includes gate signal generation circuits 110 to 140 in addition to the clock output circuit 30. The clock signal CLK1 output from the clock output circuit 30 is applied to a clock line LN1, and the clock signal CLK2 output from the clock output circuit 30 is applied to a clock line LN2. It can be understood that the clock lines LN1 and LN2 are also included as components of the switch control circuit 12.

[0034] The gate signal generation circuits 110 to 140 generate gate signals for the transistors TR1 to TR4, respectively. The gate signal generation circuits 110 to 140 have a common configuration. Specifically, the gate signal generation circuit 110 includes a transistor TRa, capacitors 111 and 112, and a resistor 113. The gate signal generation circuit 120 includes a transistor TRb, capacitors 121 and 122, and a resistor 123. The gate signal generation circuit 130 includes a transistor TRc, capacitors 131 and 132, and a resistor 133. The gate signal generation circuit 140 includes a transistor TRd, capacitors 141 and 142, and a resistor 143.

[0035] The transistors TR1 to TR4 can be considered to function as main transistors, and in this case, the transistors TRa to TRd can be considered to function as sub-transistors. The transistors TR1 to TR4 and TRa to TRd are P-channel MOSFETs. The absolute value of the gate threshold voltage Vth of each of the transistors TR1 to TR4 and TRa to TRd (e.g., 0.6 V) is assumed to be smaller than the internal power supply voltage Vreg (e.g., 4 V). Therefore, for example, when the gate potential of transistor TR1 is lower than the source potential of transistor TR1 by the voltage Vreg, transistor TR1 is in the on state. The same is true for transistors TR2 to TR4 and TRa to TRd.

[0036] The connection relationships of the circuit elements shown in FIG. 5 will be described.

[0037] The source of transistor TR1 is connected to terminal TM1, and the drain of transistor TR1 is connected to terminal 21. The source of transistor TRa is connected to terminal TM1, and the drain of transistor TRa is connected to node ND1. Node ND1 is connected to the gate of transistor TR1 and to a first terminal of capacitor 111. A second terminal of capacitor 111 is connected to clock line LN1. The gate of transistor TRa is connected to node NDa. A first terminal of capacitor 112 is connected to node NDa, and a second terminal of capacitor 112 is connected to clock line LN2. Node NDa is also connected to terminal TM1 via resistor 113.

[0038] The source of transistor TR2 is connected to terminal TM2, and the drain of transistor TR2 is connected to terminal 22. The source of transistor TRb is connected to terminal TM2, and the drain of transistor TRb is connected to node ND2. Node ND2 is connected to the gate of transistor TR2 and to a first end of capacitor 121. A second end of capacitor 121 is connected to clock line LN1. The gate of transistor TRb is connected to node NDb. A first end of capacitor 122 is connected to node NDb, and a second end of capacitor 122 is connected to clock line LN2. Node NDb is also connected to terminal TM2 via resistor 123.

[0039] The source of transistor TR3 is connected to terminal TM1, and the drain of transistor TR3 is connected to terminal 22. The source of transistor TRc is connected to terminal TM1, and the drain of transistor TRc is connected to node ND3. Node ND3 is connected to the gate of transistor TR3 and to a first terminal of capacitor 131. A second terminal of capacitor 131 is connected to clock line LN2. The gate of transistor TRc is connected to node NDc. A first terminal of capacitor 132 is connected to node NDc, and a second terminal of capacitor 132 is connected to clock line LN1. Node NDc is also connected to terminal TM1 via resistor 133.

[0040] The source of transistor TR4 is connected to terminal TM2, and the drain of transistor TR4 is connected to terminal 21. The source of transistor TRd is connected to terminal TM2, and the drain of transistor TRd is connected to node ND4. Node ND4 is connected to the gate of transistor TR4 and to a first terminal of capacitor 141. A second terminal of capacitor 141 is connected to clock line LN2. The gate of transistor TRd is connected to node NDd. A first terminal of capacitor 142 is connected to node NDd, and a second terminal of capacitor 142 is connected to clock line LN1. Node NDd is also connected to terminal TM2 via resistor 143.

[0041] The operation of the transistor TR1 and the gate signal generating circuit 110 will be described with reference to FIG. 6. This operation will be described starting from the low level period of the clock signal CLK1. During the low level period of the clock signal CLK1, the transistor TRa is off and the transistor TR1 is on. At time t1, a rising edge occurs in the clock signal CLK1 and a falling edge occurs in the clock signal CLK2. Just before time t1, the node NDa has a voltage V INM is added.

[0042] The level change of the clock signal CLK2 at time t1 is transmitted to the node NDa through the capacitor 112. Then, at time t1, the gate potential of the transistor TRa becomes lower than the source potential of the transistor TRa by the voltage Vreg, and as a result, the transistor TRa turns on.

[0043] The turn-on of transistor TRa at time t1 instantly causes the voltage at node ND1 to rise substantially to voltage V INMAs a result of this rise, the absolute value of the gate-source voltage of transistor TR1 becomes smaller than the absolute value of the gate threshold voltage Vth, turning off transistor TR1. After time t1, a charging current flows from terminal TM1 through resistor 113 to capacitor 112, causing the potential at node NDa to rise. At time t2, the absolute value of the gate-source voltage of transistor TRa becomes smaller than the absolute value of the gate threshold voltage Vth, turning off transistor TRa. The time difference between times t1 and t2 is set to be shorter than half one cycle of clock signal CLK1 or CLK2 (the capacitance value of capacitor 112 and the resistance value of resistor 113 are set so that this occurs).

[0044] Time t3 is the time when half of one cycle of the clock signal CLK1 or CLK2 has elapsed from time t1. After time t1, the voltage of the node ND1 immediately before time t3 is substantially equal to the voltage V INM At time t3, a falling edge occurs in clock signal CLK1 and an up edge occurs in clock signal CLK2. The level change of clock signal CLK1 at time t3 is transmitted to node ND1 through capacitor 111. Then, at time t3, the gate potential of transistor TR1 becomes lower than the source potential of transistor TR1 by voltage Vreg, and as a result, transistor TR1 turns on. Thereafter, the circuit operation described above at time t1 is performed every time a falling edge occurs in clock signal CLK2, and the circuit operation described above at time t3 is performed every time a falling edge occurs in clock signal CLK1.

[0045] The operation of the transistor TR2 and the gate signal generation circuit 120 is similar to that of the transistor TR1 and the gate signal generation circuit 110 (see FIG. 8). The symbols "TR1", "TRa", "111", "112", "113", "ND1", "NDa", "TM1", "V INM" are used in the operation of the transistor TR2 and the gate signal generating circuit 120, respectively. INP ". The ON period of the transistor TR1 and the ON period of the transistor TR2 are the same. During the ON period of the transistor TR1, "V OUTM =V INM " and during the ON period of transistor TR2, "V OUTP =V INP "

[0046] In this way, at the timing (t1) of the falling edge of the clock signal CLK2, the level change of the clock signal CLK2 is transmitted to the gates of the transistors TRa and TRb through the capacitors 112 and 122, turning on the transistors TRa and TRb, thereby turning off the transistors TR1 and TR2. After that, through the turn-off of the transistors TRa and TRb (through t2), at the timing (t3) of the falling edge of the clock signal CLK1, the level change of the clock signal CLK1 is transmitted to the gates of the transistors TR1 and TR2 through the capacitors 111 and 121, thereby turning on the transistors TR1 and TR2.

[0047] 7, the operation of the transistor TR3 and the gate signal generation circuit 130 will be described. The operation will be described starting from the low level section of the clock signal CLK2. During the low level section of the clock signal CLK2, the transistor TRc is off and the transistor TR3 is on. At time t3, a rising edge occurs in the clock signal CLK2 and a falling edge occurs in the clock signal CLK1. Just before time t3, the node NDc has a voltage V INM is added.

[0048] The level change of the clock signal CLK1 at time t3 is transmitted to the node NDc through the capacitor 132. Then, at time t3, the gate potential of the transistor TRc becomes lower than the source potential of the transistor TRc by the voltage Vreg, and as a result, the transistor TRc turns on.

[0049] The turn-on of transistor TRc at time t3 instantly causes the voltage at node ND3 to rise substantially to voltage V INM As a result of this rise, the absolute value of the gate-source voltage of transistor TR3 becomes smaller than the absolute value of gate threshold voltage Vth, turning transistor TR3 off. After time t3, a charging current flows from terminal TM1 to capacitor 132 through resistor 133, causing the potential of node NDc to rise. At time t4, the absolute value of the gate-source voltage of transistor TRc becomes smaller than the absolute value of gate threshold voltage Vth, turning transistor TRc off. The time difference between times t3 and t4 is set to be shorter than half one cycle of clock signal CLK1 or CLK2 (the capacitance value of capacitor 132 and the resistance value of resistor 133 are set so that this occurs).

[0050] Time t5 is the time when half of one cycle of the clock signal CLK1 or CLK2 has elapsed from time t3. After time t3, the voltage of the node ND3 immediately before time t5 is substantially equal to the voltage V INM At time t5, a falling edge occurs in clock signal CLK2 and an up edge occurs in clock signal CLK1. The level change in clock signal CLK2 at time t5 is transmitted to node ND3 via capacitor 131. Then, at time t5, the gate potential of transistor TR3 becomes lower than the source potential of transistor TR3 by voltage Vreg, and as a result, transistor TR3 turns on. Thereafter, the circuit operation described above at time t3 is performed every time a falling edge occurs in clock signal CLK1, and the circuit operation described above at time t5 is performed every time a falling edge occurs in clock signal CLK2.

[0051] The operation of the transistor TR4 and the gate signal generation circuit 140 is similar to that of the transistor TR3 and the gate signal generation circuit 130 (see FIG. 8). The symbols "TR3", "TRc", "131", "132", "133", "ND3", "NDc", "TM1", "V INM " are used in the operation of the transistor TR4 and the gate signal generating circuit 140, respectively. INP ". The ON period of the transistor TR3 and the ON period of the transistor TR4 are the same. During the ON period of the transistor TR3, "V OUTP =V INM " and during the ON period of the transistor TR4, "V OUTM =V INP "

[0052] In this way, at the timing (t3) of the falling edge of the clock signal CLK1, the level change of the clock signal CLK1 is transmitted to the gates of the transistors TRc and TRd through the capacitors 132 and 142, turning on the transistors TRc and TRd, thereby turning off the transistors TR3 and TR4. After that, through the turn-off of the transistors TRc and TRd (through t4), at the timing (t5) of the falling edge of the clock signal CLK2, the level change of the clock signal CLK2 is transmitted to the gates of the transistors TR3 and TR4 through the capacitors 131 and 141, thereby turning on the transistors TR3 and TR4.

[0053] FIG. 8 shows the waveforms of signals and voltages at each part in FIG. 5 and the state transitions of each transistor.

[0054] Here, specific numerical examples relating to the current sensor 10 are given. The internal power supply voltage Vreg is, for example, 4.0 V. The common-mode voltage V CM The maximum voltage assumed is 40.0 V, and the actual common-mode voltage V CMWhen the sense voltage V is 40.0V, SNS If is 0.1V, (V INP , V INM )=(40.0,39.9) (units are volts).

[0055] In this numerical example, if a configuration (hereinafter referred to as a hypothetical configuration) were adopted in which a gate signal of the internal power supply voltage Vreg or 0V were supplied to each transistor constituting the switches SW1 to SW4, a voltage of 36V or 40V would be applied between the gate and source of each transistor. In other words, in the hypothetical configuration, each transistor constituting the switches SW1 to SW4 would be required to have a high breakdown voltage. Achieving a high breakdown voltage would result in larger transistors and increased costs for the current sensor 10.

[0056] 5, a voltage exceeding the internal power supply voltage Vreg is not applied between the gate and source of each of the transistors TR1 to TR4 (the same applies to the transistors TRa to TRd). This makes it possible to use transistors with low breakdown voltage, which is expected to reduce the size of the transistors and the cost of the current sensor 10.

[0057] The breakdown voltage of the semiconductor substrates connected to terminals TM1, TM2, 21, and 22 is the common-mode voltage V CM Since capacitors 23 and 24 are provided between the terminals 21 and 22 and the circuit 13, the breakdown voltage of each component in the circuit 13 is CM Regardless of the voltage, it is sufficient if it is slightly higher than the internal power supply voltage Vreg.

[0058] Some modifications, applied techniques, supplementary points, etc. to the above-described embodiment will be described.

[0059] In the above embodiment, it is assumed that the voltage Vreg is a voltage generated from the power supply voltage VDD, but the voltage Vreg may be the power supply voltage VDD itself supplied to the terminal TM4 from outside the current sensor 10. In this case, the internal power supply circuit 14 can be omitted from the current sensor 10.

[0060] Sense resistor R SNS is externally connected to the current sensor 10 as described above, SNS may be built into the current sensor 10.

[0061] Sense resistor R SNS The above description has been given of a configuration in which the sense resistor R is provided on the higher potential side than the load LD. SNS may be provided on the lower potential side of the load LD.

[0062] The current sensor 10 may be installed in a vehicle such as an automobile, and may be applied to any load LD in the vehicle. However, the current sensor 10 is not limited to in-vehicle use, and may be used for any purpose.

[0063] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0064] The channel types of the FETs (field effect transistors) shown in each embodiment are merely examples. The channel type of any FET can be changed between P-channel and N-channel types without departing from the spirit of the above.

[0065] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0066] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0067] A current sensor (10; see FIG. 1) according to one aspect of the present disclosure includes a sense resistor (R SNSa square wave generating circuit (11) connected to the first and second input terminals and configured to be able to generate a square wave signal having an amplitude proportional to the voltage across the sense resistor; and a current detection signal (S OUT and a current detection signal output circuit (13) configured to be able to output a current detection signal (first configuration).

[0068] In a configuration that directly monitors the voltage between the first and second input terminals, the elements that receive the voltage at the first and second input terminals must have a withstand voltage that is equal to or greater than the voltage applied to each input terminal. Increasing the required withstand voltage leads to larger elements and higher costs. By using a method that generates a square wave signal with an amplitude proportional to the voltage across the sense resistor and outputs a current detection signal based on the square wave signal, as in the first configuration, it is possible to reduce the withstand voltage required for the elements that receive the voltage at the first and second input terminals.

[0069] In the current sensor according to the first configuration (see FIG. 2), the square wave generating circuit has first and second output terminals (21, 22), a first switch (SW1) provided between the first input terminal and the first output terminal, a second switch (SW2) provided between the second input terminal and the second output terminal, a third switch (SW3) provided between the first input terminal and the second output terminal, and a fourth switch (SW4) provided between the second input terminal and the first output terminal, and the current sensor may be configured (second configuration) further including a switch control circuit (12) configured to generate the square wave signal between the first output terminal and the second output terminal by controlling the states of the first to fourth switches.

[0070] In a current sensor according to the second configuration (see Figures 3 and 4), the switch control circuit may be configured (third configuration) to generate the square wave signal between the first output terminal and the second output terminal by alternately switching between a first state (ST1) in which the first switch and the second switch are controlled to be in an on state and the third switch and the fourth switch are controlled to be in an off state, and a second state (ST2) in which the first switch and the second switch are controlled to be in an off state and the third switch and the fourth switch are controlled to be in an on state.

[0071] In the current sensor according to the second or third configuration, the first to fourth switches are first to fourth main transistors (TR1 to TR4) each formed of a field effect transistor, and the switch control circuit includes a first sub-transistor (TRa) provided between the first input terminal and the gate of the first main transistor, a second sub-transistor (TRb) provided between the second input terminal and the gate of the second main transistor, a third sub-transistor (TRc) provided between the first input terminal and the gate of the third main transistor, a fourth sub-transistor (TRd) provided between the second input terminal and the gate of the fourth main transistor, and a clock output circuit (30) configured to output a first clock signal (CLK1) which is a rectangular wave signal and a second clock signal (CLK2) which corresponds to an inverted signal of the first clock signal, and the switch control circuit may be configured (fourth configuration) to be able to control each main transistor to an on or off state by controlling the gate voltage of each main transistor via each sub-transistor using the first and second clock signals.

[0072] In the current sensor according to the fourth configuration, the switch control circuit includes a first gate signal generation circuit (110) including the first sub-transistor, a second gate signal generation circuit (120) including the second sub-transistor, a third gate signal generation circuit (130) including the third sub-transistor, a fourth gate signal generation circuit (140) including the fourth sub-transistor, a first clock line (LN1) to which the first clock signal is applied, and a second clock line (LN2) to which the second clock signal is applied. Each gate signal generating circuit has a first capacitor, a second capacitor, and a resistor, and in the first gate signal generating circuit, the first capacitor (111) is provided between the gate of the first main transistor and the first clock line, the second capacitor (112) is provided between the gate of the first sub-transistor and the second clock line, and the resistor (113) is provided between the gate of the first sub-transistor and the first input terminal, and in the second gate signal generating circuit, the first capacitor (121) is provided between the gate of the second sub-transistor and the first input terminal. The third gate signal generation circuit may have a configuration (fifth configuration) in which the first capacitor (131) is provided between the gate of the third main transistor and the second clock line, the second capacitor (132) is provided between the gate of the third sub-transistor and the first clock line, and the resistor (123) is provided between the gate of the second sub-transistor and the second input terminal; in the third gate signal generation circuit, the first capacitor (131) is provided between the gate of the third main transistor and the second clock line, the second capacitor (132) is provided between the gate of the third sub-transistor and the first clock line, and the resistor (133) is provided between the gate of the third sub-transistor and the first input terminal; and in the fourth gate signal generation circuit, the first capacitor (141) is provided between the gate of the fourth main transistor and the second clock line, the second capacitor (142) is provided between the gate of the fourth sub-transistor and the first clock line, and the resistor (143) is provided between the gate of the fourth sub-transistor and the second input terminal.

[0073] According to the fifth configuration, the voltage applied between the electrodes of each transistor can be set to be equal to or less than the potential difference between the first and second levels, regardless of the voltage applied to the first or second input terminal. In other words, it is not necessary to provide each transistor with a withstand voltage corresponding to the voltage applied to the first or second input terminal, and each transistor can be made smaller.

[0074] In the current sensor according to the fifth configuration, the signal levels of the first and second clock signals change between first and second levels that are different from each other, whereby a first timing (t1, t5) at which the signal level of the first clock signal switches from the first level to the second level and the signal level of the second clock signal switches from the second level to the first level and a second timing (t3) at which the signal level of the first clock signal switches from the second level to the first level and the signal level of the second clock signal switches from the first level to the second level alternates, and at the first timing (see t1 in FIG. 6 ), the level change of the second clock signal is transmitted to the gates of the first and second sub-transistors through the second capacitors in the first and second gate signal generation circuits, turning on the first and second sub-transistors, thereby turning off the first and second main transistors, and then the first and second sub-transistors are turned off (see t2 in FIG. 6 ). At the second timing (see t3 in FIG. 6 ), a level change of the first clock signal is transmitted to the gates of the first and second main transistors through the first capacitors in the first and second gate signal generation circuits, thereby turning on the first and second main transistors; at the second timing (see t3 in FIG. 7 ), a level change of the first clock signal is transmitted to the gates of the third and fourth sub-transistors through the second capacitors in the third and fourth gate signal generation circuits, thereby turning on the third and fourth sub-transistors, thereby turning off the third and fourth main transistors; thereafter, after the third and fourth sub-transistors are turned off (see t4 in FIG. 7 ), at the first timing (see t5 in FIG. 7 ), a level change of the second clock signal is transmitted to the gates of the third and fourth main transistors through the first capacitors in the third and fourth gate signal generation circuits, thereby turning on the third and fourth main transistors (a sixth configuration). [Explanation of symbols]

[0075] 10 Current Sensor 11 Square wave generation circuit 12 Switch control circuit 13 Current detection signal output circuit 14 Internal power circuit 21, 22 terminals (internal terminals) TM1 to TM5 terminals (external terminals) R SNS Sense Resistor SW1 to SW4 switches 30 Clock output circuit TR1~TR4 Transistors (main transistors) TRa~TRd Transistors (sub-transistors) 110, 120, 130, 140 Gate signal generation circuit 111, 121, 131, 141 Capacitor (first capacitor) 112, 122, 132, 142 Capacitors (second capacitors) 113, 123, 133, 143 Resistors LN1, LN2 clock lines

Claims

1. first and second input terminals configured to be connectable to both ends of a sense resistor; a square wave generating circuit connected to the first and second input terminals and configured to generate a square wave signal having an amplitude proportional to a voltage across the sense resistor; a current detection signal output circuit configured to be able to output a current detection signal corresponding to the current flowing through the sense resistor based on the square wave signal, The square wave generating circuit comprises: first and second output terminals; a first switch provided between the first input terminal and the first output terminal; a second switch provided between the second input terminal and the second output terminal; a third switch provided between the first input terminal and the second output terminal; a fourth switch provided between the second input terminal and the first output terminal, The current sensor further includes a switch control circuit configured to generate the square wave signal between the first output terminal and the second output terminal by controlling states of the first to fourth switches. , current sensor.

2. The switch control circuit is configured to generate the square wave signal between the first output terminal and the second output terminal by alternately switching between a first state in which the first switch and the second switch are controlled to an on state and the third switch and the fourth switch are controlled to an off state, and a second state in which the first switch and the second switch are controlled to an off state and the third switch and the fourth switch are controlled to an on state.

10. The current sensor of claim 1.

3. the first to fourth switches are first to fourth main transistors each configured by a field effect transistor, The switch control circuit a first sub-transistor provided between the first input terminal and the gate of the first main transistor; a second sub-transistor provided between the second input terminal and the gate of the second main transistor; a third sub-transistor provided between the first input terminal and the gate of the third main transistor; a fourth sub-transistor provided between the second input terminal and the gate of the fourth main transistor; a clock output circuit configured to output a first clock signal that is a square wave signal and a second clock signal that is an inverted signal of the first clock signal; The switch control circuit is configured to be able to control each main transistor to an on or off state by controlling the gate voltage of each main transistor through each sub-transistor using the first and second clock signals.

3. The current sensor according to claim 1 or 2.

4. The switch control circuit a first gate signal generating circuit including the first sub-transistor; a second gate signal generating circuit including the second sub-transistor; a third gate signal generating circuit including the third sub-transistor; a fourth gate signal generating circuit including the fourth sub-transistor; a first clock line to which the first clock signal is applied; a second clock line to which the second clock signal is applied; Each gate signal generating circuit has a first capacitor, a second capacitor, and a resistor; In the first gate signal generation circuit, the first capacitor is provided between the gate of the first main transistor and the first clock line, the second capacitor is provided between the gate of the first sub-transistor and the second clock line, and the resistor is provided between the gate of the first sub-transistor and the first input terminal; In the second gate signal generation circuit, the first capacitor is provided between the gate of the second main transistor and the first clock line, the second capacitor is provided between the gate of the second sub-transistor and the second clock line, and the resistor is provided between the gate of the second sub-transistor and the second input terminal; In the third gate signal generation circuit, the first capacitor is provided between the gate of the third main transistor and the second clock line, the second capacitor is provided between the gate of the third sub-transistor and the first clock line, and the resistor is provided between the gate of the third sub-transistor and the first input terminal; In the fourth gate signal generation circuit, the first capacitor is provided between the gate of the fourth main transistor and the second clock line, the second capacitor is provided between the gate of the fourth sub-transistor and the first clock line, and the resistor is provided between the gate of the fourth sub-transistor and the second input terminal.

4. The current sensor according to claim 3.

5. the signal levels of the first and second clock signals change between first and second levels which are different from each other, whereby a first timing at which the signal level of the first clock signal switches from the first level to the second level and the signal level of the second clock signal switches from the second level to the first level and a second timing at which the signal level of the first clock signal switches from the second level to the first level and the signal level of the second clock signal switches from the first level to the second level occur alternately; At the first timing, a level change of the second clock signal is transmitted to the gates of the first and second sub-transistors through the second capacitors in the first and second gate signal generation circuits, thereby turning on the first and second sub-transistors, and thereby turning off the first and second main transistors; thereafter, after the first and second sub-transistors are turned off, at the second timing, a level change of the first clock signal is transmitted to the gates of the first and second main transistors through the first capacitors in the first and second gate signal generation circuits, thereby turning on the first and second main transistors; At the second timing, a level change of the first clock signal is transmitted to the gates of the third and fourth sub-transistors through the second capacitors in the third and fourth gate signal generating circuits, thereby turning on the third and fourth sub-transistors, and thereby turning off the third and fourth main transistors. Thereafter, after the third and fourth sub-transistors are turned off, at the first timing, a level change of the second clock signal is transmitted to the gates of the third and fourth main transistors through the first capacitors in the third and fourth gate signal generating circuits, thereby turning on the third and fourth main transistors.

5. The current sensor according to claim 4.

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