Signal processing circuit with zero crossing detection

Abstract

Signal processing circuit (10) comprising a modulation unit (11) for generating a modulated signal, an amplification unit (12) for amplifying the modulated signal and thereby creating an amplified modulated signal and a demodulation unit (14) for demodulating the amplified modulated signal and thereby creating a demodulated signal. The signal processing circuit (10) further comprises a zero current detection unit (13) connected to an output of the amplification unit (12) upstream of the demodulation unit and configured to detect a zero crossing of a current based on the amplified modulated signal.

Description

[0001] P2920PC00

[0002] SIGNAL PROCESSING CIRCUIT WITH ZERO CROSSING DETECTION

[0003] The present invention relates to a signal processing circuit with zero crossing detection (ZCD). The present invention also relates to a current transducer with a signal processing circuit with ZCD.

[0004] In power electronics, important building blocks like DC-DC converters use Zero Current Switching (ZCS) circuits to eliminate the switching losses that occur when power MOSFETs turn on. DC-DC converters are often assisted by current transducer circuits to monitor load current, and these may have the Zero Crossing Detection on board. Current transducers may comprise a magnetic field sensor, such as a Hall sensor comprising at least one Hall element (also known as Hall cell) and a signal processing circuit with a modulation, amplification and demodulation stage implementing the so called spinning current technique. In current sensor circuits of the prior art, zero crossing detection takes place after the demodulation stage (see figure 1).

[0005] While the trend is to increase the switching frequency of DC-DC converters for better efficiency, this requires their current control loop to react faster. Switching at the zero crossing of the output current should ideally happen with both high accuracy and high speed. These are often mutually exclusive requirements.

[0006] Accurate open loop current sensors based on the Hall effect use the spinning current technique, which modulates the signal. This technique allows to achieve great accuracy, but comes at the cost of a slower output response, because of the demodulation of the signal that must follow spinning. In these products, classical ZCD architectures therefore suffer from a relatively long response time.

[0007] In view of the foregoing, it is an object of the invention to provide a signal processing circuit with zero crossing detection that is fast and accurate.

[0008] It is also an object of the invention to provide a current transducer comprising a signal processing circuit with zero crossing detection that is fast and accurate.

[0009] Objects of the invention have been achieved by providing a signal processing circuit according to claim 1 and by providing a current transducer according to claim 11 .

[0010] Dependent claims set out various advantageous features of embodiments of the invention. P2920PC00

[0011] Disclosed herein is a signal processing circuit comprising a modulation unit for generating a modulated signal, an amplification unit for amplifying the modulated signal and thereby creating an amplified modulated signal and a demodulation unit for demodulating the amplified modulated signal and creating a demodulated signal.

[0012] The signal processing circuit further comprises a zero current detection unit connected to an output of the amplification unit upstream of the demodulation unit, the zero current detection unit configured to detect a zero crossing of a current based on the amplified modulated signal.

[0013] In an advantageous embodiment, the signal processing circuit further comprises another amplification unit connected to an output of the demodulation unit for amplifying the demodulated signal and thereby creating an amplified demodulated signal.

[0014] In an advantageous embodiment, the signal processing circuit further comprises a zero current switching circuit configured to output a change of state signal for controlling the state of one or more transistors of an external system, during the zero crossing of the current based on an output of the zero current detection unit.

[0015] In an advantageous embodiment, the zero current detection unit comprises a detection mode selection circuit for configuring the zero current detection unit for a single threshold mode and for a window threshold mode.

[0016] In an advantageous embodiment, the zero current detection unit comprises a threshold generator and sampling circuit comprising input switches and at least one sampling capacitor for sampling the amplified modulated signal and a reference signal.

[0017] In an advantageous embodiment, the amplified modulated signal and the reference signal are differential signals and the at least one sampling capacitor are two sampling capacitors.

[0018] In an advantageous embodiment, the threshold generator and sampling circuit is configured to sample the amplified modulated signal and the reference signal twice per modulation cycle.

[0019] In an advantageous embodiment, the threshold generator and sampling circuit is configured to sample each of the differential signals by each of the two sampling capacitors once per modulation cycle. P2920PC00

[0020] Also disclosed herein is a current transducer comprising a Hall sensor comprising at least one Hall element and a signal processing circuit according to any preceding embodiment, wherein the at least one Hall element is connected to the signal processing circuit and the signal processing circuit is configured to subsequently modulate, amplify and demodulate a signal from the at least one Hall element.

[0021] Further advantageous features of the invention will be apparent from the following detailed description of embodiments of the invention and the accompanying illustrations.

[0022] Brief description of the figures

[0023] Figure 1 is a schematic view of a signal processing circuit of the prior art;

[0024] Figure 2 is a schematic view of a signal processing circuit according to an embodiment of the invention;

[0025] Figure 3 is a schematic view of a high-pass filter and a zero current detection unit of a signal processing circuit according to an embodiment of the invention;

[0026] Figure 4 is a schematic view of a high-pass filter and a zero current detection unit of a signal processing circuit according to an embodiment of the invention;

[0027] Figure 5 is a schematic view of a modulated signal and control signals generated by a signal processing circuit according to an embodiment of the invention;

[0028] Figure 6 is a schematic view of a current transducer according to an embodiment of the invention.

[0029] Referring to the figures, a signal processing circuit 10 according to embodiments of the invention comprises a modulation unit 11 for generating a modulated signal, an amplification unit 12 for amplifying the modulated signal and thereby creating an amplified modulated signal and a demodulation unit 14 for demodulating the amplified modulated signal and thereby creating a demodulated signal, characterized in that the signal processing circuit 10 further comprises a zero current detection unit 13 connected to an output of the amplification unit 12 and configured to detect a zero crossing of a current based on the amplified modulated signal.

[0030] The signal processing circuit 10 may further comprise another amplification unit 30 connected to an output of the demodulation unit 14 for amplifying the demodulated signal and thereby creating an amplified demodulated signal.

[0031] In preferred embodiments, the signal processing 10 further comprises a zero current switching circuit 20 configured to change the state of switches of an external power P2920PC00 semiconductor (e.g. of a DC-DC converter) connected to an external controller (e.g. of the DC-DC converter).

[0032] In advantageous embodiments, the signal processing circuit 10 is used for processing a sensor signal.

[0033] In a preferred embodiment, the signal processing circuit 10 is part of a Hall sensor 2 of a current transducer 1. The Hall sensor 2 further comprises a Hall element 3. The modulation unit 11 in combination with the Hall element 3 generates a modulated signal Vin+, Vin-, which is subsequently processed by the amplification unit 12, the demodulation unit 14 and the other amplification unit 30 of the signal processing circuit 10. The current transducer 1 may further comprise a power supply 4 for the signal processing circuit 10. The power supply 4 may comprise a battery. Alternatively, or in addition, the current transducer 1 may further comprise an interface such as a socket for connecting an external power supply (not shown in the figures).

[0034] The Hall sensor 2 may comprise a plurality of Hall elements. The Hall element 3 or the plurality of Hall elements and the signal processing circuit 10 may be integrated on a single semiconductor chip, such as a single silicon chip.

[0035] The Hall sensor 2 implements the spinning current technique. This technique is well known and essentially works as follows. The Hall element 3 is connected to a modulation unit, which is configured to generate a modulated signal from the Hall element by “spinning”, i.e. , rotating the directions of the bias current and the sensing voltage. In practice, the rotation is discrete with an increment angle of, for example 90° or 180°. The directions of the bias current and the sensing voltage are perpendicular to each other in each phase of the modulation.

[0036] The directions are defined by electrodes on the Hall element. The modulation unit is configured to switch the bias current and the sensing voltage between the different electrodes to spin the directions of the bias current and the sensing voltage.

[0037] In an exemplary embodiment, the Hall element 3 comprises four electrodes defining two orthogonal directions (and their opposite directions) for the bias current and the sensing voltage. Two orthogonal magnetic field directions may be sensed with this geometry if the bias current and the sensing voltage are spun at an increment angle of 90°. Alternatively, a single magnetic field direction is sensed if the bias current and the sensing voltage are spun at an increment angle of 180°. P2920PC00

[0038] The demodulation unit 14 is configured to chronologically combine and correct the signs of the Hall voltages sensed in different phases of a modulation cycle for each magnetic field sensing direction.

[0039] In the illustrated embodiments, the signal comprises a positive signal Vin+ and a negative signal Vin- and the signal processing circuit 10 separately processes the positive and negative signals in the modulation unit 11 , in the amplification unit 12 and in the demodulation unit 14. In preferred embodiments, the amplified modulated positive and negative signals Vin+, Vin- are filtered by a high-pass filter 15 to remove an offset. The high-pass filter 15 may be an RC filter comprising a first resistor R1 and a first capacitor C1 for the positive signal Vin+ and a second resistor R2 and a second capacitor C2 for the negative signal Vin-. The first and second capacitor C1 , C2 may be connected to ground or to a bias voltage Vb. The outputs of the high-pass filter 15 provide the filtered positive signal Vi+ and the negative filtered signal Vi-. These filtered positive and negative signals Vi+, Vi- are fed into the zero current detection unit 13.

[0040] The zero current detection unit 13 may be a threshold type detector 13a, 13b suitable for detecting a zero crossing of a unipolar signal. A positive threshold detector 13a returns a positive zero current detection output when the signal is below a positive threshold and a negative zero current detection output otherwise. A negative threshold detector 13b returns a positive zero current detection output when the signal is above a negative threshold and a negative zero current detection output otherwise.

[0041] The zero current detection unit 13 may be a window type detector suitable for detecting a zero crossing of a bipolar signal. This type of detector has a positive threshold and a negative threshold and returns a positive zero current detection output when the signal is between the negative threshold and the positive threshold and it returns a negative zero current detection output otherwise. A window type detector 13 may be implemented by a combination of a positive threshold detector 13a and a negative threshold detector 13b.

[0042] In a preferred embodiment, the zero current detection unit 13 is configurable to operate as a threshold type detector or as a window type detector through the control input “config”. The zero current detection unit 13 operates as a window type detector if “config” is set to TRUE. The negative threshold detector 13b is disabled if “config” is set to FALSE and the zero current detection unit 13 becomes a threshold type detector. P2920PC00

[0043] The zero current detection unit 13 may further comprise a control input EN for enabling or disabling the function of the zero current detection unit 13.

[0044] An implementation of a configurable zero current detection unit 13 with a positive threshold detector 13a, a negative threshold detector 13b and a detection mode selection circuit 16 comprising Boolean operators is illustrated in figure 3.

[0045] The positive and negative threshold detectors 13a, 13b may be identical. The positive and negative threshold detectors 13a, 13b are merely differently connected to the input voltages Vi+, Vi- and to the reference voltages Vref+, Vref-. The reference voltages Vref+, Vref- are used for setting the threshold. In the embodiment of figure 4, the same reference voltages Vref+, Vref- are applied to the positive and negative threshold detectors 13a, 13b, which leads to symmetric thresholds.

[0046] In alternative embodiments, the positive and negative threshold detectors 13a, 13b are differently implemented, or they have asymmetric thresholds, e.g., different reference voltages Vref+, Vref- are applied to the positive and negative threshold detectors 13a, 13b.

[0047] In the embodiment illustrated in figure 4, the zero current detection unit 13, i.e. , each of the positive and negative threshold detectors 13a, 13b is implemented using switched-capacitor techniques to realize the ZCD functions.

[0048] Each of the positive and negative threshold detectors 13a, 13b comprises a threshold generator 17a, 17b comprising input and reset switches and a control signal generator for generating control signals for opening and closing the input and reset switches.

[0049] The input switches SW1a-SW6a, SW1b-SW6b connect the input voltages Vi+, Vi- and the reference voltages Vref+, Vref- to and disconnect them from NMOS voltage followers 18a, 18b. The NMOS voltage followers 18a, 18b are connected via sampling capacitors C3a, C4a, C3b, C4b to a differential comparator COMPa, COMPb (i.e., with a differential output comprising a first output and a second output complementary to the first output). The differential comparator COMPa, COMPb is reset by two bypasses from inputs to outputs of the differential comparator and reset switches SW7a, SW8a, SW7b, SW8b in the bypasses.

[0050] The first control signal cp1 controls the first and sixth input switches SW1a, SW6a, SW1b, SW6b. The second control signal <p2 controls the second and fifth input switches SW2a, SW5a, SW2b, SW5b. P2920PC00

[0051] For the positive threshold detector 13a, the first control signal cp1 charges the first sampling capacitor C3a with the positive input voltage Vi+ and the second sampling capacitor C4a with the negative input voltage Vi-. The second control signal <p2 charges the first sampling capacitor C3a with the negative input voltage Vi- and the second sampling capacitor C4a with the positive input voltage Vi+. The third control signal q>34 charges the first sampling capacitor C3a with the negative reference input voltage Vref- and the second sampling capacitor C4a with the positive reference voltage Vref+. The third control signal q>34 also resets the differential comparator COMPa.

[0052] For the negative threshold detector 13b, the positive and negative input voltages and the positive and negative reference voltages are swapped.

[0053] All the control signals cp1 , cp2, q>34 are synchronized with the modulation of the modulated signal. The active high states of the control signals q>1 , cp2, q>34 preferably do not overlap. For example, the control signals <p1 , cp2, q>34 may be square waves, which are high at different, non-overlapping fractions of a period of the modulated signal. The third control signal q>34 is a sum of the two control signals <p3 and <p4 illustrated in figure 5.

[0054] The modulated signal is sampled with opposite signs only during high phases cp1 and <p2 of each cycle, the other phases are used exclusively for sampling and validation of the comparator function. The illustrated circuit allows two detections for every cycle of the modulation. This is accomplished by releasing the comparator reset switches during both cp1 and <p2 (when phase q>34 is low).

[0055] At the output, a latch circuit controlled by a clock generates the ZCD outputs Q1 and Q2.

[0056] The present invention proposes to have the ZCD function happen before the demodulation in the signal path, on the still modulated signal (resulting from spinning in the example of the Hall sensor-based current transducer).

[0057] The ZCD function may be made programmable and incorporate features for greater versatility, such as hysteresis, offset adjustment, threshold programming, and various detection mode options (e.g., window detection or threshold detection). This allows the user to select the most appropriate detection scheme based on the application needs and constraints. P2920PC00

[0058] List of references

[0059] Current transducer 1

[0060] Hall sensor 2

[0061] Hall element 3 signal processing circuit 10, 10’ modulation unit 11 , 11’ amplification unit 12, 12’, 30, 30’ zero current detection unit(s) 13, 13a, 13b, 13’ detection mode selection circuit 16 threshold generator and sampling circuit 17a, 17b input and reset switches SW1a, SW2a, SW3a, SW4a, SW5a, SW6a, SW7a, SW8a, SW1b, SW2b, SW3b, SW4b, SW5b, SW6b, SW7b, SW8b

[0062] NMOS voltage followers 18a, 18b sampling capacitors C3a, C4a, C3b, C4b bypasses 19a, 19b comparator circuit differential comparator COMPa, COMPb output circuit latch LCHa, LCHb input voltages Vi+, Vi- reference voltages Vref+, Vref- control inputs EN, config output signals Q1, Q2, ZCD out control signals q>1 , cp2, cp3, cp4, q>34 zero current switching circuit 20 demodulation unit 14 high-pass filter, RC filter 15 resistors R1 , R2 capacitor C1 , C2 input voltages Vin+, Vin- bias voltage Vb output voltages Vi+ , Vi- power supply 4

Claims

9P2920PC00Claims1. Signal processing circuit (10) comprising a modulation unit (11) for generating a modulated signal, an amplification unit (12) for amplifying the modulated signal and thereby creating an amplified modulated signal and a demodulation unit (14) for demodulating the amplified modulated signal and thereby creating a demodulated signal, characterized in that the signal processing circuit (10) further comprises a zero current detection unit (13) connected to an output of the amplification unit (12) upstream of the demodulation unit and configured to detect a zero crossing of a current based on the amplified modulated signal.

2. Signal processing circuit according to the claim 1 , wherein the signal processing circuit is suitable for a Hall sensor (2) comprising at least one Hall element (3), wherein the modulation unit (11) is connectable to the at least one Hall element (3) and configured to apply a spinning bias current to the at least one Hall element (3) and pick up a spinning Hall voltage of the at least one Hall element (3) to generate the modulated signal.

3. Signal processing circuit according to the directly preceding claim, wherein demodulation unit (14) is configured to chronologically combine and correct signs of the spinning Hall voltages sensed in different phases of a modulation cycle.

4. Signal processing circuit according to any preceding claim, further comprising another amplification unit (30) connected to an output of the demodulation unit (14) for amplifying the demodulated signal and thereby creating an amplified demodulated signal.

5. Signal processing circuit according to any preceding claim, further comprising a zero current switching circuit (20) configured to output a change of state, for controlling one or more transistors of an external system, during the zero crossing of the current based on an output of the zero current detection unit (13).

6. Signal processing circuit according to any preceding claim, wherein the zero current detection unit (13) comprises a detection mode selection circuit (16) for configuring the zero current detection unit (13) for a single threshold mode and for a window threshold mode.

7. Signal processing circuit according to any preceding claim, wherein the zero current detection unit (13) comprises a threshold generator and sampling circuit (17a, 17b) comprising input switches and at least one sampling capacitor for sampling the amplified modulated signal and a reference signal.

8. Signal processing circuit according to the directly preceding claim, wherein theP2920PC00 amplified modulated signal and the reference signal are differential signals and the at least one sampling capacitor are two sampling capacitors.

9. Signal processing circuit according to the directly preceding claim, wherein the threshold generator and sampling circuit (17a, 17b) is configured to sample the amplified modulated signal and the reference signal twice per modulation cycle.

10. Signal processing circuit according to the directly preceding claim, wherein the threshold generator and sampling circuit (17a, 17b) is configured to sample each of the differential signals by each of the two sampling capacitors once per modulation cycle.

11. Current transducer (1) comprising a Hall sensor (2) comprising at least one Hall element (3) and a signal processing circuit (10) according to any preceding claim, wherein the at least one Hall element (3) is connected to the modulation unit (11) and the modulation unit (11) is configured to apply a spinning bias current to the at least one Hall element (3) and pick up a spinning Hall voltage of the at least one Hall element (3) to generate the modulated signal.

12. Current transducer (1) according to the directly preceding claim, wherein the Hall sensor (2) is integrated on a single semiconductor chip.

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