A wireless receiving chip capable of listening to Bluetooth broadcasts and its application circuit

Abstract

The present invention discloses a wireless receiving chip capable of listening to Bluetooth broadcasts and its application circuit. Among them, the chip includes at least four receiving and demodulating modules, decoders with the same number as the receiving and demodulating modules, a data packet filtering and caching module, a wireless receiving management module, a communication interface control module, and a clock module. Three of them are broadcast channel receiving and demodulating modules, which work on 3 Bluetooth broadcast channels respectively, and listen to Bluetooth broadcast packets on the corresponding broadcast channels in real time. The remaining receiving and demodulating module is an extended broadcast packet receiving and demodulating module for receiving extended broadcast packets. The present invention uses 4 independent receiving and demodulating modules working on 4 receiving channels. Each receiving and demodulating module can work independently without mutual influence, greatly improving the receiving efficiency and speed of broadcast packets and also increasing the anti-interference ability.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless chips, and particularly relates to a wireless receiving chip capable of listening to Bluetooth broadcasts and its application circuit. Background Art

[0002] In BLE (Bluetooth Low Energy) communication, the GFSK modulation method is adopted, which operates in the 2.4GHz ISM band with a frequency range of 2.400 - 2.4835GHz. This frequency range is divided into 40 channels (f = 2402 + k * 2MHz, k = 0, 1, …, 39), with a channel spacing of 2MHz. Among them, there are 3 broadcast channels (2402MHz, 2426MHz, 2480MHz) and 37 data channels, and adaptive frequency hopping is used.

[0003] BLE (Bluetooth Low Energy) device broadcasts are divided into two categories, one is traditional broadcast data, and the other is extended broadcast (supported after BLE5.0). When a BLE device sends traditional broadcasts, the BLE device will sequentially send broadcast data on three main broadcast channels (channels 37, 38, and 39). According to the BLE protocol, the method of sending extended broadcasts is as follows:

[0004] First, broadcast data is sequentially sent on several main broadcast channels, and the broadcast data type is marked as ADV_EXT_IND, which carries relevant information of the second broadcast channel (channel number, reception time limit Aux Offset, etc.);

[0005] After receiving a broadcast data packet of the ADV_EXT_IND type, the receiving device, according to the information carried therein [including the channel number and PHY (physical layer) information], listens for an extended broadcast packet of the AUX_ADV_IND type on the second broadcast channel (one of channels 0 - 36). If a compliant broadcast packet starts to be transmitted within the required time limit, this broadcast packet is the extended broadcast packet.

[0006] A traditional broadcast packet can have 6 - 37 data including 6 - byte broadcast device address information. The data that can be broadcast by an extended broadcast packet can reach up to 254 bytes at most.

[0007] Since the frequency range in which BLE operates is an unlicensed frequency band, in addition to Bluetooth devices, there are also devices such as WIFI and ZIGBEE that operate in this range, and there is a relatively high probability of conflict in space in wireless communication. In existing BLE chips, they can only operate on one channel at the same time. When receiving the master broadcast information, the chip operates on one of the three channels 37, 38, and 39. When the broadcast information is sent, if the channel is just interfered with, the broadcast data this time cannot be successfully received, and it is necessary to wait for the next round of broadcast to come and then try to receive it. Even if the receiving device switches the receiving channel, there is a certain probability of being interfered with and the reception fails every time a round of broadcast comes.

[0008] Although each round of broadcast is sent on 3 master broadcast channels, as long as the channel where the receiving end is located at that time is interfered with, the broadcast data of this time cannot be received. This causes it to take a relatively long time for the receiving end to successfully receive the complete broadcast message. Summary of the Invention

[0009] In view of the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a wireless receiving chip capable of listening to Bluetooth broadcasts and its application circuit, which can improve the response efficiency of Bluetooth broadcast packets.

[0010] To solve the above technical problems, the present invention adopts the following technical solutions:

[0011] A wireless receiving chip capable of listening to Bluetooth broadcasts, which includes:

[0012] At least four receiving and demodulating modules, three of which are broadcast channel receiving and demodulating modules, which respectively operate on 3 broadcast channels of Bluetooth and monitor the Bluetooth broadcast packets on the corresponding broadcast channels in real time; the remaining receiving and demodulating module is an extended broadcast packet receiving and demodulating module, which receives extended broadcast packets;

[0013] Decoders with the same number as the receiving and demodulating modules;

[0014] Packet filtering and caching module;

[0015] Wireless receiving management module;

[0016] Communication interface control module;

[0017] Clock module;

[0018] The clock module is connected to the receiving and demodulating modules, decoders, packet filtering and caching module, wireless receiving management module, and communication interface control module. Each receiving and demodulating module is respectively connected to the packet filtering and caching module through a decoder. The packet filtering and caching module is connected to the communication interface control module, and the wireless receiving management module is connected to the receiving and demodulating modules, decoders, packet filtering and caching module, and communication interface control module

[0019] As an improvement of the present invention, the wireless receiving chip further includes a first low-noise amplifier. The input end of the first low-noise amplifier is connected to the antenna pin of the wireless receiving chip, and the output end of the low-noise amplifier is connected to each receiving and demodulating module.

[0020] As an improvement of the present invention, the receiving and demodulating module includes: a first clock generation unit, a first quadrature mixer, a first band-pass filter, a first VGA amplifier, a first analog-to-digital converter, and a first digital down-conversion and demodulation unit. The first clock generation unit is connected to the first quadrature mixer and the first digital down-conversion and demodulation unit. The first quadrature mixer performs mixing processing on the amplified received signal to generate two orthogonal low intermediate frequency signals, which are respectively filtered by a first band-pass filter, amplified by a first VGA amplifier, and subjected to analog-to-digital conversion by a first analog-to-digital converter, and then sent to the first digital down-conversion and demodulation unit to generate a baseband signal by the first digital down-conversion and demodulation unit.

[0021] As an improvement of the present invention, the receiving and demodulating module includes: a second clock generation unit, a second low-noise amplifier, a second quadrature mixer, a second band-pass filter, a second VGA amplifier, a second analog-to-digital converter, and a second digital down-conversion and demodulation unit. The signal received by the antenna is amplified by the second low-noise amplifier and subjected to mixing processing by the second quadrature mixer to generate two orthogonal low intermediate frequency signals, which are respectively filtered by a second band-pass filter, amplified by a second VGA amplifier, and subjected to analog-to-digital conversion by a second analog-to-digital converter, and then sent to the second digital down-conversion and demodulation unit to generate a baseband signal by the second digital down-conversion and demodulation unit.

[0022] As an improvement of the present invention, the decoder connected to the broadcast channel receiving and demodulating module includes: a first clock management unit and a first packet header detection unit, a first address filtering unit, a first PDU data dewhitening unit, a first PDU data CRC check unit, a first PDU data cache management unit, and a first PDU data sending unit connected in sequence.

[0023] As an improvement of the present invention, the decoder connected to the extended broadcast packet receiving and demodulating module includes: a first configuration management unit, a second clock management unit and a second packet header detection unit, a second address filtering unit, a second PDU data dewhitening unit, a second PDU data CRC check unit, a second PDU data cache management unit, and a second PDU data sending unit connected in sequence.

[0024] As a further improvement of the present invention, the data packet filtering and caching module includes a duplicate data packet pre-filtering unit, a first data packet filtering unit with the same number as the receiving and demodulating modules, a second data packet filtering unit with the same number as the extended broadcast packet receiving and demodulating modules, a second configuration management unit, and a data packet management unit; the duplicate data packet pre-filtering unit is connected to each broadcast channel receiving and demodulating module, de-duplicates the data packets received by the three broadcast channel receiving and demodulating modules and then sends them to the first data packet filtering unit, which filters the data packets and sends them to the data packet management unit for caching; the second data packet filtering unit receives the data packets output by the extended broadcast packet receiving and demodulating module, filters them, and sends them to the data packet management unit for caching.

[0025] As a further improvement of the present invention, the wireless receiving management module includes a configuration register management unit, a configuration register, and a configuration value update management unit. The configuration register management unit is connected to the configuration value update management unit, and the configuration register is connected to the configuration register management unit and the configuration value update management unit.

[0026] As a further improvement of the present invention, the communication interface control module includes a communication interface selection management unit, a protocol parsing unit, an internal bus, a communication interface for the data packet management module, and a communication interface for the wireless management module. The communication interface selection management unit is connected to the protocol parsing unit, and the protocol parsing unit is connected to the communication interface for the data packet management module and the communication interface for the wireless management module through the internal bus.

[0027] The present invention also provides an application circuit of the wireless receiving chip, including an inductor, a crystal oscillator, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an antenna, and the wireless receiving chip according to any one of claims 1-9. The VDD pin of the wireless receiving chip is connected to the 3.3V power supply terminal and is also grounded through the first capacitor. The X1 pin of the wireless receiving chip is connected to one end of the crystal oscillator and is also grounded through the third capacitor. The X2 pin of the wireless receiving chip is connected to the other end of the crystal oscillator and is also grounded through the second capacitor. The ANT pin of the wireless receiving chip is sequentially connected to one end of the sixth capacitor and one end of the fifth capacitor through the inductor and the fourth capacitor. The other end of the sixth capacitor is connected to the antenna and is also grounded through the seventh capacitor.

[0028] Compared with the prior art, the wireless receiving chip capable of listening to Bluetooth broadcasts and its application circuit provided by the present invention work on 4 receiving channels through 4 independent receiving and demodulating modules. Each receiving and demodulating module can work independently without mutual influence, greatly improving the receiving efficiency and speed of broadcast packets and also increasing the anti-interference ability. Description of the Drawings

[0029] Figure 1Schematic diagram of the package structure of the wireless receiving chip capable of listening to Bluetooth broadcasts provided by the present invention.

[0030] Figure 2 Block diagram of the structure of the wireless receiving chip capable of listening to Bluetooth broadcasts provided by the first preferred embodiment of the present invention.

[0031] Figure 3 Block diagram of the structure of the receiving and demodulating module of the wireless receiving chip in the first preferred embodiment of the present invention.

[0032] Figure 4 Block diagram of the structure of the wireless receiving chip capable of listening to Bluetooth broadcasts provided by the second preferred embodiment of the present invention.

[0033] Figure 5 Block diagram of the structure of the receiving and demodulating module of the wireless receiving chip in the second preferred embodiment of the present invention.

[0034] Figure 6 Block diagram of the structure of the phase-locked loop frequency multiplier unit of the wireless receiving chip provided by the present invention.

[0035] Figure 7 Block diagram of the structure of the first decoder of the wireless receiving chip provided by the present invention.

[0036] Figure 8 Block diagram of the structure of the second decoder of the wireless receiving chip provided by the present invention.

[0037] Figure 9 Block diagram of the structure of the data packet filtering and caching module of the wireless receiving chip provided by the present invention.

[0038] Figure 10 Block diagram of the structure of the wireless receiving management module of the wireless receiving chip provided by the present invention.

[0039] Figure 11 Block diagram of the structure of the communication interface control module of the wireless receiving chip provided by the present invention.

[0040] Figure 12 Schematic diagram of the application circuit of the wireless receiving chip provided by the present invention.

[0041] Figure 13 Schematic diagram of the upper circuit of the application circuit of the wireless receiving chip provided by the present invention for remotely controlling a fan.

[0042] Explanation of the attached figure annotations:

[0043] Receiving and demodulating module 10, broadcast channel receiving and demodulating module 11, first clock generation unit 111, first quadrature mixer 112, first band-pass filter 113, first VGA amplifier 114, first analog-to-digital converter 115, first digital down-conversion and demodulation unit 116, extended broadcast packet receiving and demodulating module 12, second clock generation unit 121, second low-noise amplifier 122, second quadrature mixer 123, second band-pass filter 124, second VGA amplifier 125, second analog-to-digital converter 126, second digital down-conversion and demodulation unit 127, decoder 20, first clock management unit 211, first packet header detection unit 212, first address filtering unit 213, first PDU data dewhitening unit 214, first PDU data CRC check unit 215, first PDU data cache management unit 216, first PDU data sending unit 217, first configuration management unit 221, second clock management unit 222, second packet header detection unit 223, second address filtering unit 224, second PDU data dewhitening unit 225, second PDU data CRC check unit 226, second PDU data cache management unit 227, second PDU data sending unit 228, phase detector 1011, low-pass filter 1012, voltage-controlled oscillator 1013, frequency divider 1014, packet filtering and caching module 30, duplicate packet pre-filtering unit 311, first packet filtering unit 312, second packet filtering unit 313, second configuration management unit 314, packet management unit 315, wireless receiving management module 40, configuration register management unit 411, configuration register 412, configuration value update management unit 413, communication interface control module 50, communication interface selection management unit 511, protocol parsing unit 512, packet management module communication interface 513, wireless receiving management module communication interface 514, clock module 60, reference clock module 70, power management module 80, first low-noise amplifier 90, inductor L1, crystal oscillator Y1, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, fifth capacitor C5, sixth capacitor C6, seventh capacitor C7, antenna RF1, wireless receiving chip U1, main control chip U2, key module 1, indicator light module 2, motor drive module 3 Detailed implementation manners

[0044] The wireless receiving chip provided by the present invention that can monitor Bluetooth broadcasts can receive GFSK (Gaussian frequency shift keying modulation) signals with a frequency range from 2.400 to 2.4835 GHz, and receive broadcast packets through at least 4 independent receiving channels, improving the response speed of the broadcast packets.

[0045] Please refer to Figure 1 , the wireless receiving chip of the present invention is a 16-pin packaged wireless chip, and its pin controls are shown in Table 1:

[0046]

[0047]

[0048] Table 1

[0049] In order to more efficiently respond to BLE broadcast packets, the wireless receiving chip of the present invention sets at least 4 independent receiving and demodulating modules in the wireless receiving part, and each receiving and demodulating module can work independently without mutual influence.

[0050] Among them, 3 of the receiving and demodulating modules are respectively fixedly working on 3 Bluetooth main broadcast channels (channels 37, 38, and 39) to receive Bluetooth broadcast packets, so as to ensure that the 3 main broadcast channels can be monitored at the same time during operation, thereby improving the receiving efficiency and speed of broadcast packets, and at the same time enhancing the anti-interference ability. Because the probability that the 3 main broadcast channels are interfered at the same time is much lower than the probability that 1 of the broadcast channels is interfered [calculated according to a simple model, assuming that the probability that a single broadcast channel is interfered is 1 / x, then the probability that the three broadcast channels are interfered at the same time is 1 / (x 3 ), where x is a natural number greater than or equal to 1].

[0051] The remaining at least 1 receiving and demodulating module is used to support the reception of extended broadcast packets, and its working channel and PHY (physical layer) symbol rate can be set according to the information in the ADV_EXT_IND broadcast message received on the main broadcast channel.

[0052] The present invention can greatly improve the scanning hit rate of the broadcast packets transmitted on the Bluetooth main broadcast channel. Compared with the existing Bluetooth chips, it can better meet the usage scenarios with low latency requirements, especially in the usage scenarios where a Bluetooth connection does not need to be established but broadcast data needs to be frequently received.

[0053] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0054] Please refer to Figure 2, in the first preferred embodiment of the present invention, the wireless receiving chip includes: at least four receiving and demodulating modules 10, a decoder 20, a data packet filtering and caching module 30, a wireless receiving management module 40, a communication interface control module 50, a clock module 60, a reference clock module 70, and a power management module 80; the reference clock module 70 is connected to the X1 and X2 pins of the wireless receiving chip, the power management module 80 is connected to the VDD and GND pins of the wireless receiving chip, and the communication interface control module 50 is connected to the SCK / SCL pin, MISO / SDA / TXD pin, MOSI / RXD pin, CSN pin, CM1 pin, CM2 pin, CE pin, and IRQ pin of the wireless receiving chip.

[0055] Among them, three of the receiving and demodulating modules are broadcast channel receiving and demodulating modules 11, which respectively work on 3 broadcast channels of Bluetooth, and real-time monitor Bluetooth broadcast packets on the corresponding broadcast channels. The remaining receiving and demodulating module is an extended broadcast packet receiving and demodulating module 12, which receives extended broadcast packets.

[0056] Preferably, there are more than 2 extended broadcast packet receiving and demodulating modules 12, so that it can work on more channels and receive more Bluetooth data.

[0057] In this embodiment, the clock module 60 is connected to the reference clock module 70, the receiving and demodulating module (10), the decoder 20, the data packet filtering and caching module 30, the wireless receiving management module 40, and the communication interface control module 50. Each receiving and demodulating module is respectively connected to the data packet filtering and caching module 30 through a decoder 20. The data packet filtering and caching module 30 is connected to the communication interface control module 50, and the wireless receiving management module 40 is connected to the receiving and demodulating module, the decoder 20, the data packet filtering and caching module 30, and the communication interface control module 50.

[0058] Optionally, the wireless receiving chip of the present invention further includes a first low-noise amplifier 90. The input end of the first low-noise amplifier 90 is connected to the antenna pin of the wireless receiving chip, and the output end of the low-noise amplifier is connected to each receiving and demodulating module. The first low-noise amplifier 90 amplifies the radio frequency signal received from the antenna, that is, the wireless signal (which includes Bluetooth broadcast packets), and then sends it to the receiving and demodulating module as shown in Figure 2 the figure.

[0059] Please refer to Figure 3 , the receiving and demodulating module includes: a first clock generation unit 111, a first quadrature mixer 112, a first band-pass filter 113, a first VGA amplifier 114 (variable gain amplifier), a first analog-to-digital converter 115, and a first digital down-conversion and demodulation unit 116.

[0060] The first clock generation unit 111 is connected to the first quadrature mixer 112 and the first digital down-conversion and demodulation unit 116. The first quadrature mixer 112 mixes the amplified received signal to generate two orthogonal low intermediate frequency signals. After being filtered by a first band-pass filter 113, amplified by a first VGA amplifier 114, and subjected to analog-to-digital conversion by a first analog-to-digital converter 115 respectively, they are sent to the first digital down-conversion and demodulation unit 116, and the first digital down-conversion and demodulation unit 116 processes them to generate a baseband signal.

[0061] In the receiving and demodulating module, the radio frequency signal amplified by the low-noise amplifier is mixed by the first quadrature mixer 112 to generate two orthogonal low intermediate frequency signals. After being filtered by a first band-pass filter 113 respectively, they are amplified by a first VGA amplifier 114, converted into digital signals through an ADC, and then the first digital down-conversion and demodulation unit 116 performs processing such as digital mixing, digital filtering, and digital demodulation to generate a baseband signal, and outputs it to the decoder 20 in digital signal mode (i.e., DS signal).

[0062] Please refer to Figure 4 and Figure 5 In the wireless receiving chip provided by the second preferred embodiment of the present invention, the receiving and demodulating module includes: a second clock generation unit 121, a second low-noise amplifier 122, a second quadrature mixer 123, a second band-pass filter 124, a second VGA amplifier 125, a second analog-to-digital converter 126, and a second digital down-conversion and demodulation unit 127.

[0063] The signal received by the antenna is amplified by the second low-noise amplifier 122, and is mixed by the second quadrature mixer 123 to generate two orthogonal low intermediate frequency signals. After being filtered by a second band-pass filter 124, amplified by a second VGA amplifier 125, and subjected to analog-to-digital conversion by a second analog-to-digital converter 126 respectively, they are sent to the second digital down-conversion and demodulation unit 127 to process and generate a baseband signal.

[0064] In this second preferred embodiment, an independent low-noise amplifier is provided in each receiving and demodulating module. After the received radio frequency signal is amplified, quadrature mixing processing is performed.

[0065] The present invention can first amplify the radio frequency signal received by the antenna through the first preferred embodiment, and then be received by the receiving and demodulating modules of each channel, or can first receive the radio frequency signal by the receiving and demodulating modules of the channel and then be amplified and processed by the receiving and demodulating module through the second preferred embodiment.

[0066] Specifically, the clock generation unit (i.e., the first and second clock generation units) of the receiving and demodulating module includes a phase-locked loop frequency multiplication circuit, such as Figure 6As shown in the figure, it includes a phase discriminator 1011, a low-pass filter 1012, a voltage-controlled oscillator 1013, and a frequency divider 1014. The phase discriminator 1011 is connected to the output end of the frequency divider 1014 and is also connected to the voltage-controlled oscillator 1013 through the low-pass filter 1012. The input end of the frequency divider 1014 is connected to the output end of the voltage-controlled oscillator 1013 and the quadrature mixer.

[0067] Therefore, the clock used by the quadrature mixer for signal mixing is generated and provided by the PLL frequency multiplication circuit. The reference clock (CLK) of the PLL frequency multiplication circuit is provided by the reference clock module 70. The frequency divider 1014 adopts a fractional frequency divider 1014, and its parameters are configured by the wireless reception management module 40 according to the required working channels. The CLK_CFG of the reception and demodulation module is a configuration input signal, and this signal in each reception and demodulation channel corresponds to CHN CFG1-CHN CFG4 of the wireless reception management module 40.

[0068] The CLK input by the reception and demodulation module serves as the reference clock of the PLL frequency multiplication circuit. The wireless reception management module 40 calculates the parameters of the fractional frequency divider 1014 according to the channel values included in the configuration information sent by the CLK_CFG of the reception and demodulation module, and uses them to configure the fractional frequency divider 1014 in the PLL, so that it operates on the desired channel.

[0069] The fractional frequency divider 1014 is a mature existing technology. For the convenience of understanding the technical solution of the present invention, the fractional frequency divider 1014 is briefly introduced here. Taking the generation of a 2402 MHz clock using a 16 MHz reference clock as an example, 2402 / 16 = 150.125. The quotient is a decimal, indicating that a conventional integer frequency divider 1014 cannot meet the requirements. At this time, the fractional frequency divider 1014 is required. The fractional frequency divider 1014 divides by frequency x times according to the counting period a and divides by frequency y times according to the counting period b. These two processes constitute a complete frequency division, so that the total frequency division value can be (a*x + b*y) / (x + y); when a = 150, b = 151, x = 7, and y = 1, a frequency division of 150.125 can be achieved. This process can be realized through digital circuits, and there are many implementation methods. The specific implementation process will not be elaborated here.

[0070] After the baseband signal is obtained in the reception and demodulation module, the baseband signal (DS) enters the decoder 20. The decoder 20 is completely implemented by digital circuits. The decoder 20 decodes the received digital code stream according to the Bluetooth broadcast packet format to obtain a packet that meets the requirements and caches it, and then only extracts the PDU part and sends it out. For the packets received by the reception channels 1-3 (i.e., the three broadcast channel reception and demodulation modules 11), the following is adopted Figure 7The decoder 20 shown samples data at the bitstream rate of the main broadcast channel. For the data packets received by the receiving channel 4 (i.e., the extended broadcast packet receiving and demodulating module 12), the decoder 20 samples data at the bitstream rate configured externally. Figure 8 The decoder 20 shown samples data at the bitstream rate configured externally.

[0071] Please refer to Figure 7 , the decoder 20 (21) connected to the broadcast channel receiving and demodulating module 11 includes: a first clock management unit 211, and a first packet header detection unit 212, a first address filtering unit 213, a first PDU data de - whitening unit 214, a first PDU data CRC check unit 215, a first PDU data cache management unit 216, and a first PDU data sending unit 217 connected in sequence. The first clock management unit 211 is connected to the reference clock module 70 to keep the data synchronized.

[0072] Specifically, the decoder 20 (21) analyzes the data packets according to the Bluetooth broadcast packet format specified by the Bluetooth protocol link layer. Among them, the Bluetooth data packet consists of 4 parts: preamble, access address, PDU (protocol data unit), and CRC (Cyclic Redundancy Check). The specific format is shown in Table 2:

[0073]

[0074] Table 2

[0075] The preamble length of the Bluetooth broadcast data packet is 1 byte with a value of 0xAA, and the access address value is 0x8E89BED6 (transmitted in little - endian mode during communication, which is 0xD6, 0x8E, 0x89, 0x8E in bytes, a total of 4 bytes). The decoder 20 only processes the subsequent parts of the Bluetooth data packets that match these two parts, and discards the non - matching ones directly. It should be noted that the PDU part of the data packet has whitening processing during transmission, so the decoder 20 needs to perform de - whitening processing when receiving. After the processed data passes the CRC check, the data packet can flow into the next link.

[0076] The types of broadcast packets currently supported by BLE (Bluetooth) are shown in Table 3 below:

[0077]

[0078] Table 3

[0079] The decoder 20(21) for processing receive channels 1 to 3 is dedicated to processing broadcast packets from the main broadcast channels (channels 37, 38, 39), while the decoder 20 for receive channel 4 is dedicated to processing broadcast packets from the second broadcast channel (one of channels 0 to 36).

[0080] The decoder 20(22) for receive channel 4 samples data from the input data stream at the corresponding symbol rate according to the PHY (physical layer) type configured by the wireless reception management module 40; the other three receive channels sample data from the data stream according to the default symbol rate (1 Msym / s);

[0081] Among the broadcast packets transmitted on the main broadcast channels, only the ADV_EXT_IND type packets are extended broadcast packets, and the rest are traditional broadcast (Legcay ADV) packets. The data packets on the second broadcast channel are all extended broadcast (Extended ADV) packets; the lengths of the PDU parts of these two types of broadcast packets are different. The maximum length of the PDU of the traditional broadcast packet is 39, and the maximum length of the PDU of the extended broadcast packet is 257 bytes.

[0082] Since before the data is sent, when Bluetooth sends a broadcast packet, it enhances the anti-interference ability of Bluetooth data by adding white noise to the data contained in the PDU. This process is called whitening. Therefore, after the decoder 20(21) receives the data packet, it needs to perform anti-whitening processing on the data in the PDU. The anti-whitening process is the same as the whitening process; this process can be implemented according to the Bluetooth protocol, which is an existing technology and will not be elaborated here.

[0083] After anti-whitening, calculate its 24-bit CRC value according to the check generation polynomial x24 + x10 + x9 + x6 + x4 + x3 + x + 1, and compare it with the CRC value in the data packet. If the check is correct, send the obtained PDU data to the data packet filtering and caching module 30.

[0084] Please refer to Figure 8 , the decoder 20 connected to the extended broadcast packet reception and demodulation module 12 includes: a first configuration management unit 221, a second clock management unit 222, and a second packet header detection unit 223, a second address filtering unit 224, a second PDU data anti-whitening unit 225, a second PDU data CRC check unit 226, a second PDU data caching management unit 227, and a second PDU data sending unit 228 connected in sequence.

[0085] Compared with the above decoder 20, it adds a first configuration management unit 221, which is used to sample data from the input data stream at the corresponding symbol rate according to the PHY type configured by the wireless reception management module 40.

[0086] Please refer to Figure 9, the packet filtering and caching module 30 includes two functions: broadcast packet filtering and caching management, and includes a duplicate packet pre-filtering unit 311, a first packet filtering unit 312 with the same number as the receiving and demodulating modules, a second packet filtering unit 313 with the same number as the extended broadcast packet receiving and demodulating module 12, a second configuration management unit 314, and a packet management unit 315; the duplicate packet pre-filtering unit 311 is connected to each broadcast channel receiving and demodulating module 11, and after de-duplicating the packets received by the three broadcast channel receiving and demodulating modules 11, it sends them to the first packet filtering unit 312, and after being filtered by the first packet filtering unit 312, it is sent to the packet management unit 315 for caching; the second packet filtering unit 313 receives the packets output by the extended broadcast packet receiving and demodulating module 12, filters them, and sends them to the packet management unit 315 for caching.

[0087] The packet filtering and caching module 30 receives the PDU packets sent by the decoders 20 of several channels, filters the received packets according to the configuration values (including filtering rules) of the wireless reception management module 40, and caches the qualified packets into the packet queue. Since the maximum length of the PDU of the traditional broadcast packet is 39 and the maximum length of the PDU of the extended broadcast packet is 257, for the convenience of processing, each of the two types of broadcast packets uses an independent FIFO (First Input First Output, first-in first-out queue); when the extended broadcast packet reception is enabled in the configuration, when the receiving and demodulating modules of channels 1 to 3 receive the ADV_EXT_IND broadcast packet, they will extract the extended broadcast auxiliary channel information from it and send these configuration information to the wireless reception management module 40. The wireless reception management module 40 will set the frequency divider 1014 parameter of the mixer phase-locked loop of the receiving and demodulating module of channel 4 according to these configuration information (which can determine the working channel), and set the sampling code rate of the decoder 20 according to the configuration of channel 4.

[0088] When filtering and caching data, the packet filtering and caching module 30 simultaneously responds to the read operation of the signal interface control module, and sends out the required read packets, that is, completes the dequeue operation of the cached packets. When the wireless reception chip of the present invention has low-cost requirements, the packet filtering and caching module 30 can also discard the filtering function; when the packet interrupt function is enabled, the packet filtering and caching module 30 will also indicate this state through the DPS signal when there are unfinished packets in the buffer.

[0089] In a specific implementation, when filtering packets, the broadcast packets output by the 4-channel decoder 20 will all be filtered first, and then the qualified packets after filtering will be cached. The filtering process is as follows:

[0090] The data provided by the 1st to 3rd path decoders 20 is for the main broadcast channel. If the configuration in the wireless management module requires filtering out duplicate broadcast packets, then according to the configuration value, only the first identical broadcast packet within a time window is retained; if filtering is not required, all the data packets from these 3 channels will undergo the next stage of filtering.

[0091] If the data packets coming from the 1st to 3rd paths are ADV_EXT_IND broadcast packets, the auxiliary information used for further receiving extended broadcast packets is extracted and sent to the wireless reception management module 40. The wireless reception management module 40 uses it to configure the working channel of the 4th reception channel and the working mode of the PHY; if the reception period of the previous extended broadcast packet has not ended, then the most recent extended broadcast packet reception operation is discarded.

[0092] If the data packets coming from the 1st to 3rd paths are not ADV_EXT_IND broadcast packets, they are all filtered as traditional broadcast packets, while the data packets coming from the 4th path are all filtered as extended broadcast packets. The basic principle of filtering is to compare whether the data of a certain bit length at a specific position in the data packet matches the requirement. Multiple positions can be compared. If all match the requirement, then the broadcast packet is retained; otherwise, it is discarded. The implementation method in this example is as follows in the configuration register 412 part of the wireless reception management module 40. In this embodiment, although the 1st to 3rd paths use independent filters, the configuration values used are the same.

[0093] Furthermore, the data packet cache management method is as follows:

[0094] After filtering the broadcast data packets that meet the requirements, they are cached in the data packet management unit 315 in a queue manner. The data packet management unit 315 includes auxiliary packet information extraction, cache management, reading management, data cache queue 1, and data cache queue 2.

[0095] Since the maximum packet lengths of traditional broadcast packets and extended broadcast packets are different, two independent FIFOs (queues) are used to store the received broadcast data packets; when enqueuing, it can be decided according to the configuration value whether to add a timestamp to the data packet, that is, add a two-byte prefix to the data packet. The two bytes are respectively the high byte and the low byte of the system time count value in the module. The system time count value is in milliseconds as the counting unit; when enqueuing, it can be decided according to the configuration value whether to mark the channel source of the data packet, that is, add the channel number of the source of this broadcast packet in front of the data packet; for the received extended broadcast packets, it is necessary to compare according to the Bluetooth protocol whether they meet the reception timeliness, and only those that meet the requirements are enqueued; when there are data packets in any one of the queues, the output data packet status signal (such as Figure 9 the DPS signal in

[0096] The data packet management unit 315 also needs to respond to the read operation of the communication interface, and the main contents include: clearing the FIFO operation; reading the data packet (letting the data packet dequeue from the FIFO and returning it to the communication management interface module); reading the FIFO status (the status of the two FIFOs, whether they are full, whether they are empty, and the number of data packets in the queue).

[0097] Certainly, in a further embodiment, the data packet filtering and caching module 30 may also use less than two to improve the data caching processing speed.

[0098] Please refer to Figure 10 , the wireless reception management module 40 includes: a configuration register 412 management unit 411, a configuration register 412, and a configuration value update management unit 413. The configuration register 412 management unit 411 is connected to the configuration value update management unit 413, and the configuration register 412 is connected to the configuration register 412 management unit 411 and the configuration value update management unit 413. Four reception channels are configured through the wireless reception management module 40.

[0099] The wireless reception management module 40 can receive the read and write configuration operations of the communication interface control module 50 through CLK, DI, and DO, and can also receive the configuration information required for receiving the extended broadcast packet sent by the data packet filtering and caching module 30 through AUX CFG IN. All the configuration information is stored in the configuration register 412 in this module. When the configuration value in the configuration register 412 changes, the configuration value update management unit 413 will send the relevant configuration value to the relevant module. EXT ADV CFG is used to configure the decoder 20 used for channel 4, and CHN CFG1 to CHN CFG4 are used to configure the reception demodulation modules of channels 1 to 4 in sequence.

[0100] Specifically, the main function of the wireless reception management module 40 is to manage all the registers related to the wireless reception function, that is, to perform read and write operations on each configuration register 412, initialize the default values of each register when powered on, update the configuration register 412 according to the operations of the internal module and the communication interface, and respond to external operations to timely set the relevant values in the internal configuration register 412 to each reception demodulation module and the decoder 20; the main configuration registers 412 are as shown in Table 4 below:

[0101]

[0102]

[0103]

[0104]

[0105]

[0106] Table 4

[0107] For ease of understanding, the present invention further supplements the description of the data packet filtering function as follows:

[0108] If the filtering enable setting is 0, it is directly enqueued; if the filtering enable bit is 1, the specific filtering logic is as follows:

[0109] Let Val be a configuration register 412 in the digital circuit, with a length equal to the maximum byte length of each group of filtering values. In the above table, for FIFO1, the length of this value is 8 bytes, and for FIFO2, the length of this value is 16; each time the filtering operation is triggered, the digital circuit will execute the following logical process:

[0110] Val = PDU[FiltPos:(FiltPos + FiltLen)]

[0111] Val = Val xor FiltVal[FiltPos:(FiltPos + FiltLen)]

[0112] Val = Val and FiltMask[FiltPos:(FiltPos + FiltLen)]

[0113] If Val is 0, the data packet can be enqueued, otherwise it is discarded.

[0114] Note: FiltPos / FiltLen / FiltVal / FiltMask above can be FiltPos123 / FiltLen123 / FiltVal123 / FiltMask123 in the configuration register 412 table, or the corresponding FiltPos4 / FiltLen4 / FiltVal4 / FiltMask4.

[0115] The present invention can add multiple groups of filtering units according to actual needs, so that the data in the PDU can be filtered in segments. Only when the data packet meets the conditions of all enabled filtering units can the data packet be enqueued, otherwise it is discarded.

[0116] Please refer to Figure 11 , the communication interface control module 50 includes a communication interface selection and management unit 511, a protocol parsing unit 512, an internal bus, a communication interface 513 of the data packet management module, and a communication interface 514 of the wireless management module. The communication interface selection and management unit 511 is connected to the protocol parsing unit 512, and the protocol parsing unit 512 is connected to the communication interface 513 of the data packet management module and the communication interface 514 of the wireless management module through the internal bus.

[0117] The communication interface controller module selects the externally enabled communication interface according to external CM1 and CM2. The protocol parsing module therein parses the externally input communication data. According to the agreed protocol, it can be divided into 3 types of external operations, and then transfers them to different modules according to the operation type. For example, it transfers the data packet reading operation to the data filtering and cache management module, and transfers the read / write register operation to the wireless reception management module 40.

[0118] Specifically, the communication interface control module 50 communicates externally by selecting the corresponding communication method according to external pins CM1 and CM2. The supported communication interfaces include UART (default 115200bps), SPI, I 2 C; among them, both SPI and I 2 C work in the slave device mode, and each byte of communication is transmitted in the order from high bit to low bit.

[0119] How many operations does the present invention support?

[0120] Instruction Name Operation Description Write Register Write Configuration Register 412 Read Register Read Configuration Register 412 Read FIFO1 Read FIFO1 Read FIFO2 Read FIFO2 Clear FIFO1 Clear All Packets in FIFO1 Clear FIFO2 Clear All Packets in FIFO2 Clear All FIFOs Clear All Packets in All FIFOs

[0121] Table 5

[0122] The protocol implementations of UART, SPI, and I2C in the communication interface are all mature technologies and are not the focus of patents, so they will not be described in detail here.

[0123] The external master device [such as the MCU (microcontroller) communicating with this chip] can realize the writing and reading of internal registers through the communication interface management module; it can also realize the reading of data packets in the receive FIFO.

[0124] When the external master device reads and writes registers, the communication interface management module will communicate with the wireless reception management module 40 through the internal bus to convey the read / write operation, playing a bridging role; when the external master device operates the FIFO, the communication interface management module will communicate with the data packet reception filtering and caching module through the internal bus to convey the relevant operation, playing a bridging role.

[0125] Furthermore, the communication interface between the communication interface management module and the external processor can be adjusted according to the chip cost requirements. For example, reducing the supported interface types can reduce the chip cost, or adding several more interfaces to increase the communication compatibility of the chip.

[0126] Furthermore, the wireless reception chip of the present invention may further include one or more Bluetooth transmission modules, adding a wireless transmission function on the basis of the wireless reception function.

[0127] Based on the above wireless reception chip U1, the present invention also provides an application circuit of the wireless reception chip U1. Please refer toFigure 12 , the application circuit of the wireless receiving chip U1 includes an inductor L1, a crystal oscillator Y1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an antenna RF1 and the wireless receiving chip U1. The VDD pin of the wireless receiving chip U1 is connected to the 3.3V power supply terminal and is also grounded through the first capacitor C1. The X1 pin of the wireless receiving chip U1 is connected to one end of the crystal oscillator Y1 and is also grounded through the third capacitor C3. The X2 pin of the wireless receiving chip U1 is connected to the other end of the crystal oscillator Y1 and is also grounded through the second capacitor C2. The ANT pin of the wireless receiving chip U1 is sequentially connected to one end of the sixth capacitor C6 and one end of the fifth capacitor C5 through the inductor L1 and the fourth capacitor C4. The other end of the sixth capacitor C6 is connected to the antenna RF1 and is also grounded through the seventh capacitor C7.

[0128] The wireless receiving chip U1 makes the crystal oscillator Y1 generate a corresponding oscillation frequency according to the clock of the reference time module. After the antenna RF1 receives radio frequency information (including Bluetooth broadcast packets), it is input into the internal receiving and demodulating module through the ANT terminal, and then is output to an external controller (such as a single-chip microcomputer) through a decoder, filtering, and buffering by a communication interface.

[0129] Such as Figure 13 shown, it is an application of the wireless receiving chip U1 and its application circuit in a remote control fan. The remote control fan includes a main control chip U2, a button module 1, an indicator light module 2, and a motor drive module 3. The button module 1, the indicator light module 2, and the motor drive module 3 are connected to the IO ports of the main control chip U2. In this embodiment, the main control chip U2 uses a single-chip microcomputer of model OB38S08A1. The SCL / SCL pin, MISO / SDA / TXD pin, MOSI / RXD pin, CSN pin, IRO pin, and CE pin of the wireless receiving chip U1 are respectively connected to the P0.0 pin, P1.6 pin, P1.7 pin, P0.1 pin, P1.3 pin, and P1.5 pin of the single-chip microcomputer. For example, when the instruction in the Bluetooth data packet of the radio frequency signal received by the wireless receiving chip U1 is to turn on the fan, the P0.7 pin of the single-chip microcomputer outputs a high level to turn on the motor. Of course, the same operation can also be performed through the instruction received by the button module 1. The working mode of the remote control fan is a prior art and will not be described in detail here.

[0130] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0131] 1. The present invention is applicable to applications that only need to complete product functions by means of Bluetooth broadcast packets. And because the success rate of receiving broadcast packets is improved, the speed of scanning broadcast packets is faster, and higher-frequency broadcast information can be received;

[0132] 2. The present invention is only used to receive Bluetooth broadcast packets and no longer requires complex protocol processing functions, which can reduce costs for applications that only need to receive broadcast packets.

[0133] 3. The data packet filtering function built into the wireless receiving chip of the present invention can monitor data packets more efficiently.

[0134] 4. The wireless receiving chip of the present invention supports simultaneous monitoring of more than four channels at the same time, which can better adapt to complex electromagnetic wave environments.

[0135] It can be understood that for those of ordinary skill in the art, equivalent substitutions or changes can be made according to the technical solution and inventive concept of the present invention, and all such changes or substitutions should fall within the protection scope of the appended claims of the present invention.

Claims

1. A wireless receiving chip capable of listening to Bluetooth broadcasts, characterized in that, it includes: At least four receiving and demodulating modules, three of which are broadcast channel receiving and demodulating modules, each working on 3 Bluetooth broadcast channels to listen to Bluetooth broadcast packets on the corresponding broadcast channels in real time; the remaining receiving and demodulating module is an extended broadcast packet receiving and demodulating module for receiving extended broadcast packets; Decoders with the same number as the receiving and demodulating modules; Packet filtering and caching module; Wireless receiving management module; Communication interface control module; Clock module; The clock module is connected to the receiving and demodulating modules, decoders, packet filtering and caching module, wireless receiving management module and communication interface control module. Each receiving and demodulating module is respectively connected to the packet filtering and caching module through a decoder. The packet filtering and caching module is connected to the communication interface control module, and the wireless receiving management module is connected to the receiving and demodulating modules, decoders, packet filtering and caching module and communication interface control module; The packet filtering and caching module includes a duplicate packet pre-filtering unit, the first packet filtering units with the same number as the receiving and demodulating modules, the second packet filtering units with the same number as the extended broadcast packet receiving and demodulating modules, a second configuration management unit and a packet management unit; the duplicate packet pre-filtering unit is connected to each broadcast channel receiving and demodulating module, de-duplicates the packets received by the three broadcast channel receiving and demodulating modules and sends them to the first packet filtering units. After being filtered by the first packet filtering units, they are sent to the packet management unit for caching; The second packet filtering units receive the packets output by the extended broadcast packet receiving and demodulating modules, filter them and send them to the packet management unit for caching; During packet filtering, the broadcast data packets output from the 4-channel decoders are first filtered and then the filtered packets are cached. The filtering process is as follows: For the data on the main broadcast channels provided by the 1st to 3rd decoders, if the configuration in the wireless management module needs to filter out duplicate broadcast packets, then according to the configuration value, the first of the same broadcast packets within a time window is retained; if filtering is not required, the data packets on these 3 channels will all go through the next step of filtering; If the data packets coming from the 1st to 3rd channels are ADV_EXT_IND broadcast packets, the auxiliary information used for further receiving extended broadcast packets is extracted and sent to the wireless receiving management module, which uses it to configure the working channel of the 4th receiving channel and the working mode of the PHY; if the receiving cycle of the previous extended broadcast packet has not ended, then discard the most recent extended broadcast packet receiving operation; If the data packets coming from the 1st to 3rd channels are not ADV_EXT_IND broadcast packets, they will all be filtered according to traditional broadcast packets, while the data packets coming from the 4th channel will all be filtered in the extended broadcast packet manner. The basic principle of filtering is to compare whether the data of a certain bit length at a specific position in the data packet matches the requirement. If multiple positions are compared and all match the requirement, then the broadcast packet is retained, otherwise it is discarded.

2. The wireless receiving chip capable of listening to Bluetooth broadcasts according to claim 1, characterized in that, It further includes a first low-noise amplifier. The input end of the first low-noise amplifier is connected to the antenna pin of the wireless receiving chip, and the output end of the low-noise amplifier is connected to each receiving and demodulating module.

3. The wireless receiving chip capable of listening to Bluetooth broadcasts according to claim 2, wherein, the receiving and demodulating module includes: a first clock generation unit, a first quadrature mixer, a first band-pass filter, a first VGA amplifier, a first analog-to-digital converter, and a first digital down-conversion and demodulation unit. The first clock generation unit is connected to the first quadrature mixer and the first digital down-conversion and demodulation unit. The first quadrature mixer mixes and processes the amplified received signal to generate two orthogonal low intermediate frequency signals. After being filtered by a first band-pass filter, amplified by a first VGA amplifier, and subjected to analog-to-digital conversion by a first analog-to-digital converter respectively, they are sent to the first digital down-conversion and demodulation unit, and the first digital down-conversion and demodulation unit processes them to generate a baseband signal.

4. The wireless receiving chip capable of listening to Bluetooth broadcasts according to claim 1, wherein, the receiving and demodulating module includes: a second clock generation unit, a second low-noise amplifier, a second quadrature mixer, a second band-pass filter, a second VGA amplifier, a second analog-to-digital converter, and a second digital down-conversion and demodulation unit. The signal received by the antenna is amplified by the second low-noise amplifier, and is mixed and processed by the second quadrature mixer to generate two orthogonal low intermediate frequency signals. After being filtered by a second band-pass filter, amplified by a second VGA amplifier, and subjected to analog-to-digital conversion by a second analog-to-digital converter respectively, they are sent to the second digital down-conversion and demodulation unit to process and generate a baseband signal.

5. The wireless receiving chip capable of listening to Bluetooth broadcasts according to claim 1, wherein, the decoder connected to the broadcast channel receiving and demodulating module includes: a first clock management unit and a first packet header detection unit, a first address filtering unit, a first PDU data dewhitening unit, a first PDU data CRC check unit, a first PDU data cache management unit, and a first PDU data sending unit connected in sequence.

6. The wireless receiving chip capable of listening to Bluetooth broadcasts according to claim 1, wherein, the decoder connected to the extended broadcast packet receiving and demodulating module includes: a first configuration management unit, a second clock management unit and a second packet header detection unit, a second address filtering unit, a second PDU data dewhitening unit, a second PDU data CRC check unit, a second PDU data cache management unit, and a second PDU data sending unit connected in sequence.

7. The wireless receiving chip capable of listening to Bluetooth broadcasts according to claim 1, wherein, the wireless receiving management module includes: a configuration register management unit, a configuration register, and a configuration value update management unit. The configuration register management unit is connected to the configuration value update management unit, and the configuration register is connected to the configuration register management unit and the configuration value update management unit.

8. The wireless receiving chip capable of listening to Bluetooth broadcasts according to claim 1, wherein, The communication interface control module includes a communication interface selection and management unit, a protocol analysis unit, an internal bus, a communication interface of the data packet management module, and a communication interface of the wireless management module. The communication interface selection and management unit is connected to the protocol analysis unit, and the protocol analysis unit is connected to the communication interface of the data packet management module and the communication interface of the wireless management module through the internal bus.

9. An application circuit of a wireless receiving chip, characterized in that it includes an inductor, a crystal oscillator, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an antenna, and the wireless receiving chip according to any one of claims 1-8. The VDD pin of the wireless receiving chip is connected to a 3.3V power supply terminal and is also grounded through the first capacitor. The X1 pin of the wireless receiving chip is connected to one end of the crystal oscillator and is also grounded through the third capacitor. The X2 pin of the wireless receiving chip is connected to the other end of the crystal oscillator and is also grounded through the second capacitor. The ANT pin of the wireless receiving chip is sequentially connected to one end of the sixth capacitor and one end of the fifth capacitor through the inductor and the fourth capacitor. The other end of the sixth capacitor is connected to the antenna and is also grounded through the seventh capacitor.

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