Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate has a display area and a non-display area arranged adjacently, and comprises a substrate, a semiconductor layer located on the substrate, the semiconductor layer comprising a plurality of semiconductor portions arranged in an array in a first direction and a second direction, and an electrostatic protection portion having opposite connecting ends and free ends, the connecting ends being connected to at least one semiconductor portion, and the free ends extending from the connecting ends to the non-display area. The electrostatic protection portion can effectively improve the electrostatic protection performance of the array substrate.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are one of the hottest topics in display research today. Compared with liquid crystal displays (LCDs), OLED displays have advantages such as low energy consumption, low production cost, self-illumination, wide viewing angle and fast response speed. Currently, OLED array substrates have begun to replace traditional LCD array substrates in display fields such as mobile phones, PDAs, and digital cameras.

[0003] To enhance the human visual experience, display panels are now boasting increasingly higher resolutions, resulting in smaller pixels and higher integration. This increased integration means a decrease in the electrostatic discharge (ESD) resistance of components. Summary of the Invention

[0004] This application provides an array substrate, a display panel, and a display device that can improve the electrostatic discharge protection capability of the array substrate.

[0005] An embodiment of the first aspect of the present invention provides an array substrate having adjacent display areas and non-display areas. The array substrate includes: a substrate; a semiconductor layer located on the substrate, the semiconductor layer including a plurality of semiconductor portions arranged in an array in a first direction and a second direction; and an electrostatic discharge protection portion having opposing connection ends and free ends, the connection ends being connected to at least one semiconductor portion, and the free ends extending from the connection ends to the non-display areas.

[0006] According to an embodiment of the first aspect of the present invention, the method further includes: at least one peripheral connection line, the peripheral connection line being connected to two or more semiconductor portions, and the connection end of the electrostatic discharge (ESD) protection portion being connected to the peripheral connection line. Since the peripheral connection line allows connection to two or more semiconductor portions, and the ESD protection portion can be connected to two or more semiconductor portions via the peripheral connection line, the same ESD protection portion can provide ESD protection to two or more semiconductor portions, simplifying the wiring structure of the array substrate.

[0007] According to any of the foregoing embodiments of the first aspect of the present invention, a plurality of semiconductor units arranged along a second direction are interconnected, and peripheral connection lines are connected to any one of the plurality of semiconductor units arranged along the second direction, and the peripheral connection lines are connected to two or more semiconductor units arranged along a first direction. This enables the electrostatic discharge (ESD) protection unit to connect to two or more rows of semiconductor units arranged along the first direction via peripheral connection lines, and to provide ESD protection to the two or more rows of semiconductor units arranged along the first direction via peripheral connection lines, further simplifying the wiring structure of the array substrate.

[0008] According to any of the foregoing embodiments of the first aspect of the present invention, the method further includes: a plurality of pixel circuits located in the display area, each pixel circuit including at least one semiconductor portion; at least one peripheral connection line located on at least one side of the plurality of pixel circuits in a second direction, and the at least one peripheral connection line connected to the plurality of semiconductor portions distributed along the first direction. On at least one side of the plurality of pixel circuits in the second direction, the peripheral connection line connects to the plurality of semiconductor portions distributed along the first direction, and further connects to multiple columns of semiconductor portions distributed along the first direction.

[0009] According to any of the foregoing embodiments of the first aspect of the present invention, there are multiple electrostatic discharge (ESD) protection units, which are spaced apart along the extension direction of the peripheral connecting line. The ESD protection performance can be improved by using multiple ESD protection units.

[0010] According to any of the foregoing embodiments of the first aspect of the present invention, a plurality of electrostatic protection parts are evenly distributed in the extension direction of the peripheral connecting line to ensure the balance of electrostatic protection.

[0011] According to any of the foregoing embodiments of the first aspect of the present invention, the spacing between two adjacent electrostatic discharge (ESD) protection portions is greater than or equal to the spacing between two adjacent pixel circuits. A larger spacing between two adjacent ESD protection portions can mitigate the increased fabrication difficulty of the array substrate caused by excessively dense ESD protection portions.

[0012] According to any of the foregoing embodiments of the first aspect of the present invention, The peripheral connection lines are located on the semiconductor layer; The array substrate also includes an insulating layer located on the side of the semiconductor layer away from the substrate. The electrostatic discharge (ESD) protection section is located in the semiconductor layer, or it is located on the side of the insulating layer away from the semiconductor layer. The semiconductor layer includes the semiconductor portion, and the peripheral interconnects are located within the semiconductor layer. The semiconductor layer can include the peripheral interconnects, allowing them to be fabricated using the same layer, material, and process as the semiconductor portion. This improves the connection strength between the peripheral interconnects and the semiconductor portion, and also simplifies the fabrication process of the array substrate, increasing its fabrication efficiency.

[0013] According to any of the foregoing embodiments of the first aspect of the present invention, the electrostatic discharge protection part is located in the semiconductor layer, and a metal discharge part is provided in the insulating layer, with the metal discharge part and the free end connected to each other. This allows the free end to release static electricity through the metal discharge part, and since the static discharge part and the semiconductor part are not on the same layer, the electrostatic discharge effect can be improved.

[0014] According to any of the foregoing embodiments of the first aspect of the present invention, the array substrate further includes a planarization layer located on the side of the insulating layer opposite to the semiconductor layer, and the planarization layer covers the metal discharge portion. By providing the planarization layer, the unevenness of the array substrate surface caused by the provision of the metal discharge portion can be improved.

[0015] According to any of the foregoing embodiments of the first aspect of the present invention, the orthographic projection of the metal discharge portion on the substrate and the orthographic projection of the free end on the substrate overlap. This reduces the distance between the metal discharge portion and the free end, simplifying the structure of the array substrate.

[0016] According to any of the foregoing embodiments of the first aspect of the present invention, the electrostatic protection portion is located on the side of the insulating layer away from the semiconductor layer, and the array substrate further includes: A planarization layer is located on the side of the electrostatic protection layer away from the semiconductor layer; the electrostatic protection layer is located in the planarization layer. The insulating layer has interconnecting vias, and the electrostatic discharge (ESD) protection components are interconnected with the peripheral connecting lines via these vias. The ESD protection components and the semiconductor components are located on different layers, allowing static electricity on the semiconductor components to be released in other layers. This mitigates the impact of static electricity release on the semiconductor components, thereby improving the ESD protection performance of the array substrate.

[0017] A second aspect of the present invention also provides a display panel comprising the array substrate provided in any of the first aspect embodiments described above.

[0018] A third aspect of the present invention also provides a display device, including the display panel provided in the second aspect of the present invention.

[0019] According to the embodiment of this application, the array substrate has adjacent display areas and non-display areas. When the array substrate is used for a display panel, the display panel can realize display in the display area. The array substrate includes a substrate and a semiconductor layer. The semiconductor layer includes a plurality of semiconductor portions arranged in an array in a first direction and a second direction. The array substrate also includes an electrostatic discharge (ESD) protection portion. The connection end of the ESD protection portion is connected to at least one semiconductor portion, and the free end of the ESD protection portion extends to the non-display area. This allows the static electricity generated by the array substrate to be transferred through the semiconductor portion to the connection end, and then from the connection end to the free end located in the non-display area. Therefore, static electricity can be released through the free end in the non-display area, effectively improving the electrostatic effect of the array substrate and enhancing the ESD protection capability of the array substrate. Attached Figure Description

[0020] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0021] Figure 1 A top view schematic diagram of an array substrate provided in a first aspect embodiment of the present invention is shown; Figure 2 A cross-sectional schematic diagram of an array substrate provided in a first aspect embodiment of the present invention is shown; Figure 3 A cross-sectional schematic diagram of an array substrate provided in a first aspect embodiment of the present invention is shown; Figure 4 This diagram shows a layout schematic of the pixel circuit of the array substrate provided in a first aspect embodiment of the present invention; Figure 5 This diagram shows a layout schematic of the semiconductor portion of an array substrate provided in a first aspect embodiment of the present invention; Figure 6 This diagram shows a layout schematic of the semiconductor portion of an array substrate provided in another embodiment of the first aspect of the present invention; Figure 7 This diagram shows a layout schematic of the semiconductor portion of an array substrate provided in yet another embodiment of the first aspect of the present invention; Figure 8 This diagram shows a layout schematic of the semiconductor portion of an array substrate provided in another embodiment of the first aspect of the present invention; Figure 9 A cross-sectional schematic diagram of an array substrate provided in a first aspect embodiment of the present invention is shown; Figure 10 A cross-sectional schematic diagram of an array substrate provided in another embodiment of the first aspect of the present invention is shown; Figure 11 This illustration shows a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 12 This is a schematic diagram of the structure of a display device provided in one embodiment of this application. Detailed Implementation

[0022] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0023] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0024] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0025] This application provides an array substrate, a display panel, and a display device, which will be described below in conjunction with the accompanying drawings. Figure 1 To be continued Figure 12 The array substrate, display panel, and display device provided in the embodiments of this application will be described.

[0026] Please see Figure 1 , Figure 1 This diagram shows a top view of an array substrate provided in a first aspect embodiment of the present invention.

[0027] like Figure 1 As shown, the array substrate 100 provided in this embodiment includes a plurality of pixel circuits 10. The plurality of pixel circuits 10 can be arranged in an array. For example, the plurality of pixel circuits 10 can be arranged in an array along an intersecting first direction X and second direction Y. Exemplarily, the first direction X can be a row direction and the second direction Y can be a column direction. Of course, the first direction X can also be a column direction and the second direction Y can also be a row direction.

[0028] For example, the array substrate 100 may also include a driver chip IC, a first gate driver circuit VSR1, a second gate driver circuit VSR2, a power signal line PVDD, a common power signal terminal, a data signal line Vdata, a first reference signal line Vref1, scan signal lines S(n-1), Sn, S(n+1), and a light emission control signal line Emit.

[0029] The first gate drive circuit VSR1 may include multiple cascaded shift registers S-VSRs. Each shift register S-VSR is connected to the pixel circuit 10 via a scan signal line. The first gate drive circuit VSR1 is used to provide scan signals to the pixel circuit 10. The driver chip IC provides a first start signal STV1 to the first gate drive circuit VSR1. Additionally, as... Figure 1 As shown, among the multiple cascaded shift registers S-VSRs, except for the first and last stage shift registers S-VSRs, the remaining shift registers S-VSRs can provide scan signals for two adjacent rows of pixel circuits 10. At this time, two rows of dummy pixel circuits can be set on the array substrate. Figure 1 (not shown in the image) are connected to the scan lines of the first and last stages of the S-VSR shift register, respectively, but the dummy pixel circuit is not used for display.

[0030] The second gate drive circuit VSR2 may include multiple cascaded shift registers E-VSR. Each shift register E-VSR is connected to the pixel circuit 10 via the light emission control signal line Emit. The second gate drive circuit VSR2 is used to provide light emission control signals to the pixel circuit 10. The driver chip IC provides a second start signal STV2 to the second gate drive circuit VSR2.

[0031] In addition, clock signal lines (not shown in the figure), high-level signal lines (VGH) (not shown in the figure), and low-level signal lines (VGL) (not shown in the figure) can be connected between the first gate drive circuit VSR1 and the driver chip IC, and between the second gate drive circuit VSR2 and the driver chip IC. The driver chip IC provides clock signals, high-level signals, and low-level signals to the first gate drive circuit VSR1 and the second gate drive circuit VSR2.

[0032] For example, such as Figure 1 As shown, the array substrate 100 may include a first gate driving circuit VSR1 and a second gate driving circuit VSR2. The first gate driving circuit VSR1 and the second gate driving circuit VSR2 may be disposed on opposite sides of the array substrate 100 in the second direction Y, or the first gate driving circuit VSR1 and the second gate driving circuit VSR2 may be disposed on the same side.

[0033] For example, the array substrate 100 may also include two first gate driving circuits VSR1 and two second gate driving circuits VSR2, with each end of the scan signal line electrically connected to a first gate driving circuit VSR1 and each end of the light emission control signal line Emit electrically connected to a second gate driving circuit VSR2.

[0034] For example, the array substrate 100 includes two first gate driving circuits VSR1, one of which is electrically connected to the pixel circuit 10 of the odd-numbered rows via a scan signal line, and the other is electrically connected to the pixel circuit 10 of the even-numbered rows via a scan signal line.

[0035] For example, the array substrate 100 includes two second gate driving circuits VSR2, one of which is electrically connected to the pixel circuit 10 of the odd-numbered rows via a light emission control signal line, and the other is electrically connected to the pixel circuit 10 of the even-numbered rows via a light emission control signal line.

[0036] The above description of the first gate drive circuit VSR1 and the second gate drive circuit VSR2 are merely examples and are not intended to limit this application.

[0037] For example, a gate drive circuit capable of simultaneously generating scanning signals and light emission control signals may also be provided. This application does not limit this.

[0038] For example, the pixel circuit 10 includes a storage capacitor Cst and a plurality of transistors, such as a power writing transistor, a data writing transistor, a driving transistor, a compensation transistor, a gate initialization transistor, a light-emitting control transistor, and an anode initialization transistor.

[0039] The first scan signal line can be understood as the scan signal line connected to the control terminal of the gate initialization transistor in the pixel circuit 10, and the second scan signal line can be understood as the scan signal line connected to the control terminals of the data write transistor, the compensation transistor, and the anode initialization transistor in the pixel circuit 10. Generally, each row of pixel circuits 10 used for display is connected to at least the first scan signal line and the second scan signal line.

[0040] For example, such as Figure 1 As shown, in two adjacent rows of pixel circuits 10, the upper row of pixel circuits 10 is connected to scan signal lines S(n-1) and Sn, and the lower row of pixel circuits 10 is connected to scan signal lines Sn and S(n+1). For the upper row of pixel circuits 10, its corresponding first scan signal line is S(n-1), and its corresponding second scan signal line is Sn; for the lower row of pixel circuits 10, its corresponding first scan signal line is Sn, and its corresponding second scan signal line is S(n+1).

[0041] The power signal line PVDD is used to provide power voltage to the driving transistors, and the voltage on PVDD can be positive. The voltage on the common power signal terminal PVEE can be negative. The first reference signal line Vref1 is used to provide a reset voltage signal, and the voltage on Vref1 can be negative.

[0042] To better understand the overall structure of the array substrate provided in the embodiments, please refer to... Figure 2 and Figure 3 . Figure 2 A cross-sectional schematic diagram of an array substrate provided in a first aspect embodiment of the present invention is shown; Figure 3 A cross-sectional schematic diagram of an array substrate provided in a first aspect embodiment of the present invention is shown.

[0043] like Figure 2 and Figure 3 As shown, the array substrate may include a display area AA and a non-display area NA disposed adjacent to each other. For example, the array substrate includes a substrate 01 and a driving circuit layer 02 disposed on one side of the substrate 01. Figure 2 The diagram also shows a planarization layer PLN, a pixel definition layer PDL, light-emitting elements (including an anode RE, an organic light-emitting layer OM, and a cathode SE), support pillars PS, a thin-film encapsulation layer (including a first inorganic layer CVD1, an organic layer IJP, and a second inorganic layer CVD2), an optical adhesive layer OCA, and a cover plate CG. Additionally, Figure 2 The first gate drive circuit VSR1, the first barrier bank Bank1, and the second barrier bank Bank2 are also shown. The first gate drive circuit VSR1 can be disposed in the non-display area NA of the drive circuit layer 02.

[0044] The pixel circuit 10 can be disposed within the driving circuit layer 02, and the pixel circuit 10 is connected to the anode RE of the light-emitting element. For example... Figure 3 As shown, the driving circuit layer 02 of the array substrate may include a gate metal layer M1, a capacitor metal layer MC, and a source / drain metal layer M2 stacked in the direction away from the substrate 01. A semiconductor layer b is disposed between the gate metal layer M1 and the substrate 01. Insulating layers are disposed between each metal layer and between the semiconductor layer b and the gate metal layer M1. For example, a gate insulating layer GI is disposed between the gate metal layer M1 and the semiconductor layer b, a capacitor insulating layer IMD is disposed between the capacitor metal layer MC and the gate metal layer M1, and an interlayer dielectric layer ILD is disposed between the source / drain metal layer M2 and the capacitor metal layer MC.

[0045] Semiconductor layer b is the semiconductor layer containing the active layer of the transistor, gate metal layer M1 is the metal conductive layer containing the gate of the transistor, capacitor metal layer MC is the metal conductive layer containing one of the plates of the capacitor, and source and drain metal layer M2 is the metal conductive layer containing the source and drain of the transistor.

[0046] For example, scan signal lines S(n-1), Sn, S(n+1) and the light emission control signal line Emit can be disposed on the gate metal layer M1. The first reference signal line Vref1 can be disposed on the capacitor metal layer MC, and the power signal line PVDD and the data signal line Vdata can be disposed on the source and drain metal layers M2. Of course, the film layers where each signal line is located can also be disposed in other ways, and this application does not limit this. It is understood that... Figure 2 and Figure 3 The diagram also schematically shows other film layers above the array substrate, for reference only.

[0047] The applicant discovered that each transistor in the pixel circuit 10 includes a semiconductor portion located in a semiconductor layer, and the semiconductor portions of multiple transistors in the same pixel circuit are typically interconnected. The fabrication process of the semiconductor portion includes high-temperature processes, such as annealing and activation processes. Static electricity generated during these high-temperature processes can have an irreversible impact on the performance of the semiconductor portion, thereby affecting the performance of the corresponding transistor.

[0048] Please see Figure 4 The diagram shows a layout schematic of the pixel circuit 10 of the array substrate 100 provided in the first aspect embodiment of the present invention.

[0049] like Figure 4 As shown, an embodiment of the first aspect of the present invention provides an array substrate 100 having adjacently disposed display areas AA and non-display areas NA. The array substrate 100 includes: a substrate 01 and a semiconductor layer b disposed on the substrate 01 and an electrostatic discharge protection portion 20. The semiconductor layer b is disposed on the substrate 01 and includes a plurality of semiconductor portions 11 arranged in an array in a first direction and a second direction. Each electrostatic discharge protection portion 20 has an opposing connection end 21 and a free end 22. The connection end 21 is connected to at least one semiconductor portion 11, and the free end 22 extends from the connection end 21 to the non-display area NA.

[0050] According to the array substrate 100 provided in the embodiments of this application, the array substrate 100 has a display area AA and a non-display area NA. When the array substrate 100 is used for a display panel, the display panel can realize display in the display area AA. The array substrate 100 includes an electrostatic discharge (ESD) protection part 20. The connection end 21 of the ESD protection part 20 is connected to at least one semiconductor part 11, and the free end 22 of the ESD protection part 20 extends to the non-display area NA. This allows the static electricity generated by the array substrate to be transmitted through the semiconductor part 11 to the connection end 21, and then from the connection end 21 to the free end 22 located in the non-display area NA. Therefore, static electricity can be released in the non-display area NA through the free end 22, effectively improving the electrostatic effect of the array substrate 100 and enhancing the ESD protection capability of the array substrate 100.

[0051] Furthermore, in the array substrate 100 provided in this embodiment of the invention, the electrostatic discharge (ESD) protection unit 20 can be considered as an antenna connected to the semiconductor unit 11. Through the discharge principle of the antenna tip (i.e., the free end 22 of the ESD protection unit 20), the static electricity generated during the manufacturing process of the array substrate 100 is released to the non-display area NA via the antenna (i.e., the ESD protection unit 20), eliminating the accumulation of static electricity throughout the array substrate 100. This effectively prevents potential damage to the array substrate 100 caused by static electricity.

[0052] It is understood that the array substrate 100 also includes a plurality of pixel circuits 10, which are located in the display area AA. The pixel circuits 10 are used to drive the display panel to display. The plurality of pixel circuits 10 are arranged in an array in the first direction and the second direction. Each pixel circuit 10 includes at least one semiconductor part 11.

[0053] There are various ways to set the electrostatic discharge protection unit 20. For example, the electrostatic discharge protection unit 20 and the pixel circuit 10 are set in a one-to-one correspondence. The semiconductor part 11 of each pixel circuit 10 is connected to the electrostatic discharge protection unit 20 to improve the electrostatic discharge protection capability of the array substrate 100.

[0054] Please see Figure 5 , Figure 5 This is a schematic layout diagram of the semiconductor section 11 of an array substrate 100 provided in a first aspect embodiment of the present invention.

[0055] like Figure 5 As shown, in some alternative embodiments, the array substrate 100 further includes: at least one peripheral connection line 30, the peripheral connection line 30 being connected to two or more semiconductor sections 11, and the connection end 21 of the electrostatic discharge protection section 20 being connected to the peripheral connection line 30.

[0056] In these alternative embodiments, two or more semiconductor units 11 can be connected via peripheral connection lines 30, and two or more semiconductor units 11 can be connected via peripheral connection lines 30, so that the same electrostatic protection unit 20 can provide electrostatic protection to two or more semiconductor units 11, simplifying the wiring structure of the array substrate 100.

[0057] Please see Figure 6 The diagram shows a schematic layout of the semiconductor portion 11 of an array substrate 100 provided in another embodiment of the first aspect of the present invention.

[0058] like Figure 6 As shown, in some optional embodiments, a plurality of semiconductor units 11 arranged along the second direction are interconnected, and a peripheral connection line 30 is connected to any one of the plurality of semiconductor units 11 arranged along the second direction, and the peripheral connection line 30 is connected to two or more semiconductor units 11 arranged along the first direction.

[0059] In these optional embodiments, the first direction is the row direction and the second direction is the column direction. Semiconductor units 11 in the same column are interconnected, and the peripheral connection line 30 can connect multiple semiconductor units 11 in the same column by connecting any one of the semiconductor units 11 in that column. When the peripheral connection line 30 is connected to two or more semiconductor units 11 arranged along the first direction, the peripheral connection line 30 can connect two or more columns of semiconductor units 11 through the two or more semiconductor units 11 arranged along the first direction. This allows the electrostatic discharge (ESD) protection unit 20 to connect two or more columns of semiconductor units 11 through the peripheral connection line 30 and provide ESD protection to the two or more columns of semiconductor units 11 through the peripheral connection line 30, further simplifying the wiring structure of the array substrate 100.

[0060] In other embodiments, optionally, the semiconductor portions 11 arranged along the first direction are interconnected, the peripheral connection line 30 is connected to any one of the plurality of semiconductor portions 11 arranged along the first direction, and the peripheral connection line 30 is connected to two or more semiconductor portions 11 arranged along the second direction.

[0061] In these optional embodiments, since the semiconductor units 11 in the same row are interconnected, the peripheral connection line 30 can connect multiple semiconductor units 11 in the same row by connecting any one of the semiconductor units 11 in that row. When the peripheral connection line 30 is connected to two or more semiconductor units 11 arranged along the second direction, the peripheral connection line 30 can connect two or more rows of semiconductor units 11 through these two or more semiconductor units 11 arranged along the second direction. This allows the electrostatic discharge protection unit 20 to connect two or more rows of semiconductor units 11 through the peripheral connection line 30 and provide electrostatic discharge protection to the two or more rows of semiconductor units 11 through the peripheral connection line 30, further simplifying the wiring structure of the array substrate 100.

[0062] Please refer to the following: Figure 7 and Figure 8 , Figure 7 This illustrates another connection method between the peripheral connection line 30 and the semiconductor section 11. Figure 8 Another connection method between the peripheral connection line 30 and the semiconductor section 11 is shown.

[0063] There are various ways to arrange the peripheral connection lines 30. To simplify the wiring structure of the array substrate 100, at least one peripheral connection line 30 is located on at least one side of the plurality of pixel circuits 10 in the second direction, that is, the peripheral connection line 30 is located on at least one side of the column direction of the plurality of pixel circuits 10. For example Figure 6 and Figure 7 As shown, the semiconductor portions 11 of the plurality of pixel circuits 10 arranged along the second direction are interconnected, and the peripheral connection lines 30 are located on the lower side of the plurality of pixel circuits 10 in the second direction. Figure 8As shown, the semiconductor sections 11 of a plurality of pixel circuits 10 arranged along the second direction are interconnected, and the peripheral connection line 30 is located on the upper side of the plurality of pixel circuits 10 in the second direction. The peripheral connection line 30 can connect multiple rows of semiconductor sections 11 on the same side by connecting multiple semiconductor sections 11, which can simplify the routing path of the peripheral connection line 30 and reduce the length of the peripheral connection line 30.

[0064] Understandable Figures 6 to 8 Only one peripheral connection line 30 is shown as an example. In other embodiments, the array substrate may include two or more peripheral connection lines 30. This arrangement can effectively improve the electrostatic protection performance of the array substrate.

[0065] At least one side of the plurality of pixel circuits 10 in the second direction, a peripheral connection line 30 connects to a plurality of semiconductor portions 11 distributed along the first direction, and further connects to multiple rows of semiconductor portions 11. Optionally, the peripheral connection line 30 is located on one side of the pixel circuit 10 in the second direction and connects to all adjacent semiconductor portions 11 arranged along the second direction, so that the peripheral connection line 30 can connect to all semiconductor portions 11, and the electrostatic discharge protection unit 20 can provide electrostatic discharge protection to all semiconductor portions 11 through the peripheral connection line 30.

[0066] Optionally, when the edge of the display area AA is irregular, and the pixel circuit 10 is distributed along the irregular path near the edge of the display area AA, the peripheral connection line 30 can extend along the irregular path, as long as the peripheral connection line 30 is located on at least one side of the plurality of pixel circuits 10 in the second direction.

[0067] There are several ways to configure the number of electrostatic discharge (ESD) protection units 20. For example, there can be only one ESD protection unit 20, connected to the outer connecting line 30. Alternatively, one ESD protection unit 20 can be connected to the middle of the outer connecting line 30 to ensure balanced ESD protection.

[0068] In some alternative embodiments, there are multiple electrostatic discharge (ESD) protection units 20, which are spaced apart along the extension direction of the peripheral connecting line 30. The ESD protection performance can be improved by using multiple ESD protection units 20.

[0069] Optionally, the plurality of electrostatic protection parts 20 are evenly distributed in the extension direction of the peripheral connecting line 30 to ensure the balance of electrostatic protection.

[0070] Optionally, with the first direction X as the row direction and the second direction Y as the column direction, when the number of pixel circuits 10 in two adjacent rows is different, that is, when the number of semiconductor units 11 in two adjacent rows is different, the peripheral connection line 30 extends along a bending path and surrounds multiple pixel circuits 10. The peripheral connection line 30 includes a first segment extending along the first direction and a second segment extending along the second direction, and the electrostatic discharge (ESD) protection unit 20 can be connected to the first segment and / or the second segment. For example, the ESD protection unit 20 is connected to the second segment and extends along the first direction. Optionally, multiple ESD protection units 20 are connected to the same second segment and spaced apart along the second direction. Alternatively, multiple ESD protection units 20 are connected to the first segment and extend along the second direction. Optionally, multiple ESD protection units 20 are connected to the same first segment and spaced apart along the first direction.

[0071] Optionally, the spacing between two adjacent electrostatic discharge (ESD) shielding portions 20 is greater than or equal to the spacing between two adjacent pixel circuits 10. For example, the spacing between two adjacent ESD shielding portions 20 is greater than or equal to the spacing between two adjacent pixel circuits 10 in a first direction, or the spacing between two adjacent ESD shielding portions 20 is greater than or equal to the spacing between two adjacent pixel circuits 10 in a second direction. A larger spacing between two adjacent ESD shielding portions 20 can mitigate the increased fabrication difficulty of the array substrate 100 caused by excessively dense ESD shielding portions 20.

[0072] Please see Figure 9 , Figure 9 This is a cross-sectional schematic diagram of an array substrate 100 provided in a first aspect embodiment of the present invention.

[0073] like Figure 9 As shown, in some optional embodiments, semiconductor layer b includes semiconductor portion 11, and peripheral connection line 30 is located in semiconductor layer b; array substrate 100 also includes insulating layer 03, which is located on the side of semiconductor layer b opposite to substrate 01.

[0074] It is understood that the peripheral connection line 30 is located in the semiconductor layer b, that is, the peripheral connection line 30 can be disposed in the same layer as the semiconductor layer b, or the semiconductor layer b includes the peripheral connection line 30.

[0075] In these optional embodiments, the semiconductor layer b may include peripheral interconnects 30, such that the peripheral interconnects 30 and the semiconductor portion 11 can be fabricated using the same layer, material, and process. This improves the connection strength between the peripheral interconnects 30 and the semiconductor portion 11, and also simplifies the fabrication process of the array substrate 100, thereby increasing the fabrication efficiency of the array substrate 100.

[0076] Optionally, a buffer layer 05 is also provided on the substrate 01.

[0077] There are various ways to configure the insulating layer 03. Optionally, the array substrate 100 also includes a metal layer located on the side of the semiconductor layer b facing away from the substrate 01. An insulating layer 03 is disposed between the semiconductor layer b and the metal layer. Typically, there are two or more metal layers, and an insulating layer 03 is disposed between each of the two or more metal layers. Therefore, the number of insulating layers 03 is two or more, meaning that there are two or more insulating layers 03 disposed on the side of the semiconductor layer b facing away from the substrate 01. It is understood that the insulating layer 03 may include a gate insulating layer, a capacitor insulating layer, or an interlayer dielectric layer, etc., and the specific configuration can be determined according to the actual situation; no specific limitations are made here.

[0078] There are several ways to install the electrostatic discharge protection unit 20, such as... Figure 9 As shown, in some optional embodiments, the static protection portion 20 is located in the semiconductor layer b. For example, the semiconductor layer b may include the electrostatic protection portion 20, and the electrostatic protection portion 20, the peripheral connection line 30, and the semiconductor portion 11 are located in the same layer structure. On the one hand, this can improve the connection strength between the peripheral connection line 30 and the semiconductor portion 11, and the connection strength between the electrostatic protection portion 20 and the peripheral connection line 30. On the other hand, it can also enable the electrostatic protection portion 20, the peripheral connection line 30, and the semiconductor portion 11 to be fabricated in the same process, further simplifying the fabrication process of the array substrate 100 and improving the fabrication efficiency of the array substrate 100.

[0079] It is understandable that the static protection part 20 being located in the semiconductor layer b means that the semiconductor layer b may include the electrostatic protection part 20 or the static protection part 20 being disposed in the same layer as the semiconductor layer b.

[0080] When the electrostatic discharge protection section 20 is located in the semiconductor layer b, optionally, a metal discharge section 40 is provided in the insulating layer 03, and the metal discharge section 40 and the free end 22 are interconnected. In these optional embodiments, the free end 22 is connected to the metal discharge section 40, so that the free end 22 can release static electricity through the metal discharge section 40. Since the static electricity release and the semiconductor section 11 are not on the same layer, the electrostatic discharge protection effect can be improved.

[0081] Optionally, the orthographic projection of the metal discharge section 40 on the substrate 01 and the orthographic projection of the free end 22 on the substrate 01 overlap. This reduces the distance between the metal discharge section 40 and the free end 22, simplifying the structure of the array substrate 100.

[0082] There are various ways to set the metal discharge section 40. In some optional embodiments, a through hole is provided on the insulating layer 03, the free end 22 is exposed through the through hole, and a metal material is provided in the through hole to form the metal discharge section 40.

[0083] In some optional embodiments, the array substrate 100 further includes a planarization layer 04 located on the side of the insulating layer 03 opposite to the semiconductor layer b, and the planarization layer 04 covers the metal discharge portion 40. In these optional embodiments, the planarization layer 04 can improve the unevenness of the surface of the array substrate 100 caused by the metal discharge portion 40.

[0084] Please see Figure 10 , Figure 10 This diagram shows a cross-sectional schematic of an array substrate 100 provided in another embodiment of the first aspect of the present invention.

[0085] like Figure 10 As shown, in some alternative embodiments, the electrostatic discharge protection part 20 is disposed on the side of the insulating layer 03 away from the semiconductor layer b. The array substrate 100 further includes: a planarization layer 04, which is located on the side of the electrostatic discharge protection part 20 away from the semiconductor layer b, and the electrostatic discharge protection part 20 is located on the planarization layer 04; a connection via is provided on the insulating layer 03, and the electrostatic discharge protection part 20 is interconnected with the peripheral connection line 30 through the connection via.

[0086] In these alternative embodiments, the electrostatic discharge protection section 20, the peripheral connection line 30, and the semiconductor section 11 are disposed on different layers, so that the static electricity on the semiconductor section 11 can be released on other layers, thereby improving the impact of static electricity release on the semiconductor section 11 and improving the electrostatic discharge protection performance of the array substrate 100.

[0087] It should be noted that the above embodiments can be combined with each other without contradiction.

[0088] This application provides another display panel, including an array substrate as described in any of the above embodiments. Figure 11 This diagram illustrates the structure of a display panel according to one embodiment of this application. Figure 11 As shown, the display panel 200 includes the array substrate 100 described in any of the above embodiments and a light-emitting layer 201 located on the array substrate 100. For example, the light-emitting layer 201 can be an organic light-emitting layer, that is, the display panel 200 can be an organic light-emitting diode (OLED) display panel. Of course, the display panel can also be other types of display panels, and this application does not limit this.

[0089] This application also provides a display device, including the array substrate provided in this application. Please refer to... Figure 12 , Figure 12 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 12 The provided display device 1000 includes the array substrate 100 provided in any of the above embodiments of this application. Figure 10This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and vehicle-mounted display devices. This application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the array substrate provided in this application embodiment. For details, please refer to the specific descriptions of the array substrate in the above embodiments. These descriptions will not be repeated here.

[0090] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, the array substrate having adjacent display areas and non-display areas, characterized in that, The array substrate includes: Substrate; A semiconductor layer is located on the substrate, and the semiconductor layer includes a plurality of semiconductor portions arranged in an array in a first direction and a second direction; An electrostatic discharge protection section has opposing connecting ends and free ends, the connecting ends being connected to at least one of the semiconductor sections, and the free ends extending from the connecting ends to the non-display area so that static electricity is transferred from the connecting ends to the free ends and released in the non-display area; A peripheral connection line is located in the semiconductor layer. The peripheral connection line includes a first segment extending along the first direction and a second segment extending along the second direction. The electrostatic protection part is connected to the first segment and / or the second segment. An insulating layer is located on the side of the semiconductor layer opposite to the substrate, and the electrostatic discharge protection portion is located on the semiconductor layer, or the electrostatic discharge protection portion is located on the side of the insulating layer opposite to the semiconductor layer; The electrostatic discharge protection unit is a plurality of such units, which are spaced apart. At least one peripheral connection line is connected to two or more of the semiconductor units, and the connection end of the electrostatic discharge protection unit is connected to the peripheral connection line.

2. The array substrate according to claim 1, characterized in that, The plurality of semiconductor portions arranged along the second direction are interconnected, and the peripheral connection line is connected to any one of the plurality of semiconductor portions arranged along the second direction, and the peripheral connection line is connected to two or more semiconductor portions arranged along the first direction.

3. The array substrate according to claim 2, characterized in that, Also includes: Multiple pixel circuits are located in the display area, and each pixel circuit includes at least one semiconductor unit; At least one of the peripheral connection lines is located on at least one side of the plurality of pixel circuits in the second direction, and at least one of the peripheral connection lines is connected to the plurality of semiconductor portions distributed along the first direction.

4. The array substrate according to claim 3, characterized in that, Multiple electrostatic protection components are spaced apart along the extension direction of the peripheral connecting line.

5. The array substrate according to claim 4, characterized in that, The multiple electrostatic protection components are evenly distributed along the extension direction of the peripheral connection line.

6. The array substrate according to claim 4, characterized in that, The spacing between two adjacent electrostatic protection parts is greater than or equal to the spacing between two adjacent pixel circuits.

7. The array substrate according to claim 1, characterized in that, The electrostatic protection part is located in the semiconductor layer, and a metal discharge part is provided in the insulating layer. The metal discharge part and the free end are connected to each other.

8. The array substrate according to claim 7, characterized in that, The array substrate further includes a planarization layer located on the side of the insulating layer away from the semiconductor layer, and the planarization layer covers the metal discharge portion.

9. The array substrate according to claim 7, characterized in that, The orthographic projection of the metal discharge section on the substrate and the orthographic projection of the free end on the substrate overlap.

10. The array substrate according to claim 1, characterized in that, The electrostatic discharge protection section is located on the side of the insulating layer away from the semiconductor layer, and the array substrate further includes: A planarization layer is located on the side of the electrostatic discharge protection portion away from the semiconductor layer, and the electrostatic discharge protection portion is located in the planarization layer; The insulating layer is provided with a connection via, and the electrostatic protection part is connected to the peripheral connection line through the connection via.

11. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 10.

12. A display device, characterized in that, Includes the display panel as described in claim 11.

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