Neural network hardware acceleration scheduling algorithm based on directed graph representation

By using a hardware acceleration scheduling algorithm for neural networks based on directed graph representation, the deployment challenge of complex network architectures in neural network accelerators is solved, achieving unified expression of temporal dependencies and efficient resource utilization, thereby improving computational and energy efficiency.

CN115687236BActive Publication Date: 2026-04-28FUDAN UNIVERSITY
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Patent Information

Application Number
CN202110850933.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-07-27
Publication Date
2026-04-28
Estimated Expiration
2041-07-27

AI Technical Summary

Technical Problem

Existing neural network accelerators face unpredictable and irregular connectivity issues when deploying complex network architectures, especially lacking a unified expression in time-dependent modules, and having low on-chip cache resource utilization efficiency, resulting in low energy efficiency.

Method used

A hardware-accelerated scheduling algorithm based on directed graph representation is adopted. By using graph theory modeling, operators are treated as nodes and dependencies as edges to construct a directed graph. The algorithm searches the graph computation path to reduce data transmission and dynamically allocates on-chip cache resources to optimize the computation order and cache utilization.

Benefits of technology

It achieves a unified representation of various neural networks and efficient resource utilization, improving the accelerator's computational and energy efficiency while reducing latency and power consumption.

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Abstract

The application provides a neural network hardware acceleration scheduling algorithm based on a directed graph representation, a target neural network is modeled based on graph theory to obtain a directed graph representation of the neural network, and further based on the directed graph, a graph calculation path search algorithm can be used to minimize data transfer between a calculation module and an on-chip storage module; moreover, based on the graph calculation path and the dependency of the directed graph, non-dependent results of the on-chip cache can be dynamically released, that is, the on-chip cache resources can be dynamically allocated, thereby greatly improving the utilization efficiency of the on-chip cache, so that more data processing can be performed in batches. The combination of the two can improve the universality of the neural network accelerator, improve the calculation efficiency, and reduce the power consumption and delay of the accelerator hardware.
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