A split-gate trench MOSFET

Abstract

The application discloses a kind of semiconductor device technical field, specifically for a kind of split gate trench MOSFET, including device cell unit, the device cell unit includes first conductive type substrate and first conductive type drift region on first conductive type substrate, second conductive type well region is equipped in the upper portion of first conductive type drift region, first conductive type drift region is opened with dielectric slot and gate precipitate slot communicated with dielectric slot, and dielectric slot is filled with high-K oxide, the gate precipitate slot is filled with precipitate gate metal gate, oxide layer one coated on precipitate gate metal gate, precipitate gate silicon carbide coated on oxide layer, silicon carbide is used as the abutment between high-K oxide and precipitate gate metal gate in the application, silicon carbide can ensure the thermal stability of itself and silicon, to prevent the interaction between existing precipitate gate metal gate and high-k gate oxide layer from influencing threshold, to improve the performance of nanometer size MOSFET.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a gate trench MOSFET. Background Technology

[0002] Separated-gate trench MOSFETs utilize the charge coupling principle of oxide layers, breaking the theoretical silicon limit of traditional trench power MOSFETs. This allows the N-type drift region to achieve a high breakdown voltage even under high doping concentrations, resulting in low on-resistance and excellent switching characteristics. They are gradually replacing traditional trench devices. Most existing trench MOSFETs use polysilicon instead of metal as their gate material. With technological advancements, high-k dielectric materials are becoming the inevitable choice to replace conventional silicon dioxide (SiO2) in order to overcome the problems of gate leakage current and reduce MOSFET feature size. However, high-k dielectric materials and polysilicon gates form bonds, resulting in the "Fermi pinning phenomenon," meaning the threshold voltage cannot be adjusted by polysilicon doping. Simultaneously, the electron mobility of the device decreases due to dipole molecular vibrations. Therefore, the HKMG process is used to solve the compatibility problem between high-k dielectrics and polysilicon gates. Using filler metal to form the metal gate may unintentionally increase the transistor's threshold voltage. Furthermore, the inhomogeneity of the metal gate leads to changes in device performance.

[0003] Application content

[0004] The purpose of this application is to provide a trench MOSFET to solve the problems mentioned in the background art, such as the increase in the threshold voltage of the transistor and the performance changes caused by the non-uniformity of the metal gate.

[0005] To achieve the above objectives, this application provides the following technical solution: a trench MOSFET, comprising a device cell unit, the device cell unit comprising a first conductivity type substrate and a first conductivity type drift region located on the first conductivity type substrate, a second conductivity type well region provided above the first conductivity type drift region, a dielectric trench and a gate deposition trench communicating with the dielectric trench are formed in the first conductivity type drift region, and the dielectric trench is filled with a high-k oxide, the gate deposition trench is filled with a deposited gate metal gate, an oxide layer I covering the deposited gate metal gate, and a deposited gate silicon carbide covering the oxide layer I;

[0006] The deposited gate silicon carbide is located between the high-k oxide and the deposited gate metal gate.

[0007] Preferably, the second conductivity type well region is provided with a first conductivity type source region, and L-shaped grooves are provided on both sides of the top of the first conductivity type drift region. P-type buried layers are provided on the L-shaped grooves, the second conductivity type well region, and the first conductivity type source region.

[0008] Preferably, a drain metal is disposed on the lower surface of the first conductivity type substrate, and the drain metal is in ohmic contact with the first conductivity type substrate.

[0009] Preferably, for an N-type MOSFET device structure, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type MOSFET device structure, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.

[0010] Preferably, an oxide layer two is provided between the inner wall of the gate deposition tank and the deposited gate silicon carbide, and an oxide layer three is also provided between the deposited gate silicon carbide and the high-k oxide.

[0011] Preferably, the second conductivity type well region is adjacent to the gate deposition tank.

[0012] Preferably, the depth of the dielectric tank is greater than the depth of the gate deposition tank.

[0013] Preferably, the gate deposition tank is covered with source metal, and the extension end of the source metal extending into the upper part of the gate deposition tank is in contact with the source region of the first conductivity type.

[0014] Compared with the prior art, the beneficial effects of this application are:

[0015] 1) Compared with the prior art, this application uses silicon carbide as the neighbor between the high-k oxide and the deposited gate metal gate. Silicon carbide can ensure its own and silicon's thermal stability. In order to prevent the interaction between the existing deposited gate metal gate and the high-k gate oxide layer from affecting the threshold, the performance of the nanoscale MOSFET is improved.

[0016] 2) This application can further alleviate the electric field concentration below the drain terminal and reduce the device's sensitivity to charge imbalance. At the same time, in the drift region near the source terminal, this structure also utilizes the auxiliary depletion and electric field modulation effect of the high-k dielectric in the drift region, optimizing the trade-off between breakdown voltage and specific on-resistance, further alleviating the substrate-assisted depletion effect at the drain terminal, reducing the device's sensitivity to charge imbalance, and ensuring the device's breakdown voltage.

[0017] 3) This application also employs trench formation by etching at the source, and introduces an N-type encapsulation region with a higher doping concentration than the drift region to encapsulate the gate oxide side and the P+ gate oxide protection region, thereby reducing the depletion region area of ​​the P+ gate oxide protection region and compensating for the increased characteristic on-resistance caused by the P+ buried layer. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of this application;

[0019] Figure 2 This is a schematic diagram of the first conductivity type drift region and L-shaped groove etching structure of this application;

[0020] Figure 3 This is a schematic diagram of the gate deposition trench etching and filling of the deposited gate silicon carbide structure in this application;

[0021] Figure 4 This is a schematic diagram of the second conductivity type well region structure formed by secondary epitaxy in this application;

[0022] Figure 5 This is a schematic diagram of the source region structure of the first conductivity type formed by three epitaxial phases in this application;

[0023] Figure 6 This is a schematic diagram of the etching structure of the deposited gate silicon carbide, the source region of the first conductivity type, and the well region of the second conductivity type in this application;

[0024] Figure 7 This is a schematic diagram of the oxide layer growth structure in this application;

[0025] Figure 8 This is a schematic diagram of the gate metal deposition structure of this application;

[0026] Figure 9 This is a schematic diagram of the source metal structure of this application.

[0027] In the figure: 1 first conductivity type drift region, 2 first conductivity type substrate, 3 drain metal, 4 high K oxide, 5 dielectric trench, 6 precipitated gate silicon carbide, 7 oxide layer, 8 precipitated gate metal gate, 9 second conductivity type well region, 10 first conductivity type source region, 11 source metal. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Example

[0030] Please see Figures 1-9 This application provides a technical solution: a trench MOSFET, comprising a device cell unit, wherein the device cell unit includes a first conductivity type substrate 2 and a first conductivity type drift region 1 located on the first conductivity type substrate 2, a second conductivity type well region 9 is provided above the first conductivity type drift region 1, a dielectric trench 5 and a gate deposition trench communicating with the dielectric trench 5 are formed in the first conductivity type drift region 1, and the dielectric trench 5 is filled with a high-k oxide 4, the gate deposition trench is filled with a deposited gate metal gate 8, an oxide layer 7 covering the deposited gate metal gate 8, and a deposited gate silicon carbide 6 covering the oxide layer 7, using silicon carbide as the adjoint between the high-k oxide and the deposited gate metal gate, silicon carbide can ensure its own and silicon's thermal stability, in order to prevent existing deposited gate metal The interaction between the gate and the high-k gate oxide layer affects the threshold voltage, thereby improving the performance of nanoscale MOSFETs. In trench-structured silicon carbide power crystals, due to their high gate threshold voltage, the thickness of the epitaxial layer of silicon carbide power crystals is about 1 / 10 of that of silicon material under the same withstand voltage conditions, even with the high critical electric field strength of silicon carbide. As a result, the on-state resistance can be effectively reduced. An oxide layer 2 is provided between the inner wall of the gate deposition trench and the deposited gate silicon carbide 6, and an oxide layer 3 is also provided between the deposited gate silicon carbide 6 and the high-k oxide 4. The second conductivity type well region 9 is adjacent to the gate deposition trench. The gate deposition trench is covered with source metal 11, and the extension end of the source metal 11 extending into the upper part of the gate deposition trench is in contact with the first conductivity type source region 10.

[0031] The second conductivity type well region 9 is provided with a first conductivity type source region 10, and L-shaped grooves are formed on both sides of the top of the first conductivity type drift region 1. P-type buried layers 12 are provided on the L-shaped grooves, the second conductivity type well region 9, and the first conductivity type source region 10. The P-type buried layer 12 is adjacent to the source metal. The trench is formed by etching at the source. By introducing an N-type wrapping region with a higher doping concentration than the drift region, the gate oxide side and the P+ gate oxide protection zone are wrapped, reducing the depletion region area of ​​the P+ gate oxide protection zone. This compensates for the increased characteristic on-resistance caused by the P+ buried layer, which can further alleviate the electric field concentration below the drain and weaken the charge imbalance sensitivity of the device. Meanwhile, in the drift region near the source end, the structure also utilizes the auxiliary depletion and electric field modulation effect of the high-k dielectric to optimize the trade-off between breakdown voltage and specific on-resistance, further alleviate the substrate-assisted depletion effect at the drain end, weaken the device's sensitivity to charge imbalance, and ensure the device's breakdown voltage. The drain metal 3 is disposed on the lower surface of the first conductivity type substrate 2, and the drain metal 3 is in ohmic contact with the first conductivity type substrate 2. The depth of the dielectric trench 5 is greater than the depth of the gate deposition trench.

[0032] For an N-type MOSFET device structure, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type MOSFET device structure, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.

[0033] Manufacturing process as follows Figures 2-9 As shown, the specific steps are as follows: (1) Thin the top silicon layer to the required thickness and etch the dielectric trench. Use anisotropic reactive ion etching to etch to the substrate, and etch the L-shaped trench to form the source trench; (2) Fill the dielectric trench with high K oxide and etch the gate precipitate trench; (3) Perform secondary epitaxy to form the second conductivity type well region; (4) Perform tertiary epitaxy to form the first conductivity type source region; (5) Etch the precipitated gate silicon carbide, the first conductivity type source region, and the second conductivity type well region to form the gate trench; (6) Use thermal oxidation technology to grow the gate oxide layer; (7) Deposit the gate metal gate; (8) Etch the precipitated gate metal gate to fabricate the source and drain electrodes.

[0034] The foregoing has shown and described the basic principles, main features, and advantages of this application. It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or basic characteristics of this application. Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects. The scope of this application is defined by the appended claims rather than the foregoing description. Therefore, it is intended to encompass all variations falling within the meaning and scope of equivalents of the claims within this application, and no reference numerals in the claims should be regarded as limiting the scope of the claims.

[0035] Although embodiments of this application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A trench MOSFET, comprising a device cell unit, the device cell unit comprising a first conductivity type substrate (2) and a first conductivity type drift region (1) located on the first conductivity type substrate (2), wherein a second conductivity type well region (9) is provided above the first conductivity type drift region (1), characterized in that: The first conductivity type drift region (1) is provided with a dielectric trench (5) and a gate deposition trench connected to the dielectric trench (5), and the dielectric trench (5) is filled with high K oxide (4). The gate deposition trench is filled with a deposited gate metal gate (8), an oxide layer (7) covering the deposited gate metal gate (8), and a deposited gate silicon carbide (6) covering the oxide layer (7). The deposited gate silicon carbide (6) is located between the high-K oxide (4) and the deposited gate metal gate (8).

2. The trench MOSFET according to claim 1, characterized in that: The second conductivity type well region (9) is provided with a first conductivity type source region (10), and L-shaped grooves are provided on both sides of the top of the first conductivity type drift region (1). P-type buried layers (12) are provided on the L-shaped grooves, the second conductivity type well region (9), and the first conductivity type source region (10).

3. A trench MOSFET according to claim 1, characterized in that: A drain metal (3) is disposed on the lower surface of the first conductivity type substrate (2), and the drain metal (3) is in ohmic contact with the first conductivity type substrate (2).

4. A trench MOSFET according to claim 1, characterized in that: For an N-type MOSFET device structure, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type MOSFET device structure, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.

5. A trench MOSFET according to claim 1, characterized in that: An oxide layer two is provided between the inner wall of the gate deposition tank and the deposited gate silicon carbide (6), and an oxide layer three is also provided between the deposited gate silicon carbide (6) and the high-K oxide (4).

6. A trench MOSFET according to claim 1, characterized in that: The second conductivity type well region (9) is adjacent to the gate deposition tank.

7. A trench MOSFET according to claim 1, characterized in that: The depth of the dielectric trench (5) is greater than the depth of the gate deposition trench.

8. A trench MOSFET according to claim 1, characterized in that: The gate deposition tank is covered with source metal (11), and the extension end of the source metal (11) extending into the upper part of the gate deposition tank contacts the source region (10) of the first conductivity type.

Images