Physical unclonable function generation apparatus and system

Abstract

The application provides a physical unclonable function generating device and system, wherein the device comprises: a first multi-feedback ring oscillator for oscillating based on an external excitation signal; a first asynchronous counter for collecting a first average oscillation frequency of the first multi-feedback ring oscillator; a second multi-feedback ring oscillator for oscillating based on the external excitation signal; a second asynchronous counter for collecting a second average oscillation frequency of the second multi-feedback ring oscillator; and a comparator for generating a response of the physical unclonable function based on the first average oscillation frequency and the second average oscillation frequency. The device utilizes the multi-feedback structure of the first multi-feedback ring oscillator and the second multi-feedback ring oscillator to introduce strong nonlinearity in the circuit, thereby increasing the nonlinearity component in the PUF design, improving the resistance to machine learning, and enhancing the randomness of the PUF.

Description

Technical Field

[0001] This invention relates to the field of semiconductor security technology, and in particular to a device and system for generating physically unclonable functions. Background Technology

[0002] A Physically Unclonable Function (PUF) is a hardware function implementation circuit that relies on chip characteristics. It is unique and random, and achieves the function function that uniquely corresponds to the excitation signal and the response signal by extracting the process parameter deviations that are inevitably introduced during chip manufacturing.

[0003] However, PUFs face algorithmic and physical security threats in practical applications, such as machine learning attacks and side-channel attacks. Deep neural networks (DNNs), logistic regression (LR), support vector machines (SVMs), and covariance matrix adaptive evolutionary strategy (CMA-ES) are four commonly used machine learning attack methods for attacking PUFs. Mathematical non-cloning is an important security property of PUFs, but most existing PUF designs lack mathematical non-cloning, meaning they lack resistance to machine learning attacks.

[0004] In simple terms, the stimulus-response pairs of the PUF can be trained using machine learning to obtain a deep learning model. The trained deep learning model can predict the stimulus-response pairs of the PUF, thereby reducing the randomness of the PUF. Summary of the Invention

[0005] In view of the above problems, the present invention provides a physically unclonable function generation apparatus and system to improve resistance to machine learning, thereby enhancing the randomness of PUF.

[0006] A first aspect of the present invention provides a physically unclonable function generation apparatus, the apparatus comprising: a first multi-feedback ring oscillator, the input of which is connected to an external excitation signal for oscillating based on the excitation signal; a first asynchronous counter, the input of which is connected to the output of the first multi-feedback ring oscillator for acquiring a first average oscillation frequency of the first multi-feedback ring oscillator; a second multi-feedback ring oscillator, the input of which is connected to the external excitation signal for oscillating based on the excitation signal; a second asynchronous counter, the input of which is connected to the output of the second multi-feedback ring oscillator for acquiring a second average oscillation frequency of the second multi-feedback ring oscillator; and a comparator, the first input of which is connected to the output of the first asynchronous counter and the second asynchronous counter for generating a physically unclonable function response based on the first average oscillation frequency and the second average oscillation frequency.

[0007] According to an embodiment of the present invention, both the first asynchronous counter and the second asynchronous counter include multiple cascaded T flip-flops; when the first output value of the last stage T flip-flop of the first asynchronous counter or the second output value of the last stage T flip-flop of the second asynchronous counter reaches a preset threshold, the comparator controls the first asynchronous counter and the second asynchronous counter to stop counting.

[0008] According to an embodiment of the present invention, the comparator includes: a delay unit for generating a delay after the first asynchronous counter and the second asynchronous counter stop counting; and a first D flip-flop for generating a response of the physically unclonable function based on the first output value and the second output value after a preset delay.

[0009] According to one embodiment of the present invention, the T flip-flop includes: a clock input port, an enable input port, an output port, and an inverting output port; the inverting output port of the previous stage T flip-flop is connected to the clock input port of the next stage T flip-flop; wherein, the clock input port of the first stage T flip-flop of the first asynchronous counter is connected to the output of the first multi-feedback ring oscillator, and the clock input port of the first stage T flip-flop of the second asynchronous counter is connected to the output of the second multi-feedback ring oscillator.

[0010] According to an embodiment of the present invention, the enable input terminals of the first stage T flip-flops of the first asynchronous counter and the second asynchronous counter are connected to the enable output terminal of the comparator; wherein, the enable output terminal is used to generate a signal to stop the first stage T flip-flop from being enabled when the first output value or the second output value reaches a preset threshold.

[0011] According to an embodiment of the present invention, both the first multi-feedback ring oscillator and the second multi-feedback ring oscillator are Galois ring oscillators or Fibonacci ring oscillators.

[0012] According to an embodiment of the present invention, the Galois ring oscillator includes 67 inverters and 66 feedback taps; the excitation signal includes 66 excitation bits, each corresponding to one of the 66 feedback taps.

[0013] According to an embodiment of the present invention, the device further includes: a first filter disposed within the first multi-feedback ring oscillator; and a second filter disposed within the second multi-feedback ring oscillator; the first filter and the second filter are used to reduce the switching speed of the oscillation signals of the first multi-feedback ring oscillator and the second multi-feedback ring oscillator by limiting the switching conditions, and to filter out oscillation signals in the first multi-feedback ring oscillator and the second multi-feedback ring oscillator that are greater than a frequency threshold; wherein the frequency threshold is less than the maximum input frequency of the first asynchronous counter and the second asynchronous counter.

[0014] According to an embodiment of the present invention, the first filter and the second filter include: an encoder for setting the set condition and reset condition of the filter; and a second D flip-flop for controlling the hold and toggling of the output of the filter.

[0015] A second aspect of the present invention provides a physically unclonable function generation system, the physically unclonable function generation system comprising an excitation signal generation device and a physically unclonable function generation device as described in any of the first aspects; wherein, the first multi-feedback ring oscillator and the second multi-feedback ring oscillator of the physically unclonable function generation device are both connected to the excitation signal.

[0016] The above-described technical solutions employed in the embodiments of the present invention can achieve the following beneficial effects:

[0017] The present invention provides a device and system for generating physically unclonable functions (PUFs). The device for generating PUFs adds a first multi-feedback ring oscillator and a second multi-feedback ring oscillator. Since the multi-feedback structure of the multi-feedback ring oscillator can introduce strong nonlinearity into the circuit, it increases the nonlinear component in the PUF design, which can improve the resistance to machine learning and thus enhance the randomness of the PUF. Attached Figure Description

[0018] To gain a more complete understanding of the invention and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, wherein:

[0019] Figure 1 The schematic diagram illustrates a structural schematic of a physically unclonable function generation device provided in an embodiment of the present invention;

[0020] Figure 2 The schematic diagram illustrates an overall structural schematic of an MF-PUF provided in an embodiment of the present invention;

[0021] Figure 3 The schematic diagram illustrates the structure of an asynchronous counter and comparator provided in an embodiment of the present invention;

[0022] Figure 4 This schematic diagram illustrates a signal waveform corresponding to a first-stage TFF provided in an embodiment of the present invention.

[0023] Figure 5 The schematic diagram illustrates a ring oscillator including a filter according to an embodiment of the present invention.

[0024] Figure 6 The diagram illustrates a signal waveform corresponding to a filter provided in an embodiment of the present invention.

[0025] Figure 7 This schematic diagram illustrates one implementation of the set and reset conditions of a filter according to an embodiment of the present invention.

[0026] Figure 8 The illustration shows a schematic diagram of a Hamming distance before and after a change in connection, provided by an embodiment of the present invention.

[0027] Figure 9 The schematic diagram illustrates the structure of a physically unclonable function generation system provided by an embodiment of the present invention. Detailed Implementation

[0028] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0030] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0031] Currently, deep learning models can be trained on the stimulus-response pairs of a PUF using machine learning. These trained models can predict the stimulus-response pairs of the PUF, thus reducing its randomness. Therefore, most existing PUF designs lack mathematical non-cloning property, meaning they lack resistance to machine learning attacks.

[0032] First, let's introduce the descriptive metrics for PUF: uniformity, reliability, uniqueness, and SAC (strict avalanche criterion) are four common metrics used to evaluate PUF designs, and their meanings are as follows:

[0033] 1. Uniformity: Describes how evenly the proportion of "1"s and "0"s is distributed across all responses to different stimuli. A PUF with poor uniformity or large deviations has low safety. Uniformity can be measured by the Hamming weights across all responses, with an ideal value of 50%.

[0034] 2. Reliability: Reflects the stability of the response when the same stimulus is applied to the same PUF instance, and can be measured by the bit error rate (BER). The BER can be obtained by evaluating the same PUF instance multiple times and calculating the average Hamming distance (HD), with an ideal value of 0. In practical applications, a BER of no more than 5% can be reduced using error-correcting codes to achieve high reliability.

[0035] 3. Uniqueness: Describes the differences between different PUF instances under the same stimulus. The same stimulus set is applied to multiple PUF instances, and the corresponding response sets are collected. The average Hamming distance between the response sets is calculated to represent uniqueness. The ideal uniqueness value is 50%.

[0036] 4. SAC: Reflects the randomness in a security design and is used to evaluate the impact of each stimulus bit on the response. The SAC property is obtained by calculating the probability that a stimulus bit flip will cause the output response to flip. According to the SAC requirement, when a stimulus bit flips, the output should flip with a probability close to 50%. The greater the deviation between the actual SAC value and the ideal value of 50%, the easier it is for an attacker to predict the response.

[0037] Based on this, the present invention provides a physically unclonable function generation device and system, proposing a novel time-delay-based strong PUF. This PUF utilizes the time delay difference between two symmetrical multi-feedback ring oscillators to generate a response, and selects an asynchronous counter of appropriate series to measure the average oscillation frequency of the multi-feedback ring oscillators to achieve the highest possible reliability within an acceptable evaluation time. Furthermore, this PUF improves upon the original chaotic ring oscillator by designing a digital filter, giving the PUF good uniformity.

[0038] To facilitate understanding of this embodiment, a physical non-cloning function generation device disclosed in this embodiment of the invention will first be described in detail.

[0039] Example 1:

[0040] See Figure 1 The apparatus shown is a device for generating physically unclonable functions, comprising: a first multi-feedback ring oscillator, a second multi-feedback ring oscillator, a first asynchronous counter, a second asynchronous counter, and a comparator.

[0041] The system comprises two multi-feedback ring oscillators, one with inputs connected to an external excitation signal for oscillation based on that signal. A first asynchronous counter has its input connected to the output of the first multi-feedback ring oscillator for acquiring its first average oscillation frequency. A second asynchronous counter has its input connected to the output of the second multi-feedback ring oscillator for acquiring its second average oscillation frequency. A comparator, with its first input connected to the output of the first asynchronous counter and its second input connected to the output of the second asynchronous counter, generates a physically non-cloning function response based on the first and second average oscillation frequencies. The excitation signal is used to select the feedback polynomial.

[0042] The present invention provides a physically unclonable function (PUF) generation device, which adds a first multi-feedback ring oscillator and a second multi-feedback ring oscillator. Since the multi-feedback structure of the multi-feedback ring oscillator can introduce strong nonlinearity into the circuit, it increases the nonlinear component in the PUF design, which can improve the resistance to machine learning and thus enhance the randomness of the PUF.

[0043] Optionally, the first and second multi-feedback ring oscillators can be the same type of multi-feedback ring oscillator, such as GARO (Galois ring oscillator) or FIRO (Fibonacci ring oscillator).

[0044] Example 2:

[0045] This embodiment provides another device for generating physically unclonable functions. The device in this embodiment employs an MF-PUF (Multiple Feedback Ring Oscillator PUF) design. MF-PUF is a novel ROPUF (Ring Oscillator PUF) design that can be constructed based on a chaotic ring oscillator. The complex feedback operations in the chaotic ring oscillator can increase the nonlinearity in the PUF, thereby improving its resistance to machine learning attacks.

[0046] In this embodiment, the MF-PUF is a delay-based strong PUF that utilizes the time difference between two identical multi-feedback ring oscillators to generate a response. The MF-PUF has a differential structure consisting of two identical multi-feedback ring oscillators, two identical asynchronous counters, and a comparator. The two multi-feedback ring oscillators oscillate under the same excitation control. The first and second asynchronous counters are used to measure the average oscillation frequency of the corresponding multi-feedback ring oscillators, and the comparator is used to compare the average oscillation frequencies to generate the response.

[0047] See Figure 2 The diagram shows an overall structure of an MF-PUF, where the excitation of the MF-PUF is used to select a specific feedback polynomial function f(x). Both the first and second multi-feedback ring oscillators are Galois ring oscillators; or, both the first and second multi-feedback ring oscillators are Fibonacci ring oscillators.

[0048] This embodiment uses GARO as an example to form a multi-feedback ring oscillator to construct an MF-PUF. Other chaotic ring oscillators can also be used as candidate objects to construct a PUF after rigorous evaluation and analysis. In order for GARO to maintain oscillation and not enter a fixed state, the excitation bit f is used in the specific implementation. r-1 The remaining excitation bits are XORed to obtain the CRP space, which reduces the space to 2. r-1 Generally speaking, 2 64 This is a general PUF CRP space size, which is large enough for implementing authentication and preventing brute-force attacks. To obtain a size of at least 2... 64 To determine the CRP space size and satisfy the condition of having no fixed state, the minimum number of inverters in an MF-PUF should be 67, corresponding to a CRP space size of 2. 65 .

[0049] Therefore, a Galois ring oscillator can include 67 inverters and 66 feedback taps, with the excitation signal comprising 66 excitation bits. This embodiment implements a GARO structure with 67 inverters and 66 feedback taps to construct an MF-PUF. For the multi-feedback ring oscillator formed by this GARO, the excitation signal comprises a total of 66 excitation bits corresponding to 66 feedback taps, of which 65 bits are user-controllable.

[0050] See Figure 3The diagram shows a schematic of an asynchronous counter and comparator. In this embodiment, an asynchronous counter can be used to measure the average frequency of a multi-feedback ring oscillator. A first asynchronous counter is used to track the rising edge of a first multi-feedback ring oscillator; a second asynchronous counter is used to track the rising edge of a second multi-feedback ring oscillator. Both the first and second asynchronous counters include multiple cascaded T flip-flops. If the first output value of the last stage of the first asynchronous counter or the second output value of the last stage of the second asynchronous counter reaches a preset threshold, the comparator is used to control the first and second asynchronous counters to stop counting.

[0051] like Figure 3 As shown, the comparator uses the output of the last stage of the counter to generate a response: comparing which stage reaches 1 first. As soon as one output reaches 1, counting is paused via the enable input, and after a certain delay (time interval), the output value of the last stage is compared to generate a response. The purpose of the delay is to allow the count value to stabilize, eliminating the influence of the asynchronous counter and comparator delays on the response. That is, the comparator is also used to generate a physically non-cloning function response based on the first and second output values ​​after a preset time interval.

[0052] like Figure 3 As shown, this asynchronous counter consists of multiple cascaded TFFs (T flip-flops) used to track the rising edge of the ring oscillator output. Each TFF includes four ports, namely the clock input port clk. mn Enable input terminal en mn Output port Q mn and inverting output port 𝑚𝑛 Where 𝑚={1,2} represents the first asynchronous counter and the second asynchronous counter respectively, 𝑛={1,2,3,...,𝑁} represents the index of each stage in an asynchronous counter, and 𝑁 is the stage number of the asynchronous counter.

[0053] Specifically, clk mn This represents the clock input port of the nth stage TFF in the nth asynchronous counter. In this embodiment, the inverted output port of the previous stage T flip-flop is connected to the clock input port of the next stage T flip-flop. Specifically, the clock input port of the first stage T flip-flop of the first asynchronous counter is connected to the output of the first multi-feedback ring oscillator, and the clock input port of the first stage T flip-flop of the second asynchronous counter is connected to the output of the second multi-feedback ring oscillator. That is, for n=1, clk 11 and clk 21 Connect the outputs of two ring oscillators, clk_clk1 and clk_clk2; for λ = 2 ∼ λ, clk mnConnected to 𝑚𝑛′ , where 𝑛′=𝑛−1.

[0054] Specifically, 𝑒𝑛 𝑚𝑛 This represents the enable input of the ith stage TFF in the ith asynchronous counter. For ith = 1, ith... 11 and 𝑒𝑛 21 These are used to control whether asynchronous counters count the next rising edge of the clock. They are controlled by the 𝑠𝑡𝑜𝑝 signal from the comparator and the 𝑠𝑡𝑎𝑟𝑡 signal from the finite state machine (FSM). For 𝑛=2∼𝑁, 𝑒𝑛 𝑚𝑛 Maintaining a high level indicates that the TFF of the corresponding stage is always enabled.

[0055] Specifically, 𝑄 𝑚𝑛 This represents the Q output port of the tfth stage TFF in the tfth asynchronous counter. For t=t, tf is connected to the comparator.

[0056] Specifically, 𝑚𝑛 This represents the inverted Q output port of the ith stage TFF in the ith asynchronous counter. For ith = 1 ~ ith−1, 𝑚𝑛 Connect to 𝑐l𝑘 𝑚𝑛′ , where 𝑛′=𝑛+1.

[0057] Due to the chaotic nature of the multi-feedback ring oscillator in the MF-PUF, reliability is a critical attribute to consider. The unreliability of multi-feedback ring oscillators primarily stems from circuit jitter, metastability, and variations in environmental conditions. The impact of these unreliable factors can be reduced through averaging; therefore, a more reliable response can be obtained by comparing the average oscillation frequencies of two multi-feedback ring oscillators.

[0058] To implement a lightweight comparator, choose an appropriate number of stages N for the asynchronous counter and utilize the output of the last stage. 1𝑁 and 𝑄 2𝑁 To generate a response, which is achieved by comparing 𝑄 1𝑁 and 𝑄 2𝑁 Whichever reaches 1 first generates the output. The enable input of the first-stage T flip-flop of the first and second asynchronous counters is connected to the enable output of the comparator; wherein, when the first output value is 1... 1𝑁 Or the second output value 𝑄 2𝑁 When the preset threshold is reached, the enable output generates a signal that de-enables the first-stage T flip-flop. As long as 𝑄 1𝑁 and 𝑄 2𝑁When one output reaches 1, an ANSI signal is generated through an OR gate, and the output signal en is output through the enable terminal. 11 and en 21 This makes the asynchronous counter in 𝑒𝑛 11 and 𝑒𝑛 21 The counting is paused under the control of the counter. In this comparator design, only 1 bit in the asynchronous counter needs to be compared to generate a response, without the need for multi-bit comparison of the entire count value, so the comparator design is lightweight.

[0059] In this embodiment, the comparator includes an OR gate, a delay unit, and a first D flip-flop. The OR gate is used to compare the output of the last stage. 1𝑁 and 𝑄 2𝑁 Which one reaches the preset threshold first; a delay unit is used to generate a delay after the first asynchronous counter and the second asynchronous counter stop counting, so that the count value in the asynchronous counter can reach stability, thereby eliminating the influence of the delay difference in the asynchronous counter and the comparator on the response; a first D flip-flop is used to generate a physically unclonable function response based on the first output value and the second output value after a preset delay.

[0060] To facilitate observation, whether the similar average oscillation frequencies of the two multi-feedback ring oscillators affect the output after stabilization... 1𝑁 and 𝑄 2𝑁 The system counts the number of times the asynchronous counter's count is 1, and outputs 𝑄 after the asynchronous counter's count reaches a stable value. 1𝑁 and 𝑄 2𝑁 Instead of outputting a single final response bit, the sampled values ​​𝑝𝑢𝑓_𝑜𝑢𝑡1 and 𝑝𝑢𝑓_𝑜𝑢𝑡2 are used. A value of 11 or 10 in 𝑝𝑢𝑓_𝑜𝑢𝑡1 and 𝑝𝑢𝑓_𝑜𝑢𝑡2 represents a response bit with a value of 1, and a value of 01 represents a response bit with a value of 0. The smaller the delay difference between the two multi-feedback ring oscillators, the more susceptible the response is to noise. Therefore, the more 11 values ​​𝑝𝑢𝑓_𝑜𝑢𝑡1 and 𝑝𝑢𝑓_𝑜𝑢𝑡2 have, the lower the reliability.

[0061] The design of the multi-feedback ring oscillator provided in this embodiment of the invention is related to an asynchronous counter. The counting speed of an asynchronous counter is determined by the output toggle rate of the corresponding ring oscillator and the internal delay of the asynchronous counter. The output toggle rate of a chaotic ring oscillator may be faster than the maximum input frequency of the corresponding asynchronous counter, causing some output toggles to be uncounted by the asynchronous counter. The maximum input frequency of the asynchronous counter is limited by the delay from the clock input to the data input in the first stage TFF of the counter, and the corresponding delay path can be as follows: Figure 3 As shown. Delay 𝑇𝑐𝑜 11and 𝑇𝑐𝑜 21 It is the internal delay between the clock input and the output of the D flip-flop (D Flip-Flop) in the first-stage TFF, delay 𝑇𝑐𝑏 11 and 𝑇𝑐𝑏 21 This is the external delay between the output terminal of the DFF and the data input terminal of the R. The maximum input frequency or the minimum countable interval between two rising edges of the asynchronous counter is different for different asynchronous counters. Asynchronous counters with a higher maximum input frequency or a smaller minimum countable interval will have a larger count value for the same input oscillation signal, which means that the asynchronous counter will introduce a deviation (poor uniformity) in the response.

[0062] See Figure 4 The diagram shows a schematic of the signal waveform corresponding to the first-stage TFF in two asynchronous counters. The signal waveforms of the first-stage TFF illustrate the relationship between the internal delay, minimum countable interval, and count value of the asynchronous counters. Assuming an identical GARO output signal 𝑔𝑎𝑟𝑜_𝑜𝑢𝑡 is used as the input to two asynchronous counters with different delays, the impact of the internal delay of the asynchronous counters on the response is verified under the condition of the same input signal. Figure 4 In the diagram, the curves represent the delay paths of the first-stage TFF in the two asynchronous counters, and the rising edges that are not counted by the counters are indicated by circles. Based on this waveform, it can be observed that because the data input of the first-stage TFF remains unchanged when certain input rising edges are triggered, the corresponding output does not change, causing these input rising edges to be uncounted by the counters.

[0063] Different internal delays in asynchronous counters result in different numbers of rising edges counted or missed for the same input signal. For example, for an internal delay of 𝑇𝑐𝑜 11 +𝑇𝑐𝑏 11 The asynchronous counter in the waveform diagram has 6 input rising edges that are not counted, while for the internal delay of 𝑇𝑐𝑜 21 +𝑇𝑐𝑏 21The asynchronous counter has four input rising edges that are not counted. The internal delay of the asynchronous counter determines the minimum countable interval, thus affecting the corresponding count value. The smaller the internal delay, the smaller the minimum countable interval, and the larger the count value for the same input signal, which introduces a deviation in the response. Therefore, if a chaotic ring oscillator is directly used to construct an MF-PUF, its response is highly correlated with the internal delay difference between the two asynchronous counters. Furthermore, if the internal delay difference between the asynchronous counters is greater than the delay difference between the two chaotic ring oscillators, then the response is mainly determined by the delay difference between the two asynchronous counters rather than the delay difference between the chaotic ring oscillators. In other words, the impact of the internal delay difference between the two asynchronous counters outweighs the impact of the delay difference between the chaotic ring oscillators on the response, making it impossible to directly use a chaotic ring oscillator to form a PUF structure.

[0064] Therefore, in this embodiment, the physical non-cloning function generation device may include a first filter and a second filter, which are used to filter signals in the first and second multi-feedback ring oscillators that are greater than the frequency threshold of the filter; wherein the frequency threshold of the filter is less than the maximum input frequency of the first and second asynchronous counters.

[0065] To eliminate the influence of the asynchronous counter on the response, the first and second filters can also be used to reduce the switching speed of the oscillation signals of the first and second multi-feedback ring oscillators by limiting the switching conditions. This means converting the high-speed switching of the outputs of the first and second multi-feedback ring oscillators into low-speed switching. In other words, by widening the interval between two adjacent rising edges through the filters, the asynchronous counter has sufficient time to keep up with the switching of the ring oscillator output. The filter takes the original high-speed switching signal as input and achieves the high-speed to low-speed switching conversion by limiting the switching conditions of the filter output. The filter design needs to consider the chaotic ring oscillator output over a period of time. The filter is triggered and may cause the filter output to switch only if there are at least a certain number of identical values ​​in the output within a certain time period.

[0066] like Figure 5 The diagram shows a ring oscillator including a filter. The initial output over a certain time period includes output signal R1 and the output signal to be generated after a certain delay by state signals R2, R3, R4, R5, and R6. The method for predicting the output value generated after the certain delay is as follows:

[0067] Predict the output to be generated after a delay of dslsh3 based on the current state signal 𝐼2;

[0068] Predict the output to be generated after a delay of dlsh3+dlsh2 based on the current state signal 𝐼3;

[0069] Predict the output to be generated after a delay of dsl_s3 + dsl_s2 + dsl_s1 based on the current state signals R4, R5, and R6.

[0070] If the value of F1 and all predicted values ​​are 1, it means that at least four 1s were generated in the output during that time period, and the filter output is set to 1. Conversely, if the value of F1 and all predicted values ​​are 0, the filter output is reset to 0. Otherwise, the filter output retains its original value. The filter described above includes an encoder and a D flip-flop; the encoder is used to set the filter's set and reset conditions; the D flip-flop is used to control the hold and toggles of the filter output.

[0071] The encoder implements the set and reset conditions, while the DFF controls the hold and toggle of the filter output. 𝑂1 and 𝑂2, corresponding to the set and reset operations, serve as the clock input signal and reset signal of the DFF, respectively. The following equations represent the set and reset conditions of the filter:

[0072]

[0073] A DFF is used to implement the flipping and holding of the filter output under the control of encoder outputs 𝑂1 and 𝑂2. 𝑂1 and 𝑂2, corresponding to the set and reset operations, are respectively used as the clock input signal and reset signal of the DFF.

[0074] The operation of the DFF is shown in Table 1. When the set condition is met, the value of 𝑂1 flips from 0 to 1, and the rising edge of 𝑂1 triggers the output of the DFF to 1. When the reset condition is met, the value of 𝑂2 becomes 1, asynchronously resetting the output of the DFF to 0. The implementation of this constraint makes the interval between two adjacent rising edges large enough, so that the asynchronous counter can keep up with the flipping of the ring oscillator output signal.

[0075]

[0076] The location of the filter also affects the response. If the filter is placed outside the chaotic ring oscillator, it introduces additional bias. For example, if the DFF in one filter is more sensitive to changes in the clock and reset inputs than the DFF in another filter, then even if both chaotic ring oscillators have the same output, the output of the more sensitive filter will produce more flips, resulting in a larger corresponding count value and introducing bias into the response. Filters placed outside the chaotic ring oscillator have the same effect on the response for all different stimuli, thus causing the response values ​​for different stimuli to be biased towards 1 or 0, resulting in poor response uniformity. Conversely, if the filter is contained inside the ring oscillator, the filter output is fed back to the entire ring oscillator, and the differences between filters affect the response under the control of the stimuli. Therefore, the effect of internal filters is different for different stimuli, preventing all responses from being biased towards the same value and introducing additional bias.

[0077] In this embodiment, the original chaotic ring oscillator structure is improved by adding a filter, forming a new multi-feedback ring oscillator structure. This eliminates the influence of the asynchronous counter on the response and avoids the filter itself introducing additional bias into the response. The final structure of the multi-feedback ring oscillator is as follows: Figure 5 As shown, the output of the filter replaces the original output of the chaotic ring oscillator as the feedback signal, and acts on the circuit state under the control of the excitation.

[0078] See Figure 6 The diagram shown is a schematic of the signal waveform corresponding to a filter. Figure 6 This is used to explain the working mechanism of the proposed filter. Here, 𝐼6=0, the corresponding feedback path is broken, therefore the feedback signal 𝐼5 does not affect the filter's behavior.

[0079] See Figure 7 The diagram illustrates one implementation of the set and reset conditions for a filter. A LUT6 is used to implement these conditions, and the delay within the LUT6 is indicated and also displayed. Figure 6 In the input signal level and the delay in LUT6, the encoder output in the filter is determined, which in turn determines the filter output.

[0080] Figure 6The dashed lines represent the waveforms of input signals R4, R3, R2, and R1, while the solid lines represent the waveforms of these input signals after certain delays d4, d3, d2, and d1, denoted as R'4, R'3, R'2, and R'1, respectively. The waveforms represented by the solid lines contain not only signal level information but also the delay information from LUT6. The waveforms of the internal and external signals of the filter can be determined by directly observing the signal values ​​at the same moment in the waveforms. The internal and external signals of the filter include the encoder outputs R1 and R2 and the filter's final output SHOW_SHOW.

[0081] When the values ​​of 𝐼'4, 𝐼'3, 𝐼'2, and 𝐼'1 are all 1011 at the same time, the value of 𝑂1 is set to 1, and the value of 𝑂2 is 0; when the values ​​of 𝐼'4, 𝐼'3, 𝐼'2, and 𝐼'1 are all 0100 at the same time, the value of 𝑂2 is set to 1, and the value of 𝑂1 is 0. Otherwise, the values ​​of 𝑂1 and 𝑂2 are both 0. The waveforms of 𝑂1 and 𝑂2 show that the output after adding the filter has fewer set and reset operations compared to the original GARO output 𝐼1. Furthermore, once `SHOW_SHOW` is set to 1, all subsequent set operations are ignored, preventing the filter output from flipping until the next reset operation is executed; similarly, once `SHOW_SHOW` is reset to 0, all subsequent reset operations are ignored until the next set operation is executed. These ignored set and reset operations further reduce output flipping. After using this filter, the new output `SHOW_SHOW` has a much smaller flip rate compared to the original output `I1`, and the interval between two adjacent rising edges in `SHOW_SHOW` is significantly increased.

[0082] To verify the effectiveness of the proposed filter, this embodiment implements and evaluates three different structures, including: structure 1, GARO without a filter; structure 2, with the filter placed outside the GARO; and structure 3, with the filter placed inside the GARO.

[0083] The difference between Structure 2 and Structure 3 lies in whether the feedback signal of the ring oscillator is generated before or after the filter. In these three structures, multiple multiplexers are placed in different positions to change the corresponding connections, and the impact of the asynchronous counter and filter on the response is verified by calculating the Hamming distance between the response sets obtained before and after the connection change. The corresponding connections are as follows:

[0084] 1. The connection between the chaotic ring oscillator GARO and the asynchronous counter in structure 1.

[0085] 2. The connection between the filter and the asynchronous counter in structure 2.

[0086] 3. Connection between the chaotic ring oscillator GARO and the filter in structure 2.

[0087] 4. The connection between the newly formed multi-feedback ring oscillator and the asynchronous counter in structure 3.

[0088] To explain the function of the multiplexer in detail, let's take connection 1 as an example. By changing the selection signal of the multiplexer corresponding to connection 1 from 0 to 1, the connections between GARO1 and asynchronous counter 1, and GARO2 and asynchronous counter 2, can be changed to connections between GARO1 and asynchronous counter 2, and GARO2 and asynchronous counter 1. By changing connection 1 and calculating the corresponding Hamming distance, the effect of the asynchronous counter on the response can be verified. By changing connections 1, 2, and 4 and calculating the corresponding Hamming distance, the effect of the filter on eliminating the influence of the asynchronous counter can be verified. Furthermore, by changing connection 3 and calculating the corresponding Hamming distance, it can be verified whether an externally placed filter introduces additional bias into the response.

[0089] To explain the effect of Hamming distance in detail, let's take connection 1 as an example again. According to the design of the asynchronous counter, when 𝑄 1𝑁 Bis 2𝑁 When the value reaches 1 first, a response with a value of 1 is generated, and when 𝑄 2𝑁 Bis 1𝑁 When the value reaches 1, a response of 0 is generated. If the asynchronous counter has no effect on the response, and the oscillation frequency of ring oscillator 1 is greater than that of ring oscillator 2, then before changing connection 1 (i.e., when the selection signal of the multiplexer corresponding to connection 1 is 0), the count value of asynchronous counter 1 of ring oscillator 1 is greater than the count value of asynchronous counter 2 of ring oscillator 2, i.e., 0. 1𝑁 Bis 2𝑁 First, a value of 1 is achieved, resulting in a response of 1. However, after changing connection 1, i.e., when the selection signal of the multiplexer corresponding to connection 1 is 1, the count value of the asynchronous counter 2 of the corresponding ring oscillator 1 is greater than the count value of the asynchronous counter 1 of the corresponding ring oscillator 2, i.e., 𝑄 2𝑁 Bis 1𝑁 First, reach 1, so that the resulting response is 0.

[0090] Therefore, if the delay in the asynchronous counter has no effect on the response, the responses to the same stimulus will be opposite before and after changing connection 1. The same applies to connections 2, 3, and 4. Thus, if the asynchronous counter has no effect on the response before applying the filter, the ideal Hamming distance obtained before and after changing connection 1 is 100%; if the asynchronous counter has no effect on the response after applying the filter, the ideal Hamming distance obtained before and after changing connections 2 and 4 is 100%; if the external filter does not introduce additional bias, the ideal Hamming distance obtained before and after changing connection 3 is 100%. However, non-ideal reliability can affect the obtained Hamming distance; therefore, as long as the corresponding Hamming distance is greater than 90%, the asynchronous counter or filter is considered not to introduce bias in the response.

[0091] In actual testing, 1000 stimuli were randomly generated, and 1000 responses were obtained from each response set to calculate the Hamming distance. A smaller calculated Hamming distance indicates a greater influence from the asynchronous counter and filter, and a larger introduced bias. The test results for 8 PUF instances are as follows: Figure 8 The diagram shown illustrates the Hamming distance before and after changing the connection, including the following four cases:

[0092] 1. The Hamming distance between two response sets corresponding to the same stimulus obtained before and after changing connection 1.

[0093] 2. The Hamming distance between two response sets corresponding to the same stimulus obtained before and after changing connection 2.

[0094] 3. The Hamming distance between two response sets corresponding to the same stimulus obtained before and after changing connection 3.

[0095] 4. Change the Hamming distance between the two response sets corresponding to the same stimulus obtained before and after connection 4.

[0096] For case 1, most Hamming distances are less than 90%, and some are even close to 0. This means that when directly using a chaotic ring oscillator to construct a PUF, the asynchronous counter has a significant impact on the response, even causing the response to be largely determined by the asynchronous counter rather than the chaotic ring oscillator. Therefore, a chaotic ring oscillator and an asynchronous counter cannot be directly used to construct a PUF. For cases 2 and 4, all Hamming distances are greater than 90%, indicating that the filter can successfully eliminate the influence of the asynchronous counter on the response. For case 3, the Hamming distance is less than 90%, indicating that the filter placed outside the ring oscillator itself will introduce additional bias into the response. Therefore, the filter cannot be placed outside the ring oscillator.

[0097] In summary, this embodiment addresses the security issues caused by the poor mathematical non-cloning property of PUFs by designing a novel strong PUF based on the delay difference between two multi-feedback ring oscillators: MF-PUF. In the MF-PUF design, an asynchronous counter is used to measure the average oscillation frequency of the two multi-feedback ring oscillators, and an appropriate number of asynchronous counter stages is determined to achieve the highest reliability within an acceptable evaluation time.

[0098] By analyzing the impact of the asynchronous counter on the response, it was demonstrated that chaotic ring oscillators cannot be directly used for PUF construction. This embodiment addresses this issue by designing a digital filter to improve the original chaotic ring oscillator structure, forming a new multi-feedback ring oscillator to eliminate the influence of the asynchronous counter on the response. Furthermore, this structure does not introduce additional deviations to the response due to the filter. Test results demonstrate that MF-PUF possesses good uniformity, reliability, uniqueness, and SAC properties. In addition, MF-PUF exhibits stronger resistance to four commonly used machine learning attack methods—DNN, SVM, LR, and CMA-ES—compared to most existing PUF designs, such as APUF, XORA PUF, LSPUF, and FFA PUF. Because of its strong resistance to machine learning attacks, good performance, and low hardware overhead, MF-PUF is a better PUF candidate than APUF and its variants.

[0099] Example 3:

[0100] Based on the aforementioned apparatus for generating physically unclonable functions, embodiments of the present invention provide a system for generating physically unclonable functions, which will be discussed below. Figure 9 The system is described in detail.

[0101] See Figure 9 The diagram shows a structural schematic of a physically unclonable function (PCF) generation system. This PCF generation system includes an excitation signal generation device and the aforementioned PCF generation device. The excitation signal generation device generates an excitation signal; both the first and second multi-feedback ring oscillators of the PCF generation device are connected to the excitation signal.

[0102] The physical unclonable function generation system provided in this embodiment of the invention has the same technical features as the physical unclonable function generation device provided in the above embodiments, so it can also solve the same technical problems and achieve the same technical effects.

[0103] Those skilled in the art will understand that the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0104] Although the invention has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to the invention without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents. Therefore, the scope of the invention should not be limited to the above embodiments, but should be determined not only by the appended claims but also by their equivalents.

Claims

1. A device for generating physically unclonable functions, characterized in that, The device includes: The first multi-feedback ring oscillator has its input terminal connected to an external excitation signal for oscillation based on the excitation signal; The first asynchronous counter has its input terminal connected to the output terminal of the first multi-feedback ring oscillator and is used to collect the first average oscillation frequency of the first multi-feedback ring oscillator. The second multi-feedback ring oscillator has its input connected to an external excitation signal for oscillation based on the excitation signal. The second asynchronous counter has its input terminal connected to the output terminal of the second multi-feedback ring oscillator and is used to acquire the second average oscillation frequency of the second multi-feedback ring oscillator. A comparator, whose first input is connected to the output of the first asynchronous counter and whose second input is connected to the output of the second asynchronous counter, is used to generate a physically unclonable function response based on the first average oscillation frequency and the second average oscillation frequency; The first filter is located within the first multi-feedback ring oscillator; The second filter is located within the second multi-feedback ring oscillator; The first filter and the second filter are used to reduce the switching speed of the oscillation signals of the first multi-feedback ring oscillator and the second multi-feedback ring oscillator by limiting the switching conditions, and to filter out oscillation signals in the first multi-feedback ring oscillator and the second multi-feedback ring oscillator that are greater than a frequency threshold. Wherein, the frequency threshold is less than the maximum input frequency of the first asynchronous counter and the second asynchronous counter.

2. The apparatus according to claim 1, characterized in that, Both the first asynchronous counter and the second asynchronous counter include multiple cascaded T flip-flops; When the first output value of the last stage T flip-flop of the first asynchronous counter or the second output value of the last stage T flip-flop of the second asynchronous counter reaches a preset threshold, the comparator controls the first asynchronous counter and the second asynchronous counter to stop counting.

3. The apparatus according to claim 2, characterized in that, The comparator includes: A delay unit is used to generate a delay after the first asynchronous counter and the second asynchronous counter stop counting; The first D flip-flop is used to generate the response of the physically unclonable function based on the first output value and the second output value after a preset delay.

4. The apparatus according to claim 2, characterized in that, The T flip-flop includes: Clock input port, enable input port, output port, and inverting output port; The inverted output port of the previous stage T flip-flop is connected to the clock input port of the next stage T flip-flop; The clock input port of the first stage T flip-flop of the first asynchronous counter is connected to the output of the first multi-feedback ring oscillator, and the clock input port of the first stage T flip-flop of the second asynchronous counter is connected to the output of the second multi-feedback ring oscillator.

5. The apparatus according to claim 4, characterized in that, The enable input terminals of the first stage T flip-flops of the first asynchronous counter and the second asynchronous counter are connected to the enable output terminal of the comparator; The enable output terminal is used to generate a signal to stop the first-stage T flip-flop from being enabled when the first output value or the second output value reaches a preset threshold.

6. The apparatus according to claim 1, characterized in that, Both the first multi-feedback ring oscillator and the second multi-feedback ring oscillator are Galois ring oscillators or Fibonacci ring oscillators.

7. The apparatus according to claim 6, characterized in that, The Galois ring oscillator includes 67 inverters and 66 feedback taps; the excitation signal includes 66 excitation bits, each corresponding to one of the 66 feedback taps.

8. The apparatus according to claim 1, characterized in that, The first filter and the second filter include: The encoder is used to set the set and reset conditions of the filter; The second D flip-flop is used to control the hold and toggling of the filter's output.

9. A system for generating physically unclonable functions, characterized in that, The physical non-cloning function generation system includes an excitation signal generation device and a physical non-cloning function generation device as described in any one of claims 1 to 8; wherein the excitation signal generation device is used to generate an excitation signal input to the physical non-cloning function generation device.

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