Hybrid integrated radio frequency power amplifier

Abstract

The application discloses a hybrid integrated radio frequency power amplifier, which comprises a signal input end, a driving amplifier, a power amplifier, an output balun and a signal output end which are sequentially connected; the driving amplifier comprises a first-stage amplifier, an inter-stage balun, a second-stage amplifier and a power combining network which are sequentially connected; the power combining network comprises a self-coupling transformer with four input ends and two output ends; the hybrid integrated radio frequency power amplifier can improve the output power, the output efficiency and the linearity of the driving amplifier, reduce the area of the power combining network on the chip and the insertion loss, and reduce the cost of the hybrid integrated radio frequency power amplifier.

Description

[Technical Field]

[0001] This invention relates to the field of electronic technology, and more particularly to a hybrid integrated radio frequency power amplifier. [Background Technology]

[0002] To reduce manufacturing costs and system size, wireless mobile communication systems need to integrate digital circuits, analog circuits, and more RF functions into a single chip. Thanks to the low cost of silicon-based materials, CMOS technology is now widely used in digital and analog circuits. However, for RF circuit design, CMOS technology has some inherent drawbacks: such as low breakdown voltage of active devices, high-loss substrates due to semiconductor properties, and low-quality-factor interconnect lines. This poses significant challenges to RF circuits designed using CMOS technology, especially RF power amplifiers. CMOS technology involves simultaneously fabricating NMOS and PMOS devices on the same silicon substrate to form a complementary metal-oxide-semiconductor integrated circuit.

[0003] Radio frequency (RF) power amplifiers are located at the end of the transmit chain in a wireless communication system. They amplify the transmitted signal to a certain power level, driving the antenna to radiate the signal without distortion over a sufficiently long distance so that it can be correctly detected by the receiving device. For cellular communication, 2G GSM communication requires the RF power amplifier at the mobile end to output more than 2W of power, while 4G and 5G communication require the RF power amplifier to be able to handle peak-to-average power ratio (PAPR) signals, and the 1dB power compression point of the RF power amplifier must also exceed 2W to ensure high linearity of output power.

[0004] Compared to CMOS technology, GaAs HBT technology is fabricated on a semi-insulating GaAs (gallium arsenide) substrate. It offers high power density, high transconductance, high breakdown voltage, good linearity, minimal signal interference, and low insertion loss of passive components, making it ideal for RF power amplifier design. Specifically, the GaAs HBT process involves simultaneously fabricating NPN heterojunction bipolar transistors on the same gallium arsenide substrate to form an integrated circuit.

[0005] The cost of GaAs wafers (heterojunction bipolar transistors) is higher than that of CMOS wafers (complementary metal-oxide-semiconductor). Common GaAs HBT processes often only provide a single NPN HBT device, which is not conducive to designing control circuits for RF power amplifiers. CMOS wafers are the cheapest, so low cost is CMOS's biggest advantage. Minimizing cost while maintaining RF power amplifier performance is key to maintaining competitiveness; therefore, using CMOS processes to design circuits as much as possible, and even achieving fully integrated circuits for baseband, memory, and RF, has always been a crucial issue in RF power amplifier design.

[0006] However, the physical characteristics of CMOS devices limit the output power of a single CMOS amplifier. To improve output power, it is necessary to power combine the output power of multiple CMOS amplifiers. Existing multi-channel CMOS power amplifiers all use magnetically coupled transformers as power combining networks to combine multiple differential output signals into a single output signal. However, since the substrate of CMOS technology is semi-insulated, the insertion loss of using magnetically coupled transformers as power combining networks is relatively large, which reduces the overall output power and efficiency of the CMOS power amplifier and also degrades linearity. Moreover, magnetically coupled transformers occupy a large area and are costly, which cannot meet the application requirements. [Summary of the Invention]

[0007] The purpose of this invention is to provide a hybrid integrated radio frequency power amplifier to solve the problems of existing radio frequency power amplifiers that use magnetic coupling transformers as the power combining network of multi-channel CMOS power amplifiers, resulting in large insertion loss, reduced output power and efficiency of the entire CMOS power amplifier, deterioration of linearity, large footprint, and high cost.

[0008] To achieve the above objectives, the present invention provides a hybrid integrated radio frequency power amplifier, which includes a signal input terminal, a driver amplifier implemented using CMOS technology, a power amplifier implemented using GaAs HBT technology, an output balun, and a signal output terminal connected in sequence and integrated on the same substrate; the driver amplifier includes a first-stage amplifier, an inter-stage balun, a second-stage amplifier, and a power combining network connected in sequence.

[0009] The input terminal of the first-stage amplifier is connected to the signal input terminal, and is used to amplify the power of the single-ended signal received by the signal input terminal;

[0010] The input terminal of the interstage balun is connected to the output terminal of the first stage amplifier, and is used to convert the single-ended signal after power amplification by the first stage amplifier into a differential signal, and output a first differential signal and a second differential signal.

[0011] The second-stage amplifier includes a first amplification unit and a second amplification unit, both composed of complementary metal-oxide-semiconductor (CMOS) semiconductors. The first input terminal and the second input terminal of the first amplification unit are respectively connected to the first output terminal and the second output terminal of the interstage balun, for amplifying the first differential signal and the second differential signal, respectively, and outputting a first amplified differential signal and a second amplified differential signal. The first input terminal and the second input terminal of the second amplification unit are respectively connected to the first output terminal and the second output terminal of the interstage balun, for amplifying the first differential signal and the second differential signal, respectively, and outputting a third amplified differential signal and a fourth amplified differential signal.

[0012] The power combining network includes an autotransformer with four input terminals and two output terminals; the first input terminal and the second input terminal of the power combining network are respectively connected to the first output terminal and the second output terminal of the first amplification unit, for receiving the first amplified differential signal and the second amplified differential signal, respectively; the third input terminal and the fourth input terminal of the power combining network are respectively connected to the first output terminal and the second output terminal of the second amplification unit, for receiving the third amplified differential signal and the fourth amplified differential signal, respectively; the power combining network combines the first amplified differential signal, the second amplified differential signal, the third amplified differential signal, and the fourth amplified differential signal into a first output signal and a second output signal, and outputs the first output signal and the second output signal through the first output terminal and the second output terminal of the power combining network, respectively;

[0013] The first input terminal and the second input terminal of the power amplifier are respectively connected to the first output terminal and the second output terminal of the power combining network, and are used to amplify the first output signal and the second output signal synthesized by the power combining network, respectively.

[0014] The first input terminal and the second input terminal of the output balun are respectively connected to the first output terminal and the second output terminal of the power amplifier, and are used to receive the first output signal and the second output signal after power amplification by the power amplifier, and combine them into a single-ended signal.

[0015] The signal output terminal is connected to the output terminal of the output balun, and is used to output a single-ended signal synthesized by the output balun.

[0016] Preferably, the autotransformer includes a first primary coil, and a first secondary coil, a second secondary coil, and a third secondary coil connected in series and coupled to the first primary coil respectively; wherein the first primary coil and the first secondary coil serve as a common winding;

[0017] The first end of the first primary coil serves as the first input terminal of the power combining network and is connected to the first output terminal of the first amplification unit to receive the first amplified differential signal; the second end of the first primary coil serves as the second input terminal of the power combining network and is connected to the second output terminal of the first amplification unit to receive the second amplified differential signal.

[0018] The first end of the primary coil serves as the first output end of the power combining network and is connected to the first input end of the power amplifier to output the first output signal.

[0019] The first end of the second-stage coil serves as the third input terminal of the power combining network and is connected to the first input terminal of the second amplification unit to receive the third amplified differential signal; the second end of the second-stage coil serves as the fourth input terminal of the power combining network and is connected to the second input terminal of the second amplification unit to receive the fourth amplified differential signal; the second end of the second-stage coil is connected to the second end of the first-stage coil.

[0020] The first end of the third-stage coil is connected to the first end of the second-stage coil, and the second end of the third-stage coil serves as the second output end of the power combining network and is connected to the second input end of the power amplifier to output the second output signal.

[0021] The center tap of the first primary coil and the center tap of the second primary coil are both connected to the operating voltage.

[0022] Preferably, the power combining network further includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor;

[0023] The two ends of the first capacitor are respectively connected to the first end of the first primary coil and the second end of the first primary coil;

[0024] The two ends of the second capacitor are respectively connected to the first end of the second-stage coil and the second end of the second-stage coil;

[0025] The two ends of the third capacitor are respectively connected to the first end of the first stage coil and the second end of the third stage coil;

[0026] The fourth capacitor is connected in series between the first terminal of the primary winding and the first input terminal of the power amplifier.

[0027] The fifth capacitor is connected in series between the second end of the third stage coil and the second input terminal of the power amplifier.

[0028] Preferably, the first-stage amplifier includes a first input matching network and a first-stage amplification unit;

[0029] The first input matching network includes a sixth capacitor, a seventh capacitor, a first resistor, and a first inductor;

[0030] The first terminal of the sixth capacitor serves as the input terminal of the first-stage amplifier and is connected to the signal output terminal.

[0031] The first terminal of the seventh capacitor is connected to the second terminal of the sixth capacitor, and the second terminal of the seventh capacitor is grounded.

[0032] The first end of the first resistor is connected to the second end of the sixth capacitor, and the second end of the first resistor is connected to the first control electrode voltage;

[0033] The first terminal of the first inductor is connected to the second terminal of the sixth capacitor;

[0034] The first stage amplification unit includes a first field-effect transistor, a second field-effect transistor, an eighth capacitor, and a second resistor;

[0035] The gate of the first field-effect transistor is connected to the second terminal of the first inductor, and the source of the first field-effect transistor is grounded;

[0036] The source of the second field-effect transistor is connected to the drain of the first field-effect transistor, and the drain of the second field-effect transistor serves as the output terminal of the first stage amplifier, which is connected to the input terminal of the interstage balun.

[0037] The first terminal of the eighth capacitor is connected to the gate of the second field-effect transistor, and the second terminal of the eighth capacitor is grounded.

[0038] The first end of the second resistor is connected to the gate of the second field-effect transistor, and the second end of the second resistor is connected to the second control voltage.

[0039] Preferably, the interstage balun includes a first transformer, a ninth capacitor, a tenth capacitor, and a third resistor;

[0040] The first transformer includes a second primary coil and a fourth secondary coil coupled to the second primary coil;

[0041] The first end of the second primary coil is connected to the operating voltage, and the second end of the second primary coil serves as the input terminal of the interstage balun.

[0042] The first end of the fourth secondary coil serves as the first output end of the interstage balun, and is connected to the first input end of the first amplification unit and the first input end of the second amplification unit, respectively; the second end of the fourth secondary coil serves as the second output end of the interstage balun, and is connected to the second input end of the first amplification unit and the second input end of the second amplification unit, respectively.

[0043] The two ends of the ninth capacitor are respectively connected to the first end of the second primary coil and the second end of the second primary coil;

[0044] The two ends of the tenth capacitor are respectively connected to the first end of the fourth secondary coil and the second end of the fourth secondary coil;

[0045] The first end of the third resistor is connected to the center tap of the fourth secondary coil, and the second end of the third resistor is connected to the first control electrode voltage.

[0046] Preferably, the first amplification unit includes a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, and a fourth resistor;

[0047] The gate of the third field-effect transistor serves as the first input terminal of the first amplification unit and is connected to the first terminal of the fourth secondary coil to receive the first differential signal. The source of the third field-effect transistor is grounded.

[0048] The source of the fourth field-effect transistor is connected to the drain of the third field-effect transistor. The drain of the fourth field-effect transistor serves as the first output terminal of the first amplification unit and is connected to the first terminal of the first primary coil to output the first amplified differential signal.

[0049] The gate of the fifth field-effect transistor serves as the second input terminal of the first amplification unit and is connected to the second terminal of the second primary coil to receive the second differential signal. The source of the fifth field-effect transistor is grounded.

[0050] The source of the sixth field-effect transistor is connected to the drain of the fifth field-effect transistor, and the gate of the sixth field-effect transistor is connected to the gate of the fourth field-effect transistor. The drain of the sixth field-effect transistor serves as the second output terminal of the first amplification unit and is connected to the second terminal of the first primary coil to output the second amplified differential signal.

[0051] The first end of the fourth resistor is connected to the gate of the fourth field-effect transistor, and the second end of the fourth resistor is connected to the second control electrode voltage.

[0052] The second amplification unit includes a seventh field-effect transistor, an eighth field-effect transistor, a ninth field-effect transistor, a tenth field-effect transistor, and a fifth resistor;

[0053] The gate of the seventh field-effect transistor serves as the first input terminal of the second amplification unit and is connected to the first terminal of the fourth secondary coil to receive the first differential signal. The source of the seventh field-effect transistor is grounded.

[0054] The source of the eighth field-effect transistor is connected to the drain of the seventh field-effect transistor. The drain of the eighth field-effect transistor serves as the first output terminal of the second amplification unit and is connected to the first terminal of the second stage coil to output the third amplified differential signal.

[0055] The gate of the ninth field-effect transistor serves as the second input terminal of the second amplification unit and is connected to the second terminal of the second primary coil to receive the second differential signal. The source of the ninth field-effect transistor is grounded.

[0056] The source of the tenth field-effect transistor is connected to the drain of the ninth field-effect transistor, the gate of the sixth field-effect transistor is connected to the gate of the eighth field-effect transistor, and the drain of the tenth field-effect transistor serves as the second output terminal of the second amplification unit, connected to the second terminal of the second stage coil, for outputting the fourth amplified differential signal.

[0057] The first end of the fifth resistor is connected to the gate of the eighth field-effect transistor, and the second end of the fifth resistor is connected to the second control electrode voltage.

[0058] Preferably, the power amplifier includes a third-stage amplifier and a linearization bias circuit;

[0059] The third-stage amplifier includes a second input matching network, a first transistor, a third input matching network, and a second transistor; the second input matching network includes an eleventh capacitor and a second inductor; the third input matching network includes a twelfth capacitor and a third inductor;

[0060] The first terminal of the eleventh capacitor serves as the first input terminal of the power amplifier and is connected to the first terminal of the first stage coil to receive the first output signal.

[0061] The first terminal of the second inductor is connected to the first terminal of the eleventh capacitor, and the second terminal of the second inductor is grounded.

[0062] The base of the first transistor is connected to the second terminal of the eleventh capacitor, the emitter of the first transistor is grounded, and the collector of the first transistor serves as the first output terminal of the power amplifier, which is connected to the first input terminal of the output balun.

[0063] The first terminal of the twelfth capacitor serves as the second input terminal of the power amplifier and is connected to the second terminal of the third stage coil to receive the second output signal.

[0064] The first terminal of the third inductor is connected to the first terminal of the twelfth capacitor, and the second terminal of the third inductor is grounded.

[0065] The base of the second transistor is connected to the second terminal of the twelfth capacitor, the emitter of the second transistor is grounded, and the collector of the second transistor serves as the second output terminal of the power amplifier, which is connected to the second input terminal of the output balun.

[0066] The output of the linearization bias circuit is connected to the base of the first transistor and the base of the second transistor, respectively.

[0067] Preferably, the linearization bias circuit includes a third transistor, a thirteenth capacitor, a fourth transistor, a sixth resistor, and a fifth transistor;

[0068] The emitter of the third transistor serves as the output terminal of the linearization bias circuit, and the collector of the third transistor is connected to the power supply voltage.

[0069] The first terminal of the thirteenth capacitor is connected to the base of the third transistor, and the second terminal of the thirteenth capacitor is grounded.

[0070] The base and collector of the fourth transistor are both connected to the base of the third transistor.

[0071] The first end of the sixth resistor is connected to the base of the third transistor, and the second end of the sixth resistor is connected to the third control voltage.

[0072] The base and collector of the fifth transistor are both connected to the emitter of the fourth transistor, and the emitter of the fifth transistor is grounded.

[0073] Preferably, the output balun includes a second transformer, a fourteenth capacitor, and a fifteenth capacitor;

[0074] The second transformer includes a third primary coil and a fifth secondary coil coupled to the third primary coil;

[0075] The first end of the third primary coil serves as the first input terminal of the output balun, used to receive the first output signal after power amplification by the power amplifier. The second end of the third primary coil serves as the second input terminal of the output balun, used to receive the second output signal after power amplification by the power amplifier. The middle tap of the third primary coil is connected to the power supply voltage.

[0076] The two ends of the fourteenth capacitor are respectively connected to the first end of the third primary coil and the second end of the third primary coil;

[0077] The first end of the fifth secondary coil serves as the output end of the output balun and is connected to the signal output end; the second end of the fifth secondary coil is grounded.

[0078] The first terminal of the fifteenth capacitor is connected to the first terminal of the fifth secondary coil, and the second terminal of the fifteenth capacitor is grounded.

[0079] Preferably, the hybrid integrated RF power amplifier further includes a seventh resistor, the first end of which is connected to the signal output terminal, and the second end of which is grounded.

[0080] Compared with the prior art, the hybrid integrated RF power amplifier of the present invention uses a driver amplifier implemented with CMOS technology and a power amplifier implemented with GaAs HBT technology, and defines the power combining network as an autotransformer. This allows the hybrid integrated RF power amplifier to improve the output power, output efficiency and linearity of the driver amplifier when using a transformer of the same capacity as the power combining network, while reducing the chip area occupied by the power combining network and reducing its insertion loss. In addition, it can also take advantage of the low cost of CMOS technology to reduce the cost of the hybrid integrated RF power amplifier. [Attached Image Description]

[0081] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0082] Figure 1 A schematic diagram of the frame structure of a hybrid integrated radio frequency power amplifier provided in an embodiment of the present invention;

[0083] Figure 2 A circuit connection diagram of a hybrid integrated radio frequency power amplifier provided for an embodiment of the present invention;

[0084] Figure 3 A circuit connection diagram of the driver amplifier in a hybrid integrated radio frequency power amplifier provided for an embodiment of the present invention;

[0085] Figure 4 A circuit connection diagram of the power amplifier in a hybrid integrated radio frequency power amplifier provided for an embodiment of the present invention;

[0086] Figure 5 A circuit connection diagram of the output balun in a hybrid integrated radio frequency power amplifier provided for an embodiment of the present invention;

[0087] Figure 6 This is a schematic diagram of the structure of an autotransformer in a hybrid integrated radio frequency power amplifier provided by an embodiment of the present invention;

[0088] Among them, 100 is a hybrid integrated RF power amplifier; 1 is a driver amplifier; 11 is a first-stage amplifier; 12 is an interstage balun; 13 is a second-stage amplifier; 14 is a power combining network; 2 is a power amplifier; 21 is a third-stage amplifier; 22 is a linearization bias circuit; 3 is an output balun; and 4 is a substrate.

Detailed Implementation Methods

[0089] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0090] This invention provides a hybrid integrated radio frequency power amplifier 100, combined with... Figures 1 to 5 As shown, it includes a signal input terminal RFin, a driver amplifier 1 implemented using CMOS technology, a power amplifier 2 implemented using GaAs HBT technology, an output balun 3, and a signal output terminal RFout, all connected in sequence and integrated on the same substrate 4; the driver amplifier 1 includes a first-stage amplifier 11, an inter-stage balun 12, a second-stage amplifier 13, and a power combining network 14, all connected in sequence.

[0091] Specifically, the input terminal of the first-stage amplifier 11 is connected to the signal input terminal RFin, and is used to amplify the power of the single-ended signal (RF1) received by the signal input terminal RFin.

[0092] The input terminal of the interstage balun 12 is connected to the output terminal of the first stage amplifier 11, and is used to convert the single-ended signal after power amplification by the first stage amplifier 11 into a differential signal, and output the first differential signal RF11 and the second differential signal RF12.

[0093] The second-stage amplifier 13 includes a first amplification unit and a second amplification unit, both of which are composed of complementary metal-oxide-semiconductor (CMOS) semiconductors. The first input terminal and the second input terminal of the first amplification unit are respectively connected to the first output terminal and the second output terminal of the interstage balun 12, for power amplification of the first differential signal RF11 and the second differential signal RF12, and outputting the first amplified differential signal RF21 and the second amplified differential signal RF22. The first input terminal and the second input terminal of the second amplification unit are respectively connected to the first output terminal and the second output terminal of the interstage balun 12, for power amplification of the first differential signal RF11 and the second differential signal RF12, and outputting the third amplified differential signal RF23 and the fourth amplified differential signal RF24.

[0094] The power combining network 14 includes an autotransformer XFM1 with four input terminals and two output terminals; the first input terminal and the second input terminal of the power combining network 14 are respectively connected to the first output terminal and the second output terminal of the first amplification unit, for receiving the first amplified differential signal RF21 and the second amplified differential signal RF22, respectively; the third input terminal and the fourth input terminal of the power combining network 14 are respectively connected to the first output terminal and the second output terminal of the second amplification unit, for receiving the third amplified differential signal RF23 and the fourth amplified differential signal RF24, respectively; the power combining network 14 combines the first amplified differential signal RF21, the second amplified differential signal RF22, the third amplified differential signal RF23, and the fourth amplified differential signal RF24 into a first output signal and a second output signal, and outputs the first output signal and the second output signal through the first output terminal and the second output terminal of the power combining network 14, respectively.

[0095] The first input terminal and the second input terminal of the power amplifier 2 are respectively connected to the first output terminal and the second output terminal of the power combining network 14, and are used to amplify the first output signal and the second output signal synthesized by the power combining network 14, respectively.

[0096] The first input terminal and the second input terminal of the output balun 3 are respectively connected to the first output terminal and the second output terminal of the power amplifier 2, and are used to receive the first output signal and the second output signal after power amplification by the power amplifier 2, and combine them into a single-ended signal.

[0097] The signal output terminal RFout is connected to the output terminal of output balun 3, and is used to output a single-ended signal synthesized from output balun 3.

[0098] like Figure 1 As shown, the hybrid integrated RF power amplifier 100 in this embodiment integrates a driver amplifier 1 implemented using CMOS technology, a power amplifier 2 implemented using GaAs HBT technology, and an output balun 3 on the same substrate 4. The driver amplifier 1 consists of an input matching network 1, a first-stage amplifier 11 (PA1), an interstage balun 12, a second-stage amplifier 13 (PA2, PA3, PA4, PA5), and a power combining network 14 with a three-port autotransformer XFM1. The power amplifier 2 implemented using GaAs HBT technology consists of differential HBT amplifiers PA7 and PA6, an input matching network 2, and an input matching network 3. The output balun 3 is implemented on the substrate 4. This hybrid integrated RF power amplifier 100 fully utilizes the advantages of the three modules, making it an effective method for designing a high-performance, cost-effective hybrid integrated RF power amplifier 100.

[0099] In this embodiment, the autotransformer XFM1 includes a first primary coil L AP1 and sequentially connected in series with the first primary coil L AP1 The first stage coil L of the coupling A1 Secondary coil L A2 and the third-stage coil L A3 Among them, the first primary coil L AP1 With the first stage coil L A1 As a common winding, the coupling coefficient is k.

[0100] First primary coil L AP1 The first end serves as the first input terminal of the power combining network 14 and is connected to the first output terminal of the first amplification unit to receive the first amplified differential signal RF21; the first primary coil L AP1 The second end serves as the second input end of the power combining network 14 and is connected to the second output end of the first amplification unit to receive the second amplified differential signal RF22.

[0101] First stage coil L A1 The first end serves as the first output end of the power combining network 14 and is connected to the first input end of the power amplifier 2 to output the first output signal.

[0102] Secondary coil L A2 The first terminal serves as the third input terminal of the power combining network 14, and is connected to the first input terminal of the second amplification unit to receive the third amplified differential signal RF23; the second stage coil L A2 The second terminal serves as the fourth input terminal of the power combining network 14, connected to the second input terminal of the second amplification unit, for receiving the fourth amplified differential signal RF24; the second stage coil L A2The second end is connected to the first stage coil L AP1 The second end is connected;

[0103] Third stage coil L A3 The first end and the second stage coil L A2 The first end is connected, and the third-stage coil L A3 The second end serves as the second output end of the power combining network 14 and is connected to the second input end of the power amplifier 2 to output the second output signal.

[0104] First primary coil L AP1 The middle tap and the secondary coil L A2 The center taps are all connected to the operating voltage VDD.

[0105] In addition, the power combining network 14 also includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5.

[0106] The two ends of the first capacitor C1 are respectively connected to the first primary coil L. AP1 The first end and the first primary coil L AP1 The second end.

[0107] The two ends of the second capacitor C2 are respectively connected to the second stage coil L. A2 The first and second stage coils L A2 The second end.

[0108] The two ends of the third capacitor C3 are respectively connected to the first primary coil L. A1 The first and third stage coils L A3 The second end.

[0109] The fourth capacitor C4 is connected in series with the primary winding L. A1 Between the first terminal of and the first input terminal of power amplifier 2.

[0110] The fifth capacitor C5 is connected in series with the third stage coil L. A3 Between the second terminal of and the second input terminal of power amplifier 2.

[0111] Specifically, the first-stage amplifier 11 includes a first input matching network and a first-stage amplification unit.

[0112] In this embodiment, the first input matching network includes a sixth capacitor C6, a seventh capacitor C7, and a first resistor R. b1 And the first inductor L1.

[0113] The first terminal of the sixth capacitor C6 serves as the input terminal of the first-stage amplifier 11 and is connected to the signal output terminal RFout.

[0114] The first terminal of the seventh capacitor C7 is connected to the second terminal of the sixth capacitor C6, and the second terminal of the seventh capacitor C7 is grounded.

[0115] First resistor R b1 The first terminal is connected to the second terminal of the sixth capacitor C6, and the first resistor R b1 The second terminal is connected to the first control electrode voltage V. G1 .

[0116] The first terminal of the first inductor L1 is connected to the second terminal of the sixth capacitor C6.

[0117] In this embodiment, the first-stage amplification unit includes a first field-effect transistor M1, a second field-effect transistor M2, an eighth capacitor C8, and a second resistor R. b2 .

[0118] The gate of the first field-effect transistor M1 is connected to the second terminal of the first inductor L1, and the source of the first field-effect transistor M1 is grounded.

[0119] The source of the second field-effect transistor M2 is connected to the drain of the first field-effect transistor M1. The drain of the second field-effect transistor M2 serves as the output terminal of the first-stage amplifier 11 and is connected to the input terminal of the interstage balun 12.

[0120] The first terminal of the eighth capacitor C8 is connected to the gate of the second field-effect transistor M2, and the second terminal of the eighth capacitor C8 is grounded.

[0121] Second resistor R b2 The first terminal is connected to the gate of the second field-effect transistor M2, and the second resistor R b2 The second terminal is connected to the second control electrode voltage V. G2 .

[0122] In this embodiment, the interstage balun 12 includes a first transformer XFM2, a ninth capacitor C9, and a tenth capacitor C. 10 and the third resistor R b3 .

[0123] The first transformer XFM2 includes a second primary coil and a fourth secondary coil coupled to the second primary coil.

[0124] The first end of the second primary coil is connected to the operating voltage VDD, and the second end of the second primary coil serves as the input terminal of the interstage balun 12, which is connected to the drain of the second field-effect transistor M2.

[0125] The first end of the fourth secondary coil serves as the first output terminal of the interstage balun 12, and is connected to the first input terminal of the first amplification unit and the first input terminal of the second amplification unit, respectively. The second end of the fourth secondary coil serves as the second output terminal of the interstage balun 12, and is connected to the second input terminal of the first amplification unit and the second input terminal of the second amplification unit, respectively.

[0126] The two ends of the ninth capacitor C9 are connected to the first end of the second primary coil and the second end of the second primary coil, respectively.

[0127] Tenth capacitor C 10 The two ends are respectively connected to the first end of the fourth secondary coil and the second end of the fourth secondary coil.

[0128] Third resistor R b3 The first terminal is connected to the center tap of the fourth secondary coil, and the third resistor R b3 The second terminal is connected to the first control electrode voltage V. G1 .

[0129] In this embodiment, the first amplification unit includes a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, and a fourth resistor R. b4 .

[0130] The gate of the third field-effect transistor M3 serves as the first input terminal of the first amplification unit and is connected to the first terminal of the fourth secondary coil to receive the first differential signal RF11. The source of the third field-effect transistor M3 is grounded.

[0131] The source of the fourth field-effect transistor M4 is connected to the drain of the third field-effect transistor M3. The drain of the fourth field-effect transistor M4 serves as the first output terminal of the first amplification unit, and is connected to the first primary coil L. AP1 The first terminal is connected to output the first amplified differential signal RF21.

[0132] The gate of the fifth field-effect transistor M5 serves as the second input terminal of the first amplification unit and is connected to the second terminal of the second primary coil to receive the second differential signal RF12. The source of the fifth field-effect transistor M5 is grounded.

[0133] The source of the sixth field-effect transistor M6 is connected to the drain of the fifth field-effect transistor M5, and the gate of the sixth field-effect transistor M6 is connected to the gate of the fourth field-effect transistor M4. The drain of the sixth field-effect transistor M6 serves as the second output terminal of the first amplification unit and is connected to the first primary coil L. AP1 The second terminal is connected to output the second amplified differential signal RF22.

[0134] Fourth resistor R b4 The first terminal is connected to the gate of the fourth field-effect transistor M4, and the fourth resistor R b4 The second terminal is connected to the second control electrode voltage V. G2 .

[0135] The second amplification unit includes the seventh field-effect transistor M7, the eighth field-effect transistor M8, the ninth field-effect transistor M9, and the tenth field-effect transistor M1. 10 and the fifth resistor Rb5 .

[0136] The gate of the seventh field-effect transistor M7 serves as the first input terminal of the second amplification unit and is connected to the first terminal of the fourth secondary coil to receive the first differential signal RF11. The source of the seventh field-effect transistor M7 is grounded.

[0137] The source of the eighth field-effect transistor M8 is connected to the drain of the seventh field-effect transistor M7. The drain of the eighth field-effect transistor M8 serves as the first output terminal of the second amplification unit, connected to the second stage coil L. A2 The first terminal is connected to output the third amplified differential signal RF23.

[0138] The gate of the ninth field-effect transistor M9 serves as the second input terminal of the second amplification unit and is connected to the second terminal of the second primary coil to receive the second differential signal RF12. The source of the ninth field-effect transistor M9 is grounded.

[0139] Tenth field-effect transistor M 10 The source of the transistor is connected to the drain of the ninth field-effect transistor M9, the gate of the sixth field-effect transistor M6 is connected to the gate of the eighth field-effect transistor M8, and the tenth field-effect transistor M... 10 The drain of the second amplifier unit serves as the second output terminal, connected to the second stage coil L. A2 The second terminal is connected to output the fourth amplified differential signal RF24.

[0140] Fifth resistor R b5 The first terminal is connected to the gate of the eighth field-effect transistor M8, and the fifth resistor R b5 The second terminal is connected to the second control electrode voltage V. G2 .

[0141] In this embodiment, the power amplifier 2 includes a third-stage amplifier 21 and a linearization bias circuit 22.

[0142] The third-stage amplifier 21 includes a second input matching network, a first transistor Q1, a third input matching network, and a second transistor Q2; the second input matching network includes an eleventh capacitor C. 11 And the second inductor L2; the third input matching network includes the twelfth capacitor C. 12 And the third inductor L3.

[0143] Eleventh capacitor C 11 The first terminal serves as the first input terminal of power amplifier 2, and is connected to the first stage coil L. A1 The first end is connected to receive the first output signal synthesized by the power combining network 14.

[0144] The first terminal of the second inductor L2 is connected to the eleventh capacitor C. 11The first end of the inductor is connected, and the second end of the second inductor L2 is grounded.

[0145] The base of the first transistor Q1 is connected to the eleventh capacitor C. 11 The second terminal of the first transistor Q1 is grounded, and the collector of the first transistor Q1 serves as the first output terminal of the power amplifier 2, which is connected to the first input terminal of the output balun 3.

[0146] The twelfth capacitor C 12 The first terminal serves as the second input terminal of power amplifier 2, and is connected to the third stage coil L. A3 The second end is connected to receive the second output signal synthesized by the power combining network 14.

[0147] The first terminal of the third inductor L3 is connected to the twelfth capacitor C. 12 The first end of the inductor is connected, and the second end of the third inductor L3 is grounded.

[0148] The base of the second transistor Q2 is connected to the twelfth capacitor C. 12 The second terminal of the second transistor Q2 is grounded, and the collector of the second transistor Q2 serves as the second output terminal of the power amplifier 2, which is connected to the second input terminal of the output balun 3.

[0149] The output of the linearization bias circuit 22 is connected to the base of the first transistor Q1 and the base of the second transistor Q2, respectively.

[0150] The linearization bias circuit 22 includes a third transistor Q3 and a thirteenth capacitor C. 13 Fourth transistor Q4, sixth resistor R b6 The fifth transistor is Q5.

[0151] The emitter of the third transistor Q3 serves as the output terminal of the linearization bias circuit 22, and is connected to the base of the first transistor Q1 and the base of the second transistor Q2, respectively. The collector of the third transistor Q3 is connected to the power supply voltage VCC.

[0152] Thirteenth capacitor C 13 The first terminal is connected to the base of the third transistor Q3, and the thirteenth capacitor C 13 The second end is grounded.

[0153] The base and collector of the fourth transistor Q4 are both connected to the base of the third transistor Q3.

[0154] Sixth resistor R b6 The first terminal is connected to the base of the third transistor Q3, and the sixth resistor R b6 The second terminal is connected to the third control electrode voltage V. REG .

[0155] The base and collector of the fifth transistor Q5 are both connected to the emitter of the fourth transistor Q4, and the emitter of the fifth transistor Q5 is grounded.

[0156] In this embodiment, the output balun 3 includes the second transformer XFM3 and the fourteenth capacitor C. 14 And the fifteenth capacitor C 15 .

[0157] The second transformer XFM3 includes a third primary coil and a fifth secondary coil coupled to the third primary coil.

[0158] The first end of the third primary coil serves as the first input terminal of the output balun 3 and is connected to the collector of the first transistor Q1 to receive the first output signal after power amplification by the power amplifier 2. The second end of the third primary coil serves as the second input terminal of the output balun 3 and is connected to the collector of the second transistor Q2 to receive the second output signal after power amplification by the power amplifier 2. The middle tap of the third primary coil is connected to the power supply voltage VCC.

[0159] Fourteenth capacitor C 14 The two ends are respectively connected in parallel to the first end of the third primary coil and the second end of the third primary coil.

[0160] The first end of the fifth secondary coil serves as the output terminal of the output balun 3 and is connected to the signal output terminal RFout. The second end of the fifth secondary coil is grounded.

[0161] The fifteenth capacitor C 15 The first terminal is connected to the first terminal of the fifth secondary coil, and the fifteenth capacitor C 15 The second end is grounded.

[0162] In this embodiment, the hybrid integrated RF power amplifier 100 further includes a seventh resistor R. L The seventh resistor R L The first terminal is connected to the signal output terminal RFout, and the seventh resistor R L The second end is grounded.

[0163] In this embodiment, the driver amplifier 1 is implemented using CMOS technology, the power amplifier 2 is implemented using GaAs HBT technology, and a low insertion loss three-port self-coupling transformer is used as a power combining network 14 to achieve impedance matching between the driver amplifier 1 and the power amplifier 2. The output balun 3 is implemented on the substrate 4.

[0164] In this embodiment, the driver amplifier 1 has a cost advantage. Although its output power is limited, it can provide sufficient driving power as a driver stage. The driver amplifier 1 is designed using CMOS technology, which makes full use of its cost advantage. The GaAs HBT device has high breakdown voltage, good linearity, and high efficiency. It is used as the power amplifier 2 to ensure the performance of the entire hybrid integrated RF power amplifier 100. The metal lines on the substrate 4 have a high quality factor. The output balun 3 is implemented on the substrate 4 with low insertion loss, and the load can obtain higher output power to improve the efficiency and linearity of the entire hybrid integrated RF power amplifier 100.

[0165] In this embodiment, the first-stage amplifier 11 has a Cascode structure. The signal input at the signal input terminal RFin is connected to the gate of the first field-effect transistor M1 of the common-source amplifier through the first input matching network composed of the sixth capacitor C6, the seventh capacitor C7, and the first inductor L1. The gate of the second field-effect transistor M2 of the common-gate amplifier is grounded through the eighth capacitor C8, and the drain of the second field-effect transistor M2 is connected to the interstage balun 12. The interstage balun 12 consists of the first transformer XFM2, the ninth capacitor C9, and the tenth capacitor C1. 10 The first transformer XFM2 has a second primary coil whose second end is connected to the drain of the second field-effect transistor M2, and the other end is connected to the working voltage VDD, forming a balun structure to realize the conversion of single-ended signals to differential signals.

[0166] In this embodiment, the output signal of the fourth secondary coil of the interstage balun 12 is connected to the input terminal of the second-stage amplifier 13. The second-stage amplifier 13 consists of two differential amplifiers connected in parallel. The first differential amplifier is composed of the third field-effect transistor M3 to the sixth field-effect transistor M6. The third field-effect transistor M3, the fourth field-effect transistor M4, the fifth field-effect transistor M5, and the sixth field-effect transistor M6 respectively form a Cascode structure. The two pairs of Cascode structure amplifiers constitute the first differential amplifier structure. The output of the first differential amplifier is connected to the first primary coil L of the three-port autotransformer XFM1. AP1 The first capacitor C1 is connected in parallel across the two ends of the first primary coil L. AP1 The two ends are used to adjust the impedance and transform it to the optimal output power impedance of the first differential amplifier.

[0167] In this embodiment, the second differential amplifier consists of the seventh field-effect transistor M7 to the tenth field-effect transistor M... 10 Composition: Seventh field-effect transistor M7, Eighth field-effect transistor M8, Ninth field-effect transistor M9, and Tenth field-effect transistor M1 10 Each pair of Cascode amplifiers forms a Cascode structure, and the two pairs of Cascode amplifiers form a second differential amplifier structure. The output of the second differential amplifier is connected to the second stage coil L of the three-port autotransformer XFM1.A2 (Common coil), the second capacitor C2 is connected in parallel with the second stage coil L. A2 The two ends are used to adjust the impedance and transform it to the optimal output power impedance of the second differential amplifier.

[0168] In this embodiment, the power combining network 14 consists of an autotransformer XFM1 and capacitors C1 through C5; the structure of the autotransformer XFM1 is as follows: Figure 6 As shown, the first primary coil L AP1 The first end and the first primary coil L AP1 The second end of both serves as the first input port Port1 of the power combining network 14, while the first primary coil L AP1 The first end and the first primary coil L AP1 The second end serves as the positive (RF1+) and negative (RF1-) terminals of the first input port Port1 of the power combining network 14, respectively; the second stage coil L A2 The first and second stage coils L A2 The second end of both serves as the second input port Port2 of the power combining network 14, while the second stage coil L A2 The first and second stage coils L A2 The second end serves as the positive (RF2+) and negative (RF2-) terminals of the second input port Port2 of the power combining network 14, respectively; the first stage coil L A1 The first and third stage coils L A3 The second end of both serves as the output port Port3 of the power combining network 14, while the first stage coil L A1 The first and third stage coils L A3 The second terminal serves as the positive (PA+) and negative (PA-) terminals of output port 3, respectively. The first capacitor C1 is connected in parallel to the first input port Port1 to tune the impedance, ensuring optimal output load at the drain output terminals of the fourth MOSFET M4 and the sixth MOSFET M6. The second capacitor C2 is connected in parallel to the first input port Port2 to adjust the output impedance of the autotransformer XFM1. VDD in output port Port3 is the DC voltage connection terminal, supplying power to the second-stage amplifier 13. The third capacitor C3 and the fourth capacitor C4 are DC blocking capacitors, used to block DC signals from being output to the next stage.

[0169] In this embodiment, the power amplifier 2 consists of a linearization bias circuit 22 and a differential third-stage amplifier 21. The linearization bias circuit 22 consists of a sixth resistor R. b6 The thirteenth capacitor C 13 The third-stage amplifier 21 consists of transistors Q3 through Q5; the third-stage amplifier 21 consists of differential pair transistors Q1 and Q2, and capacitor C.11 Second inductor L2, twelfth capacitor C 12 The input matching network consists of the first transistor Q1 to the fifth transistor Q5, and the second transformer XFM3 and the fourteenth capacitor C. 14 The fifteenth capacitor C 15 The output balun 3 network on substrate 4 enables the load (seventh resistor R) to be connected. L The output impedance is transformed to the optimal output impedance of the third-stage amplifier 21.

[0170] Compared with the prior art, the hybrid integrated RF power amplifier 100 of this embodiment uses a driver amplifier 1 implemented with CMOS technology and a power amplifier 2 implemented with GaAs HBT technology, and defines the power combining network 14 as an autotransformer XFM1. This allows the hybrid integrated RF power amplifier 100 to improve the output power, output efficiency and linearity of the driver amplifier 1 when using a transformer of the same capacity as the power combining network 14, while reducing the chip area occupied by the power combining network 14 and reducing its insertion loss. In addition, the cost advantage of CMOS technology can be used to reduce the cost of the hybrid integrated RF power amplifier 100.

[0171] The "connection" described above refers to either an "electrical connection" or a "communication connection," meaning that the two components connected to each other are either "electrically connected" or "communication connected."

[0172] The above description is merely an embodiment of the present invention. It should be noted that those skilled in the art can make improvements without departing from the inventive concept of the present invention, but these improvements all fall within the protection scope of the present invention.

Claims

1. A hybrid integrated radio frequency power amplifier, characterized in that, The hybrid integrated RF power amplifier includes a signal input terminal, a driver amplifier implemented using CMOS technology, a power amplifier implemented using GaAsHBT technology, an output balun, and a signal output terminal, all connected in sequence and integrated on the same substrate; the driver amplifier includes a first-stage amplifier, an inter-stage balun, a second-stage amplifier, and a power combining network, all connected in sequence. The input terminal of the first-stage amplifier is connected to the signal input terminal, and is used to amplify the power of the single-ended signal received by the signal input terminal; The input terminal of the interstage balun is connected to the output terminal of the first stage amplifier, and is used to convert the single-ended signal after power amplification by the first stage amplifier into a differential signal, and output a first differential signal and a second differential signal. The second-stage amplifier includes a first amplification unit and a second amplification unit, both composed of complementary metal-oxide-semiconductor (CMOS) semiconductors. The first input terminal and the second input terminal of the first amplification unit are respectively connected to the first output terminal and the second output terminal of the interstage balun, for amplifying the first differential signal and the second differential signal, respectively, and outputting a first amplified differential signal and a second amplified differential signal. The first input terminal and the second input terminal of the second amplification unit are respectively connected to the first output terminal and the second output terminal of the interstage balun, for amplifying the first differential signal and the second differential signal, respectively, and outputting a third amplified differential signal and a fourth amplified differential signal. The power combining network includes an autotransformer with four input terminals and two output terminals; the first input terminal and the second input terminal of the power combining network are respectively connected to the first output terminal and the second output terminal of the first amplification unit, for receiving the first amplified differential signal and the second amplified differential signal, respectively; the third input terminal and the fourth input terminal of the power combining network are respectively connected to the first output terminal and the second output terminal of the second amplification unit, for receiving the third amplified differential signal and the fourth amplified differential signal, respectively; the power combining network combines the first amplified differential signal, the second amplified differential signal, the third amplified differential signal, and the fourth amplified differential signal into a first output signal and a second output signal, and outputs the first output signal and the second output signal through the first output terminal and the second output terminal of the power combining network, respectively; The first input terminal and the second input terminal of the power amplifier are respectively connected to the first output terminal and the second output terminal of the power combining network, and are used to amplify the first output signal and the second output signal synthesized by the power combining network, respectively. The first input terminal and the second input terminal of the output balun are respectively connected to the first output terminal and the second output terminal of the power amplifier, and are used to receive the first output signal and the second output signal after power amplification by the power amplifier, and combine them into a single-ended signal. The signal output terminal is connected to the output terminal of the output balun, and is used to output a single-ended signal synthesized by the output balun.

2. The hybrid integrated RF power amplifier as described in claim 1, characterized in that, The autotransformer includes a first primary coil, and a first secondary coil, a second secondary coil, and a third secondary coil connected in series and coupled to the first primary coil respectively; wherein the first primary coil and the first secondary coil serve as a common winding. The first end of the first primary coil serves as the first input terminal of the power combining network and is connected to the first output terminal of the first amplification unit to receive the first amplified differential signal; the second end of the first primary coil serves as the second input terminal of the power combining network and is connected to the second output terminal of the first amplification unit to receive the second amplified differential signal. The first end of the primary coil serves as the first output end of the power combining network and is connected to the first input end of the power amplifier to output the first output signal. The first end of the second-stage coil serves as the third input terminal of the power combining network and is connected to the first input terminal of the second amplification unit to receive the third amplified differential signal; the second end of the second-stage coil serves as the fourth input terminal of the power combining network and is connected to the second input terminal of the second amplification unit to receive the fourth amplified differential signal; the second end of the second-stage coil is connected to the second end of the first-stage coil. The first end of the third-stage coil is connected to the first end of the second-stage coil, and the second end of the third-stage coil serves as the second output end of the power combining network and is connected to the second input end of the power amplifier to output the second output signal. The center tap of the first primary coil and the center tap of the second primary coil are both connected to the operating voltage.

3. The hybrid integrated RF power amplifier as described in claim 2, characterized in that, The power combining network also includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor; The two ends of the first capacitor are respectively connected to the first end of the first primary coil and the second end of the first primary coil; The two ends of the second capacitor are respectively connected to the first end of the second-stage coil and the second end of the second-stage coil; The two ends of the third capacitor are respectively connected to the first end of the first stage coil and the second end of the third stage coil; The fourth capacitor is connected in series between the first terminal of the primary winding and the first input terminal of the power amplifier. The fifth capacitor is connected in series between the second end of the third stage coil and the second input terminal of the power amplifier.

4. The hybrid integrated RF power amplifier as described in claim 2, characterized in that, The first-stage amplifier includes a first input matching network and a first-stage amplification unit; The first input matching network includes a sixth capacitor, a seventh capacitor, a first resistor, and a first inductor; The first terminal of the sixth capacitor serves as the input terminal of the first-stage amplifier and is connected to the signal output terminal. The first terminal of the seventh capacitor is connected to the second terminal of the sixth capacitor, and the second terminal of the seventh capacitor is grounded. The first end of the first resistor is connected to the second end of the sixth capacitor, and the second end of the first resistor is connected to the first control electrode voltage; The first terminal of the first inductor is connected to the second terminal of the sixth capacitor; The first stage amplification unit includes a first field-effect transistor, a second field-effect transistor, an eighth capacitor, and a second resistor; The gate of the first field-effect transistor is connected to the second terminal of the first inductor, and the source of the first field-effect transistor is grounded; The source of the second field-effect transistor is connected to the drain of the first field-effect transistor, and the drain of the second field-effect transistor serves as the output terminal of the first stage amplifier, which is connected to the input terminal of the interstage balun. The first terminal of the eighth capacitor is connected to the gate of the second field-effect transistor, and the second terminal of the eighth capacitor is grounded. The first end of the second resistor is connected to the gate of the second field-effect transistor, and the second end of the second resistor is connected to the second control voltage.

5. The hybrid integrated RF power amplifier as described in claim 4, characterized in that, The interstage balun includes a first transformer, a ninth capacitor, a tenth capacitor, and a third resistor; The first transformer includes a second primary coil and a fourth secondary coil coupled to the second primary coil; The first end of the second primary coil is connected to the operating voltage, and the second end of the second primary coil serves as the input terminal of the interstage balun. The first end of the fourth secondary coil serves as the first output end of the interstage balun, and is connected to the first input end of the first amplification unit and the first input end of the second amplification unit, respectively; the second end of the fourth secondary coil serves as the second output end of the interstage balun, and is connected to the second input end of the first amplification unit and the second input end of the second amplification unit, respectively. The two ends of the ninth capacitor are respectively connected to the first end of the second primary coil and the second end of the second primary coil; The two ends of the tenth capacitor are respectively connected to the first end of the fourth secondary coil and the second end of the fourth secondary coil; The first end of the third resistor is connected to the center tap of the fourth secondary coil, and the second end of the third resistor is connected to the first control electrode voltage.

6. The hybrid integrated RF power amplifier as described in claim 5, characterized in that, The first amplification unit includes a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, and a fourth resistor; The gate of the third field-effect transistor serves as the first input terminal of the first amplification unit and is connected to the first terminal of the fourth secondary coil to receive the first differential signal. The source of the third field-effect transistor is grounded. The source of the fourth field-effect transistor is connected to the drain of the third field-effect transistor. The drain of the fourth field-effect transistor serves as the first output terminal of the first amplification unit and is connected to the first terminal of the first primary coil to output the first amplified differential signal. The gate of the fifth field-effect transistor serves as the second input terminal of the first amplification unit and is connected to the second terminal of the second primary coil to receive the second differential signal. The source of the fifth field-effect transistor is grounded. The source of the sixth field-effect transistor is connected to the drain of the fifth field-effect transistor, and the gate of the sixth field-effect transistor is connected to the gate of the fourth field-effect transistor. The drain of the sixth field-effect transistor serves as the second output terminal of the first amplification unit and is connected to the second terminal of the first primary coil to output the second amplified differential signal. The first end of the fourth resistor is connected to the gate of the fourth field-effect transistor, and the second end of the fourth resistor is connected to the second control electrode voltage. The second amplification unit includes a seventh field-effect transistor, an eighth field-effect transistor, a ninth field-effect transistor, a tenth field-effect transistor, and a fifth resistor; The gate of the seventh field-effect transistor serves as the first input terminal of the second amplification unit and is connected to the first terminal of the fourth secondary coil to receive the first differential signal. The source of the seventh field-effect transistor is grounded. The source of the eighth field-effect transistor is connected to the drain of the seventh field-effect transistor. The drain of the eighth field-effect transistor serves as the first output terminal of the second amplification unit and is connected to the first terminal of the second stage coil to output the third amplified differential signal. The gate of the ninth field-effect transistor serves as the second input terminal of the second amplification unit and is connected to the second terminal of the second primary coil to receive the second differential signal. The source of the ninth field-effect transistor is grounded. The source of the tenth field-effect transistor is connected to the drain of the ninth field-effect transistor, the gate of the sixth field-effect transistor is connected to the gate of the eighth field-effect transistor, and the drain of the tenth field-effect transistor serves as the second output terminal of the second amplification unit, connected to the second terminal of the second stage coil, for outputting the fourth amplified differential signal. The first end of the fifth resistor is connected to the gate of the eighth field-effect transistor, and the second end of the fifth resistor is connected to the second control electrode voltage.

7. The hybrid integrated RF power amplifier as described in claim 3, characterized in that, The power amplifier includes a third-stage amplifier and a linearization bias circuit. The third-stage amplifier includes a second input matching network, a first transistor, a third input matching network, and a second transistor; the second input matching network includes an eleventh capacitor and a second inductor; the third input matching network includes a twelfth capacitor and a third inductor; The first terminal of the eleventh capacitor serves as the first input terminal of the power amplifier and is connected to the first terminal of the first stage coil to receive the first output signal. The first terminal of the second inductor is connected to the first terminal of the eleventh capacitor, and the second terminal of the second inductor is grounded. The base of the first transistor is connected to the second terminal of the eleventh capacitor, the emitter of the first transistor is grounded, and the collector of the first transistor serves as the first output terminal of the power amplifier, which is connected to the first input terminal of the output balun. The first terminal of the twelfth capacitor serves as the second input terminal of the power amplifier and is connected to the second terminal of the third stage coil to receive the second output signal. The first terminal of the third inductor is connected to the first terminal of the twelfth capacitor, and the second terminal of the third inductor is grounded. The base of the second transistor is connected to the second terminal of the twelfth capacitor, the emitter of the second transistor is grounded, and the collector of the second transistor serves as the second output terminal of the power amplifier, which is connected to the second input terminal of the output balun. The output of the linearization bias circuit is connected to the base of the first transistor and the base of the second transistor, respectively.

8. The hybrid integrated RF power amplifier as described in claim 7, characterized in that, The linearization bias circuit includes a third transistor, a thirteenth capacitor, a fourth transistor, a sixth resistor, and a fifth transistor. The emitter of the third transistor serves as the output terminal of the linearization bias circuit, and the collector of the third transistor is connected to the power supply voltage. The first terminal of the thirteenth capacitor is connected to the base of the third transistor, and the second terminal of the thirteenth capacitor is grounded. The base and collector of the fourth transistor are both connected to the base of the third transistor. The first end of the sixth resistor is connected to the base of the third transistor, and the second end of the sixth resistor is connected to the third control voltage. The base and collector of the fifth transistor are both connected to the emitter of the fourth transistor, and the emitter of the fifth transistor is grounded.

9. The hybrid integrated RF power amplifier as described in claim 8, characterized in that, The output balun includes a second transformer, a fourteenth capacitor, and a fifteenth capacitor; The second transformer includes a third primary coil and a fifth secondary coil coupled to the third primary coil; The first end of the third primary coil serves as the first input terminal of the output balun, used to receive the first output signal after power amplification by the power amplifier. The second end of the third primary coil serves as the second input terminal of the output balun, used to receive the second output signal after power amplification by the power amplifier. The middle tap of the third primary coil is connected to the power supply voltage. The two ends of the fourteenth capacitor are respectively connected to the first end of the third primary coil and the second end of the third primary coil; The first end of the fifth secondary coil serves as the output end of the output balun and is connected to the signal output end; the second end of the fifth secondary coil is grounded. The first terminal of the fifteenth capacitor is connected to the first terminal of the fifth secondary coil, and the second terminal of the fifteenth capacitor is grounded.

10. The hybrid integrated RF power amplifier as described in claim 1, characterized in that, The hybrid integrated RF power amplifier also includes a seventh resistor, the first end of which is connected to the signal output terminal, and the second end of which is grounded.

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