An instruction decoding module, a generation method and device thereof, and a chip architecture simulator

Abstract

This specification discloses an instruction decoding module and its generation method, apparatus, and chip architecture simulator. The method for generating the instruction decoding module provides a way to generate the module based on a two-level decoding table using a computing device. This reduces the manpower required and resource consumption during the development of microarchitecture hardware, thereby improving the development efficiency. Specifically, the method first determines the grouped feature codes corresponding to each code position in the instruction encoding from the instruction feature set. Then, it groups the instruction encodings in the two-level decoding table according to the grouped feature codes to obtain an encoding search tree. Finally, the instruction decoding module is generated based on this encoding search tree. The entire generation process is simple and improves the generation efficiency of the instruction decoding module.

Description

Technical Field

[0001] This specification relates to the field of semiconductor technology, specifically to software simulation technology for computer architecture in the field of semiconductor technology, and more specifically to an instruction decoding module and its generation method, apparatus, and chip architecture simulator. Background Technology

[0002] Computer system architecture simulators include system-level architecture simulators and processor microarchitecture simulators. Processor microarchitecture simulators are software tools used to assist in the design, verification, and optimization of microarchitecture hardware.

[0003] In the process of designing and optimizing microarchitecture hardware using processor microarchitecture simulators, it is often necessary to extend the instructions. This requires designers to make significant modifications to the processor microarchitecture simulator according to hardware iterations, which consumes a lot of development resources. Summary of the Invention

[0004] To address the aforementioned technical issues, this specification provides an instruction decoding module and its generation method, apparatus, and chip architecture simulator, aiming to automatically generate instruction decoding modules using computing devices, thereby reducing the manpower required in the microarchitecture hardware development process and reducing the consumption of development resources.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0006] Firstly, embodiments of this specification provide a method for generating an instruction decoding module, applied to a computing device. The method for generating the instruction decoding module includes:

[0007] Obtain a secondary decoding table, which includes the correspondence between instruction codes and the information carried by the instruction codes;

[0008] In the instruction feature set, group feature codes corresponding to each code position in the instruction encoding are determined. The group feature codes are used to describe the code value characteristics of the code position corresponding to the group feature codes in the instruction encoding. The instruction feature set includes multiple group feature codes.

[0009] The instruction codes in the secondary decoding table are grouped according to the grouping feature code to obtain an encoding search tree. In the encoding search tree, the grouping feature code corresponds to the non-leaf node of the encoding search tree, and the leaf node of the encoding search tree includes at least one of the instruction codes.

[0010] The instruction decoding module is generated based on the encoding search tree.

[0011] In some implementations, the instruction feature set includes multiple sets of candidate feature codes, each set of candidate feature codes includes multiple candidate feature codes, and any one of the candidate feature codes in each set of candidate feature codes corresponds to a multiple code position in the instruction encoding;

[0012] The candidate feature code is used to describe the code value characteristics of the multi-bit code position corresponding to the candidate feature code, and the group feature code is determined from multiple candidate feature codes in each group of candidate feature codes.

[0013] In some implementations, determining the grouped feature codes corresponding to each code position in the instruction encoding within the instruction feature set includes:

[0014] In each group of candidate feature codes, the candidate feature code with the smallest grouping difference is determined as the grouping feature code corresponding to the non-leaf node of the encoding search tree. The grouping difference represents the difference in the number of instruction codes and the number of identical instruction codes between the two nodes obtained after grouping according to the candidate feature codes.

[0015] In some implementations, the grouping difference is equal to the weighted sum of the difference in the number of instruction codes between the two nodes obtained after grouping according to the candidate feature codes and the number of identical instruction codes.

[0016] In some implementations, in the grouping difference degree, a first weight is greater than a second weight, wherein the first weight is the weight of the number of identical instruction codes in two nodes obtained after grouping according to the candidate feature codes, and the second weight is the weight of the difference in the number of instruction codes in two nodes obtained after grouping according to the candidate feature codes.

[0017] In some implementations, the instruction encoding is an N-bit instruction encoding, and the candidate feature code corresponds to the position of M consecutive code bits in the instruction encoding, where N and M are both integers greater than 1, and N is greater than M.

[0018] In some implementations, N is divisible by M.

[0019] In some implementations, generating the instruction decoding module based on the encoding search tree includes:

[0020] According to the hierarchical order of the nodes in the encoding search tree, each node of the encoding search tree is compiled into a function to obtain the instruction decoding module.

[0021] In some implementations, compiling each node of the encoding search tree into a function according to the hierarchical order of the nodes in the encoding search tree to obtain the instruction decoding module includes:

[0022] According to the hierarchical order of the nodes of the encoding search tree, the non-leaf nodes of the encoding search tree are compiled into judgment functions, and the leaf nodes of the encoding search tree are compiled into return functions to obtain the instruction decoding module;

[0023] The judgment function is used to place the instruction code in the non-leaf node into two nodes at the next level, based on whether the instruction code in the non-leaf node matches the group feature code corresponding to the non-leaf node.

[0024] The return function is used to return the instruction code information carried in the leaf node corresponding to the instruction code.

[0025] Secondly, embodiments of this specification provide an instruction decoding module, including: a plurality of functions determined according to an encoding search tree, wherein each function corresponds one-to-one with a node of the encoding search tree, and the calling relationship of the plurality of functions is determined according to the node order of the encoding search tree;

[0026] The encoding search tree is obtained by grouping the instruction codes in the secondary decoding table according to the group feature code. The group feature code is used to describe the code value characteristics of the code position corresponding to the group feature code in the instruction code. The secondary decoding table includes the correspondence between the instruction code and the information carried by the instruction code.

[0027] Thirdly, embodiments of this specification provide a chip architecture simulator, including the instruction decoding module as described above.

[0028] Fourthly, embodiments of this specification provide an apparatus for generating an instruction decoding module, applied to a computing device. The apparatus for generating the instruction decoding module includes:

[0029] The acquisition module is used to acquire a secondary decoding table, which includes the correspondence between instruction codes and the information carried by the instruction codes;

[0030] The feature module is used to determine, in the instruction feature set, group feature codes corresponding to each code position in the instruction encoding, wherein the group feature codes are used to describe the code value characteristics of the code position corresponding to the group feature codes in the instruction encoding; the instruction feature set includes multiple group feature codes;

[0031] A grouping module is used to group the instruction codes in the secondary decoding table according to the grouping feature code to obtain an encoding search tree. In the encoding search tree, the grouping feature code corresponds to a non-leaf node of the encoding search tree, and the leaf node of the encoding search tree includes at least one instruction code.

[0032] A generation module is used to generate the instruction decoding module based on the encoding search tree.

[0033] Fifthly, embodiments of this specification provide an electronic device, including: a processor and a memory;

[0034] The memory is connected to the processor and is used to store computer programs;

[0035] The processor is configured to implement the instruction decoding module generation method described above by running a computer program stored in the memory.

[0036] Sixthly, embodiments of this specification provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method for generating the instruction decoding module as described above.

[0037] In a seventh aspect, embodiments of this specification provide a computer program product or a computer program, the computer program product including a computer program stored in a computer-readable storage medium; the processor of the computer device reads the computer program from the computer-readable storage medium, and when the processor executes the computer program, it implements the steps of the above-described method for generating the instruction decoding module.

[0038] As can be seen from the above technical solutions, the embodiments of this specification provide an instruction decoding module and its generation method, apparatus, and chip architecture simulator. The method for generating the instruction decoding module provides a way to generate the module based on a two-level decoding table using a computing device. This reduces the manpower required for microarchitecture hardware development, lowers development resource consumption, and improves development efficiency. Specifically, the method first determines the grouped feature codes corresponding to each code position in the instruction encoding within the instruction feature set. Then, it groups the instruction encodings in the two-level decoding table according to the grouped feature codes to obtain an encoding search tree. Finally, the instruction decoding module is generated based on this encoding search tree. The entire generation process is simple and beneficial for improving the generation efficiency of the instruction decoding module. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0040] Figure 1This specification provides a feasible application scenario for a method for generating an instruction decoding module, as illustrated in the embodiments of this specification.

[0041] Figure 2 A flowchart illustrating a method for generating an instruction decoding module provided in an embodiment of this specification;

[0042] Figure 3 A schematic diagram of an instruction encoding provided for an embodiment of this specification;

[0043] Figure 4 This is a schematic diagram illustrating how a secondary decoding table is grouped to obtain an encoding search tree, as provided in an embodiment of this specification.

[0044] Figure 5 A schematic diagram of the structure of an instruction decoding module generation device provided in an embodiment of this specification;

[0045] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this specification. Detailed Implementation

[0046] Unless otherwise defined, the technical or scientific terms used in the embodiments of this specification shall have the ordinary meaning understood by one of ordinary skill in the art to which this specification pertains. The terms "first," "second," and similar terms used in the embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to avoid confusion of constituent elements.

[0047] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0048] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0049] Exemplary scenario

[0050] refer to Figure 1 , Figure 1 This document illustrates possible application scenarios for the instruction decoding module generation method provided in the embodiments of this specification. Figure 1 This scenario involves using a microarchitecture simulator to assist in processor core design iteration. In this scenario, both simulator 1 and simulator 2 refer to the microarchitecture simulator. The processor core design scheme (hereinafter referred to as the core design scheme) needs to be aligned with the microarchitecture simulator software (i.e., the software logic is consistent with the hardware logic). A series of verification and optimization processes, such as prefetching, caching, decoding, issuing, execution, and renaming, are performed using the microarchitecture simulator. Based on the verification and optimization results, verification and optimization suggestions are generated to guide the optimization and adjustment of the core design scheme. For example, in... Figure 1 In the process, core design scheme 1 is aligned with the software of simulator 1, allowing simulator 1 to perform a series of verification and optimizations on core design scheme 1, obtaining verification and optimization suggestions to guide the optimization and adjustment of core design scheme 1. After the version iteration of core design scheme 1 yields core design scheme 2, the above steps need to be repeated. Core design scheme 2 is aligned with the software of simulator 2, allowing simulator 2 to perform a series of verification and optimizations on core design scheme 2, obtaining verification and optimization suggestions to guide the optimization and adjustment of core design scheme 2.

[0051] As described in the background section, during the version iteration of the core design scheme, the instruction decoding module of the simulator needs to be significantly modified along with the version iteration of the core design scheme, consuming a lot of development resources. For example, taking the commonly used microarchitecture simulation open source project Gem5 as an example, simulators based on Gem5 need to invest a lot of manpower and time in instruction decoding alignment when facing this situation.

[0052] Therefore, the method for generating the instruction decoding module provided in the embodiments of this specification can easily and quickly generate the instruction decoding module based on the computing device, which is beneficial to improving the generation efficiency of the instruction decoding module and reducing the development resources required in the process of generating the instruction decoding module.

[0053] The method for generating the instruction decoding module provided in the embodiments of this specification will now be described exemplarily with reference to the accompanying drawings.

[0054] Exemplary methods

[0055] This specification provides an embodiment of a method for generating an instruction decoding module, applicable to computing devices, such as... Figure 2 As shown, the method for generating the instruction decoding module includes:

[0056] S101: Obtain the secondary decoding table, which includes the correspondence between instruction codes and the information carried by the instruction codes.

[0057] The size of the Level 2 decoding table is determined by the hardware design (e.g., processor core design). The Level 2 decoding table typically includes the same number of instruction codes required in the hardware design. The process of obtaining the Level 2 decoding table can involve the hardware design team inputting it through an external interface provided by the computing device, the computing device reading it from a pre-stored storage device, or other computing devices transmitting it to the computing device responsible for executing the instruction decoding module's generation method. This specification does not limit the specific method used; it depends on the actual situation.

[0058] S102: In the instruction feature set, determine the group feature code corresponding to each code position in the instruction encoding. The group feature code is used to describe the code value characteristics of the code position corresponding to the group feature code in the instruction encoding. The instruction feature set includes multiple group feature codes.

[0059] refer to Figure 3 , Figure 3 This paper illustrates a feasible structure for a 32-bit instruction encoding. Each bit of the 32-bit instruction encoding can have a value of 0, 1, or ?. The ? indicates that the value at that code position can be either 0 or 1. A block feature code corresponds to a specific code position in the instruction encoding and is used to describe the code value characteristics at that corresponding code position. For example, assuming the code positions in the 32-bit instruction encoding are bits 0 to 31, and the block feature code length is 4 bits, then the block feature codes corresponding to different code positions can be used to describe the code value characteristics of bits 0 to 3, bits 4 to 7, bits 8 to 11... bits 24 to 27, and bits 28 to 31 of the instruction encoding, respectively. Each bit of the block feature code has three possible values: 0, 1, and ?. The ? indicates that the value at that code position can be either 0 or 1.

[0060] S103: Group the instruction codes in the secondary decoding table according to the grouping feature code to obtain an encoding search tree. In the encoding search tree, the grouping feature code corresponds to the non-leaf nodes of the encoding search tree, and the leaf nodes of the encoding search tree include at least one of the instruction codes.

[0061] Once the grouping feature code is determined, the instruction codes in the secondary decoding table can be grouped according to the determined grouping feature code. Figure 4 A feasible process for grouping is illustrated in an exemplary manner, in Figure 4In the secondary decoding table, there are a total of six 8-bit instruction codes: 1001? ? ? ?, 11? ? 0010, 1011? ? ? ?, 11? ? 0011, 0100? ? ? 1, and 0100? ? 1?. The group feature code is a 4-bit feature code, corresponding to bits 0-3 and bits 4-7 of the instruction code, respectively. Specifically, the group feature code used to describe the value characteristics of bits 0-3 of the instruction code can be 11? ?, 01? ?, and ? ? 11. The group feature code used to describe the value characteristics of bits 4-7 of the instruction code can be ? ? 1. Therefore, in the grouping process, the six instruction codes are first classified using the group feature code 11? ?, satisfying the value characteristic 11? ? ? ? ? ?. The instruction code that does not satisfy the value characteristic 11 is assigned to the left node of the second level of the encoding search tree, while the instruction code that does not satisfy the value characteristic 11 is assigned to the right node of the second level of the encoding search tree. At this time, the left node of the second level has two instruction codes, 11? ? 0010 and 11? ? 0011, and the right node of the second level has four instruction codes, 1001? ? ? ?, 1011? ? ? ?, 0100? ? ? 1 and 0100? ? 1?.

[0062] The nodes of the second level are further grouped. The left nodes of the second level are grouped using the grouping feature code 1, which describes the value characteristics of bits 4-7. Instruction codes satisfying the value characteristic 1 are assigned to the first leaf node from the left of the third level (11??0010), while instruction codes not satisfying the value characteristic 1 are assigned to the second leaf node from the left of the third level (11??0011). The right nodes of the second level are grouped using the grouping feature code 01, which describes the value characteristics of bits 0-3. Instruction codes satisfying the value characteristic 01? ? ? ? ? are assigned to the third leaf node from the left of the third level (0100???1 and 0100???1?), while instruction codes not satisfying the value characteristic 01? ? ? ? ? The instruction codes are assigned to the fourth leaf node from the left in the third level (1001??? and 1011???).

[0063] At this point, the instruction code in the third leaf node from the left of the third level cannot be further divided. The instruction code in the fourth node from the left of the third level is then grouped using the grouping feature code ? ? 11 that describes the value characteristics of bits 0-3. Instruction codes satisfying ? ? 11 ? ? ? are assigned to the left leaf node of the fourth level (1011 ????), while those not satisfying ? ? 11 ? ? ? are assigned to the right leaf node of the fourth level (1001 ????). This completes the grouping process and yields the encoding search tree.

[0064] Regarding how to determine whether the instruction codes within a node can be further divided, if two or more instruction codes cannot be distinguished by the values ​​at certain code positions, these instruction codes are considered indivisible. For example, the instruction codes 0? and 1? cannot be distinguished by the values ​​at certain code positions.

[0065] In a two-level decoding table, the indivisible cases usually fall into two categories:

[0066] 1. Both have the exact same instruction code, for example (10110111, 10110111). This is usually an instruction alias. They are actually the same instruction code.

[0067] 2. The two instruction codes are not completely identical, but indistinguishable, for example (???1, ???1?, ???1??, 1???). This situation usually indicates a further subdivision of the operands of an instruction code in the second-level decoder table. Objectively, a single 32-bit instruction code will not match two instruction codes simultaneously. In other words, in this case, the only valid instructions are (0001, 0010, 0100, 1000).

[0068] S104: Generate the instruction decoding module based on the encoding search tree.

[0069] After obtaining the encoding search tree, an instruction decoding module describing the encoding search tree can be generated based on the grouping logic of the encoding search tree, thus realizing the generation of the instruction decoding module.

[0070] An exemplary embodiment of this specification provides a feasible method for determining grouped feature codes from an instruction feature set. Specifically, the instruction feature set includes multiple sets of candidate feature codes, each set of candidate feature codes includes multiple candidate feature codes, and any one of the candidate feature codes in each set corresponds to a multiple code position in the instruction encoding;

[0071] The candidate feature code is used to describe the code value characteristics of the multi-bit code position corresponding to the candidate feature code, and the group feature code is determined from multiple candidate feature codes in each group of candidate feature codes.

[0072] For example, when the instruction encoding is 32 bits and the block feature code is 4 bits, there are a total of 80 candidate features describing a specific code position (e.g., bits 0-3). (Each bit has 3 possible values, so the 4-bit block feature code has a total of 3 possible values.) 4= 81 types, after removing the invalid feature "???", there are a total of 80. Therefore, there are a total of 640 candidate feature codes describing all positions in a 32-bit instruction code. From the above description, we can see that candidate feature codes are usually used to describe the code value characteristics of several consecutive bit positions in an instruction code. Correspondingly, grouped feature codes are also usually used to describe the code value characteristics of several consecutive bit positions in an instruction code, thus reducing the complexity of grouped feature code partitioning.

[0073] In step S102, at least one group feature code needs to be determined from a set of candidate feature codes describing specific code positions in the instruction code as a group feature code for subsequent grouping of the instruction code. Continuing with the example above, if the instruction code is 32 bits long and the candidate feature codes are 4 bits long, the instruction code is divided into 4-bit segments. Each 4-bit code position corresponds to 80 candidate feature codes. These 80 candidate feature codes form a set. At least one group feature code needs to be determined from these 80 candidate feature codes corresponding to each 4-bit code position to describe that code position, proceeding to the subsequent grouping steps. For example, for code positions 0-3, the corresponding candidate feature codes could be: "000?", "1??1", "??0?", and "1000", totaling 80. At least one group feature code describing code positions 0-3 can be determined from these 80 candidate feature codes according to a certain determining logic, so that the determined group feature code can describe code positions 0-3 in the subsequent grouping process. For example, in... Figure 3 In this process, at least eight block feature codes, from block feature code 1 to block feature code 8, are identified to describe the code value characteristics of positions 0-3, 4-7...24-27, and 28-31 of the 32-bit instruction code, respectively. Of course, the number of block feature codes used to describe positions 0-3 can be more than one.

[0074] In this embodiment, in the instruction feature set, a set of candidate feature codes is designed for the same multi-bit code position of the instruction encoding. The set of candidate feature codes includes multiple candidate feature codes. When the generation method of the instruction decoding module is applied to different hardware projects, a group of feature codes that are more suitable for describing each code position of the instruction encoding in the secondary decoding table can be selected from the multiple candidate feature codes, thereby improving the applicability of the generation method of the instruction decoding module.

[0075] To improve the decoding efficiency and reduce the size of the generated instruction decoding module, the depth of the encoding search tree can be limited. Specifically, in one embodiment of this specification, in each group of candidate feature codes, the candidate feature code with the smallest grouping difference is determined as the grouping feature code corresponding to the non-leaf node of the encoding search tree. The grouping difference characterizes the difference in the number of instruction codes and the number of identical instruction codes between the two nodes obtained after grouping according to the candidate feature codes.

[0076] In some cases, when grouping according to certain grouping feature codes, two instruction codes may be assigned to two nodes simultaneously. For example, for instruction code 11? ?, the grouping feature code ? ? 00 will cause this instruction to be assigned to two nodes at the same time.

[0077] To minimize the difference in the number of instruction codes between the two grouped nodes and to minimize the number of instruction codes simultaneously assigned to both nodes, this embodiment introduces the concept of grouping difference degree. Minimizing the grouping difference degree means that the number of instruction codes in the two grouped nodes is as uniform as possible, and the number of instruction codes simultaneously assigned to both nodes is as small as possible. Determining the grouping feature codes corresponding to each non-leaf node from the candidate feature codes according to the principle of minimizing grouping difference degree can effectively limit the depth of the encoding search tree, thereby improving the decoding efficiency of the generated instruction decoding module and reducing the size of the instruction decoding module.

[0078] In some cases, it is necessary to emphasize a specific factor in the grouping difference (i.e., the difference in the number of instruction codes between two nodes or the number of identical instruction codes between two nodes) to meet different requirements of the encoding search tree. Therefore, in some embodiments, the grouping difference is equal to the weighted sum of the difference in the number of instruction codes between two nodes and the number of identical instruction codes obtained after grouping according to the candidate feature codes. That is, in this embodiment, weights are assigned to the difference in the number of instruction codes between two nodes and the number of identical instruction codes, so that the determination of the grouping difference can emphasize different factors according to actual needs, meet the different requirements of different hardware design projects, and improve the applicability of the method.

[0079] In one embodiment of this specification, to avoid the possibility of continuously selecting candidate feature codes that allow all instruction codes to be assigned to two nodes simultaneously during grouping, which could result in a very deep (multiple levels) encoding search tree and even prevent the tree from being constructed, this embodiment uses a first weight greater than a second weight in the grouping difference. The first weight is the weight of the number of identical instruction codes in the two nodes obtained after grouping according to the candidate feature codes, and the second weight is the weight of the difference in the number of instruction codes in the two nodes obtained after grouping according to the candidate feature codes.

[0080] That is, the group difference satisfies the following formula (1):

[0081] P = α|Size1 - Size2| + βSize repeat (1);

[0082] Where α and β are the second weight and the first weight, respectively. Size1 and Size2 represent the number of instruction codes in the two nodes after grouping according to the candidate feature codes, and |Size1-Size2| represents the difference in the number of instruction codes in the two nodes after grouping according to the candidate feature codes. repeat This represents the number of identical instruction codes in the two nodes obtained after grouping according to the candidate feature codes. In this embodiment, α is less than β, which avoids the problem of continuously selecting candidate feature codes that allow all instruction codes to be assigned to both nodes simultaneously as grouping feature codes during the grouping process.

[0083] As mentioned above, in order to reduce the complexity of partitioning candidate feature codes and group feature codes and improve grouping efficiency, the candidate feature codes and group feature codes are used to describe the corresponding positions of consecutive multiple code bits in the instruction encoding. That is, in one embodiment of this specification, the instruction encoding is an N-bit instruction encoding, and the candidate feature codes correspond to the positions of consecutive M code bits in the instruction encoding, where N and M are both integers greater than 1, and N is greater than M.

[0084] That is, when the instruction encoding is 32 bits, the alternative feature codes can be 4 bits, 8 bits, or other feature codes less than 32 bits. To improve grouping efficiency, in one embodiment of this specification, N is divisible by M.

[0085] In one embodiment of this specification, a feasible method for generating an instruction decoding module based on an encoding search tree is provided. Specifically, generating the instruction decoding module based on the encoding search tree includes:

[0086] According to the hierarchical order of the nodes in the encoding search tree, each node of the encoding search tree is compiled into a function to obtain the instruction decoding module.

[0087] Compiling each node of the encoded search tree into a function means compiling the actions of the grouping or instruction decoding of each node, which encode the information carried by the instruction encoding, into the corresponding function. This generation method is simple, easy to implement, and has the characteristics of fast generation speed.

[0088] Specifically, in one embodiment of this specification, compiling each node of the encoding search tree into a function according to the hierarchical order of the nodes of the encoding search tree to obtain the instruction decoding module includes:

[0089] According to the hierarchical order of the nodes in the encoding search tree, the non-leaf nodes of the encoding search tree are compiled into judgment functions, and the leaf nodes of the encoding search tree are compiled into return functions to obtain the instruction decoding module.

[0090] The judgment function is used to place the instruction code in the non-leaf node into two nodes at the next level based on whether the instruction code in the non-leaf node matches the group feature code corresponding to the non-leaf node.

[0091] The return function is used to return the instruction code information carried in the leaf node corresponding to the instruction code.

[0092] When a leaf node contains multiple instruction codes, it is necessary to determine which instruction code should be returned based on the matching between the actual input instruction code and the instruction codes in the leaf node.

[0093] In this embodiment, generating the instruction decoding module through simple judgment and return functions helps to improve the generation speed of the instruction decoding module and reduce the logical complexity of the instruction decoding module itself.

[0094] Exemplary instruction decoding module and chip architecture simulator

[0095] Accordingly, embodiments of this specification also provide an instruction decoding module, including: a plurality of functions determined according to an encoding search tree, wherein the functions correspond one-to-one with the nodes of the encoding search tree, and the calling relationship of the plurality of functions is determined according to the node order of the encoding search tree;

[0096] The encoding search tree is obtained by grouping the instruction codes in the secondary decoding table according to the group feature code. The group feature code is used to describe the code value characteristics of the code position corresponding to the group feature code in the instruction code. The secondary decoding table includes the correspondence between the instruction code and the information carried by the instruction code.

[0097] Accordingly, this specification also provides a chip architecture simulator, including the instruction decoding module as described in the above embodiments.

[0098] The instruction decoding module provided in this embodiment belongs to the same application concept as the instruction module generation method provided in the above embodiments of this specification. It can be an instruction decoding module generated based on the instruction module generation method provided in the above embodiments. Technical details not described in detail in this embodiment can be found in the specific processing content of the instruction decoding module generation method provided in the above embodiments of this specification, and will not be repeated here.

[0099] Exemplary device

[0100] Accordingly, embodiments of this specification also provide an apparatus for generating an instruction decoding module, such as... Figure 5 As shown, the instruction decoding module generation device, applied to a computing device, includes:

[0101] The acquisition module 100 is used to acquire a secondary decoding table, wherein the secondary decoding table includes the correspondence between instruction codes and the information carried by the instruction codes;

[0102] Feature module 200 is used to determine, in the instruction feature set, group feature codes corresponding to each code position in the instruction encoding, wherein the group feature codes are used to describe the code value characteristics of the code position corresponding to the group feature codes in the instruction encoding; the instruction feature set includes multiple group feature codes;

[0103] Grouping module 300 is used to group the instruction codes in the secondary decoding table according to the grouping feature code to obtain an encoding search tree. In the encoding search tree, the grouping feature code corresponds to the non-leaf node of the encoding search tree, and the leaf node of the encoding search tree includes at least one of the instruction codes.

[0104] The generation module 400 is used to generate the instruction decoding module based on the encoding search tree.

[0105] The instruction decoding module generation apparatus provided in this embodiment belongs to the same concept as the instruction decoding module generation method provided in the above embodiments of this specification. It can execute the instruction decoding module generation method provided in any of the above embodiments of this specification and has the corresponding functional modules and beneficial effects of executing the instruction decoding module generation method. Technical details not described in detail in this embodiment can be found in the specific processing content of the instruction decoding module generation method provided in the above embodiments of this specification, and will not be repeated here.

[0106] Exemplary electronic devices

[0107] Another embodiment of this specification also provides an electronic device, see [link to documentation]. Figure 6 As shown, an exemplary embodiment of this specification also provides an electronic device, including: a memory and a processor, the memory storing a computer program, the processor executing the computer program and performing steps in the method for generating an instruction decoding module according to various embodiments of this specification as described in the foregoing embodiments.

[0108] The internal structure of the electronic device can be as follows: Figure 6 As shown, the electronic device includes a processor, memory, network interface, and input device connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it follows the steps of the instruction decoding module generation method according to various embodiments of this specification described in the above embodiments.

[0109] The processor may include the main processor, as well as baseband chips, modems, etc.

[0110] The memory stores a computer program that executes the technical solution of this invention, and may also store an operating system and other key business functions. Specifically, the computer program may include program code, which includes computer operation instructions. More specifically, the memory may include read-only memory (ROM), other types of static storage devices capable of storing static information and instructions, random access memory (RAM), other types of dynamic storage devices capable of storing information and instructions, disk storage, flash memory, etc.

[0111] The processor can be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present invention. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0112] Input devices may include devices that receive data and information input by the user, such as keyboards, mice, cameras, scanners, light pens, voice input devices, touch screens, pedometers, or gravity sensors.

[0113] Output devices may include devices that allow information to be output to the user, such as displays, printers, speakers, etc.

[0114] The communication interface may include any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0115] The processor executes the computer program stored in the memory and calls other devices, which can be used to implement the various steps of any of the instruction decoding module generation methods provided in the above embodiments of this specification.

[0116] The electronic device may also include a display component and a voice component. The display component may be a liquid crystal display screen or an e-ink display screen. The input device of the electronic device may be a touch layer covering the display component, or a button, trackball or touchpad set on the casing of the electronic device, or an external keyboard, touchpad or mouse, etc.

[0117] Those skilled in the art will understand that Figure 6 The structures shown are merely block diagrams of some structures related to the solutions described in this specification and do not constitute a limitation on the electronic devices to which the solutions described in this specification are applied. Specific electronic devices may include more or fewer components than shown in the figures, or may combine certain components, or may have different component arrangements. In some cases, the electronic device may also be referred to as a computing device.

[0118] Exemplary computer program products and computer-readable storage media

[0119] In addition to the methods and devices described above, the method for generating an instruction decoding module provided in the embodiments of this specification can also be a computer program product, which includes a computer program that, when run by a processor, causes the processor to perform the steps in the method for generating an instruction decoding module according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0120] The computer program product described herein can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments described herein. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0121] Furthermore, embodiments of this specification also provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor of the steps in the method for generating an instruction decoding module according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0122] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the implementation methods of this specification, and are not intended to limit the scope of this specification.

[0123] It is understood that in the various embodiments described in this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments described in this specification.

[0124] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0125] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0126] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0127] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0128] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0129] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0130] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0131] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0132] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0133] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0134] The above description is merely a specific embodiment of this specification, but the scope of protection of this specification is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this specification should be determined by the scope of the claims.

Claims

1. A method for generating an instruction decoding module, characterized in that, Applied to computing devices, the method for generating the instruction decoding module includes: Obtain a secondary decoding table, which includes the correspondence between instruction codes and the information carried by the instruction codes; In the instruction feature set, group feature codes corresponding to each code position in the instruction encoding are determined. The group feature codes are used to describe the code value characteristics of the code position corresponding to the group feature codes in the instruction encoding. The instruction feature set includes multiple group feature codes. The code position corresponding to the group feature code refers to the correspondence between the group feature code and a specific code position in the instruction encoding. The instruction codes in the secondary decoding table are grouped according to the grouping feature code to obtain an encoding search tree. In the encoding search tree, the grouping feature code corresponds to the non-leaf node of the encoding search tree, and the leaf node of the encoding search tree includes at least one of the instruction codes. The instruction decoding module is generated based on the encoding search tree.

2. The method according to claim 1, characterized in that, The instruction feature set includes multiple sets of candidate feature codes, each set of candidate feature codes includes multiple candidate feature codes, and any one of the candidate feature codes in each set of candidate feature codes corresponds to multiple code positions in the instruction encoding; The candidate feature code is used to describe the code value characteristics of the multi-bit code position corresponding to the candidate feature code, and the group feature code is determined from multiple candidate feature codes in each group of candidate feature codes.

3. The method according to claim 2, characterized in that, The step of determining the grouped feature code corresponding to each code position in the instruction encoding within the instruction feature set includes: In each group of candidate feature codes, the candidate feature code with the smallest grouping difference is determined as the grouping feature code corresponding to the non-leaf node of the encoding search tree. The grouping difference represents the difference in the number of instruction codes and the number of identical instruction codes between the two nodes obtained after grouping according to the candidate feature codes.

4. The method according to claim 3, characterized in that, The grouping difference is equal to the weighted sum of the difference in the number of instruction codes between the two nodes obtained after grouping according to the candidate feature codes and the number of identical instruction codes.

5. The method according to claim 4, characterized in that, In the grouping difference degree, the first weight is greater than the second weight. The first weight is the weight of the number of identical instruction codes in the two nodes obtained after grouping according to the candidate feature codes, and the second weight is the weight of the difference in the number of instruction codes in the two nodes obtained after grouping according to the candidate feature codes.

6. The method according to claim 2, characterized in that, The instruction encoding is an N-bit instruction encoding, and the candidate feature code corresponds to the position of M consecutive code bits in the instruction encoding. N and M are both integers greater than 1, and N is greater than M.

7. The method according to claim 6, characterized in that, N is divisible by M.

8. The method according to any one of claims 1 to 7, characterized in that, The step of generating the instruction decoding module based on the encoding search tree includes: According to the hierarchical order of the nodes in the encoding search tree, each node of the encoding search tree is compiled into a function to obtain the instruction decoding module.

9. The method according to claim 8, characterized in that, The step of compiling each node of the encoding search tree into a function according to the hierarchical order of the nodes in the encoding search tree to obtain the instruction decoding module includes: According to the hierarchical order of the nodes of the encoding search tree, the non-leaf nodes of the encoding search tree are compiled into judgment functions, and the leaf nodes of the encoding search tree are compiled into return functions to obtain the instruction decoding module; The judgment function is used to place the instruction code in the non-leaf node into two nodes at the next level, based on whether the instruction code in the non-leaf node matches the group feature code corresponding to the non-leaf node. The return function is used to return the instruction code information carried in the leaf node corresponding to the instruction code.

10. An instruction decoding module, characterized in that, include: Multiple functions are determined according to the encoding search tree, and each function corresponds one-to-one with a node in the encoding search tree. The calling relationship of the multiple functions is determined according to the node order of the encoding search tree. The encoding search tree is obtained by grouping the instruction codes in the secondary decoding table according to the group feature code. The group feature code is used to describe the code value characteristics of the code position corresponding to the group feature code in the instruction code. The secondary decoding table includes the correspondence between the instruction code and the information carried by the instruction code. The code position corresponding to the group feature code refers to the correspondence between the group feature code and a specific code position of the instruction code.

11. A chip architecture simulator, characterized in that, include: The instruction decoding module as described in claim 10.

12. A device for generating an instruction decoding module, characterized in that, Applied to computing devices, the instruction decoding module generation apparatus includes: The acquisition module is used to acquire a secondary decoding table, which includes the correspondence between instruction codes and the information carried by the instruction codes; A feature module is used to determine, within an instruction feature set, grouped feature codes corresponding to each code position in the instruction encoding. The grouped feature codes describe the code value characteristics of the code position corresponding to the grouped feature code in the instruction encoding. The instruction feature set includes multiple grouped feature codes. The code position corresponding to the grouped feature code refers to the correspondence between the grouped feature code and a specific code position in the instruction encoding. A grouping module is used to group the instruction codes in the secondary decoding table according to the grouping feature code to obtain an encoding search tree. In the encoding search tree, the grouping feature code corresponds to a non-leaf node of the encoding search tree, and the leaf node of the encoding search tree includes at least one instruction code. A generation module is used to generate the instruction decoding module based on the encoding search tree.

13. An electronic device, characterized in that, include: Processor and memory; The memory is connected to the processor and is used to store computer programs; The processor is configured to implement the method for generating the instruction decoding module as described in any one of claims 1-9 by running a computer program stored in the memory.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the method for generating the instruction decoding module as described in any one of claims 1-9.

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