Methods, apparatuses, devices, media, and program products for layout mapping

Abstract

Embodiments of the present disclosure relate to methods, devices, media and program products for layout mapping. Some embodiments of the present disclosure provide a method for layout mapping. In the method according to the present disclosure, constraint information for layout and routing is extracted from the original layout and original circuit to be mapped, and a new circuit under a new process is automatically laid out and routed based on the extracted constraint information to obtain a new layout for implementing the new circuit. In this way, the scheme according to the present disclosure avoids the misalignment, overlap and design rule checking problems caused by direct replacement of hierarchy or parameterized cells in the conventional scheme to the greatest extent, so that the workload of the designer can be greatly reduced.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to the field of chip design, and more specifically to methods, apparatus, devices, media, and program products for layout mapping. Background Technology

[0002] In integrated circuit (IC) design, it is often necessary to transfer chip layouts designed for one process technology to another. Typically, the process parameters and design rules for two different processes are not the same. For example, process parameters for a specific process may include the unit resistance and unit capacitance of metals under that process, and design rules for a specific process may include that the active area spacing and metal line spacing of devices should be greater than predetermined values. Therefore, chip layout mapping (also known as layout migration) is required to ensure that the chip layout for the other process meets the design requirements.

[0003] Currently, conventional mapping schemes for chip layouts from one process technology to another include: exporting a Graphic Design Exchange System (GDS) file describing the original layout from the original layout using Electronic Design Automation (EDA) software; having designers write or obtain hierarchical migration scripts from the tape-out vendor; and using these scripts to manipulate the GDS file to replace layers in the original layout, resulting in a new layout for the new process technology. Because the design rules for the new process differ from those of the original process, the new layout obtained in this way often contains numerous Design Rule Check (DRC) errors. Therefore, designers need to invest significant time in correcting these DRC issues to obtain a new layout usable for tape-out. Consequently, conventional layout mapping schemes heavily rely on manual intervention by designers, resulting in low efficiency and a longer chip development cycle. Summary of the Invention

[0004] In view of the above problems, embodiments of this disclosure are intended to provide a scheme for layout mapping.

[0005] According to a first aspect of this disclosure, a method for layout mapping is provided, comprising: determining first constraint information associated with the first circuit based on a first netlist file representing a first circuit and a first layout for implementing the first circuit, the first netlist file and the first layout being associated with a first process, the first constraint information indicating at least the placement and routing rules of devices in the first circuit in the first layout; determining a second netlist file associated with the second process based on the first netlist file and a process design kit associated with the second process, the second netlist file representing a second circuit, the second process being different from the first process, the second circuit having the same circuit topology as the first circuit; and determining a second layout associated with the second process for implementing the second circuit based on the first constraint information and the second netlist file. This method utilizes automatic placement and routing based on constraint information from the original layout to replace the conventional approach of directly replacing hierarchical or parameterized cells. In this way, the method according to this disclosure can minimize misalignment, overlap, and DRC problems found in conventional approaches, thus significantly reducing the workload of designers. Furthermore, the method according to this disclosure does not need to be customized for different processes, thereby achieving decoupling of layout mapping from process.

[0006] In some implementations, the placement rules include the relative positional information of multiple devices in the first circuit within the first layout, and the routing rules include the interconnection information of the multiple devices in the first circuit within the first layout. Since the relative positional relationships between devices, such as alignment and symmetry, as well as interconnection information, have a significant impact on the quality of the final layout design, considering the relative positional information and interconnection information of multiple devices in the layout mapping allows for the inheritance of mature designs in this regard from the first layout, thereby improving the quality of the obtained second layout and increasing the efficiency of layout porting.

[0007] In some implementations, determining the first constraint information based on the first netlist file and the first layout includes: comparing the first layout and the first netlist file to extract the correspondence between the devices and connections in the first circuit and the patterns in the first layout; and extracting the first constraint information from the first layout based on the correspondence. In this way, the relationship between the first circuit and the first layout can be established, facilitating subsequent analysis of the first layout and the extraction of layout and routing rules from it.

[0008] In some implementations, the first constraint information also indicates the layout and routing rules of the auxiliary device in the first layout. The auxiliary device is not included in the first circuit, and the pattern corresponding to the auxiliary device is included in the first layout. Determining the first constraint information also includes: obtaining layer information of the first layout, the layer information indicating the position of pattern elements in the corresponding layers of the first layout; and analyzing the layer information to extract the layout and routing rules of the auxiliary device in the first layout. Since the arrangement of the auxiliary device in the first layout embodies rich engineering design experience and affects the characteristics of surrounding devices, the method according to this implementation can also map the arrangement of the auxiliary device in the first layout to the second layout, thereby further improving the layout and routing quality of the second layout.

[0009] In some implementations, determining the second netlist file includes replacing the devices in the first netlist file with corresponding devices in a process design kit associated with the second process to obtain the second netlist file. In this way, a second netlist file for the second process can be obtained relatively easily and quickly based on the first netlist file for the first process.

[0010] In some implementations, determining the second layout includes: determining second constraint information associated with the second circuit based on the first constraint information and the second netlist file, the second constraint information indicating at least the placement and routing rules for devices in the second circuit; and determining the second layout based on the second constraint information. In this way, the placement and routing rules for the second layout used to implement the new circuit can be determined based on the placement and routing rules in the first layout, thereby inheriting the mature design of the first layout as much as possible, reducing overlap, misalignment, and DRC issues, and thus improving the efficiency of layout mapping.

[0011] In some implementations, determining the second constraint information includes: extracting a first layout feature associated with a first process from the first constraint information. The first layout feature at least indicates the composition of a first device group, and the layout and routing rules of the first device group in a first layout. The first device group includes multiple devices in the first layout that satisfy at least one combination condition in a set of combination conditions, including: multiple devices belonging to the same type of device, or multiple devices forming a functional block; grouping devices in a second circuit with reference to the first layout feature to obtain a second layout feature associated with a second process. The second layout feature at least indicates the composition of a second device group corresponding to the first device group, and the layout and routing rules of the second device group. The second device group includes multiple devices from a second process; and determining the second constraint information based on the second layout feature. Since integrated circuits often include a large number of devices in practice, grouping the devices in the circuit simplifies the constraint information used for placement and routing, thereby improving the efficiency of layout mapping.

[0012] In some implementations, the first constraint information also indicates the layout and routing rules for auxiliary devices in the first layout. The auxiliary devices are not included in the first circuit, and the patterns corresponding to the auxiliary devices are included in the first layout. The combination condition set also includes: the patterns corresponding to devices in the first circuit are surrounded by patterns corresponding to the auxiliary devices in the first layout. Since the arrangement of auxiliary devices embodies rich engineering design experience, considering auxiliary devices when grouping devices allows for more rational grouping of devices and allows for the inheritance of mature designs from the first layout, thereby further improving the layout and routing quality of the second layout.

[0013] In some implementations, determining the second constraint information based on the second layout feature includes: receiving user operations on graphical elements associated with the second layout feature via a user interface; adjusting the second layout feature based on the operations to obtain a target layout feature; and determining the second constraint information based on the target layout feature. In this way, the second layout feature can be presented to the user in an intuitive manner, allowing the user to edit the second constraint information in real time and visually presenting the modified layout to the user.

[0014] In some implementations, determining the second layout based on the second constraint information includes: assembling multiple device template units to form a second device group, where each device template unit corresponds to a device in the second process; connecting the device template units in the second device group based on the second constraint information; arranging the second device group and the device template units corresponding to other devices based on the second constraint information; and connecting the second device group and the device template units corresponding to other devices based on the second constraint information. In this way, devices in the second circuit can be laid out and routed hierarchically using device template units. Since the device template units are adaptively designed to prevent overlap when assembling them, misalignment, overlap, and DRC issues can be avoided during the layout and routing of the second layout, thus minimizing the need for later layout modifications by designers.

[0015] In some implementations, device template cells can be designed by extending the corresponding layout hierarchy in the parameterized cell to the boundary of the device cell. This approach prevents overlap when multiple device template cells are joined, thus ensuring that misalignment, overlap, and DRC issues do not occur when joining device template cells to form a second device group.

[0016] In some implementations, the first constraint information further indicates the parasitic capacitance and parasitic resistance (RC) parameters of the conductors in the first layout, and the second constraint information further indicates the width, length, or spacing of multiple conductors used in the second process. Determining the second constraint information includes calculating the width, length, or spacing of the multiple conductors used in the second process based on the RC parameters and the metallic properties associated with the second process. This approach aims to ensure that the RC parameters of the second layout are as consistent as possible with those of the first layout.

[0017] In some implementations, determining the second layout includes: determining candidate layouts associated with the second process for implementing the second circuit based on second constraint information; updating the second constraint information based on the RC parameters of the conductors in the candidate layout and the conductors in the first layout if the deviation is greater than a predetermined threshold; and determining the second layout based on the updated second constraint information. In this way, the constraint information used for placement and routing can be adaptively adjusted according to the RC parameters of the candidate layout, thereby ensuring that the RC parameters of the second layout are consistent with those of the first layout.

[0018] According to a second aspect of this disclosure, an apparatus for layout mapping is provided. The apparatus includes a first constraint information determination module, a second netlist file determination module, and a second layout determination module. The first constraint information determination module is configured to determine first constraint information associated with the first circuit based on a first netlist file representing a first circuit and a first layout for implementing the first circuit. The first netlist file and the first layout are associated with a first process, and the first constraint information at least indicates placement and routing rules for devices in the first circuit in the first layout. The second netlist file determination module is configured to determine a second netlist file associated with a second process based on the first netlist file and a process design kit associated with a second process. The second netlist file represents a second circuit, the second process being different from the first process, and the second circuit having the same circuit topology as the first circuit. The second layout determination module is configured to determine a second layout associated with the second process for implementing the second circuit based on the first constraint information and the second netlist file. This apparatus utilizes automatic placement and routing based on constraint information from the original layout to replace the conventional approach of directly replacing hierarchical or parameterized cells. In this way, the apparatus according to this disclosure can avoid misalignment, overlap, and DRC problems found in conventional solutions to the greatest extent possible, thus significantly reducing the workload of designers. Furthermore, the apparatus according to this disclosure does not need to be customized for different processes, thereby enabling decoupling of layout mapping from process technology.

[0019] In some implementations, the placement rules include the relative positional information of multiple devices in the first circuit within the first layout, and the routing rules include the interconnection information of the multiple devices in the first circuit within the first layout. Since the relative positional relationships between devices, such as alignment and symmetry, as well as interconnection information, have a significant impact on the quality of the final layout design, considering the relative positional information and interconnection information of multiple devices in the layout mapping allows for the inheritance of mature designs in this regard from the first layout, thereby improving the quality of the obtained second layout and increasing the efficiency of layout porting.

[0020] In some implementations, the first constraint information determination module is further configured to: compare the first layout and the first netlist file to extract the correspondence between the devices and connections in the first circuit and the patterns in the first layout; and extract the first constraint information from the first layout based on the correspondence. In this way, the relationship between the first circuit and the first layout can be established, thereby facilitating subsequent analysis of the first layout and the extraction of layout and routing rules from it.

[0021] In some implementations, the first constraint information also indicates the layout and routing rules of auxiliary devices in the first layout. The auxiliary devices are not included in the first circuit, and the corresponding patterns are included in the first layout. The first constraint information determining module is further configured to: acquire layer information of the first layout, the layer information indicating the position of pattern elements in the corresponding layers of the first layout; and analyze the layer information to extract the layout and routing rules of the auxiliary devices in the first layout. Since the arrangement of auxiliary devices in the first layout embodies rich engineering design experience and affects the characteristics of surrounding devices, the device according to this implementation can also map the arrangement of auxiliary devices in the first layout to the second layout, thereby further improving the layout and routing quality of the second layout.

[0022] In some implementations, the second netlist file determination module is further configured to replace the devices in the first netlist file with corresponding devices in a process design kit associated with the second process to obtain the second netlist file. In this way, a second netlist file for the second process can be obtained relatively easily and quickly based on the first netlist file for the first process.

[0023] In some implementations, the second layout determination module is further configured to: determine second constraint information associated with the second circuit based on the first constraint information and the second netlist file, wherein the second constraint information at least indicates the placement and routing rules for devices in the second circuit; and determine the second layout based on the second constraint information. In this way, the placement and routing rules for the second layout used to implement the new circuit can be determined based on the placement and routing rules in the first layout, thereby inheriting the mature design of the first layout as much as possible to reduce overlap, misalignment, and DRC issues, thus improving the efficiency of layout mapping.

[0024] In some implementations, determining the second constraint information associated with the second circuit based on the first constraint information and the second netlist file includes: extracting a first layout feature associated with the first process from the first constraint information, the first layout feature indicating at least the composition of a first device group, and the layout and routing rules of the first device group in the first layout, the first device group including multiple devices in the first layout that satisfy at least one combination condition in a combination condition set, the combination condition set including: multiple devices belonging to the same type of device, or multiple devices forming a functional block; grouping the devices in the second circuit with reference to the first layout feature to obtain a second layout feature associated with the second process, the second layout feature indicating at least the composition of the second device group, and the layout and routing rules of the second device group, the second device group corresponding to the first device group, and the second device group including multiple devices of the second process; and determining the second constraint information based on the second layout feature. Since integrated circuits often include a large number of devices in practice, grouping the devices in the circuit can simplify the constraint information used for placement and routing, thereby improving the efficiency of layout mapping.

[0025] In some implementations, the first constraint information also indicates the layout and routing rules for auxiliary devices in the first layout. The auxiliary devices are not included in the first circuit, and the patterns corresponding to the auxiliary devices are included in the first layout. The combination condition set also includes: the patterns corresponding to devices in the first circuit are surrounded by patterns corresponding to the auxiliary devices in the first layout. Since the arrangement of auxiliary devices embodies rich engineering design experience, considering auxiliary devices when grouping devices allows for more rational grouping of devices and allows for the inheritance of mature designs from the first layout, thereby further improving the layout and routing quality of the second layout.

[0026] In some implementations, determining the second constraint information based on the second layout feature includes: receiving user operations on graphical elements associated with the second layout feature via a user interface; adjusting the second layout feature based on the operations to obtain a target layout feature; and determining the second constraint information based on the target layout feature. In this way, the second layout feature can be presented to the user in an intuitive manner, allowing the user to edit the second constraint information in real time and visually presenting the modified layout to the user.

[0027] In some implementations, determining the second layout based on the second constraint information includes: assembling multiple device template units to form a second device group, where each device template unit corresponds to a device in the second process; connecting the device template units in the second device group based on the second constraint information; arranging the second device group and the device template units corresponding to other devices based on the second constraint information; and connecting the second device group and the device template units corresponding to other devices based on the second constraint information. In this way, devices in the second circuit can be laid out and routed hierarchically using device template units. Since the device template units are adaptively designed to prevent overlap when assembling them, misalignment, overlap, and DRC issues can be avoided during the layout and routing of the second layout, thus minimizing the need for later layout modifications by designers.

[0028] In some implementations, device template cells can be designed by extending the corresponding layout hierarchy in the parameterized cell to the boundary of the device cell. This approach prevents overlap when multiple device template cells are joined, thus ensuring that misalignment, overlap, and DRC issues do not occur when joining device template cells to form a second device group.

[0029] In some implementations, the first constraint information also indicates the parasitic capacitance and resistance (RC) parameters of the conductors in the first layout, and the second constraint information also indicates the width, length, or spacing of multiple conductors used in the second process. Determining the second constraint information associated with the second circuit based on the first constraint information and the second netlist file includes calculating the width, length, or spacing of multiple conductors used in the second process based on the RC parameters and the metal properties associated with the second process. This approach aims to keep the RC parameters of the second layout as consistent as possible with those of the first layout.

[0030] In some implementations, determining the second layout based on the second constraint information includes: determining candidate layouts associated with the second process for implementing the second circuit based on the second constraint information; updating the second constraint information based on the RC parameters of the conductors in the candidate layout and the RC parameters of the conductors in the first layout if the deviation is greater than a predetermined threshold; and determining the second layout based on the updated second constraint information. In this way, the constraint information used for placement and routing can be adaptively adjusted according to the RC parameters of the candidate layout, thereby ensuring that the RC parameters of the second layout are consistent with those of the first layout.

[0031] According to a third aspect of this disclosure, an electronic device is provided. The electronic device includes: at least one processor; and at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, which, when executed by the at least one processor, cause the electronic device to perform the method according to the first aspect of this disclosure. This electronic device utilizes automatic placement and routing based on constraint information of a first layout to replace the conventional approach of directly replacing hierarchical or parameterized units. In this way, misalignment, overlap, and DRC problems in conventional approaches can be avoided to the greatest extent, thus significantly reducing the workload of designers.

[0032] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided. This computer-readable storage medium stores a computer program that, when executed by a processor, implements the method according to a first aspect of this disclosure. This computer-readable storage medium utilizes constraint information based on a first layout for automatic placement and routing, replacing the conventional approach of directly replacing hierarchical or parameterized units. In this way, misalignment, overlap, and DRC problems found in conventional approaches can be avoided to the greatest extent possible, thus significantly reducing the workload of designers.

[0033] According to a fifth aspect of this disclosure, a computer program product is provided, comprising computer-executable instructions that, when executed by a processor, cause a computer to implement the method according to a first aspect of this disclosure. This computer program product utilizes constraint information based on a first layout for automatic placement and routing, replacing the conventional approach of directly replacing hierarchical or parameterized units. In this way, misalignment, overlap, and DRC problems inherent in conventional approaches can be avoided to the greatest extent possible, thus significantly reducing the workload of designers.

[0034] The summary section is provided to present the chosen concepts in a simplified form, which will be further described in the detailed description below. The summary section is not intended to identify key or principal features of this disclosure, nor is it intended to limit the scope of this disclosure. Attached Figure Description

[0035] The above and other objects, features, and advantages of embodiments of the present disclosure will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated in the drawings by way of example and not limitation.

[0036] Figure 1 A block diagram of an example environment according to some embodiments of the present disclosure is shown;

[0037] Figure 2 A schematic block diagram of an exemplary first circuit to be ported is shown;

[0038] Figure 3 The following diagram illustrates the implementation. Figure 2 A schematic diagram of the first layout of the first circuit shown;

[0039] Figure 4 A flowchart of a method for layout mapping according to some embodiments of the present disclosure is shown;

[0040] Figure 5 A flowchart of a method for determining first constraint information according to some embodiments of the present disclosure is shown;

[0041] Figure 6 A flowchart of a method for determining a second layout according to some embodiments of the present disclosure is shown;

[0042] Figure 7 A schematic diagram of graphics for presenting a second layout feature according to some embodiments of the present disclosure is shown;

[0043] Figure 8 A block diagram of an example apparatus for layout mapping according to some embodiments of the present disclosure is shown; and

[0044] Figure 9 A schematic block diagram of an example device that can be used to implement some embodiments of this disclosure is shown. Detailed Implementation

[0045] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0046] The term "comprising" and its variations as used herein signify an open-ended inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". Terms such as "upper", "lower", "front", "rear", etc., indicating placement or relative positional relationships, are based on the orientation or relative positional relationships shown in the accompanying drawings and are used only for the purpose of describing the principles of this disclosure, and are not intended to indicate or imply that the elements referred to must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as limiting this disclosure.

[0047] The term "hierarchy" or "layer" used in this document refers to a layer of a layout. The term "design rule check" refers to the process of checking whether the physical layout of an integrated circuit meets design rules, which are a set of geometric and connectivity constraints specified to allow for the production of qualified chips. The term "parameterized cell" refers to a component or assembly of a circuit whose structure depends on one or more parameters. In other words, a parameterized cell is a cell automatically generated by EDA software based on the values ​​of these parameters.

[0048] As mentioned above, layout mapping is used to transfer an original layout designed for an existing process to a new process to obtain a new layout for the new process. Conventional layout mapping schemes typically include the following two methods: First, using a customized script, the layout design data of the original layout is directly replaced hierarchically, replacing all levels under the original process with levels under the new process, and then the designer manually corrects the DRC to obtain the new layout; Second, using a customized script, the parameter cells (PCells) of the original layout are replaced, replacing all PCells of the original process with PCells of the new process, and then the designer manually corrects the DRC to obtain the new layout.

[0049] However, both conventional approaches have their own problems. For example, the first approach is often only suitable for layout mapping between two very similar processes; otherwise, due to large differences in device architecture and size, designers may find it difficult or even impossible to obtain a usable new layout by modifying the DRC. For the second approach, the custom scripts used are strongly dependent on the process, meaning that layout mapping between any two processes requires separate custom scripts, thus limiting layout mapping efficiency.

[0050] Embodiments of this disclosure propose a scheme for layout mapping to address one or more of the aforementioned problems and other potential issues. In the scheme according to this disclosure, constraint information for placement and routing is extracted from the original layout and original circuit to be mapped, and the new circuit under the new process is automatically placed and routed based on the extracted constraint information to obtain a new layout for implementing the new circuit. The scheme according to this disclosure utilizes automatic placement and routing based on the constraint information of the original layout to replace the process of directly replacing hierarchical or parameterized cells in conventional schemes. In this way, the scheme according to this disclosure avoids misalignment, overlap, and DRC problems caused by directly replacing hierarchical or parameterized cells in conventional schemes to a large extent, thus significantly reducing the workload of designers. Furthermore, the scheme according to this disclosure does not need to be customized for different processes, thereby achieving decoupling of layout mapping from process technology.

[0051] Figure 1A block diagram of an example environment 100 according to some embodiments of the present disclosure is shown. Figure 1 As shown, the example environment 100 may generally include an electronic device 140. In some embodiments, the electronic device 140 may be a device with computing capabilities, such as a personal computer, workstation, or server. The scope of this disclosure is not limited in this respect.

[0052] Electronic device 140 can acquire as input a first netlist file 110 characterizing a first circuit, a first layout 120 for implementing the first circuit, and a process design kit (PDK) 130 associated with a second process, wherein the first netlist file 110 and the first layout 120 are associated with the first process. In practice, it may be necessary to change chip manufacturers to fabricate the first circuit. In some embodiments, the first process may be the original process provided by the original chip manufacturer, while the second process may be a new process provided by a new chip manufacturer. The scope of this disclosure is not limited in this respect.

[0053] In some embodiments, the first netlist file 110 may indicate device information and connection relationships of devices in the first circuit. Device information may include, for example, parameter information of the device such as width, length, etc., the name of the library in which the device resides, etc. In some embodiments, the first netlist file 110 may also indicate information such as process parameters used to implement the first circuit. Process parameters may include, for example, the unit resistance and potential capacitance of a metal under a first process. The scope of this disclosure is not limited in this respect. In some embodiments, the first layout 120 may indicate the layout and routing information of the first circuit in the layout. In some embodiments, the first layout 120 may be provided to the electronic device 140, for example, in the form of a GDS file. The scope of this disclosure is not limited in this respect.

[0054] In some embodiments, PDK 130 may be a document provided by a chip manufacturer to describe semiconductor process details such as device information and process parameters. It should be understood that, in the context of this disclosure, PDK 130 may also represent any other suitable data information capable of indicating the name of a circuit device and its parameter names under a particular process. The scope of this disclosure is not limited in this respect.

[0055] In some embodiments, the first netlist file 110, the first layout 120, and the PDK 130 may be input into the electronic device 140 by a user. In some embodiments, at least a portion of the first netlist file 110, the first layout 120, and the PDK 130 may have been pre-stored in the electronic device 140. In some embodiments, the electronic device 140 may also be communicatively coupled to other devices to obtain at least a portion of the first netlist file 110, the first layout 120, and the PDK 130 from those other devices. The scope of this disclosure is not limited in this respect.

[0056] Electronic device 140 extracts the layout and routing rules of the circuit under the first process based on the first netlist file 110 and the first layout 120 as first constraint information. Based on this first constraint information, it determines second constraint information for the layout and routing of the corresponding circuit under the second process, and automatically performs layout and routing by considering this second constraint information, thereby obtaining a second layout 150 under the second process as output. This will be discussed in detail below. Figures 2 to 7 Let me describe it in detail.

[0057] Figure 2 A schematic block diagram of an exemplary first circuit 200 to be ported is shown, and Figure 3 The following diagram illustrates the implementation. Figure 2 A schematic diagram of the first layout 120 of the first circuit 200 is shown. For illustrative and simplification purposes, Figure 2 and Figure 3 Only a portion of the modules of the first circuit 200 and the corresponding areas in the first layout 120 are shown, and... Figure 3 The wiring information and specific layout pattern in the first layout 120 are omitted.

[0058] exist Figure 2 In this embodiment, the first circuit 200 exemplarily includes four circuit modules: module A 210-1, module B 210-2, module C 210-3, and module D 210-4 (collectively referred to individually or collectively as circuit module 210). In one embodiment, module A 210-1 may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), module B 210-2 may be, for example, a current mirror, module C 210-3 may be, for example, a current amplifier, and module D 210-4 may be, for example, a filter. It should be understood that the number of circuit modules included in the first circuit 200 may be any other suitable value, and the circuit modules included in the first circuit 200 may correspond to any other suitable circuit unit or device; the scope of this disclosure is not limited in this respect.

[0059] exist Figure 3 In the first version 120, it is exemplarily included: a first module region 310, guard ring regions (Tap) 320-1 and 320-2 (each individually or collectively referred to as Tap 320), a second module region 330, first device regions 340-1 and 340-2 (each individually or collectively referred to as first device region 340), dummy device regions 350-1 to 350-4 (each individually or collectively referred to as Dummy 350), a second device region 360, and a third device region 370. In one embodiment, the first module region 310 may correspond to a current mirror, the second module region 330 may correspond to a current amplifier, the first device region may correspond to a MOSFET, and the second device region 360 and the third device region 370 may correspond to a resistor and a capacitor in a filter, respectively. It should be noted that, since Figure 3 Since it is not drawn to scale, in practice, the first module region 310 and the second module region 330 can be composed of device regions that are the same as or similar to the first device region 340, the filling device region 350, the second device region 360, and the third device region 370. It should be understood that... Figure 3 The map areas and their layouts shown are illustrative only and are not necessarily drawn to scale. The scope of this disclosure is not limited in this respect.

[0060] In the following text, reference will be made to Figure 2 The first circuit 200 shown and Figure 3 The first layout 120 shown illustrates the solution according to this disclosure. It should be understood that the solution according to this disclosure can also be applied to any other suitable circuit and its corresponding layout, and the scope of this disclosure is not limited in this respect.

[0061] Figure 4 A flowchart of a method 400 for layout mapping according to some embodiments of the present disclosure is shown. In some embodiments, method 400 may be performed by, for example... Figure 1 The illustrated electronic device 140 performs this action. It should be understood that method 400 may also include additional boxes not shown and / or the boxes shown may be omitted, and the scope of this disclosure is not limited in this respect.

[0062] In block 402, electronic device 140 determines first constraint information associated with the first circuit 200 based on a first netlist file 110 characterizing the first circuit 200 and a first layout 120 for implementing the first circuit 200, the first netlist file 110 and the first layout 120 being associated with a first process, the first constraint information indicating at least the placement rules and routing rules for devices in the first circuit 200 in the first layout 120. In the context of this disclosure, "placement rules" refer to rules associated with the locations of devices allocated in the layout, and "routing rules" refer to rules associated with the connections of devices in the layout.

[0063] In some embodiments, layout rules may include relative position information of multiple devices in the first layout 120, such as alignment of multiple devices with respect to their upper or lower boundaries, alignment of multiple devices with respect to their central axis, mirror symmetry of multiple devices with respect to the central axis of the layout, vertical or horizontal adjacency of multiple devices, spacing between the boundaries of multiple devices, spacing between the active areas of multiple devices, etc. In some embodiments, routing rules may include interconnection information of multiple devices in the layout, such as the name of the net used to implement the interconnection, the connection end between the net and the device, the conductor segments (shapes) included in the net, the layout level where the conductor segments are located, the symmetry relationship between multiple nets, etc. In some embodiments, the first constraint information may also include device information of the devices in the first circuit 200, such as parameter information of the device such as width, length, etc., the name of the library where the device is located, etc. It should be understood that the first constraint information may also include information not listed and / or the listed information may be omitted, and the scope of this disclosure is not limited in this respect.

[0064] In some embodiments, the electronic device 140 may utilize the correspondence between the first circuitry 200 and the first layout 120 to extract first constraint information from the first layout 120. This will be discussed in conjunction with the following. Figure 5 Further detailed description.

[0065] In block 404, electronic device 140 determines a second netlist file associated with a second process based on a first netlist file 110 and a process design kit 130 associated with the second process. The second netlist file represents a second circuit, which differs from the first process and has the same circuit topology as the first circuit 200. In the context of this disclosure, two circuits having the same circuit topology indicates a one-to-one correspondence between the transistor-level devices in the two circuits. Since the device names and parameter names of the same devices are often different under different processes, device mapping and parameter mapping need to be performed on the first circuit 200 based on the PDK 130 for the second process to obtain a second circuit for the second process corresponding to the first circuit 200.

[0066] In some embodiments, the electronic device 140 may replace the devices in the first netlist file 110 representing the first circuit 200 with corresponding devices in the PDK 130 for the second process to obtain a second netlist. Exemplarily, the electronic device 140 may obtain the device name and parameter name of the device in the PDK 130 for the second process, and use the obtained device name and parameter name to replace the device name and parameter name of the corresponding device in the first netlist file 110, thereby obtaining a second netlist for the second process.

[0067] At box 406, electronic device 140 can determine a second layout 150 associated with a second process for implementing a second circuit, based on first constraint information and a second netlist file. In some embodiments, electronic device 140 can determine second constraint information associated with the second circuit, based on the first constraint information and the second netlist file, the second constraint information indicating at least the placement and routing rules for devices in the second circuit. Electronic device 140 can determine the second layout 150 based on the determined second constraint information. This will be discussed in conjunction with the following. Figure 6 and Figure 7 Further detailed description.

[0068] Figure 5 A flowchart of a method 500 for determining first constraint information according to some embodiments of the present disclosure is shown. For example, method 500 may be as follows: Figure 4 An example implementation of box 402 is shown. In some embodiments, method 500 may be provided by, for example... Figure 1 The illustrated electronic device 140 performs this action. It should be understood that method 500 may also include additional boxes not shown and / or the boxes shown may be omitted, and the scope of this disclosure is not limited in this respect.

[0069] In block 502, electronic device 140 can compare first layout 120 and first netlist file 110 to extract the correspondence between devices and connections in first circuit 200 and patterns in first layout 120. For example, electronic device 140 can perform a layout versus schematic (LVS) check on first layout 120 and first netlist file 110 using software to generate a Standard Verification Database (SVDB) file containing the correspondence between devices and connections in first circuit 200 and patterns in first layout 120. An exemplary correspondence is that a MOSFET in first circuit 200 corresponds to a first device region 340-1 in first layout 120. In this way, electronic device 140 can establish the relationship between first circuit 200 and first layout 120 used to implement first circuit 200, thereby facilitating subsequent analysis of first layout 120 and extraction of layout and routing rules from first layout 120.

[0070] In block 504, electronic device 140 can extract first constraint information from first layout 120 based on the correspondence between components and connections in first circuit 200 and patterns in first layout 120. For example, refer to Figure 3 The electronic device 140 can extract the coordinate information of the first device regions 340-1 and 340-2 from the first layout 120. By analyzing the coordinate information, the electronic device 140 determines that the first device regions 340-1 and 340-2 are aligned with their left and right boundaries, and that they are vertically adjacent. Therefore, the electronic device 140 can determine that the layout rule for the two MOSFETs in the first circuit 200 corresponding to the first device regions 340-1 and 340-2 is that their left and right boundaries are aligned and they are vertically adjacent. Furthermore, the electronic device 140 can also extract device information such as the width and length of the MOSFET corresponding to the first device region 340-1 from the first layout 120.

[0071] In some embodiments, the electronic device 140 can associate the connection between two devices in the first circuit 200 with the Net connecting the corresponding pattern in the first layout 120 according to the above correspondence, and extract the wire segments, coordinate information, and size information of the Net in each layout layer from the first layout 120. Similar to determining the relative position information of the devices, by analyzing the coordinate information of multiple wire segments, the electronic device 140 can determine the relative positional relationships such as alignment and symmetry between multiple wire segments. In this way, the electronic device 140 can obtain the wiring rules between the various devices in the first circuit 200 from the first layout 120.

[0072] In some embodiments, the first constraint information may also indicate the layout and routing rules of auxiliary devices in the first layout 120. In the foregoing of this disclosure, "auxiliary device" refers to a device that is not included in the first circuit 200, and whose corresponding pattern is included in the first layout 120. Exemplarily, auxiliary devices may be arranged in the layout for reasons such as ensuring chip manufacturability, avoiding the influence of light reflection and diffraction during photolithography on the pattern accuracy and size of the device, or avoiding the influence of noise signals in the chip on critical signals, etc. Examples of auxiliary devices include, but are not limited to, Tap 320 and Dummy 350 in the layout. Electronic device 140 may use software to parse the GDS file of the first layout 120 to obtain layer information of the first layout 120, which indicates the position of pattern elements in the corresponding layers of the first layout 120. The electronic device 140 can further analyze and process the acquired layer information, for example, by comparing the layer information with a feature pattern pattern representing an auxiliary device to determine whether an auxiliary device exists in the first layout 120, and when an auxiliary device exists, determine the size information, coordinate information, and connection information of the auxiliary device with surrounding devices in the first layout 120. In the context of this disclosure, a "feature pattern pattern" representing a device refers to a device-specific pattern used in a layout design to implement the device.

[0073] In some embodiments, the electronic device 140 can determine the layout rules associated with the auxiliary device using the coordinate information of the auxiliary device and the remaining devices in the first layout 120. For example, the electronic device 140 can determine exemplary relative position information by analyzing the coordinate information of Dummy 350-1 to 350-4 and the first device regions 340-1 and 340-2, such that Dummy 350-1 and 350-3 are respectively arranged to the left of the first device regions 340-1 and 340-2, and Dummy 350-2 and 350-4 are respectively arranged to the right of the first device regions 340-1 and 340-2, and Dummy 350-1 and 350-2 are aligned with the first device region 340-1 about its upper and lower boundaries, thereby obtaining the layout rules between Dummy 350-1 to 350-4 and the corresponding MOSFETs. In some embodiments, the electronic device 140 can determine the wiring rules between the auxiliary device and other devices in a manner similar to that described above for determining the wiring rules of the devices in the first circuit 200, which will not be repeated here. Since the arrangement of auxiliary components involves a wealth of engineering design experience and can affect the characteristics of other surrounding components, the method according to this embodiment can map the arrangement of auxiliary components in the first layout 120 to the second layout 150, thereby further improving the layout and routing quality of the second layout 150.

[0074] Figure 6 A flowchart of a method 600 for determining a second version of FIG150 according to some embodiments of the present disclosure is shown. For example, method 600 may be as follows: Figure 4 An example implementation of box 406 is shown. In some embodiments, method 600 may be provided by, for example... Figure 1 The illustrated electronic device 140 performs this action. It should be understood that method 600 may also include additional boxes not shown and / or the boxes shown may be omitted, and the scope of this disclosure is not limited in this respect.

[0075] In block 602, electronic device 140 extracts a first layout feature associated with a first process from the first constraint information. The first layout feature indicates at least the composition of a first device group and the layout and routing rules of the first device group in the first layout 120. The first device group includes multiple devices in the first layout 120 that satisfy at least one combination condition in a set of combination conditions, including: multiple devices belonging to the same type of device, or multiple devices forming a functional block. Since the first circuit 200 often includes a large number of devices in practice, this disclosure simplifies the first constraint information by grouping the devices, thereby improving the efficiency of layout mapping.

[0076] In some embodiments, the electronic device 140 may group devices of the same type in the first circuit 200 into a first device group. For example, the electronic device 140 may group multiple MOSFETs into a group. The electronic device 140 may also group multiple resistors into a group. In some embodiments, the electronic device 140 may group all devices in a functional block consisting of multiple devices into a group. For example, the electronic device 140 may group resistors and capacitors constituting an RC filter into a group.

[0077] In some embodiments, when auxiliary devices such as Dummy 350 and Tap 320 are present in the first layout 120, the positional relationship between the auxiliary devices and these devices can also be considered when grouping the devices. For example, if it is determined that the pattern corresponding to a device in the first circuit 200 is surrounded by a pattern corresponding to an auxiliary device in the first layout 120, the electronic device 140 can group these devices together. For example, in Figure 3 In the first layout 120 shown, since the first module region 310 is surrounded by Tap 320-1, the electronic device 140 can group the devices in the first module region 310 into one group. Similarly, the electronic device 140 can group the devices in the second module region 330 into one group. For example, since the first device regions 340-1 and 340-2 are surrounded by Dummy 350, the electronic device 140 can group the MOSFETs corresponding to the first device regions 340-1 and 340-2 into one group. Since the arrangement of auxiliary devices embodies rich design experience of engineers, by considering auxiliary devices when grouping devices, the devices can be grouped more rationally, and the mature design of the first layout 120 can be inherited, thereby further improving the layout and routing quality of the second layout 150.

[0078] It should be understood that devices can also be grouped according to any other suitable criteria, and the scope of this disclosure is not limited in this respect. In some embodiments, the electronic device 140 may also classify auxiliary devices into a corresponding first device group. In some embodiments, the electronic device 140 may record the name or number of the device surrounding each auxiliary device. The scope of this disclosure is not limited in this respect.

[0079] After determining the device groups, the electronic device 140 can extract the layout rules and routing rules between multiple first device groups from the first constraint information. In some embodiments, the electronic device 140 can determine the coordinate information of the first device group based on the coordinate information of each device in the first device group, and obtain the relative positional relationship between multiple first device groups according to the coordinate information of the first device group. For example, the electronic device 140 can determine that the first device group corresponding to the first module region 310 and multiple device groups corresponding to the second module region 330 are aligned about their upper boundaries and are mirror-symmetric about the central axis of the layout.

[0080] In some embodiments, the electronic device 140 can also group the traces in the layout based on the grouping of devices. For example, the electronic device 140 can divide the traces in the layout into two parts: intra-group traces and inter-group traces. Intra-group traces are the traces between devices in each first device group, while inter-group traces are the traces between multiple first device groups. The electronic device 140 can extract the routing rules associated with intra-group traces and the routing rules associated with inter-group traces from the routing rules in the first constraint information.

[0081] In block 604, electronic device 140 groups devices in the second circuit according to a first layout feature to obtain a second layout feature associated with a second process. The second layout feature at least indicates the composition of the second device group corresponding to the first device group, as well as the layout and routing rules of the second device group. The second device group includes multiple devices of the second process. In some embodiments, electronic device 140 can group devices in the second circuit according to the grouping method of the devices in the first circuit 200, based on the correspondence between devices in the first circuit 200 and devices in the second circuit. In other words, multiple devices grouped together under the first process are also grouped together under the second process. Furthermore, the layout and routing rules between the second device groups are consistent with the layout and routing rules between the first group of devices. In this way, when performing layout mapping, the second layout 150 can be designed as much as possible according to the layout and routing method of the first layout 120 to inherit the superior circuit characteristics of the first layout 120.

[0082] In block 606, electronic device 140 determines second constraint information based on second layout features. In some embodiments, electronic device 140 may directly determine the layout and routing rules of devices in the second circuit in the second layout 150 based on the second layout features. For example, electronic device 140 may first determine the relative positional relationship and wiring arrangement of devices in each second device group within the group based on the relative positional relationship and wiring arrangement of devices in the first layout 120. Then, electronic device 140 may further determine the relative positional relationship and wiring arrangement between the second device groups.

[0083] In some embodiments, the electronic device 140 may display graphics representing the features of the second layout on a user interface. Figure 7 A schematic diagram of a graphic 700 for presenting a second layout feature according to some embodiments of the present disclosure is shown. For illustrative and simplified purposes, Figure 7 Only a portion of the graphic elements are shown in the diagram. In diagram 700, ellipses 710-1 to 710-8 (individually or collectively referred to as ellipse 710) represent the positions and areas of corresponding second device groups within the second device group. The dashed line 720 located in the center of diagram 700 indicates the central axis of the layout. Furthermore, dashed lines 730 indicate the adjacency relationships between the various second device groups. In some embodiments, ellipses 710 may have different colors to represent different symmetry relationships. For example, the two ellipses 710 corresponding to two first device groups that are mirror-symmetrical about the central axis may be shown in green, and the ellipse 710 corresponding to a first device group that is self-symmetrical about the central axis may be shown in red. In this way, the second layout features can be presented to the user in an intuitive manner. It should be understood that... Figure 7 The graphic elements ellipse 710, dashed line 720, and dotted line 730 in the diagram are merely exemplary, and the second layout feature can be represented by any suitable graphic element; the scope of this disclosure is not limited in this respect.

[0084] In some embodiments, the electronic device 140 can receive user operations on graphic elements in the graphic 700 via a user interface. For example, a user can change the position of a graphic element by dragging it using an input device such as a mouse. The electronic device 140 can receive this drag operation from the user and determine the changed position of the graphic element as the new position of the corresponding second device group in the second layout 150. It then uses the new position to determine the relative positional relationship between the second device group and other second device groups in the second layout 150, thereby adjusting the second layout feature to obtain a target layout feature corresponding to the changed graphic. The electronic device 140 can determine the second constraint information based on the target layout feature in a manner similar to the description above regarding the second layout feature. In this way, the user can edit the second constraint information in real time and the modified layout can be visually presented to the user.

[0085] In some embodiments, the electronic device 140 can also convert non-layout constraints in the first constraint information into layout constraints in the second constraint information. For example, if the first constraint information also indicates the parasitic capacitance and parasitic resistance RC parameters of the wires in the first layout 120, the electronic device 140 can also convert the RC constraints into the width, length, or spacing of the plurality of wires for the second process in the second constraint information. In some embodiments, the electronic device 140 can use known metal properties under the second process, such as the unit resistance and unit capacitance of the metal, to calculate the width, length, or spacing between the wires used to implement the interconnection under the second process based on the RC parameters, so as to make the RC parameters of the second layout 150 as consistent as possible with those of the first layout 120.

[0086] In block 608, electronic device 140 determines a second layout 150 based on second constraint information. In some embodiments, electronic device 140 may hierarchically place and route devices in a second circuit based on the second constraint information. For example, electronic device 140 may first arrange devices in various second device groups. Electronic device 140 may stitch multiple device template cells to form a second device group based on constraint information in the second constraint information relating to devices in the corresponding second device group. In the context of this disclosure, a “device template cell” refers to a device cell developed for a second process, similar to a PCell in PDK 130. Each device in the second process has a corresponding device template cell. In some embodiments, the device template cell may be designed based on a PCell in PDK 130. For example, by extending the corresponding layout hierarchy in the PCell to the boundary of the device cell, overlap is avoided when stitching multiple device template cells. Furthermore, DRC issues can be eliminated by pre-running DRC verification and modifying the layout design in the device cell based on the verification results. This method prevents misalignment, overlap, and DRC issues when splicing device template cells to form a second device group, thus minimizing the need for later layout corrections by designers. Therefore, it improves the efficiency and automation of layout mapping.

[0087] Electronic device 140 can connect device template units in the second device group according to the second constraint information. In some embodiments, based on the wire segments used to implement the connection in the first layout 120, electronic device 140 can stretch the wire segments so that the stretched wire segments can be adapted to the layout of the second layout 150, and use the stretched wire segments to connect the corresponding devices, while keeping the circuit topology structure formed after the wire segments and devices are connected consistent with that in the first layout 120.

[0088] After completing the placement and routing of each second device group, the electronic device 140 can perform upper-level placement and routing. The electronic device 140 can arrange the second device groups and corresponding device template cells based on the relative positions of the second device groups and other devices indicated in the second constraint information. Similar to component routing, the electronic device 140 can, based on the wire segments used for interconnection in the first layout 120, extend and retract the wire segments to adapt them to the layout of the second layout 150, and use the extended and retracted wire segments to connect devices in the corresponding device groups, while maintaining the circuit topology of the obtained second layout 150 consistent with that in the first layout 120. In this way, the placement and routing of the second circuit can be automatically completed based on the determined second constraint information to obtain a candidate layout.

[0089] In some embodiments, electronic device 140 can calculate the RC parameters of the conductors in the candidate layout and compare the RC parameters of the candidate layout with the RC parameters of the first layout 120. If the deviation between the two is greater than a predetermined threshold, electronic device 140 can adjust the width, length, or distance of the relevant conductors and update the second constraint information accordingly. Electronic device 140 can then perform placement and routing of the second circuit based on the updated second constraint information to obtain an updated candidate layout. This process can be performed iteratively until the deviation between the RC parameters of the obtained candidate layout and the RC parameters of the first layout 120 is less than the predetermined threshold. In this way, the RC parameters of the second layout 150 can be kept consistent with those of the first layout 120.

[0090] Through the above combination Figures 1 to 7 As described, the layout mapping method of this disclosure can extract constraint information for placement and routing from the original layout and circuit to be mapped, and automatically place and route the new circuit under the new process based on the extracted constraint information to obtain a new layout for implementing the new circuit. In this way, the method of this disclosure avoids misalignment, overlap, and DRC problems caused by directly replacing layers or parameterized cells in conventional solutions to a large extent, thus significantly reducing the workload of designers. In addition, the method of this disclosure does not need to be customized for different processes, thereby achieving decoupling of layout mapping from process.

[0091] The above text has already referenced Figures 1 to 7 An example implementation of the method according to this disclosure has been described in detail, and the implementation of the corresponding apparatus will be described below.

[0092] Figure 8 A block diagram of an example apparatus 800 for layout mapping according to some embodiments of the present disclosure is shown. This apparatus 800 can, for example, be used to implement... Figure 1 The electronic device 140 shown is an example. Figure 8 As shown, the device 800 may include a first constraint information determination module 802, configured to determine first constraint information associated with the first circuit based on a first netlist file representing the first circuit and a first layout for implementing the first circuit. The first netlist file and the first layout are associated with a first process, and the first constraint information at least indicates the placement and routing rules of devices in the first circuit in the first layout. The device 800 may also include a second netlist file determination module 804, configured to determine a second netlist file associated with a second process based on the first netlist file and a process design kit associated with the second process. The second netlist file represents a second circuit, the second process being different from the first process, and the second circuit having the same circuit topology as the first circuit. Furthermore, the device 800 may also include a second layout determination module 806, configured to determine a second layout associated with the second process and used to implement the second circuit based on the first constraint information and the second netlist file.

[0093] In some embodiments, the first constraint information determination module 802 is further configured to: compare the first layout and the first netlist file to extract the correspondence between the devices and connections in the first circuit and the patterns in the first layout; and extract the first constraint information from the first layout based on the correspondence.

[0094] In some embodiments, the layout rules include the relative position information of multiple devices in the first circuit in the first layout, and the wiring rules include the connection information of multiple devices in the first circuit in the first layout.

[0095] In some embodiments, the first constraint information further indicates the layout rules and wiring rules of the auxiliary device in the first layout, wherein the auxiliary device is not included in the first circuit and the pattern corresponding to the auxiliary device is included in the first layout, and the first constraint information determination module 802 is further configured to: obtain layer information of the first layout, the layer information indicating the position of the pattern element in the corresponding layer of the first layout; and analyze the layer information to extract the layout rules and wiring rules of the auxiliary device in the first layout.

[0096] In some embodiments, the second layout determination module 806 is further configured to: determine second constraint information associated with the second circuit based on the first constraint information and the second netlist file, the second constraint information indicating at least the layout rules and routing rules of the devices in the second circuit; and determine the second layout based on the second constraint information.

[0097] In some embodiments, determining the second constraint information associated with the second circuit based on the first constraint information and the second netlist file includes: extracting a first layout feature associated with a first process from the first constraint information, the first layout feature indicating at least the composition of a first device group and the layout and routing rules of the first device group in a first layout, the first device group including multiple devices in the first layout that satisfy at least one combination condition in a combination condition set, the combination condition set including: multiple devices belonging to the same type of device, or multiple devices forming a functional block; grouping the devices in the second circuit with reference to the first layout feature to obtain a second layout feature associated with the second process, the second layout feature indicating at least the composition of a second device group and the layout and routing rules of the second device group, the second device group corresponding to the first device group, and the second device group including multiple devices of the second process; and determining the second constraint information based on the second layout feature.

[0098] In some embodiments, the first constraint information further indicates the layout rules and wiring rules of the auxiliary device in the first layout, wherein the auxiliary device is not included in the first circuit and the pattern corresponding to the auxiliary device is included in the first layout, and the combination condition set further includes: the pattern corresponding to the device in the first circuit is surrounded by the pattern corresponding to the auxiliary device in the first layout.

[0099] In some embodiments, determining the second constraint information based on the second layout feature includes: receiving user operations on graphical elements associated with the second layout feature via a user interface; adjusting the second layout feature based on the operations to obtain a target layout feature; and determining the second constraint information based on the target layout feature.

[0100] In some embodiments, determining the second layout based on the second constraint information includes: splicing multiple device template units to form a second device group based on the second constraint information, wherein the multiple device template units correspond to multiple devices in the second process; connecting the device template units in the second device group based on the second constraint information; arranging the second device group and the device template units corresponding to other devices based on the second constraint information; and connecting the second device group and the device template units corresponding to other devices based on the second constraint information.

[0101] In some embodiments, the first constraint information further indicates the parasitic capacitance and parasitic resistance RC parameters of the conductors in the first layout, and the second constraint information further indicates the width, length, or spacing of a plurality of conductors used in the second process. Determining the second constraint information associated with the second circuit based on the first constraint information and the second netlist file includes: calculating the width, length, or spacing of a plurality of conductors used in the second process based on the RC parameters and the metal properties associated with the second process.

[0102] In some embodiments, determining a second layout based on second constraint information includes: determining a candidate layout associated with a second process for implementing a second circuit based on the second constraint information; updating the second constraint information based on the RC parameters of the conductors in the candidate layout and the conductors in the first layout if the deviation between the RC parameters of the conductors in the candidate layout and the RC parameters of the conductors in the first layout is greater than a predetermined threshold; and determining the second layout based on the updated second constraint information.

[0103] In some embodiments, the second netlist file determination module 804 is further configured to replace the devices in the first netlist file with corresponding devices in a process design kit associated with the second process to obtain a second netlist file.

[0104] The modules and / or units included in device 800 can be implemented in various ways, including software, hardware, firmware, or any combination thereof. In some embodiments, one or more units can be implemented using software and / or firmware, such as machine-executable instructions stored on a storage medium. In addition to or as an alternative to machine-executable instructions, some or all of the units in device 800 can be implemented at least partially by one or more hardware logic components. By way of example and not limitation, exemplary types of hardware logic components that can be used include field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chips (SoCs), complex programmable logic devices (CPLDs), and so on.

[0105] Figure 8 The modules and / or units shown can be implemented, in whole or in part, as hardware modules, software modules, firmware modules, or any combination thereof. In particular, in some embodiments, the processes, methods, or procedures described above can be implemented by hardware in a storage system, a host corresponding to the storage system, or other computing devices independent of the storage system.

[0106] Figure 9 A schematic block diagram of an example device 900 that can be used to implement some embodiments of the present disclosure is shown. Device 900 can be used to implement an electronic device. Figure 9 As shown, device 900 includes a central processing unit (CPU) 901, which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) 902 or loaded from storage unit 908 into random access memory (RAM) 903. RAM 903 may also store various programs and data required for the operation of device 900. CPU 901, ROM 902, and RAM 903 are interconnected via bus 904. Input / output (I / O) interface 905 is also connected to bus 904.

[0107] Multiple components in device 900 are connected to I / O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of monitors, speakers, etc.; storage unit 908, such as disk, optical disk, etc.; and communication unit 909, such as network card, modem, wireless transceiver, etc. Communication unit 909 allows device 900 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0108] Processing unit 901 executes the various methods and processes described above, such as method 400. For example, in some embodiments, method 400 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by CPU 901, one or more steps of method 400 described above may be performed. Alternatively, in other embodiments, CPU 901 may be configured to execute method 400 by any other suitable means (e.g., by means of firmware).

[0109] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload programmable logic devices (CPLDs), and so on.

[0110] Program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0111] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0112] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0113] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for layout mapping, characterized in that, The method includes: Based on a first netlist file characterizing a first circuit and a first layout for implementing the first circuit, first constraint information associated with the first circuit is determined, wherein the first netlist file and the first layout are associated with a first process, and the first constraint information at least indicates the layout rules and routing rules of the devices in the first circuit in the first layout. Based on the first netlist file and the process design kit associated with the second process, a second netlist file associated with the second process is determined. The second netlist file represents a second circuit, the second process being different from the first process, and the second circuit having the same circuit topology as the first circuit. Based on the first constraint information and the second netlist file, a second layout associated with the second process and used to implement the second circuit is determined.

2. The method according to claim 1, characterized in that, Based on a first netlist file characterizing the first circuit and a first layout for implementing the first circuit, the first constraint information associated with the first circuit is determined, including: The first layout and the first netlist file are compared to extract the correspondence between the components and connections in the first circuit and the patterns in the first layout; and Based on the correspondence, the first constraint information is extracted from the first map.

3. The method according to claim 1 or 2, characterized in that, The layout rules include the relative position information of multiple devices in the first circuit in the first layout, and the wiring rules include the connection information of multiple devices in the first circuit in the first layout.

4. The method according to claim 2 or 3, characterized in that, The first constraint information also indicates the layout and routing rules of auxiliary devices in the first layout, wherein the auxiliary devices are not included in the first circuit and the pattern corresponding to the auxiliary devices is included in the first layout. The determination of the first constraint information associated with the first circuit based on the first netlist file characterizing the first circuit and the first layout for implementing the first circuit further includes: Obtain the layer information of the first map, wherein the layer information indicates the position of the pattern element in the corresponding layer of the first map; and The layer information is analyzed to extract the layout and routing rules of the auxiliary device in the first layout.

5. The method according to any one of claims 1 to 4, characterized in that, Based on the first constraint information and the second netlist file, the second layout for implementing the second circuit, associated with the second process, includes: Based on the first constraint information and the second netlist file, second constraint information associated with the second circuit is determined, wherein the second constraint information at least indicates the placement and routing rules of the devices in the second circuit; and Based on the second constraint information, the second layout is determined.

6. The method according to claim 5, characterized in that, The second constraint information associated with the second circuit, determined based on the first constraint information and the second netlist file, includes: Extract a first layout feature associated with the first process from the first constraint information. The first layout feature indicates at least the composition of the first device group and the layout and routing rules of the first device group in the first layout. The first device group includes multiple devices in the first layout that satisfy at least one combination condition in the combination condition set. The combination condition set includes: multiple devices belonging to the same type of device, or multiple devices forming a functional block. The devices in the second circuit are grouped according to the first layout feature to obtain a second layout feature associated with the second process. The second layout feature at least indicates the composition of the second device group, as well as the layout and routing rules of the second device group. The second device group corresponds to the first device group and includes multiple devices of the second process. Based on the second layout feature, the second constraint information is determined.

7. The method according to claim 6, characterized in that, The first constraint information also indicates the layout and wiring rules of the auxiliary device in the first layout, wherein the auxiliary device is not included in the first circuit and the pattern corresponding to the auxiliary device is included in the first layout, and the combination condition set further includes: the pattern corresponding to the device in the first circuit is surrounded by the pattern corresponding to the auxiliary device in the first layout.

8. The method according to claim 6 or 7, characterized in that, Determining the second constraint information based on the second layout feature includes: The user interface is used to receive user actions on graphical elements associated with the second layout feature. Based on the aforementioned operation, the second layout feature is adjusted to obtain the target layout feature; and Based on the target layout features, the second constraint information is determined.

9. The method according to any one of claims 6 to 8, characterized in that, The second layout is determined based on the second constraint information, including: Based on the second constraint information, multiple device template units are spliced ​​together to form the second device group, and the multiple device template units respectively correspond to multiple devices in the second process; Based on the second constraint information, connect the device template units in the second device group; Based on the second constraint information, arrange the second device group and device template units corresponding to other devices; and Based on the second constraint information, the second device group and the device template unit corresponding to other devices are connected.

10. The method according to claim 5, characterized in that, The first constraint information also indicates the parasitic capacitance and parasitic resistance RC parameters of the conductors in the first layout, and the second constraint information also indicates the width, length, or spacing of multiple conductors used in the second process. The second constraint information associated with the second circuit, determined based on the first constraint information and the second netlist file, includes: Based on the RC parameters and the metal properties associated with the second process, the width, length, or spacing of the plurality of wires used in the second process is calculated.

11. The method according to claim 10, characterized in that, The second layout is determined based on the second constraint information, including: Based on the second constraint information, candidate layouts associated with the second process for implementing the second circuit are determined; If the deviation between the RC parameters of the conductors in the candidate layout and the RC parameters of the conductors in the first layout is greater than a predetermined threshold, then the second constraint information is updated based on the RC parameters of the conductors in the first layout; and The second layout is determined based on the updated second constraint information.

12. The method according to any one of claims 1 to 11, characterized in that, Determining the second netlist file associated with the second process based on the first netlist file and the process design suite associated with the second process includes: Replace the devices in the first netlist file with the corresponding devices in the process design suite associated with the second process to obtain the second netlist file.

13. An apparatus for layout mapping, characterized in that, The device includes: The first constraint information determination module is configured to determine first constraint information associated with the first circuit based on a first netlist file characterizing the first circuit and a first layout for implementing the first circuit. The first netlist file and the first layout are associated with a first process. The first constraint information at least indicates the layout rules and routing rules of the devices in the first circuit in the first layout. The second netlist file determination module is configured to determine a second netlist file associated with the second process based on the first netlist file and a process design kit associated with the second process. The second netlist file represents a second circuit, the second process being different from the first process, and the second circuit having the same circuit topology as the first circuit. The second layout determination module is configured to determine a second layout associated with the second process and used to implement the second circuit, based on the first constraint information and the second netlist file.

14. The apparatus according to claim 13, characterized in that, The first constraint information determination module is further configured to: The first layout and the first netlist file are compared to extract the correspondence between the devices and connections in the first circuit and the patterns in the first layout. as well as Based on the correspondence, the first constraint information is extracted from the first map.

15. The apparatus according to claim 13 or 14, characterized in that, The layout rules include the relative position information of multiple devices in the first circuit in the first layout, and the wiring rules include the connection information of multiple devices in the first circuit in the first layout.

16. The apparatus according to claim 14 or 15, characterized in that, The first constraint information also indicates the layout and routing rules of the auxiliary device in the first layout, wherein the auxiliary device is not included in the first circuit and the pattern corresponding to the auxiliary device is included in the first layout, and the first constraint information determining module is further configured to: Obtain the layer information of the first map, wherein the layer information indicates the position of the pattern element in the corresponding layer of the first map; as well as The layer information is analyzed to extract the layout and routing rules of the auxiliary device in the first layout.

17. The apparatus according to any one of claims 13 to 16, characterized in that, The second layout determination module is also configured as follows: Based on the first constraint information and the second netlist file, second constraint information associated with the second circuit is determined, wherein the second constraint information at least indicates the placement and routing rules of the devices in the second circuit; and Based on the second constraint information, the second layout is determined.

18. The apparatus according to claim 17, characterized in that, The second constraint information associated with the second circuit, determined based on the first constraint information and the second netlist file, includes: Extract a first layout feature associated with the first process from the first constraint information. The first layout feature indicates at least the composition of the first device group and the layout and routing rules of the first device group in the first layout. The first device group includes multiple devices in the first layout that satisfy at least one combination condition in the combination condition set. The combination condition set includes: multiple devices belonging to the same type of device, or multiple devices forming a functional block. The devices in the second circuit are grouped according to the first layout feature to obtain a second layout feature associated with the second process. The second layout feature at least indicates the composition of the second device group, as well as the layout and routing rules of the second device group. The second device group corresponds to the first device group and includes multiple devices of the second process. Based on the second layout feature, the second constraint information is determined.

19. The apparatus according to claim 18, characterized in that, The first constraint information also indicates the layout and wiring rules of the auxiliary device in the first layout, wherein the auxiliary device is not included in the first circuit and the pattern corresponding to the auxiliary device is included in the first layout, and the combination condition set further includes: the pattern corresponding to the device in the first circuit is surrounded by the pattern corresponding to the auxiliary device in the first layout.

20. The apparatus according to claim 18 or 19, characterized in that, Determining the second constraint information based on the second layout feature includes: The user interface is used to receive user actions on graphical elements associated with the second layout feature. Based on the aforementioned operation, the second layout feature is adjusted to obtain the target layout feature; and Based on the target layout features, the second constraint information is determined.

21. The apparatus according to any one of claims 18 to 20, characterized in that, The second layout is determined based on the second constraint information, including: Based on the second constraint information, multiple device template units are spliced ​​together to form the second device group, and the multiple device template units respectively correspond to multiple devices in the second process; Based on the second constraint information, connect the device template units in the second device group; Based on the second constraint information, arrange the second device group and device template units corresponding to other devices; and Based on the second constraint information, the second device group and the device template unit corresponding to other devices are connected.

22. The apparatus according to claim 17, characterized in that, The first constraint information also indicates the parasitic capacitance and parasitic resistance RC parameters of the conductors in the first layout, and the second constraint information also indicates the width, length, or spacing of multiple conductors used in the second process. The second constraint information associated with the second circuit, determined based on the first constraint information and the second netlist file, includes: Based on the RC parameters and the metal properties associated with the second process, the width, length, or spacing of the plurality of wires used in the second process is calculated.

23. The apparatus according to claim 22, characterized in that, The second layout is determined based on the second constraint information, including: Based on the second constraint information, candidate layouts associated with the second process for implementing the second circuit are determined; If the deviation between the RC parameters of the conductors in the candidate layout and the RC parameters of the conductors in the first layout is greater than a predetermined threshold, then the second constraint information is updated based on the RC parameters of the conductors in the first layout; and The second layout is determined based on the updated second constraint information.

24. The apparatus according to any one of claims 13 to 23, characterized in that, The second netlist file determination module is also configured as follows: Replace the devices in the first netlist file with the corresponding devices in the process design suite associated with the second process to obtain the second netlist file.

25. An electronic device, characterized in that, The electronic device includes: At least one processor; and At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions, when executed by the at least one processor, causing the electronic device to perform the method according to any one of claims 1 to 12.

26. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 12.

27. A computer program product, characterized in that, The computer program product includes computer-executable instructions that, when executed by a processor, cause the computer to perform the method according to any one of claims 1 to 12.

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