A montgomery modular multiplier based on parallel structure and encoding
By designing a 2-base, 2-path parallel Montgomery modular multiplier and combining pre-computation and input data encoding, the computational efficiency and resource utilization of the Montgomery modular multiplier are optimized. This solves the problems of slow computation speed and high resource consumption in lightweight applications, achieving faster computation speed and lower resource overhead.
CN116893800BActive Publication Date: 2026-06-23UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Patent Information
- Application Number
- CN202310551639.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-05-16
- Publication Date
- 2026-06-23
- Estimated Expiration
- 2043-05-16
AI Technical Summary
Technical Problem
Existing Montgomery modular multipliers suffer from slow computation speed, high resource consumption, and difficulty in parallel computing in lightweight application scenarios, resulting in poor efficiency of the overall information security solution.
Method used
Design a two-base, two-path parallel Montgomery modular multiplier that combines pre-computation and input data encoding to optimize circuit modules through two-path parallel iterative computation, shortening the critical path and reducing additional area overhead.
Benefits of technology
The cycle delay of the Montgomery modular multiplier has been reduced to half of its original value, optimizing circuit resource utilization and making it suitable for lightweight applications.
✦ Generated by Eureka AI based on patent content.
Abstract
The application discloses a Montgomery modular multiplier based on parallel structure and coding, comprising a pre-computation storage unit, a control unit and two groups of iterative computation modules, the iterative computation module comprising an input selection control unit, a multiplexer, a CSA addition unit, an output shift unit and a register group. The Montgomery modular multiplier adds an additional shift compensation operation, decomposes the cyclic iterative computation of the partial product into two groups of parallel computation, realizes two-way parallel of 2-base Montgomery modular multiplication, and reduces the cycle delay of the original 2-base Montgomery modular multiplication to 1 / 2 of the original. In combination with the characteristics of the two-way parallel design, the input data is re-encoded, the additional shift compensation operation and the partial product are pre-computed, the original three additions are converted into a multiplexing and an addition, the additional area overhead caused by the parallel of the circuit module is optimized, the critical path of the overall operation is shortened, and the Montgomery modular multiplier can be better deployed in a lightweight application scenario.
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