A finite field error correction encoding and decoding method and system for a computing and storage integrated system

Abstract

The application discloses a finite field error correction encoding and decoding method and system for an integrated storage and calculation system, which is suitable for error correction tasks after sum and accumulation in analog in-memory calculation and error correction tasks of reading data from a general memory. The application uses non-binary q-order finite field operation to process input code words, uses a preprocessed generating matrix to obtain an encoding result belonging to the finite field and generate an error correction code, and restores at an output end, so that the error rate of in-memory calculation results is reduced and the reliability is improved. Based on the encoding and decoding method, the application discloses a corresponding decoding circuit system design, which is divided into a check node and a variable node, the connection between the check node and the variable node is defined by a check matrix, and belief propagation based on a finite field is adopted. After multiple iterations of belief propagation between the check node and the variable node, the error correction result converges and the final decoding result is obtained.

Description

Technical Field

[0001] This invention belongs to the field of in-memory computing technology, specifically relating to an in-memory computing error correction encoding and decoding method and system based on finite fields. Background Technology

[0002] Currently, mainstream computing chips typically employ the traditional von Neumann architecture. However, as Moore's Law approaches saturation, the bottleneck effect caused by the separation of memory and computing units in the traditional von Neumann architecture is becoming increasingly prominent. The bandwidth of the data bus connecting memory and computing units and the power consumption of data transfer limit further improvements in the latency and energy efficiency of computing chips.

[0003] Against this backdrop, researchers have proposed a series of novel computing paradigms, with in-memory computing technology, which integrates storage and computation functions, becoming a core technological path to break through the bottlenecks of the traditional von Neumann architecture. By adding appropriate peripheral circuits inside or around the memory, computational capabilities can be endowed to memory cells, thereby reducing the need for data transfer and mitigating the bottleneck effects of data bus bandwidth and power consumption. However, existing in-memory computing unit designs lack circuitry for correcting soft errors in the memory, which limits their robustness as memory. Furthermore, during simulated in-memory computation operations, the memory performs current summation based on Kirchhoff's laws to complete partial summation and accumulation operations, further reducing computational robustness and making error correction of the results after partial summation and accumulation even more urgent.

[0004] Furthermore, various novel high-efficiency memory cells, such as resistive random access memory (RRAM), phase-change memory (PCM), and magnetic induction change memory (MIM), are often employed in the implementation of analog in-memory computing to achieve higher throughput and energy efficiency ratios than traditional memories. However, because the process maturity of these novel devices is still being ramped up, their non-ideal characteristics are more prone to soft errors. Therefore, the reliable implementation of analog in-memory computing based on novel memories urgently requires error correction encoding and decoding methods and systems for both partial and cumulative errors.

[0005] In traditional memory, error correction coding methods are mostly sparse binary codes. This coding method not only has a higher code rate than Hamming codes, but also possesses the ability to perform multi-bit error correction. However, in analog in-memory computing applications, because such codewords can only distinguish between parity errors at specific bits, they cannot correct errors in the accumulated results of analog in-memory computing. Therefore, an encoding / decoding method that can directly correct the accumulated results of multiple bits, along with its corresponding decoding circuit, can significantly reduce the probability of erroneous bits occurring and greatly improve the reliability of analog in-memory computing circuits in practical applications. Summary of the Invention

[0006] To address the robustness issue of simulated in-memory computation output results, this invention proposes for the first time to encode the in-memory computation results and stored data using finite-field sparse coding, and then restore them at the output end. This reduces the bit error rate of the in-memory computation results and improves their reliability. Simultaneously, leveraging the characteristics of non-binary sparse coding, the finite field used for encoding is adjusted, using a field obtained by modulo a prime number for encoding. This increases the overall code rate of the stored information and enables the coding to support verification of both the in-memory computation portion and the accumulated output codeword. For clarity, the variables used are listed in the table below.

[0007] variable name describe X Information bit codeword <![CDATA[G e ]]> Generating matrix n Encoded information bit length m Encoding check bit length Z Encoding full codeword q The number of elements in a finite field, i.e., the prime number used to generate the finite field. LLR log-likelihood value H Verification matrix

[0008] As mentioned earlier, the encoding process of this invention uses non-binary sparse encoding. To ensure that the computational rules between encoded codewords are the same as those for normal integer fields, this invention replaces the Galois field of the non-binary sparse encoding with a finite field Q derived from the integer field computation result modulo a prime number q, i.e.

[0009] When using it, the same as traditional non-binary encoding, a generator matrix G is required. e All elements are in a finite field Q, which passes through the identity matrix I. n×n Parity bit generation matrix M n×m Composition, namely:

[0010] G e =[I n×n |M n×m ]

[0011] After converting the information codeword in the integer field to the finite field Q, encoding can be completed using a generator matrix. Decoding requires another matrix, the parity check matrix H, which consists of m rows and n+m columns of finite field elements, and must satisfy...

[0012] G e ×H T ={0} n×m

[0013] Where H TThis represents the transpose of the parity-check matrix. The decoding process is completed jointly by n+m variable nodes V and m parity nodes C. The parity-check matrix H actually records the connection relationships and connection weights from the n+m variable nodes to the m parity nodes. When a codeword is input to a variable node, it estimates the probability of its possible values ​​based on the input value of that bit, generating a log-likelihood vector (LLR). The number of LLR vectors is determined by the order of the finite field Q, i.e., the prime number q used to generate the finite field. The largest value in this vector represents the initial value of the current bit in this loop. Afterwards, the variable nodes pass the probability vector to the parity nodes according to the connections specified by the parity-check matrix H. In the parity nodes, the passing results from the variable nodes are checked to see if they conform to the encoding rules, i.e., whether they are correct. If correct or the loop upper limit is reached, the loop ends and the codeword result is output; otherwise, the log-likelihood value iteration process is performed within each parity node C, and the updated log-likelihood value is returned to the variable node V according to the parity-check matrix H. In each variable node, combining the initial value and the return value of the check node generates a new codeword, and the above iteration process is repeated until the loop ends. The specific encoding and decoding process is as follows:

[0014] 1) For an n-bit information codeword X, first generate its mapping X in a finite field Q of order q. Q ,Right now

[0015] X Q =X%q

[0016] 2) After obtaining the finite field codeword X Q Then, using the generating matrix G e Encode it, and let the generated codeword be Z. o ,but

[0017] Z0 = X Q ×G e

[0018] All operations are performed within a specified finite field Q of order q.

[0019] 3) During decoding, let the input codeword be Z, and for each element z... i Generate a log-likelihood value LLR ij (in Characteristic element z i p is the probability p of element j in a finite field j The generated log-likelihood values ​​are as follows:

[0020] LLR ij =lg(p j )

[0021] 4) Input the log-likelihood value obtained in the previous step into the variable node V.k ,in Stored as initial log-likelihood value LLR k_prior Simultaneously record the LLR value of the variable node output. k_voutput LLR (Likelihood of Input Variable Nodes) k_input All are LLR k_prior The element corresponding to its maximum value is the initial codeword element value.

[0022] 5) In the l-th iteration, the variable node V k LLR k_voutput and Send the verification matrix H to the corresponding verification node C. ξ ,in When ξ < m, the LLR needs to be swapped by performing operations based on the elements in the parity check matrix H. k_voutput The order, that is If a < q, then Where h is the element in the check matrix H corresponding to the connection between this check node and the variable node, and q is a prime number used to generate the finite field of the encoding. Represents the verification node C ξ Received variable node V k The log-likelihood value, and the verification node C ξ Received variable node V k The perceived code value is denoted as

[0023] 6) If for all The vector H corresponding to the check node in the check matrix H i(1×(n+m)) ,have

[0024]

[0025] Then it passes the check and jumps to step 10). If the loop limit is reached, it also jumps to step 10. Otherwise, it continues to step 7.

[0026] 7) At each verification node C ξ In China, it will be based on To propagate and thus obtain LLR output_ξ And send the corresponding log-likelihood values ​​back to each variable node, where Represents the verification node C ξ All log-likelihood values ​​obtained from the variable nodes connected to it, LLR output_ξ This indicates that node C is verified after the propagation process. ξ The propagation process for all log-likelihood values ​​to be passed to the variable nodes is as follows:

[0027] Suppose that the log-likelihood values ​​of two adjacent pairs are {A0, A1, ..., A...} q-1} and {B0, B1, ..., B q-1 The result obtained after propagation is {Y0, Y1, ..., Y}. q-1},So

[0028]

[0029]

[0030] This process is defined as F(X, Y), where X and Y each represent a set of log-likelihood values; after propagation, it is assumed that the current verification node is connected to Ψ variable nodes, and its log-likelihood value is LLR. ψ ,in And ψ < Ψ, and assume that the results of its forward and backward propagation are {L} respectively. f1 L f2 ,..., L f (Ψ-1)} and {L b1 L b2 , ..., L b(Ψ-1)},in

[0031] L fi =F(L f(ψ-1) LLR ψ-1 ), L bi =F(L b(ψ+1) LLR ψ ), ψ=1, 2, 3,..., Ψ-1

[0032] L f0 =L bΨ =0

[0033] The final output passed to the variable node is {L} O1 L O2 , ..., L OΨ The expression is

[0034]

[0035] As can be seen, for all L Oψ None of them contain the LLR information originally sent by the variable node. ψ This means that the influence of its own transmitted information is eliminated.

[0036] 8) At each variable node V k In the end, the final result will be determined by the received LLR. k_vinput And the previously stored initial value LLR k_prior The summation yields the output codeword

[0037] 9) Start iterating again from step 4);

[0038] 10) Based on the input codeword Z and the output codeword Z in the finite field O The final result X of the information bits is obtained. O .

[0039] The decoder circuit section of this invention is as follows: Figure 1 As shown, it consists of two parts: variable nodes and check nodes. The connection between the variable nodes and check nodes is based on the check matrix H, where each row corresponds to a check node and each column corresponds to a variable node. During the transfer of log-likelihood values ​​between the variable nodes and check nodes, the sequence of transferred log-likelihood values ​​needs to be modified according to the finite field arithmetic rules to truly represent the probability of each node obtaining each value in the finite field (see step 5 above). The overall pipeline design concept of the circuit is to decouple the check nodes and variable nodes, allowing the two parts of the circuit to be designed in serial or parallel pipelines respectively. The data transfer pipeline between the check nodes and variable nodes is completed through the connection circuit between the variable nodes and check nodes. The interaction between the in-memory calculation circuit and the output circuit of the decoder circuit is all performed through the variable nodes. In this process, only codeword interaction occurs; the calculation of the log-likelihood value is completed inside the decoder.

[0040] In the variable node, it receives the corresponding input codeword from the in-memory computing unit, calculates and stores the initial log-likelihood value, connects them according to the parity check matrix, and sends them to the check node via the intermediate circuit. Simultaneously, it is also responsible for the corresponding information bit output process, passing the output value obtained after iteration, i.e., the information bit X, to the next stage circuit.

[0041] In the verification node, it verifies the codeword Z received from the variable node. O Perform validation. If the validation passes or the maximum number of iterations is reached, return the obtained input value directly and output it at the variable node. Otherwise, it is necessary to use the input value obtained from the variable node. The corresponding propagation and update are performed. During this process, quantization is required to prevent overflow, and the results are returned to the corresponding variable nodes for the next round of iteration and update.

[0042] In the connection section between the variable nodes and the check nodes, the connections need to be adjusted according to the different elements in the check matrix. This connection can be accomplished through a multiplexer or directly through adjustments to the circuit interconnects. Meanwhile, due to limited on-chip space, the number of check nodes and variable nodes may be limited. The output value of the variable node will be distributed to different check nodes depending on the state of the built-in state machine in the connection circuit.

[0043] By matching the clock of the error correction decoder circuit with the clock of the in-memory computation circuit, the codeword generation process and the verification process can be timed, thereby saving intermediate memory.

[0044] The finite field error correction encoding and decoding method and system provided by this invention for in-memory computing systems are applicable to: 1) error correction tasks involving partial and cumulative calculations in simulated in-memory computations; and 2) error correction tasks involving reading data from conventional memory. In terms of encoding and decoding principles, this invention utilizes non-binary q-order finite field operations to process the input codeword, and uses a pre-processed generator matrix to obtain the encoding results belonging to the same finite field, thereby generating the error correction code. Due to the closed nature of operations within the finite field, different codewords, after partial and cumulative calculations in in-memory computations, can still satisfy the preset error correction function during encoding, thus achieving an encoding and decoding method that simultaneously supports single-codeword error correction and error correction after multi-codeword accumulation. Based on this encoding and decoding method, this invention provides a corresponding decoding circuit system design, divided into two parts: a verification node and a variable node. The connection between the verification node and the variable node is defined by the verification matrix and employs confidence propagation based on a finite field: 1) Each verification node receives the log-likelihood values ​​of multiple connected variable nodes and, based on these likelihood values ​​and the weights of the verification matrix, derives the confidence value passed back to each connected variable node; 2) Each variable node receives the returned confidence values ​​from multiple connected verification nodes and, combined with its own likelihood value, calculates the corresponding error correction result. After multiple iterations of confidence propagation between the verification node and the variable node, the error correction result converges, yielding the final decoding result. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the decoder circuit structure based on finite field sparse coding of the present invention.

[0046] Figure 2 This is a schematic diagram of the variable node function in the decoder circuit based on finite field sparse coding of the present invention.

[0047] Figure 3 This is a schematic diagram of the verification node function in the decoder circuit based on finite field sparse coding of the present invention.

[0048] Figure 4 This is a flowchart of the decoder operation based on finite field sparse coding of the present invention. Detailed Implementation

[0049] To more clearly illustrate the objectives, technical solutions, and advantages of this invention, the invention will be further described in detail below with reference to the accompanying drawings. The description herein is merely illustrative and is not intended to limit the scope of the invention.

[0050] This invention proposes a novel error-correcting code and its decoding circuit. This encoding method employs non-binary encoding, which, compared to traditional binary encoding, can represent specific numerical values ​​rather than merely parity, thus endowing this code value with the ability to verify multi-valued elements. When applied to in-memory computing scenarios, the error-correcting code can be used to verify the calculated results.

[0051] Traditional non-binary sparse coding uses the Galois field as its finite field. However, operations on this field differ fundamentally from integer operations. When applied to in-memory computation, traditional non-binary sparse coding will no longer reside in its original field after multiplication and addition operations. Therefore, we shift the coding field of non-binary sparse coding from the Galois field to a finite field obtained by modulo a specific prime number using integer operations. This approach ensures that the result after linear multiplication and addition operations, i.e., the output result, remains within the specified field and can be decoded using the original decoding method, thus improving the reliability of the computation result. During encoding, codewords are generated directly by matrix multiplication of the information codeword and the generator matrix. However, the specific decoding method is more complex, such as... Figure 4 The diagram shown illustrates the specific decoding process. The detailed encoding and decoding process is as follows:

[0052] 1) For an n-bit information codeword X, first generate its mapping X in a finite field Q of order q. Q ,Right now

[0053] X Q =X%q

[0054] 2) After obtaining the finite field codeword X Q Then, using the generating matrix G e Encode it, and let the generated codeword be Z. o ,but

[0055] Z0 = X Q ×G e

[0056] All operations are performed within a specified finite field Q of order q.

[0057] 3) During decoding, let the input codeword be Z, and for each element z... i Generate a log-likelihood value LLR ij ,in Characteristic element z i p is the probability p of element j in a finite field j The generated log-likelihood values ​​are as follows:

[0058] LLR ij =lg(p j )

[0059] 4) Input the obtained log-likelihood value into the variable node V. k ,in Stored as initial log-likelihood value LLR k_prior Simultaneously record the LLR value of the variable node output. k_voutput LLR (Likelihood of Input Variable Nodes) k_input All are LLR k_prior The element corresponding to its maximum value is the initial codeword element value.

[0060] 5) In the l-th iteration, the variable node V k LLR k_voutput and Send the verification matrix H to the corresponding verification node C. ξ ,in When ξ < m, the LLR needs to be swapped by performing operations on the elements in the check matrix. k_voutput The order, that is If a < q, then Where h is the element in the check matrix H corresponding to the connection between this check node and the variable node, and q is a prime number used to generate the finite field of the encoding. Represents the verification node C ξ Received variable node V k The log-likelihood value, and the verification node C ξ Received variable node V k The perceived code value is denoted as

[0061] 6) If for all The vector H corresponding to the check node in the check matrix H i(1×(n+m)) ,have

[0062]

[0063] Then it passes the check and jumps to step 10). If the loop limit is reached, it also jumps to step 10. Otherwise, it continues to step 7.

[0064] 7) At each verification node C ξ In China, it will be based on To propagate and thus obtain LLR output_ξ And send the corresponding log-likelihood values ​​back to each variable node, where Represents the verification node C ξ All log-likelihood values ​​obtained from the variable nodes connected to it, LLR output_ξ This indicates that after the propagation process, the verification node C... ξThe propagation process for all log-likelihood values ​​to be passed to the variable node is as follows:

[0065] Suppose that the log-likelihood values ​​of two adjacent pairs are {A0, A1, ..., A...} q-1} and {B0, B1, ..., B q-1 The result obtained after propagation is {Y0, Y1, ..., Y}. q-1},So

[0066]

[0067]

[0068] This process is defined as F(X, Y), where X and Y each represent a set of log-likelihood values; after propagation, it is assumed that the current verification node is connected to Ψ variable nodes, and its log-likelihood value is LLR. ψ ,in And ψ < Ψ, and assume that the results of its forward and backward propagation are {L} respectively. f1 L f2 , ..., L f(Ψ-1)} and {L b1 L b2 , ..., L b(Ψ-1)},in

[0069] L fi =F(L f(ψ-1) LLR ψ-1 ), L bi =F(L b(ψ+1) LLR ψ ), ψ=1, 2, 3,..., Ψ-1

[0070] L f0 =L bΨ =0

[0071] The final output passed to the variable node is {L} O1 L O2 , ..., L OΨ The expression is

[0072]

[0073] As can be seen, for all L Oψ None of them contain the LLR information originally sent by the variable node. ψ This means that the influence of its own transmitted information is eliminated.

[0074] 8) At each variable node V k In the end, the final result will be determined by the received LLR. k _ vinputAnd the previously stored initial value LLR k_prior The summation yields the output codeword

[0075] 9) Start iterating again from step 4);

[0076] 10) Based on the input codeword Z and the output codeword Z in the finite field O The final result X of the information bits is obtained. O .

[0077] Based on the above encoding and decoding algorithms, the decoding circuit part of this invention is as follows: Figure 1 As shown, it consists of two parts: variable nodes and verification nodes.

[0078] like Figure 2 As shown, in the variable node, it receives the corresponding input codeword from the in-memory computing unit, calculates and stores the initial log-likelihood value, connects them according to the parity check matrix, and sends them to the check node via the intermediate circuit. Simultaneously, it is also responsible for the corresponding information bit output process, passing the output value obtained after iteration, i.e., information bit X, to the next stage circuit.

[0079] like Figure 3 As shown, in the verification node, it uses the codeword Z received from the variable node. O Perform validation. If the validation passes or the maximum number of iterations is reached, return the obtained input value directly and output it at the variable node. Otherwise, it is necessary to use the input value obtained from the variable node. The corresponding propagation update is performed. During this process, in order to prevent the log-likelihood value from overflowing, a quantization operation is required, and the results are returned to the corresponding variable nodes for the next round of iteration update.

[0080] In the connection section between the variable nodes and the check nodes, the connections need to be adjusted according to the different elements in the check matrix. This connection can be accomplished through a multiplexer or directly through adjustments to the circuit interconnects. Meanwhile, due to limited on-chip space, the number of check nodes and variable nodes may be limited. The output value of the variable node will be distributed to different check nodes depending on the state of the built-in state machine in the connection circuit.

[0081] By matching the clock of the error correction decoder circuit with the clock of the in-memory computation circuit, the codeword generation process and the verification process can be timed, thereby saving intermediate memory.

[0082] This invention proposes a code and its decoding circuit that are applicable to both in-memory calculation summation results and storage system error correction codes. It does not depend on the read operation of the stored content, nor is it limited by the number of rows in the in-memory calculation summation. It can directly perform decoding operations through the calculation results, thereby improving the reliability and accuracy of the output results and effectively reducing the bit error rate.

[0083] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be determined by the claims.

Claims

1. A finite-field error correction encoding and decoding method for in-memory computing systems, wherein the encoding process uses non-binary sparse coding, and the code field of this non-binary sparse coding is a finite field Q obtained by taking the modulo of a specific prime number q in integer operations. During encoding, the information codewords in the integer field are first converted into the finite field Q, and then the generator matrix G is used. e Encoding is complete, the generator matrix G e Through the identity matrix I n×n Parity bit generation matrix M n×m Composition, namely: in, n is the length of the encoded information bits, and m is the length of the encoded check bits; The decoding process is completed jointly by n + m variable nodes V and m check nodes C. A check matrix H, composed of m rows and n + m columns of finite field elements, records the connection relationships and weights from the n + m variable nodes to the m check nodes. This check matrix H satisfies: Where H T This represents the transpose of the parity check matrix. During decoding, the variable node first generates a log-likelihood vector (LLR) based on the input codeword. The number of LLR vectors is determined by the order of the finite field Q. The largest value in this vector represents the initial value of the current bit in this loop. Afterwards, the variable node passes the probability vector to the check node according to the connection specified by the check matrix H. The check node will check whether the result of the variable node's transmission conforms to the encoding specification, i.e., whether it is correct. If it is correct or the loop upper limit is reached, the loop ends and the codeword result is output. Otherwise, the log-likelihood value iteration process will be performed in each check node, and the updated likelihood value will be returned to the variable node according to the check matrix H. In each variable node, the initial value and the return value of the check node are combined to generate a new codeword, and the above iteration process is performed again until the loop ends. The encoding and decoding process includes the following steps: 1) For an n-bit information codeword X, first generate its mapping X in a finite field Q of order q. Q ,Right now 2) Using the generating matrix G e For finite field codeword X Q Encode the codeword, and let the generated codeword be Z0. All operations are performed in a finite field Q of order q; 3) During decoding, let the input codeword be Z, and for each element z... i Generate a log-likelihood value LLR ij Characteristic element z i p is the probability p of element j in a finite field j Specifically: in ; 4) Input the log-likelihood value obtained in the previous step into the variable node V. k ,in Stored as initial log-likelihood values Simultaneously record the likelihood value of the variable node output. Likelihood values ​​of input variables All The element corresponding to its maximum value is the initial codeword element value. ; 5) In the l-th iteration, the variable node V k Will and Send the verification matrix H to the corresponding verification node ,in During the process, it is necessary to perform operations and swap elements according to the elements in the verification matrix H. The order, that is have, , where h is the element in the check matrix H corresponding to the connection between this check node and the variable node, and q is a prime number used to generate the finite field of the encoding. Representative verification node Received variable node V k The log-likelihood value, and the verification node Received variable node V k The perceived code value is denoted as ; 6) If for all , The vector corresponding to the check node in the check matrix H ,have If the loop reaches its limit, it will also jump to step 10; otherwise, it will continue to step 7. 7) At each verification node In China, it will be based on To spread and thus obtain And send the corresponding log-likelihood values ​​back to each variable node, where Representative verification node All log-likelihood values ​​obtained from the variable nodes connected to it. This indicates the verification node after the propagation process. The propagation process for all log-likelihood values ​​to be passed to the variable nodes is as follows: Suppose that the two adjacent log-likelihood values ​​are respectively and The result obtained after propagation is ,So Define this process as F(X,Y), where X and Y each represent a set of log-likelihood values; after propagation, assume the current verification node is the same as... Connecting the nodes of each variable, its log-likelihood value is ,in and And assuming that the results of its forward and backward propagation are respectively and ,in The output is then finally passed to the variable node. The expression is As can be seen, for all None of them contain the information originally sent by the variable node. This means that the influence of its own transmitted information is eliminated; 8) At each variable node V k In the end, the final result will be determined by the recipient. and the previously stored initial value The summation yields the output codeword ; 9) Start iterating again from step 4); 10) Based on the input codeword Z and the output codeword Z0 in the finite field, the final result of the information bits X0 is obtained.

2. A system for implementing the finite-field error correction encoding / decoding method for in-memory computing systems as described in claim 1, characterized in that, The decoder circuit of this system consists of two parts: variable nodes and check nodes. The variable nodes and check nodes are connected according to a check matrix H, where each row corresponds to a check node and each column corresponds to a variable node. The variable nodes receive the corresponding input codewords from the in-memory computing unit, calculate and store the initial log-likelihood value, and connect it according to the check matrix, sending it to the check nodes via intermediate circuits. Simultaneously, the variable nodes are responsible for the corresponding information bit output process, passing the output value obtained after iteration, i.e., information bit X, to the next stage circuit. The check nodes verify the codeword Z0 received from the variable nodes. If it passes verification or the iteration count reaches the upper limit, the obtained input value is directly returned and output at the variable node; otherwise, the check node needs to verify the input value obtained from the variable nodes. The corresponding propagation update is performed. During this process, in order to prevent the log-likelihood value from overflowing, a quantization operation is required, and the results are returned to the corresponding variable nodes for the next round of iteration update.

3. The system as described in claim 2, characterized in that, In the connection circuit of the variable node and the check node, the connection between the variable node and the check node needs to be adjusted according to the different elements in the check matrix. This part of the connection is completed by a multiplexer or directly by adjusting the circuit interconnects.

4. The system as described in claim 3, characterized in that, The output value of the variable node is distributed to different verification nodes according to the state of the built-in state machine in the connected circuit.

5. The system as described in claim 2, characterized in that, By matching the clock of the error correction decoder circuit with the clock of the in-memory computation circuit, the timing of the codeword generation process and the verification process is matched.

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