Superconducting quantum control multiplexing device and method of making the same

Abstract

The application discloses a superconducting quantum control multiplexing device and a preparation method thereof. Embodiments of the application greatly simplify a superconducting quantum test system, are beneficial to the large-scale development of a superconducting quantum computing circuit, and realize compatibility with a superconducting integrated circuit in a preparation process.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of quantum computing technology, and in particular to a superconducting quantum control multiplexing device and its fabrication method. Background Technology

[0002] With the rapid development of quantum computers, large-scale development of quantum computers has become an inevitable trend, and the number of qubits will continue to increase. In current superconducting quantum systems, in order to control qubits, the devices used to control qubits need to pass through a series of devices such as attenuators and filters at room temperature via a coaxial cable several meters long, finally reaching the mK temperature range to control the qubits. Each qubit requires a microwave control line.

[0003] With the large-scale development of quantum computers, the number of control microwave lines required for tens of millions of qubits is also increasing, which undoubtedly poses huge challenges to power consumption, cost, space, and volume.

[0004] The best solution to overcome these challenges would be to place the room temperature control circuitry and the quantum processor in the same temperature range for operation. Summary of the Invention

[0005] This application provides a superconducting quantum control multiplexing device and its fabrication method, which can greatly simplify the superconducting quantum testing system and is conducive to the large-scale development of superconducting quantum computing circuits.

[0006] This invention provides a superconducting quantum-controlled multiplexing device, comprising: two or more first filters, two or more isolators, two or more capacitors, and three bias line circuits integrated on a single chip; wherein,

[0007] The first filter is used to filter input signals of different frequencies from a microwave control line;

[0008] An isolator is used to convert signals from a filter and output them. An isolator is a four-port device, with two ports for impedance matching loads, one port for input, and one port for output. The input and output ports of the isolator are each connected to a balun.

[0009] A capacitor is installed in the isolator, and the center operating frequency of the isolator is adjusted by adjusting the capacitance value.

[0010] The bias line circuit is used to adjust the bias magnetic field of the isolator. Each bias line of the bias line circuit is connected to a second filter.

[0011] In one exemplary instance, the first filter is a coplanar waveguide CPW with a wavelength of λ / 2; the second filter is a low-pass filter LPF.

[0012] In one exemplary instance, the three bias line circuits extend through the isolator and include: a bias line circuit for a cosine signal, a bias line circuit for a sine signal, and a global magnetic field bias line circuit.

[0013] In one exemplary instance, the two ports of the isolator are respectively impedance-matched to loads including: respectively connected to resistors with a pre-resistance of 50 ohms;

[0014] Alternatively, the two ports of the isolator may be impedance-matched to loads including λ / 4 wavelength CPW filters respectively.

[0015] In one exemplary instance, the superconducting quantum control multiplexing device is a five-port device, the input terminal of which is connected to the input terminal of the first filter to receive input signals of different frequencies from a microwave control line; the output terminal of the superconducting quantum control multiplexing device is the output port of the isolator.

[0016] The first filter includes four λ / 2 wavelength CPW filters; the isolator includes four isolators; the capacitor includes eight capacitors, with two capacitors in each isolator; the three bias line circuits include one bias line circuit for Cosine signal, one bias line circuit for Sine signal, and one global magnetic field bias line circuit.

[0017] The balun comprises eight filters, and the second filter comprises eight filters, which are LPFs.

[0018] The impedance matching load consists of eight 50Ω gold ingot resistors or eight λ / 4 wavelength CPWs.

[0019] In one exemplary instance, it also includes: a superconducting quantum interference device (SQUID) array disposed in the isolator;

[0020] The SQUID array comprises 768 SQUIDs, with 192 SQUIDs configured in each of the isolators;

[0021] The superconducting quantum-controlled multiplexed microwave device is based on a tunable Wheatstone inductor bridge, the inductor being composed of the SQUID string.

[0022] This application also provides a method for fabricating a superconducting quantum control multiplexing device, characterized in that the method for fabricating the superconducting quantum control multiplexing device described in any one of the above claims includes:

[0023] The first sample was obtained by growing silicon dioxide (SiO2) thin films on both sides of a silicon wafer using a thermal oxidation method.

[0024] Multiple patterns of the superconducting quantum control multiplexing device are formed by sequentially performing photolithography on the front side of the first sample.

[0025] The reverse side of the sample after forming multiple patterns is processed to form the on-chip superconducting control multiplexer.

[0026] In one exemplary instance, the multiple photolithography steps include ten steps;

[0027] The process of sequentially performing multiple photolithography steps on the front side of the first sample to form multiple patterns for the superconducting quantum control multiplexing device includes:

[0028] The first photolithography is performed on the front side of the first sample to prepare a three-layer thin film A, and the first pattern is obtained by peeling it off to obtain the second sample;

[0029] A Nb thin film B is prepared on the front side of the second sample, and a second photolithography is performed to etch the Nb thin film. Then, a first SiO2 thin film is grown using radio frequency magnetron sputtering technology as the first protective layer of the Nb thin film B, and the second pattern is obtained by peeling off to obtain the third sample.

[0030] Thin film C is prepared on the front side of the third sample, and a third photolithography is performed to etch the third pattern to obtain the fourth sample;

[0031] A fourth photolithography was performed on the front side of the fourth sample, and SiO2 and Al-AlOx were etched to obtain a through-hole pattern, thus obtaining the fifth sample.

[0032] A fifth photolithography was performed on the front side of the fifth sample to prepare an Au thin film E, and the fifth pattern was obtained by peeling it off to obtain the sixth sample.

[0033] On the front side of the sixth sample, a SiO2 thin film was prepared as a dielectric layer for capacitors and cross-line by plasma-enhanced chemical vapor deposition (PECVD). Then, a sixth photolithography was performed and etched to obtain the sixth pattern, namely the SiO2 dielectric layer pattern, to obtain the seventh sample.

[0034] A Nb thin film G is prepared on the front side of the seventh sample, and then a seventh photolithography is performed and etched to obtain the seventh pattern, so as to obtain the eighth sample. The seventh pattern includes: a cross-line pattern, a capacitor upper electrode pattern, a Balun pattern, and an LPF pattern.

[0035] A second SiO2 thin film was grown on the front side of the eighth sample as a second protective layer for the Nb thin film G. Then, the eighth photolithography was performed and etched to obtain the through-hole pattern to obtain the ninth sample.

[0036] A Nb thin film I was prepared on the front side of the ninth sample, and then a ninth photolithography was performed, followed by etching to obtain a bias line pattern, in order to obtain the tenth sample.

[0037] The tenth photolithography is performed on the front side of the tenth sample to etch SiO2 in the blank areas of the device, thus obtaining the tenth pattern and the eleventh sample.

[0038] In one exemplary instance, processing the reverse side of the sample after forming multiple patterns to form the on-chip superconducting control multiplexer includes:

[0039] An Al thin film was prepared on the reverse side of the eleventh sample to obtain the on-chip superconducting control multiplexer.

[0040] In one exemplary instance, the multiple photolithography steps include four steps;

[0041] The process of sequentially performing multiple photolithography steps on the front side of the first sample to form multiple patterns for the superconducting quantum control multiplexing device includes:

[0042] The first photolithography is performed on the front side of the first sample to prepare a three-layer thin film A, and the first pattern is obtained by peeling it off to obtain the second sample;

[0043] A second photolithography was performed on the front side of the second sample to prepare an Nb thin film B. The Nb thin film was etched, and a first SiO2 thin film was regrown as a protective layer for the Nb thin film B. The second pattern was then peeled off to obtain the third sample.

[0044] A third photolithography is performed on the front side of the third sample to prepare thin film C, and the third pattern is etched to obtain the fourth sample;

[0045] The fourth photolithography was performed on the front side of the fourth sample to prepare an Au thin film D, and the eleventh pattern was obtained by peeling it off to obtain the twelfth sample.

[0046] In one exemplary instance, processing the reverse side of the sample after forming multiple patterns to form the on-chip superconducting control multiplexer includes:

[0047] An Al thin film was prepared on the reverse side of the twelfth sample to obtain the on-chip superconducting control multiplexer.

[0048] In one exemplary instance, the thickness of the thin film A is 300–330 nm;

[0049] The material of the thin film A includes three layers: Nb, Al-AlOx, and Nb.

[0050] In one exemplary instance, the thickness of the thin film A is 330 nm.

[0051] In one exemplary instance, the thickness of the Nb thin film B is 160 nm; the thickness of the first protective layer is 100–250 nm.

[0052] In one exemplary instance, the thickness of the first protective layer is 250 nm.

[0053] In one exemplary instance, the thickness of the thin film C is 150–300 nm; the material of the thin film C is Nb.

[0054] In one exemplary instance, the thickness of the thin film C is 160 nm.

[0055] In one exemplary instance, the thickness of the Au thin film E is 135–225 nm.

[0056] In one exemplary instance, the thickness of the Au thin film E is 225 nm.

[0057] In one exemplary instance, the thickness of the SiO2 dielectric layer is 300–500 nm.

[0058] In one exemplary instance, the thickness of the SiO2 dielectric layer is 250 nm.

[0059] In one exemplary instance, the thickness of the Nb thin film G is 300–600 nm.

[0060] In one exemplary instance, the thickness of the Nb thin film G is 160 nm.

[0061] In one exemplary instance, the thickness of the second protective layer is 300–500 nm.

[0062] In one exemplary instance, the thickness of the second protective layer is 250 nm.

[0063] In one exemplary instance, the thickness of the Nb thin film I is 300–600 nm.

[0064] In one exemplary instance, the thickness of the Nb thin film I is 160 nm.

[0065] In one exemplary instance, the thickness of the Au thin film E is 135–225 nm.

[0066] In one exemplary instance, the thickness of the Au thin film E is 225 nm.

[0067] In one exemplary instance, the thickness of the Al film is 300–600 nm.

[0068] In one exemplary instance, the Al film has a thickness of 600 nm.

[0069] The superconducting quantum control multiplexing device provided in this application greatly simplifies the superconducting quantum testing system and is conducive to the large-scale development of superconducting quantum computing circuits.

[0070] The fabrication method of the superconducting quantum control multiplexing device provided in this application is compatible with superconducting integrated circuits in terms of process, which greatly simplifies the superconducting quantum testing system and is conducive to the large-scale development of superconducting quantum computing circuits.

[0071] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0072] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0073] Figure 1 This is a schematic diagram of the composition structure of the superconducting quantum control multiplexing device in the embodiments of this application;

[0074] Figure 2 This is a schematic flowchart of one embodiment of the fabrication method of the superconducting quantum control multiplexed device in this application.

[0075] Figure 3(a) shows the embodiment of this application. Figure 2 A schematic diagram of the layout of an on-chip superconducting control multiplexer MCC-1 in one of the fabrication methods shown;

[0076] Figure 3(b) shows the implementation of this application. Figure 2 A schematic diagram of the layout of another on-chip superconducting control multiplexer MCC-2 in one of the fabrication methods shown;

[0077] Figure 3(c) shows the implementation of this application. Figure 2 A schematic diagram of the core region layout of an on-chip superconducting control multiplexer in one of the fabrication methods shown in the figure;

[0078] Figure 3(d) shows the implementation of this application. Figure 2 A schematic diagram of the design of the alignment mark in one of the preparation methods shown;

[0079] Figure 3(e) shows the implementation of this application. Figure 2 A schematic cross-sectional view of one of the preparation methods shown;

[0080] Figure 4(a) shows the embodiment of this application. Figure 2 A schematic diagram of the layout of another on-chip superconducting control multiplexer MCC-1 in another fabrication method shown;

[0081] Figure 4(b) shows the implementation method used in this application. Figure 2 A schematic diagram of the layout of another on-chip superconducting control multiplexer MCC-2 in another fabrication method shown;

[0082] Figure 4(c) shows the implementation of this application. Figure 2 A schematic diagram of the core region layout of the on-chip superconducting control multiplexer in another fabrication method shown;

[0083] Figure 4(d) shows the implementation method used in this application. Figure 2 A cross-sectional view of another preparation method shown. Detailed Implementation

[0084] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0085] Figure 1 This is a schematic diagram of the composition structure of the superconducting quantum control multiplexing device in the embodiments of this application, as shown below. Figure 1 As shown, it includes: two or more first filters 9, two or more isolators, two or more capacitors, and three bias line circuits integrated on a single chip; wherein,

[0086] The first filter 9 is used to filter input signals of different frequencies from a microwave control line;

[0087] Isolator 16 is used to convert and output the signal from the filter. The isolator is a two-port device, in which the two ports are impedance-matched loads, one port is the input port and the other port is the output port; the input port and the output port of the isolator are respectively connected to baluns.

[0088] Capacitor 13 is installed in the isolator, and the center operating frequency of the isolator is adjusted by adjusting the capacitance value of the capacitor.

[0089] The bias line circuit 15 is used to adjust the bias magnetic field of the isolator. Each bias line of the bias line circuit is connected to a second filter 12.

[0090] In one exemplary instance, the first filter 9 is used for frequency selection. Input signals of different frequencies from a single microwave control line enter the superconducting quantum control multiplexing device. The first filter 9 divides the microwave signals of different frequencies, and then transmits them separately into N channels. Finally, each channel is isolated by an isolator 16 (e.g., ...). Figure 1 The output ports of the first isolator, second isolator...Nth isolator shown in the diagram are used to achieve direct operational control of the qubits. In one embodiment, the first filter 9 may include, but is not limited to, a λ / 2 wavelength coplanar waveguide (CPW) as a filter with frequency selection function;

[0091] In one exemplary embodiment, the second filter 12 is used to isolate the microwave field from the bias line, preventing the radio frequency bias signal from interfering with the operation of the microwave circuit, while reducing additional losses from coupling with the bias line. In one embodiment, the second filter 12 may include, but is not limited to, a low-pass filter (LPF).

[0092] In one exemplary instance, three bias line circuits 15 run through all isolators 16 (e.g., Figure 1 The first isolator, the second isolator, ... the Nth isolator shown in the figure include: a bias line circuit for a Cosine signal, a bias line circuit for a Sine signal, and a global magnetic field bias line circuit.

[0093] In one exemplary instance, Barron 10 (such as...) Figure 1 The structures Balun11, Balun12, Balun21, Balun22, Balun31, Balun32, Balun41, and Balun42 are used to realize the conversion structure between balanced and unbalanced transmission lines, that is, the conversion between CPW and microstrip lines.

[0094] In one exemplary instance, two of the ports of isolator 16 used for impedance matching are respectively connected to a pre-resistance resistor 11. In one embodiment, resistor 11 is a 50Ω gold ingot resistor; or, two of the ports of isolator 16 used for impedance matching are respectively connected to a λ / 4 wavelength CPW filter 11.

[0095] In one exemplary instance, the center frequency of the superconducting quantum control multiplexing device can be changed by adjusting the area of ​​capacitor 14.

[0096] In one exemplary instance, the superconducting quantum control multiplexer (MCC) is a five-port device. The input terminal of the superconducting quantum control multiplexer is connected to the input terminal of the first filter 9 to receive input signals of different frequencies from a microwave control line. The output terminal of the superconducting quantum control multiplexer includes the output ports of each isolator 16. The first filter 9 includes four λ / 2 wavelength CPW filters. The isolators 16 include four. The capacitors 13 include eight, with two capacitors 13 disposed in each of the isolators 16. The three bias line circuits 15 include a bias line circuit for a cosine signal, a bias line circuit for a sine signal, and a global magnetic field bias line circuit. The baluns 10 include eight, and the second filters 12 include eight LPFs. The impedance matching load 11 includes eight 50Ω gold block resistors or eight λ / 4 wavelength CPWs. In one embodiment, the superconducting quantum control multiplexing device may further include a superconducting quantum interference device (SQUID) array disposed in the isolator 16; wherein the SQUID array may include 768 SQUIDs, with 192 SQUIDs disposed in each isolator 16. In one embodiment, the superconducting quantum control multiplexing device is based on an adjustable Wheatstone inductor bridge, wherein the inductor is composed of SQUID strings.

[0097] In one exemplary instance, bias line circuit 15 is used to adjust the magnetic flux in a SQUID, thereby regulating the superconducting quantum control multiplexing device. In one embodiment, bias line circuit 15 may include a first bias line circuit, a second bias line circuit, and a third bias line circuit. The first bias line circuit runs through each isolator 16, for example, it can be disposed on a set of SQUIDs running through each isolator, and is a cosine signal bias line circuit, i.e., a cosine bias line circuit. The second bias line circuit runs through each isolator 16, for example, it can be disposed on another set of SQUIDs running through each isolator, and is a sine signal bias line circuit, i.e., a sine bias line circuit. The third bias line circuit runs through the core region of the entire device and is an on-chip coil circuit, i.e., a global magnetic field bias line circuit.

[0098] In one embodiment, the superconducting quantum control multiplexing device provided in this application is a five-port device based on an adjustable Wheatstone inductor bridge, wherein the inductors are composed of SQUID strings. It operates at a temperature range of 20 mK and a frequency range of 4-8 GHz, covering the entire operating frequency range of the qubit. This superconducting quantum control multiplexing device in this embodiment can achieve direct operation of four qubits using a single microwave control line with a control multiplexing ratio of 1:4. It features non-reciprocity, small size, and integration with superconducting circuits. Furthermore, it protects the quantum chip from interference, greatly simplifies the superconducting quantum testing system, and is beneficial for the large-scale development of superconducting quantum computing circuits.

[0099] The superconducting quantum control multiplexing device provided in this application greatly simplifies the superconducting quantum testing system and is conducive to the large-scale development of superconducting quantum computing circuits.

[0100] Figure 2 This is a schematic flowchart of one embodiment of the fabrication method of the superconducting quantum-controlled multiplexed device in this application, as shown below. Figure 2 As shown, it includes:

[0101] Step 100: Silicon dioxide (SiO2) films are grown on both sides of the silicon wafer using thermal oxidation to obtain the first sample.

[0102] In one embodiment, the silicon wafer can be 4 inches. <100> N-type single-sided polished silicon wafer. In one embodiment, the thickness of the SiO2 thin film can be, for example, 400 nanometers (nm).

[0103] Step 101: Perform multiple photolithography steps sequentially on the front side of the first sample to form multiple patterns of the superconducting quantum control multiplexing device.

[0104] In one embodiment of the fabrication method, step 101 may include: sequentially performing ten photolithography operations on the front side of the first sample to form ten patterns of a superconducting quantum control multiplexing device, specifically including:

[0105] Step 1011a: Perform photolithography on the front side of the first sample to form a first pattern, and obtain the second sample.

[0106] In one embodiment, a first photolithography is performed on the front side of the sample obtained after step 100 to prepare a three-layer thin film A, and then the first pattern is obtained by peeling off. In one embodiment, thin film A can be a superconducting metal film A, with a thickness of, for example, 300-330 nm. The material of the superconducting metal film A can be, but is not limited to, Nb, Al-AlOx, and Nb three layers. In one embodiment, the thickness of the superconducting metal film A can be 330 nm. In one embodiment, the three-layer thin film A can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0107] Step 1012a: Perform photolithography on the front side of the second sample to form a second pattern, thus obtaining the third sample.

[0108] In one embodiment, an Nb thin film B is prepared on the front side of the sample obtained after step 1011a. A second photolithography is performed to etch the Nb thin film, and a first SiO2 thin film is regrown as the first protective layer (SiO2 protective layer) of the Nb thin film B. The second pattern is then obtained by peeling off the film. Step 102 defines the Josephson junction (JJ junction) using a self-aligned process. In one embodiment, the Nb thin film B can be prepared using methods such as DC magnetron sputtering, RF magnetron sputtering, or evaporation. In one embodiment, the first SiO2 thin film can be grown using methods such as DC magnetron sputtering, RF magnetron sputtering, or evaporation. In one embodiment, the Nb thin film B can be prepared using DC magnetron sputtering, and the first SiO2 thin film can be grown using RF magnetron sputtering.

[0109] In one embodiment, the thickness of the Nb thin film B can be, for example, 160 nm; the thickness of the SiO2 protective layer can be, for example, 100–250 nm. In one embodiment, the thickness of the SiO2 protective layer can be 250 nm.

[0110] Step 1013a: Perform photolithography on the front side of the third sample to form the third pattern, thus obtaining the fourth sample.

[0111] In one embodiment, a thin film C is prepared on the front side of the sample obtained after step 1012a, and a third photolithography is performed to etch a third pattern.

[0112] In one embodiment, the thin film C can be a superconducting metal film C with a thickness of, for example, 150–300 nm. The material of the superconducting metal film C can be, but is not limited to, Nb. In one embodiment, the thickness of the superconducting metal film C can be 160 nm. In one embodiment, the thin film C can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0113] Step 1014a: Perform photolithography on the front side of the fourth sample to form the fourth pattern, thus obtaining the fifth sample.

[0114] In one embodiment, after obtaining the front side of the sample through step 1013a, a fourth photolithography is performed, and SiO2 and Al-AlOx are etched to obtain the fourth pattern, namely the through-hole pattern.

[0115] Step 1015a: Perform photolithography on the front side of the fifth sample to form the fifth pattern, thus obtaining the sixth sample.

[0116] In one embodiment, a fifth photolithography is performed on the front side of the sample obtained after step 1014a to prepare an Au thin film E, and then the fifth pattern is obtained by peeling off.

[0117] In one embodiment, the thickness of the Au thin film E can be, for example, 135–225 nm. In another embodiment, the thickness of the Au thin film E can be 225 nm. In one embodiment, the Au thin film E can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0118] Step 1016a: Perform photolithography on the front side of the sixth sample to form the sixth pattern, thus obtaining the seventh sample.

[0119] In one embodiment, on the front side of the sample obtained after step 1015a, a SiO2 thin film is prepared as a dielectric layer for capacitors and cross-line using plasma-enhanced chemical vapor deposition (PECVD), and then a sixth photolithography is performed to etch the sixth pattern, namely the SiO2 dielectric layer pattern.

[0120] In one embodiment, the thickness of the SiO2 dielectric layer can be, for example, 300–500 nm. In another embodiment, the thickness of the SiO2 dielectric layer can be 250 nm.

[0121] Step 1017a: Perform photolithography on the front side of the seventh sample to form the seventh pattern, thus obtaining the eighth sample.

[0122] In one embodiment, on the front side of the sample obtained after step 1016a, an Nb thin film G is formed, and then a seventh photolithography is performed to etch a seventh pattern, which includes: a cross-line pattern, a capacitor upper electrode pattern, a Balun pattern, and an LPF pattern.

[0123] In one embodiment, the thickness of the Nb thin film G can be, for example, 300–600 nm. In another embodiment, the thickness of the Nb thin film G can be 160 nm. In one embodiment, the Nb thin film G can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0124] Step 1018a: Perform photolithography on the front side of the eighth sample to form the eighth pattern, thus obtaining the ninth sample.

[0125] In one embodiment, a second SiO2 film is grown on the front side of the sample obtained after step 1017a as a second protective layer for the Nb film G. Then, an eighth photolithography step is performed, and the eighth pattern, i.e., the through-hole pattern, is obtained by etching. In one embodiment, the second SiO2 film can be grown by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0126] In one embodiment, the thickness of the second protective layer can be, for example, 300-500 nm. In another embodiment, the thickness of the second protective layer can be 250 nm.

[0127] Step 1019a: Perform photolithography on the front side of the ninth sample to form the ninth pattern, thus obtaining the tenth sample.

[0128] In one embodiment, an Nb thin film I is prepared on the front side of the sample obtained after step 1018a, and then a ninth photolithography is performed to etch the ninth pattern, namely the bias line pattern.

[0129] In one embodiment, the thickness of the Nb thin film I can be, for example, 300–600 nm. In another embodiment, the thickness of the Nb thin film I can be 160 nm. In one embodiment, the Nb thin film I can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0130] Step 1020a: Perform photolithography on the front side of the tenth sample to form the tenth pattern, thus obtaining the eleventh sample.

[0131] In one embodiment, a tenth photolithography step is performed on the front side of the sample obtained after step 1019a to etch SiO2 in the blank areas of the device, thereby reducing device loss and obtaining the tenth pattern.

[0132] Step 111: Process the reverse side of the sample after forming multiple patterns to form an on-chip superconducting control multiplexer.

[0133] In one embodiment, step 111 may include: preparing an Al thin film on the reverse side of the sample obtained after step 1020a, i.e., the eleventh sample reverse side, to obtain an on-chip superconducting control multiplexed device. In one embodiment, the thickness of the Al thin film may be, for example, 300–600 nm. In one embodiment, the thickness of the Al thin film may be 600 nm. In one embodiment, the Al thin film may be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0134] The fabrication method of the superconducting quantum control multiplexing device provided in this application is compatible with superconducting integrated circuits in terms of process, which greatly simplifies the superconducting quantum testing system and is conducive to the large-scale development of superconducting quantum computing circuits.

[0135] In another embodiment of the preparation method, Figure 2 Step 101 may include: performing four photolithography processes sequentially on the front side of the first sample to form four patterns for the superconducting quantum-controlled multiplexing device, specifically including:

[0136] Step 1011b: Perform photolithography on the front side of the first sample to form the first pattern, and obtain the second sample.

[0137] In one embodiment, a first photolithography is performed on the front side of the sample obtained after step 100 to prepare a three-layer thin film A, and then the first pattern is obtained by peeling off.

[0138] In one embodiment, thin film A can be a superconducting metal film A, with a thickness of, for example, 300-330 nm. The material of the superconducting metal film A can be, but is not limited to, Nb, Al-AlOx, and a three-layer Nb composition. In one embodiment, the thickness of the superconducting metal film A can be 330 nm. In one embodiment, thin film A can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0139] Step 1012b: Perform photolithography on the front side of the second sample to form a second pattern, thus obtaining the third sample.

[0140] In one embodiment, a second photolithography is performed on the front side of the sample obtained after step 1011b to prepare an Nb thin film B. The Nb thin film is then etched, and a first SiO2 thin film is regrown as the first protective layer of the Nb thin film B, i.e., the SiO2 protective layer. The second pattern is then obtained by peeling off the film. Step 202 defines the Josephson junction (JJ junction) by employing a self-aligned process.

[0141] In one embodiment, the thickness of the Nb thin film B can be, for example, 160 nm; the thickness of the SiO2 first protective layer can be, for example, 100–250 nm. In one embodiment, the thickness of the SiO2 first protective layer can be 250 nm. In one embodiment, the Nb thin film B can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation. In one embodiment, the first SiO2 thin film can be grown by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation. In one embodiment, the Nb thin film B can be prepared by DC magnetron sputtering, and the first SiO2 thin film can be grown by radio frequency magnetron sputtering.

[0142] Step 1013b: Perform photolithography on the front side of the third sample to form the third pattern, thus obtaining the fourth sample.

[0143] In one embodiment, a thin film C is prepared on the front side of the sample obtained after step 1012b, a third photolithography is performed, and a third pattern is obtained by etching. In another embodiment, the thin film C can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0144] In one embodiment, the thin film C can be a superconducting metal film C with a thickness of, for example, 150–300 nm. The material of the superconducting metal film C can be, but is not limited to, Nb. In one embodiment, the thickness of the superconducting metal film C can be 160 nm.

[0145] Step 1014b: Perform photolithography on the front side of the fourth sample to form the eleventh pattern, thus obtaining the twelfth sample.

[0146] In one embodiment, after obtaining the front side of the sample through step 1013b, a fourth photolithography is performed to prepare an Au thin film D, which is then peeled off to obtain an eleventh pattern. In another embodiment, the Au thin film D can be prepared using methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0147] In one embodiment, the thickness of the Au thin film E can be, for example, 135–225 nm. In another embodiment, the thickness of the Au thin film E can be 225 nm.

[0148] In another embodiment, step 111 may include: preparing an Al thin film on the reverse side of the sample obtained after step 1014b, i.e., the twelfth sample reverse side, to obtain an on-chip superconducting control multiplexed device. In one embodiment, the thickness of the Al thin film may be, for example, 300–600 nm. In one embodiment, the thickness of the Al thin film may be 600 nm. In one embodiment, the Al thin film may be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0149] The fabrication method of the superconducting quantum control multiplexing device provided in this application is compatible with superconducting integrated circuits in terms of process, which greatly simplifies the superconducting quantum testing system and is conducive to the large-scale development of superconducting quantum computing circuits.

[0150] Figure 3(a) shows the embodiment of this application. Figure 2The diagram shows a layout of an on-chip superconducting control multiplexer MCC-1 fabricated using a specific method. In Figure 3(a): 1 represents the pad for port 1, 2 represents the pad for port 2, 3 represents the pad for port 3, 4 represents the pad for port 4, 5 represents the pad for port 5, 6 represents the cosine bias line, 7 represents the sine bias line, 8 represents the global magnetic field bias line, 9 represents the λ / 2 wavelength CPW, 10 represents the balun, 111 represents the 50Ω gold ingot resistor, and 12 represents the LPF. As shown in Figure 4(a), the on-chip superconducting control multiplexer MCC-1 in this embodiment includes 5 ports, 4 λ / 2 wavelength CPWs, 8 baluns, 8 LPFs, 768 SQUIDs, 1152 JJ junctions, 8 capacitors, 1 cosine bias line, 1 sine bias line, 1 global magnetic field bias line, 13 pads, and 8 50Ω gold ingot resistors. In this embodiment, the microwave signal enters the on-chip superconducting control multiplexing device MCC-1 through port 1. The microwave signal of different frequencies is divided by a λ / 2 wavelength CPW and then separately transmitted into four channels, and output through ports 2, 3, 4, and 5 respectively, ultimately achieving direct manipulation and control of the qubits. In one embodiment, the JJ junction can be a circle with a diameter of 3.5 μm, based on a self-aligned superconducting niobium junction process. Referring to Figure 3(c), the on-chip superconducting control multiplexing device MCC-1 in this embodiment also includes a crossover line 15 for connecting different layers of metal thin films.

[0151] Figure 3(b) shows the implementation of this application. Figure 2The diagram shows a layout of another on-chip superconducting controlled multiplexed device (MCC-2) in one of the fabrication methods illustrated in Figure 3(b). In Figure 3(b), 1 represents the pad for port 1, 2 represents the pad for port 2, 3 represents the pad for port 3, 4 represents the pad for port 4, 5 represents the pad for port 5, 6 represents the cosine bias line, 7 represents the sine bias line, 8 represents the global magnetic field bias line, 9 represents the λ / 2 wavelength CPW, 10 represents the balun, 112 represents the λ / 4 wavelength CPW, and 12 represents the LPF. As shown in Figure 4(b), the on-chip superconducting controlled multiplexed device (MCC-2) in this embodiment includes 5 ports, 4 λ / 2 wavelength CPWs, 8 baluns, 8 LPFs, 768 SQUIDs, 1152 JJ junctions, 8 capacitors, 1 cosine bias line, 1 sine bias line, 1 global magnetic field bias line, 13 pads, and 8 λ / 4 wavelength CPWs. In this embodiment, the microwave signal enters the on-chip superconducting control multiplexing device MCC-1 through port 1. The microwave signal of different frequencies is divided by a λ / 2 wavelength CPW and then separately transmitted into four channels, and output through ports 2, 3, 4, and 5 respectively, ultimately achieving direct manipulation and control of the qubits. In one embodiment, the JJ junction can be a circle with a diameter of 3.5 μm, based on a self-aligned superconducting niobium junction process. Referring to Figure 3(c), the on-chip superconducting control multiplexing device MCC-1 in this embodiment also includes a crossover line 15 for connecting different layers of metal thin films.

[0152] As shown in Figure 3(c), the following is adopted: Figure 2 The schematic diagram of the core region (i.e. isolator 16) of the on-chip superconducting control multiplexing device MCC-1 and on-chip superconducting control multiplexing device MCC-2 in one of the fabrication methods shown in Figure 3(c) shows that 4 represents the cosine bias line, 5 represents the sine bias line, 6 represents the global magnetic field bias line, 13 represents the capacitor, 14 represents the SQUID array, and 15 represents the cross line.

[0153] Common alignment marks, with the first and second layers being cross-shaped, only allow for the use of smaller cross-shaped marks over larger ones. It's crucial to carefully consider whether each layer should be designed with a large or small cross-shaped mark, and whether the mask should be a bright or dark plate. To simplify the overlay process and improve accuracy, this application's embodiment uses a new alignment mark diagram, as shown in Figure 3(d). Figure 2 The alignment mark design shown in the preparation method illustrates a method where the first layer of alignment marks is polygonal, while the second and subsequent layers are cross-shaped. The cross-shaped marks are overlaid on the polygonal marks of the first layer. This eliminates the need to consider whether the alignment marks of subsequent layers are large or small cross-shaped, or whether the mask is bright or dark, ensuring accurate overlay and providing a clearer visual representation of the alignment effect. This novel alignment mark design simplifies the overlay process and improves overlay accuracy.

[0154] Figure 3(e) shows the implementation of this application. Figure 2 A cross-sectional view of one of the preparation methods shown in Figure 3(e) is illustrated, where different grayscale blocks represent... Figure 2 The substance produced in one of the different process steps shown is as follows: Figure 2 One of the preparation methods shown here will not be described in detail here.

[0155] Figure 4(a) shows the embodiment of this application. Figure 2 The diagram shows a layout of another on-chip superconducting control multiplexed device (MCC-1) prepared by another method. The difference between Figure 4(a) and Figure 3(a) is that Figure 4(a) has four layers, each corresponding to a photolithography mask pattern, requiring four photolithography steps. Figure 3(a) has ten layers, each corresponding to a photolithography mask pattern, requiring ten photolithography steps. In Figure 4(a): 1 represents the pad for port 1, 2 represents the pad for port 2, 3 represents the pad for port 3, 4 represents the pad for port 4, 5 represents the pad for port 5, 6 represents the cosine bias line, 7 represents the sine bias line, 8 represents the global magnetic field bias line, 9 represents the λ / 2 wavelength CPW, 10 represents the balun, 111 represents the 50Ω gold ingot resistor, and 12 represents the LPF. As shown in Figure 4(a), the on-chip superconducting control multiplexing device MCC-1 in this embodiment includes 5 ports, 4 λ / 2 wavelength CPWs, 8 Baluns, 8 LPFs, 768 SQUIDs, 1152 JJ junctions, 8 capacitors, 1 cosine bias line, 1 sine bias line, 1 global magnetic field bias line, 13 pads, and 8 50Ω gold block resistors. In this embodiment, the microwave signal enters the on-chip superconducting control multiplexing device MCC-1 through port 1. The microwave signal of different frequencies is divided by the λ / 2 wavelength CPWs and then separately transmitted into the 4 channels, and output through ports 2, 3, 4, and 5 respectively, ultimately realizing direct operation and control of the qubits. In one embodiment, the JJ junction can be a circle with a diameter of 3.5 μm, based on a self-aligned superconducting niobium junction process. Referring to Figure 4(c), the on-chip superconducting control multiplexing device MCC-1 in this embodiment also includes a crossover line 15 for connecting different layers of metal thin films.

[0156] Figure 4(b) shows the implementation method used in this application. Figure 2The diagram shows a layout of another on-chip superconducting control multiplexed device, MCC-2, prepared using another fabrication method. The difference between Figure 4(b) and Figure 3(b) is that Figure 4(b) is a four-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring four photolithography steps. Figure 3(b) is a ten-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring ten photolithography steps. In Figure 4(b), 1 represents the pad for port 1, 2 represents the pad for port 2, 3 represents the pad for port 3, 4 represents the pad for port 4, 5 represents the pad for port 5, 6 represents the cosine bias line, 7 represents the sine bias line, 8 represents the global magnetic field bias line, 9 represents the λ / 2 wavelength CPW, 10 represents the Balun, 112 represents the λ / 4 wavelength CPW, and 12 represents the LPF. As shown in Figure 4(b), the on-chip superconducting control multiplexing device MCC-2 in this embodiment includes 5 ports, 4 λ / 2 wavelength CPWs, 8 Baluns, 8 LPFs, 768 SQUIDs, 1152 JJ junctions, 8 capacitors, 1 cosine bias line, 1 sine bias line, 1 global magnetic field bias line, 13 pads, and 8 λ / 4 wavelength CPWs. In this embodiment, the microwave signal enters the on-chip superconducting control multiplexing device MCC-1 through port 1. The microwave signal of different frequencies is divided by the λ / 2 wavelength CPWs and then separately transmitted into 4 channels, and output through ports 2, 3, 4, and 5 respectively, ultimately realizing direct operation and control of the qubits. In one embodiment, the JJ junction can be a circle with a diameter of 3.5 μm, based on a self-aligned superconducting niobium junction process. Referring to Figure 4(c), the on-chip superconducting control multiplexing device MCC-1 in this embodiment also includes a crossover line 15 for connecting different layers of metal thin films.

[0157] As shown in Figure 4(c), the following is adopted: Figure 2 The diagram shows the layout of the core region (i.e., isolator 16) of the on-chip superconducting controlled multiplexed device MCC-1 and on-chip superconducting controlled multiplexed device MCC-2 in another fabrication method shown in Figure 4(c). The difference between Figure 4(c) and Figure 3(c) is that Figure 4(c) is a four-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring four photolithography steps. Figure 3(c) is a ten-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring ten photolithography steps. As shown in Figure 4(c), 4 represents a cosine bias line, 5 represents a sine bias line, 6 represents a global magnetic field bias line, 13 represents a capacitor, 14 represents a SQUID array, and 15 represents a cross-line.

[0158] Figure 2The design of the alignment marks in another preparation method shown in Figure 3(d) is illustrated. The alignment marks in the first layer are polygonal, while those in the second and subsequent layers are cross-shaped. The cross-shaped marks are used to overlay the polygonal marks in the first layer. This eliminates the need to consider whether the alignment marks in later layers are large or small cross-shaped, or whether the mask is bright or dark, ensuring accurate overlay and providing a clearer visual representation of the alignment effect. This novel alignment mark design simplifies the overlay process and improves overlay accuracy.

[0159] Figure 4(d) shows the implementation method used in this application. Figure 2 A cross-sectional view of another preparation method shown in Figure 4(d) is presented, where different grayscale blocks represent... Figure 2 The substance produced in another different process step shown is as follows: Figure 2 Another preparation method shown will not be described in detail here.

[0160] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A superconducting quantum-controlled multiplexing device, characterized in that, include: Two or more first filters, two or more isolators, two or more capacitors, and three bias line circuits are integrated on a single chip; among them, The first filter is used to filter input signals of different frequencies from a microwave control line; An isolator is used to convert signals from a filter and output them. An isolator is a four-port device, with two ports for impedance matching loads, one port for input, and one port for output. The input and output ports of the isolator are each connected to a balun. A capacitor is installed in the isolator, and the center operating frequency of the isolator is adjusted by adjusting the capacitance value. The bias line circuit is used to adjust the bias magnetic field of the isolator. Each bias line of the bias line circuit is connected to a second filter. The superconducting quantum control multiplexing device is a five-port device. The input terminal of the superconducting quantum control multiplexing device is connected to the input terminal of the first filter to receive input signals of different frequencies from a microwave control line. The output terminal of the superconducting quantum control multiplexing device is the output port of the isolator. The first filter comprises four, namely Wavelength coplanar waveguide (CPW); the isolators include 4; the capacitors include 8, with 2 capacitors in each isolator; the three bias line circuits include one bias line circuit for Cosine signals, one bias line circuit for Sine signals, and one global magnetic field bias line circuit. The balun comprises eight filters, and the second filter comprises eight filters, which are low-pass filters (LPFs). The impedance matching load includes eight 50Ω gold ingot resistors or eight... Wavelength CPW.

2. The superconducting quantum control multiplexing device according to claim 1, wherein, The first filter is The first is a coplanar waveguide (CPW) with a wavelength of 1000 Hz; the second is a low-pass filter (LPF).

3. The superconducting quantum control multiplexing device according to claim 1, wherein, The three bias line circuits run through the isolator and include: a bias line circuit for a Cosine signal, a bias line circuit for a Sine signal, and a global magnetic field bias line circuit.

4. The superconducting quantum control multiplexing device according to claim 1, wherein, The two ports of the isolator are respectively impedance-matched to loads including: resistors with a pre-resistance of 50 ohms connected to each port. Alternatively, the two ports of the isolator may be impedance-matched to loads comprising: respectively connected to Wavelength CPW filter.

5. The superconducting quantum control multiplexing device according to claim 1, further comprising: A superconducting quantum interference device (SQUID) array is disposed in the isolator; The SQUID array comprises 768 SQUIDs, with 192 SQUIDs configured in each of the isolators; The superconducting quantum-controlled multiplexed microwave device is based on a tunable Wheatstone inductor bridge, the inductor being composed of the SQUID string.

6. A method for fabricating a superconducting quantum-controlled multiplexed device, characterized in that, For fabricating the superconducting quantum control multiplexing device according to any one of claims 1 to 5, comprising: Silicon dioxide was grown on both sides of the silicon wafer using a thermal oxidation method. Thin film, to obtain the first sample; Multiple patterns of the superconducting quantum control multiplexing device are formed by sequentially performing photolithography on the front side of the first sample. The reverse side of the sample after forming multiple patterns is processed to form the on-chip superconducting control multiplexer.

7. The preparation method according to claim 6, wherein, The multiple photolithography process includes ten steps; The process of sequentially performing multiple photolithography steps on the front side of the first sample to form multiple patterns for the superconducting quantum control multiplexing device includes: The first photolithography is performed on the front side of the first sample to prepare a three-layer thin film A, and the first pattern is obtained by peeling it off to obtain the second sample; A niobium (Nb) thin film B was prepared on the front side of the second sample, followed by a second photolithography process to etch the Nb film. Then, a first layer of silicon dioxide was grown using radio frequency magnetron sputtering. The thin film serves as the first protective layer for the Nb thin film B, and is peeled off to obtain the second pattern, thus obtaining the third sample; Thin film C is prepared on the front side of the third sample, and a third photolithography is performed to etch the third pattern to obtain the fourth sample; A fourth photolithography and etching process was performed on the front side of the fourth sample. Aluminum and its oxides Al-AlOx were used to obtain a through-hole pattern to obtain the fifth sample; A fifth photolithography was performed on the front side of the fifth sample to prepare a gold Au thin film E, and the fifth pattern was obtained by peeling it off to obtain the sixth sample. On the front side of the sixth sample, plasma-enhanced chemical vapor deposition (PECVD) was used to prepare the sample. The thin film serves as the dielectric layer for capacitors and cross-lines, and then a sixth photolithography step is performed, followed by etching to obtain the sixth pattern. Dielectric layer patterning to obtain the seventh sample; A Nb thin film G is prepared on the front side of the seventh sample, and then a seventh photolithography is performed and etched to obtain the seventh pattern to obtain the eighth sample. The seventh pattern includes: a cross-line pattern, a capacitor upper electrode pattern, a balun pattern, and an LPF pattern. A second layer was grown on the front side of the eighth sample. The thin film serves as the second protective layer for the Nb thin film G. Then, the eighth photolithography is performed, and the through-hole pattern is etched to obtain the ninth sample. A Nb thin film I was prepared on the front side of the ninth sample, and then a ninth photolithography was performed, followed by etching to obtain a bias line pattern, in order to obtain the tenth sample. The tenth photolithography step was performed on the front side of the tenth sample to etch the blank areas of the device. The tenth pattern is obtained, which leads to the eleventh sample.

8. The preparation method according to claim 7, wherein, The process of processing the reverse side of the sample after forming multiple patterns to form the on-chip superconducting control multiplexer includes: An aluminum Al thin film was prepared on the reverse side of the eleventh sample to obtain the on-chip superconducting control multiplexer.

9. The preparation method according to claim 6, wherein, The multiple photolithography process includes four steps; The process of sequentially performing multiple photolithography steps on the front side of the first sample to form multiple patterns for the superconducting quantum control multiplexing device includes: The first photolithography is performed on the front side of the first sample to prepare a three-layer thin film A, and the first pattern is obtained by peeling it off to obtain the second sample; A second photolithography step is performed on the front side of the second sample to prepare the Nb thin film B. The Nb thin film is then etched, and the first layer is regrown. The thin film serves as a protective layer for the Nb thin film B, and is peeled off to obtain a second pattern, thus obtaining a third sample; A third photolithography is performed on the front side of the third sample to prepare thin film C, and the third pattern is etched to obtain the fourth sample; The fourth photolithography was performed on the front side of the fourth sample to prepare an Au thin film D, and the eleventh pattern was obtained by peeling it off to obtain the twelfth sample.

10. The preparation method according to claim 9, wherein, The process of processing the reverse side of the sample after forming multiple patterns to form the on-chip superconducting control multiplexer includes: An Al thin film was prepared on the reverse side of the twelfth sample to obtain the on-chip superconducting control multiplexer.

11. The preparation method according to claim 7 or 9, wherein, The thickness of the thin film A is 300~330nm; The material of the thin film A includes three layers: Nb, Al-AlOx, and Nb.

12. The preparation method according to claim 11, wherein, The thickness of the thin film A is 330 nm.

13. The preparation method according to claim 7, wherein, The thickness of the Nb thin film B is 160 nm; the thickness of the first protective layer is 100~250 nm.

14. The preparation method according to claim 13, wherein, The thickness of the first protective layer is 250 nm.

15. The preparation method according to claim 7 or 9, wherein, The thickness of the thin film C is 150~300 nm; the material of the thin film C is Nb.

16. The preparation method according to claim 15, wherein, The thickness of the thin film C is 160 nm.

17. The preparation method according to claim 7, wherein, The thickness of the Au thin film E is 135~225 nm.

18. The preparation method according to claim 17, wherein, The thickness of the Au thin film E is 225 nm.

19. The preparation method according to claim 7, wherein, The The thickness of the dielectric layer is 300~500 nm.

20. The preparation method according to claim 19, wherein, The The thickness of the dielectric layer is 250 nm.

21. The preparation method according to claim 7, wherein, The thickness of the Nb thin film G is 300~600 nm.

22. The preparation method according to claim 21, wherein, The thickness of the Nb thin film G is 160 nm.

23. The preparation method according to claim 7, wherein, The thickness of the second protective layer is 300~500 nm.

24. The preparation method according to claim 23, wherein, The thickness of the second protective layer is 250 nm.

25. The preparation method according to claim 7, wherein, The thickness of the Nb thin film I is 300~600 nm.

26. The preparation method according to claim 25, wherein, The thickness of the Nb thin film I is 160 nm.

27. The preparation method according to claim 8 or 10, wherein, The thickness of the Al film is 300~600 nm.

28. The preparation method according to claim 27, wherein, The thickness of the Al film is 600 nm.

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